Method of forming monolithic light emitting diode precursors
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PLESSEY SEMICON LTD
- Filing Date
- 2020-12-03
- Publication Date
- 2026-07-03
Smart Images
Figure CN114788003B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to light-emitting diodes (LEDs). Specifically, this disclosure relates to LEDs comprising group III nitrides. Background Technology
[0002] Miniature LED arrays are typically defined as having a size of 100 × 100 μm or less. 2 LED arrays. Micro LED arrays are self-emissive components in microdisplays / projectors, suitable for a variety of devices such as smartwatches, head-mounted displays, head-up displays, cameras, viewfinders, multi-point excitation sources, and microprojectors.
[0003] One type of micro-LED array comprises multiple LEDs formed from group III nitrides. Group III nitride LEDs are inorganic semiconductor LEDs, including GaN and alloys of GaN with InN and AlN in the active light-emitting region. Compared to conventional large-area LEDs, group III nitride LEDs can be driven at significantly higher current densities and emit higher light power densities, for example, in organic light-emitting diodes (OLEDs) with organic compounds as the light-emitting layer.
[0004] In a known process for fabricating LEDs containing group III nitrides, such as the process disclosed by Wong, MS in "High efficiency of III-nitride micro-light emitting diodes by sidewall passivation using atomic layer deposition" Optics express, Vol. 26, No. 16, August 6, 2018, a micro-LED structure and an ITO contact layer are deposited on a sapphire substrate. A separate micro-LED mesa structure is then defined using a reactive ion etching (RIE) step in which a portion of the ITO layer and the micro-LED structure are removed. This etching process results in a micro-LED structure extending from the substrate with exposed sidewall surfaces. The RIE step introduces defects into the sidewall surfaces of the micro-LED mesa, creating charge trapping sites on the sidewall surfaces. The presence of trapping sites on the sidewall surfaces reduces the external quantum efficiency (EQE) of the micro-LED.
[0005] As the surface size of LEDs shrinks to the micro-LED size, the ratio of LED perimeter to LED surface area increases. Therefore, sidewall surface defects, which may be caused by etching, have a more significant impact on device EQE.
[0006] As explained by Wong, MS et al., one method to improve the EQE of micro-LEDs is to deposit a dielectric passivation layer on the sidewall surface. For example, a dielectric passivation layer containing SiO2 can be used to cover the sidewall surface of the LED mesa structure in an attempt to passivate sidewall defects.
[0007] An alternative process for forming LEDs containing group III nitrides uses selective region growth (SAG) technology. For example, UK patent application GB 1811109.6 discloses growing LED precursors through holes in a mask layer. Each LED precursor is formed as a columnar structure having a regular trapezoidal cross-section perpendicular to the substrate. The material in the mask is such that, under growth conditions, no additional material is grown directly on the mask, but only on the exposed portion of the underlying buffer layer surface. Another notable feature of selective region growth of group III nitrides along the
[0001] direction is that, depending on growth parameters such as growth temperature, pressure, and V / III ratio, a tilted surface relative to the (0001) plane (also called the c-plane) is obtained around the perimeter of the growth portion of the c-plane semiconductor defined by the opening region of the patterned mask. The tilted surface is typically oriented along the {101} or {102} plane of the wurtzite crystal and exhibits a reduced polarization field compared to the c-plane surface (semi-polar surface). Therefore, the inclined surface (sidewall) of the LED precursor is not formed by an etching step.
[0008] The object of the present invention is to provide an improved method for forming an LED precursor and an improved LED precursor, which at least solves a problem associated with prior art methods and arrays, or at least provides a commercially useful alternative. Summary of the Invention
[0009] The object of this invention is to provide an LED precursor with improved EQE. Therefore, the object of this invention is to form the LED structure using a process that does not introduce defects into the sidewalls of the LED structure, such as defects generated by etching steps.
[0010] According to a first aspect of this disclosure, a method for forming a monolithic LED precursor is provided. The method includes:
[0011] (a) Provide a substrate having a top surface;
[0012] (b) A first semiconductor layer comprising a group III nitride is formed on the top surface of the substrate;
[0013] (c) Selectively masking a first semiconductor layer with an LED mask layer, the LED mask layer including an aperture defining an LED well through the thickness of the LED mask layer to an unmasked portion of the first semiconductor layer, the LED well including a well sidewall extending from the top surface of the first semiconductor layer to the top surface of the LED mask layer;
[0014] (d) Selectively forming a monolithic LED stack within an LED well on the unmasked portion of the first semiconductor layer, the monolithic LED stack comprising:
[0015] An n-type semiconductor layer, comprising a group III nitride, is formed on the first semiconductor layer;
[0016] An active layer is formed on a first semiconductor layer. The active layer includes one or more quantum trap layers and contains group III nitrides.
[0017] A p-type semiconductor layer, comprising a group III nitride, is formed on the second semiconductor layer;
[0018] In this process, the LED stack sidewalls extending from the top surface of the first semiconductor layer of the monolithic LED stack are consistent with the LED well sidewalls of the LED mask layer.
[0019] The LED stack sidewalls of a monolithic LED stack are formed against the LED well sidewalls of an LED mask layer. Therefore, the LED stack sidewalls are shaped by the LED mask layer. This allows for the formation and shaping of monolithic LED stacks without etching the LED stack sidewalls, thus preventing etching-induced damage from being introduced into the monolithic LED stack. By reducing or eliminating damage to the LED stack sidewalls during manufacturing, the EQE of the resulting LEDs can be improved.
[0020] The cross-sectional shape of a monolithic LED stack in a plane perpendicular to the first semiconductor layer is controlled by the cross-sectional shape of the LED well in the LED mask layer. Therefore, unlike the SAG process, the sidewall shape of the LED structure can be controlled by providing different geometries based on the cross-sectional shape of the LED mask sidewalls that define the LED well. In other words, the cross-sectional area of the monolithic LED stack on the first semiconductor layer is consistent with the cross-sectional area of the unmasked portion of the first semiconductor layer exposed by the LED well (i.e., the cross-sectional area of the LED well). In contrast, in the SAG process, the LED is formed on top of the mask layer, allowing the shape and size of the LED cross-section to differ from the mask aperture.
[0021] In the manufacturing process of monolithic LED stacks, the presence of an LED mask layer leads to the formation of LED stack sidewall surfaces that are in direct contact with the LED mask sidewalls. Therefore, the LED stack sidewalls are formed from a passivation layer (LED mask sidewall) already in place. Thus, the method of forming the LED precursor can provide an LED precursor with improved EQE using an efficient and economical manufacturing process.
[0022] In some embodiments, selectively masking the first semiconductor layer with an LED mask layer includes: depositing an LED mask layer on the top surface of the first semiconductor layer; and selectively removing a first portion of the LED mask layer by means of its thickness to form an LED well. Therefore, the LED mask layer can be formed using photolithography.
[0023] In some implementations, the LED well sidewalls extend in a direction substantially perpendicular to the top surface of the first semiconductor layer. Therefore, a monolithic LED stack can be formed by LED stack sidewalls extending in a direction substantially perpendicular to the top surface of the first semiconductor layer. Conversely, in the SAG process, the LED sidewalls may be tilted relative to the normal due to the growth process.
[0024] In some embodiments, a portion of the LED well sidewall extending between the top surface of the first semiconductor layer and the LED mask layer is inclined relative to a direction perpendicular to the top surface of the first semiconductor layer. For example, in some embodiments, the LED well sidewall may include a first portion and a second portion, the first portion extending substantially perpendicular to the first semiconductor layer, and the second portion extending in a direction inclined relative to the direction perpendicular to the top surface of the first semiconductor layer. The first portion may be disposed between the second portion and the top surface of the first semiconductor layer, or vice versa. In some embodiments, substantially all of the LED well sidewall may be inclined relative to a direction perpendicular to the top surface of the first semiconductor layer.
[0025] In some embodiments, the LED well sidewall of this portion may be tilted such that, in a plane parallel to the top surface of the first semiconductor layer, the cross-sectional area of the LED well decreases in the direction from the top surface of the first semiconductor layer toward the top surface of the LED mask layer. Alternatively, the LED well sidewall of this portion may be tilted such that, in a plane parallel to the top surface of the first semiconductor layer, the cross-sectional area of the LED well increases in the direction from the top surface of the first semiconductor layer toward the top surface of the LED mask layer. Therefore, the structure of the resulting monolithic LED stack can be defined by shaping the LED well sidewalls, which improves light extraction from the LED. For example, the reduced surface area can provide a light collimation structure.
[0026] In some embodiments, the collimation portion of each LED well sidewall extending from the first semiconductor layer extends generally in a direction perpendicular to the first semiconductor layer; the tapered portion of each LED well sidewall extending between the collimation portion and the top surface of the LED mask layer is inclined such that, in a plane parallel to the top surface of the first semiconductor layer, the cross-sectional area of the LED well decreases from the top surface of the first semiconductor layer toward the top surface of the LED mask layer.
[0027] In some implementations, the method of the first aspect further includes:
[0028] (f) Remove a second portion of the LED mask layer from the top surface of the LED mask layer, so that the LED mask layer and the top surface of the monolithic LED stack form a planar surface.
[0029] Therefore, during manufacturing, a portion of the LED mask layer used to form a monolithic LED stack can be retained to serve as an insulator to fill the gaps in the LED stack sidewalls. By not removing the portion of the LED mask layer that contacts the LED stack sidewalls, damage to the LED stack sidewalls can be reduced and / or prevented, and the manufacturing process can be simplified.
[0030] In some implementations, a polishing process is used to remove the second portion of the LED mask layer. In other implementations, a selective etchant can be used to remove the LED mask layer. Therefore, it is possible to selectively remove the LED mask layer without etching the individual LED stacks.
[0031] In some implementations, the method of the first aspect further includes:
[0032] (f) After forming a monolithic LED stack, selectively remove all LED mask layers.
[0033] Therefore, after forming the monolithic LED stack, all LED mask layers can be removed. The method may further include depositing a gap-filling insulator on the top surface of the first semiconductor layer surrounding the monolithic LED stack, the gap-filling insulator forming a planarized surface with the top surface of the monolithic LED stack.
[0034] Once the planarized surface is formed, the method may further include:
[0035] (g) Bonding the planarized surface of the LED precursor to another substrate including backplane electronics; optionally,
[0036] (h) Remove the substrate from the first semiconductor layer.
[0037] Therefore, the LED precursor of the first aspect can be manufactured to be compatible with flip-chip bonding surfaces. Specifically, in some embodiments, the LED precursor can be manufactured and prepared for bonding substrates to backplane electronics without the use of an etching step.
[0038] In some embodiments, the LED mask layer includes a dielectric, such as SiO2 or SiN. x .
[0039] In some embodiments, the cross-sectional area of the LED well on the first semiconductor layer is no greater than 100 μm × 100 μm. Therefore, the method of the first aspect can be used to manufacture micro LED precursors. In particular, the cross-sectional area of the LED well on the first semiconductor layer may be no greater than 50 μm × 50 μm, 30 μm × 30 μm, 20 μm × 20 μm, 10 μm × 10 μm, 5 μm × 5 μm, 2 μm × 2 μm, or 1 μm × 1 μm, and thus, micro LED precursors with corresponding cross-sectional areas are manufactured according to the method of the first aspect.
[0040] According to a second aspect of this disclosure, a method for manufacturing an LED array precursor is provided. The method, according to a first aspect of this disclosure, includes forming a plurality of LED precursors on a substrate.
[0041] Therefore, the second approach can be combined with any of the optional features listed above. Attached Figure Description
[0042] This disclosure will now be described in conjunction with the following non-limiting drawings. Further advantages of this disclosure will become apparent when considered in conjunction with the drawings and with reference to the detailed description, wherein:
[0043] Figure 1 A flowchart of a method for forming an LED array according to an embodiment of the present disclosure is shown;
[0044] Figure 2 A schematic diagram of an LED mask layer comprising multiple LED wells formed on a first semiconductor layer is shown.
[0045] Figure 3 This shows the formation of monolithic LED stacks. Figure 2 A schematic diagram of each LED well structure;
[0046] Figure 4 It shows Figure 3 A detailed view of section A, showing the interface between the LED stack sidewalls and the LED well sidewalls according to the first growth mechanism;
[0047] Figure 5 It shows Figure 3A detailed view of section A, showing the interface between the LED stack sidewalls and the LED well sidewalls according to the second growth mechanism;
[0048] Figure 6 A schematic diagram of an LED well sidewall with a blunt tilt angle is shown.
[0049] Figure 7 A schematic diagram of an LED well sidewall with a sharp tilt angle is shown.
[0050] Figure 8 A schematic diagram of a composite LED well sidewall with a first LED well sidewall portion and a second LED well sidewall portion is shown.
[0051] Figure 9 It shows in Figure 3 A schematic diagram of the contact layer formed on a single LED stacked structure;
[0052] Figure 10 It shows Figure 9 A schematic diagram of the structure after chemical mechanical polishing;
[0053] Figure 11 The backplane electronic substrate and Figure 10 A schematic diagram of structural alignment;
[0054] Figure 12 This illustrates the process of a silicon substrate separating from its substrate after bonding. Figure 11 A schematic diagram showing the removal process from the structure;
[0055] Figure 13 It shows in Figure 12 A schematic diagram of a structure for forming a further light extraction structure on the light-emitting surface of the first semiconductor layer;
[0056] Figure 14 This shows the contact layer formed after the LED mask layer is removed. Figure 3 A schematic diagram of a single LED stacked structure;
[0057] Figure 15 This shows the formation of gap-filling insulators in Figure 14 A schematic diagram of the structure;
[0058] Figure 16 It shows the relationship with Figure 15 A schematic diagram of a backplane electronic substrate with aligned structure;
[0059] Figure 17 This illustrates the process of a silicon substrate separating from its substrate after bonding. Figure 16 A schematic diagram showing the removal of elements from the structure;
[0060] Figure 18 It shows in Figure 17A schematic diagram of a structure in which a further light extraction structure is formed on the light-emitting surface of the first semiconductor layer;
[0061] Figure 19 A schematic diagram of an LED including a crosstalk reduction structure is shown. Detailed Implementation
[0062] According to embodiments of this disclosure, a method 100 for forming an LED precursor is provided. The LED precursor includes a plurality of group III nitride layers. A flowchart of method 100 is shown below. Figure 1 As shown.
[0063] It should be noted that, according to the term "precursor" in LED precursor, the described LED precursor does not necessarily include the electrical contacts for each LED, such as those used to allow light emission, nor does it necessarily include the associated circuitry. Of course, the addition of additional electrical contacts and associated circuitry is not excluded in LED precursors and their formation methods. Therefore, the term "precursor" as used in this disclosure is intended to include the final product (i.e., LEDs, LED arrays, etc.).
[0064] This disclosure relates to various top surfaces of LED precursor layers. In this disclosure, the concept of a top surface is considered relative to the substrate 10 forming the LED precursor. That is, the top surface of a layer is the surface of the corresponding layer that is furthest from the substrate 10 in a direction perpendicular to the substrate.
[0065] like Figure 1 As shown, method 100 includes the following steps:
[0066] (a) Providing a substrate (101);
[0067] (b) Forming a first semiconductor layer (102) on a substrate;
[0068] (c) Selectively mask the first semiconductor layer (103);
[0069] (d) Selectively forming a stack of monolithic LEDs in the LED trap (104);
[0070] (e) Forming a planarized surface (105) comprising a stack of monolithic LEDs;
[0071] (f) Align and bond the LED precursor to the backplane electronic substrate (106);
[0072] (g) Remove substrate (107).
[0073] In step 101, a substrate 10 is provided. The substrate 10 can be any substrate suitable for use with a group III nitride semiconductor layer. For example, the substrate 10 can be formed from a range of materials, including silicon, GaN, sapphire, silicon carbide, SiO2, or any other known material of substrate 10 known in the art. In some embodiments, the substrate may comprise a silicon wafer, a sapphire wafer, or a SiC wafer. The substrate 10 includes a top surface 12 suitable for forming a group III nitride layer thereon.
[0074] In step 102, a first semiconductor layer 20 is formed on the top surface 12 of the substrate 10. The first semiconductor layer 20 comprises a group III nitride. In some embodiments, the first semiconductor layer 20 comprises GaN. In some embodiments, the first semiconductor layer 20 may be n-type doped. For example, the first semiconductor layer may comprise n-type doped GaN. The n-type dopant may be any suitable n-type dopant for group III nitrides, such as Si or Ge. The first semiconductor layer 20 may be n-type doped with a donor density of about 10-1. 16 -10 19 cm -3 .
[0075] The first semiconductor layer 20 may be provided as a continuous layer substantially over the entire top surface 12 of the substrate 10. The first semiconductor layer 20 includes a top surface 22, which is generally aligned with the top surface 12 of the substrate 10. Thus, the top surface 22 of the first semiconductor layer 22 is located on the opposite side of the first semiconductor layer 20 from the top surface 12 of the substrate 10.
[0076] The first semiconductor layer 20 can be deposited using any suitable deposition technique known in the art for forming group III nitride layers. For example, the first semiconductor layer 20 comprising n-type doped GaN can be deposited by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or remote plasma chemical vapor deposition (RPCVD).
[0077] In some embodiments, the first semiconductor layer 20 may have a thickness of at least 500 nm in a direction perpendicular to the substrate surface. Therefore, the first semiconductor layer 20 can provide a substantially uniform layer on the substrate 10, suitable for the formation of multiple LED precursors thereon. In some embodiments, the thickness of the first semiconductor layer 20 perpendicular to the substrate surface 12 may be at least 700 nm, 1 μm, 1.3 μm, or 1.5 μm. In some embodiments, the thickness of the first semiconductor layer 20 perpendicular to the substrate surface 12 may be no greater than 2 μm.
[0078] In step 103, the LED mask layer 30 is selectively formed on the top surface of the first semiconductor layer 20. For example... Figure 2 As shown, the LED mask layer 30 is selectively formed to define a plurality of LED wells 31 by extending the thickness of the LED mask layer 30 to the unmasked portion 24 of the first semiconductor layer 20.
[0079] In some embodiments, selectively masking the first semiconductor layer 20 with the LED mask layer 30 includes depositing the LED mask layer on the top surface 22 of the first semiconductor layer 20. For example, in some embodiments, the LED mask layer 30 is initially formed as a substantially continuous layer on the top surface 22 of the first semiconductor layer 20. Then, a first portion of the LED mask layer 30 is selectively removed based on the thickness of the LED mask layer to form an LED well 31. For example, the LED mask layer 30 can be selectively etched to remove portions of the LED mask layer 30 to define each LED well 31. In other embodiments, the first semiconductor layer 30 can be selectively patterned using a suitable patterning layer, followed by deposition of the LED mask layer 30 onto exposed portions of the first semiconductor layer 20. The patterning layer can then be removed to define, for example,... Figure 2 The LED trap 31 is shown. Therefore, it should be understood that the holes in the LED mask layer 30 can be formed by photolithography methods known in the art.
[0080] LED mask layer 30 includes multiple apertures. Each aperture defines an LED well through the thickness of LED mask layer 30. Each LED well defines a container volume for forming an LED precursor (i.e., a monolithic LED stack). Figure 2 As shown, each LED well 31 includes an LED well sidewall 34 extending from the top surface 22 of the first semiconductor layer 20 to the top surface 32 of the LED mask layer. The LED well sidewall 34 defines the LED well 31.
[0081] The LED mask layer 30 may comprise a material that serves as an electrical insulator. Specifically, the LED mask layer 30 may comprise a material on which the growth rate of group III nitrides is significantly lower than that on the first semiconductor layer 20. For example, the LED mask layer may comprise: SiN x SiON or SiO2.
[0082] The holes in the LED mask layer 30 define each LED well 31, thereby defining the shape of the monolithic LED stack formed in the LED wells. The shape and size of the holes (LED wells 31) in the plane of the top surface 22 of the first semiconductor layer 20 (and the plane parallel thereto) define the surface area of the LED. The cross-sectional shape of each LED well can be any desired two-dimensional shape. For example, the cross-sectional shape of the LED well 31 can be elliptical, triangular, rectangular, pentagonal, hexagonal, or any other polygon (regular or irregular).
[0083] In some embodiments, the LED precursor is a micro-LED precursor. Therefore, the cross-sectional shape of each LED well 31 can define a cross-sectional area no larger than 100 μm × 100 μm (i.e., the shape is suitable for a 100 μm × 100 μm region). In some embodiments, the cross-sectional shape of each LED well 31 can be no larger than: 50 μm × 50 μm, 30 μm × 30 μm, 20 μm × 20 μm, 10 μm × 10 μm, 5 μm × 5 μm, 2 μm × 2 μm, or 1 μm × 1 μm. Therefore, micro-LEDs can be formed according to the method of this embodiment.
[0084] The LED mask layer 30 can have a thickness in a direction perpendicular to the first semiconductor layer 20, such that a monolithic LED stack is formed within the LED well 31. The thickness of the LED mask layer 30 will depend on the desired thickness of the monolithic LED stack 40. For example, in some embodiments, the thickness of the LED mask layer is set to be at least 100 nm thicker than the thickness of the monolithic LED stack 40. In some embodiments, the thickness of the LED mask layer is set to be at least 500 nm, 700 nm, 1 μm, 2 μm, or 5 μm thicker than the thickness of the monolithic LED stack 40. In some embodiments, the thickness of the LED mask layer can be at least 2 μm. In other embodiments, the thickness of the LED mask layer 30 can be at least 3 μm, 5 μm, or 10 μm. In some embodiments, the thickness of the LED mask layer 30 can be no greater than 30 μm. Therefore, the LED mask layer 30 can be configured in an efficient manner without causing excessive shading of the LED well 31.
[0085] In step 104, a monolithic LED stack 40 can be formed in each LED well 31. The monolithic LED stack 40 is formed on the exposed top surface 22 of the first semiconductor layer. Thus, the monolithic LED stack is in electrical contact with the first semiconductor layer 20. An example of the monolithic LED stack 40 formed according to this step 104 is as Figure 3 shown.
[0086] Each monolithic LED stack 40 includes multiple layers. Each layer may contain group-III nitrides. In particular, the monolithic LED stack 40 includes an n-type semiconductor layer 42, an active layer 44, and a p-type semiconductor layer 46. As Figure 3 shown, the sidewalls of the monolithic LED stack 40 formed by each layer form the LED stack sidewalls 47. The LED stack sidewalls 47 of each monolithic stack extend from the top surface 22 of the first semiconductor layer 20 to the top surface of the monolithic LED stack (e.g., the top surface of the p-type semiconductor layer 46).
[0087] The n-type semiconductor layer 42 contains group-III nitrides and is formed on the first semiconductor layer. The n-type semiconductor layer 42 may contain group-III nitrides. The n-type semiconductor layer 42 can be doped with a suitable electron donor, such as Si or Ge. The n-type semiconductor layer 42 is deposited as a continuous layer on the exposed portion of the first semiconductor layer 20. The n-type semiconductor layer 42 can improve the charge carrier injection of the first active layer 21 of the first LED.
[0088] The n-type semiconductor layer 42 may have a thickness of at least 100 nm in a direction perpendicular to the surface 22 of the first semiconductor layer. In some embodiments, the n-type semiconductor layer 42 may have a thickness not greater than 2 μm in a direction perpendicular to the surface 22 of the first semiconductor layer.
[0089] The active layer 44 is formed on the first semiconductor layer 42. The active layer includes one or more quantum well sub-layers. The active layer contains group-III nitrides. In Figure 3 embodiments, the active layer 44 may include one or more quantum well layers (not shown). Thus, the active layer 44 can be multiple quantum well layers. The quantum well layers in the active layer 44 may include group-III nitride semiconductors, preferably including In-containing group-III nitride alloys. For example, in Figure 3 embodiments, the active layer 44 may include alternating layers of GaN and In X Ga 1-X N, where 0 < X ≤ 1. In particular, in some embodiments, the active layer 42 may contain In X Ga 1-XN layers, where 0 < X ≤ 0.5. Thus, in some embodiments, the active layer 42 of the LED precursor can be configured to output light having a wavelength of at least 360 nm and not greater than 650 nm. The wavelength of the light generated by the active layer 42 can be controlled by controlling the thickness and In content (X) of the quantum well layer. The active layer 44 can be deposited using any suitable method for fabricating III-nitride thin films, such as metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), remote plasma chemical vapor deposition (RPCVD), or molecular beam epitaxy (MBE). For example, in some embodiments, the active layer 44 can have a total thickness of at least 50 nm (i.e., the combination of all layers of the active layer 40) in a direction perpendicular to the first semiconductor surface 22. In some embodiments, the total thickness of the active layer 44 can be not greater than 300 nm.
[0090] The p-type semiconductor layer 46 comprises III-nitride. For example, the p-type layer can comprise GaN. The p-type semiconductor layer 46 is formed on the active layer. The p-type semiconductor layer 46 can be doped with a suitable electron acceptor, such as Mg. The p-type semiconductor layer 46 can have an acceptor density (NA) of about 10 17 -10 21 cm -3 . The p-type semiconductor layer 46 can be formed as a continuous layer covering most (e.g., all) of the exposed surface of the active layer 44 in each LED well 31. In some embodiments, the p-type semiconductor layer 46 can have a thickness of at least 50 nm in a direction perpendicular to the first semiconductor layer 22. In some embodiments, the thickness of the p-type semiconductor layer 46 in a direction perpendicular to the first semiconductor layer 22 can be not greater than 400 nm.
[0091] In some embodiments, each layer of the monolithic LED stack 40 can be deposited using any suitable method for fabricating III-nitride thin films, such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
[0092] It should be understood that the layers of the monolithic LED stack 40 will be formed substantially on the exposed surface of the first semiconductor layer 20, rather than on the surface of the LED mask layer 30. Therefore, the monolithic LED stack 40 will be formed within the LED well 31 defined by the LED mask layer 30. Since the layers of the monolithic LED stack 40 are formed within the LED well 31, the LED stack sidewalls of the monolithic LED stack conform to the LED well sidewalls of the LED mask layer 30. That is, the LED well sidewalls 34 are configured to form the LED stack sidewalls 47 during the growth of the monolithic LED stack. Therefore, the LED well sidewalls of the LED well 31 can be used to control the shape of the grown monolithic LED stack 40. Specifically, various different shapes and profiles of the LED stack sidewalls can be achieved, as explained in more detail below.
[0093] It should be understood that the total thickness of the monolithic LED stack 40 will depend on the number of layers and the thickness of each layer forming the monolithic LED stack. For example, the monolithic LED stack 40 may have a thickness of at least 400 nm in the direction perpendicular to the surface 22 of the first semiconductor layer. In some embodiments, the monolithic LED stack 40 may have a thickness of no more than 2.7 μm in the direction perpendicular to the surface 22 of the first semiconductor layer.
[0094] Figure 4 and Figure 5 Detailed views of two possible interfaces between the LED well sidewall 34 and the monolithic LED stack 40 are shown. Figure 4 In this structure, the layers of the monolithic LED stack 40 have been grown in a generally uniform manner, each extending across the LED well 31. Therefore, in Figure 4 In this implementation, the growth rate of each layer of the monolithic LED stack is substantially the same across all regions of the LED well 31. Specifically, the growth rate of the layers of the monolithic LED stack 40 is generally the same in the region of the LED well 31 near the LED well sidewall 34 as it is in the region toward the center of the LED well sidewall 31.
[0095] exist Figure 5 In this embodiment, the layer of the monolithic LED stack 40 facing the LED well sidewall 34 has a different thickness than the layer facing the center of the LED well 31 (perpendicular to the first semiconductor layer 20). Figure 5 As shown, due to the lower growth rate, the layers of the monolithic LED stack 40 may be thinner in the region near the LED well sidewall 34. Due to the wurtzite crystal structure of the group III nitride layers, the layers 42, 44, and 46 of the monolithic LED stack can be grown along the inclined plane in this region. Figure 5 In this configuration, the LED stack sidewall 47 extends in a direction substantially perpendicular to the first semiconductor layer 20, such that it aligns with the LED well sidewall 34. The top surface of the p-type semiconductor layer 46 extends away from the LED well sidewall 34.
[0096] exist Figure 4 and Figure 5 It should be understood that the LED stack sidewall 47 is consistent with the LED well sidewall 34 of the LED well. Figure 10 and Figure 11 In this configuration, each layer of the monolithic LED stack 40 terminates at an LED well sidewall 34. That is, each monolithic LED stack 40 is separated from other monolithic LED stacks 40 by an LED mask layer 30. Therefore, the layers of each monolithic LED stack 40 are discontinuous with the layers of other monolithic LED stacks 40. Accordingly, the forming layers of each monolithic LED stack 40 are appropriately electronically isolated from other monolithic LED stacks 40 that may be formed on the same first semiconductor layer 20 for LED formation. Therefore, the method for forming an LED precursor according to this embodiment can reduce or eliminate processing steps related to the deposition of electrically isolated LED stacks during LED precursor formation.
[0097] In some implementations, it is understood that the mask layer 30 also serves as a passivation layer for the LED stack sidewalls 47. Therefore, as... Figure 4 and Figure 5 As shown, the mask layer 30 passivates the surface condition of the LED stack sidewalls 47. Therefore, the LED precursor formed according to the method of this embodiment can incorporate the passivation layer as part of the manufacturing process, thereby making the manufacturing of the LED precursor more efficient.
[0098] exist Figures 2-5 In this embodiment, the LED well sidewall 34 is described as extending generally perpendicular to the first semiconductor layer 20. In other embodiments, the LED well sidewall 34 may be configured to impart different sidewall profiles on the LED stack sidewall 47. Examples of such LED well sidewalls include... Figures 6-8 As shown.
[0099] exist Figure 6 and Figure 7 In this configuration, a portion of the LED well sidewall 34 extending between the top surface 32 of the first semiconductor layer 20 and the LED mask layer 30 is inclined relative to a direction perpendicular to the top surface of the first semiconductor layer 20. Figure 6 and Figure 7 In this embodiment, the LED well sidewalls 34 have the same angle of inclination on all surfaces defining the LED wells 31 of the LED mask layer 30. Of course, in other embodiments, the angle of inclination of the LED well sidewalls 34 may vary depending on the perimeter of the LED well 31.
[0100] exist Figure 6In this configuration, the LED well sidewall 34 is inclined relative to the vertical direction (of the first semiconductor layer 20), such that in a plane parallel to the top surface 22 of the first semiconductor layer 20, the cross-sectional area of the LED well 31 increases in the direction from the top surface 22 of the first semiconductor layer 20 toward the top surface 32 of the LED mask layer. Figure 6 In the middle, the LED sidewall 34 is inclined at an obtuse angle (α) between the LED well sidewall 34 and the exposed surface 24 of the first semiconductor layer 20.
[0101] exist Figure 7 In this configuration, the LED well sidewall 34 is inclined relative to the vertical direction (of the first semiconductor layer 20), such that in a plane parallel to the top surface 22 of the first semiconductor layer 20, the cross-sectional area of the LED well 31 decreases in the direction from the top surface of the first semiconductor layer toward the top surface 32 of the LED mask layer 30. Figure 7 In the middle, the LED sidewall 34 is inclined at an acute angle (β) between the LED well sidewall 34 and the exposed surface 24 of the first semiconductor layer 20.
[0102] exist Figure 8 In this design, the LED well sidewall 34 has a composite profile comprising multiple LED well sidewall portions. Therefore, the LED well sidewall 34 may include a first LED well sidewall portion 34a extending along a first direction and a second LED well sidewall portion 34b extending along a second direction. Figure 8 In one embodiment, the first LED sidewall portion 34a extends from the first semiconductor layer 20 to the second LED sidewall portion 34b, and the second LED sidewall portion 34b extends from the first LED sidewall portion 34a to the top surface 32 of the LED mask layer 30. For example... Figure 8 As shown, the first LED sidewall portion 34a extends along a first direction substantially perpendicular to the first semiconductor layer, and the second LED well sidewall portion 34b extends along a second direction inclined relative to the vertical direction. It should be understood that... Figure 8 This is one possible example of a composite profile. In other embodiments, the composite profile may be formed by multiple LED well sidewall portions. Each LED well sidewall portion extends in a corresponding direction, either vertically or at an angle (acute or obtuse) relative to the vertical direction, to form any desired composite profile.
[0103] exist Figure 8In this configuration, the active layer 44 of the monolithic LED stack 40 is arranged along a portion of the second LED well sidewall portion 34b. An n-type semiconductor layer 42 is arranged to fill the first LED well sidewall portion 34a. Therefore, the monolithic LED stack 40 includes an elongated columnar portion of the n-type semiconductor layer extending between the active layer 44 and the first semiconductor layer 20 (towards the light-emitting surface 28). Thus, the n-type semiconductor layer 42 acts as a light-guiding structure for the LED precursor, helping to improve light extraction efficiency and / or enhance the collimation of the light extracted from the LED.
[0104] Thus, in Figure 8 In this LED stack, a collimating portion 34a of each LED well sidewall extends from the first semiconductor layer 20 in a direction substantially perpendicular to the first semiconductor layer 20. This collimating portion results in a collimating portion 47a forming the LED stack sidewall. The collimating portion of the LED stack sidewall extends from the first semiconductor layer 20 in a direction substantially perpendicular to the first semiconductor layer 20. The LED well sidewall also includes a tapered portion 34b extending between the collimating portion 34a and the top surface 32 of the LED mask layer 30. The tapered portion 34a is inclined at an acute angle such that, in a plane parallel to the top surface 22 of the first semiconductor layer 20, the cross-sectional area of the LED well 31 decreases in the direction from the top surface of the first semiconductor layer toward the top surface of the LED mask layer 30. This results in the formation of the tapered portion 47b of the LED stack sidewall, which is inclined at an acute angle. The tapered portion 47b of the LED stack sidewall extends from the collimating portion 47a to the top surface of the monolithic LED stack 40.
[0105] The composite profile of the LED mask sidewalls can be formed using photolithography techniques known to those skilled in the art.
[0106] although Figures 6-8 The example of the LED mask sidewall 34 shown includes a generally planar (i.e., flat) surface. It should also be understood that in other embodiments, the LED mask sidewall 34 may include recessed or protruding portions. Therefore, the LED stack sidewall 47 may also include recessed or protruding portions.
[0107] An LED precursor can be provided by depositing a monolithic LED stack 40 in an LED well 31. Following steps 101-104, the LED precursor can be further processed to form an LED by adding electrical contacts and associated circuitry. Figure 1 Steps 105 to 107 outline the additional process steps used to form an LED.
[0108] Once a monolithic LED stack 40 is formed in the LED well 31, step 105 of the method includes forming contacts with the monolithic LED stack and planarizing the contact surfaces for substrate bonding. Step 105 can be performed in various ways depending on the degree of further processing of the LED mask layer 30. Two possible methods will now be described. In the first method, as... Figures 9-13 As shown, the LED trap sidewall 34 is retained. In the second method, as... Figures 14-18 As shown, the LED mask layer 30 is removed before depositing the contact layer.
[0109] In the first method, an anode contact layer 50 may be formed on the top surface of the p-type semiconductor layer 46. The anode contact layer may comprise any suitable material for forming an ohmic contact with the p-type semiconductor layer 46.
[0110] The anode contact layer 50 can be patterned using any suitable patterning technique. For example, photolithography can be used to pattern the anode contact layer 50. Figure 9 In the example shown, the anode contact layer 50 is patterned to cover the top surface of each monolithic LED stack 40. The anode contact layer 50 is deposited in the LED well 31. Therefore, the top surface of the LED mask layer 30 extends beyond the anode contact layer 50 in a direction perpendicular to the first semiconductor layer. By depositing the anode contact layer 50 in the LED well, the anode contact layer is formed as part of the monolithic LED stack 40.
[0111] After the anode contact layer 50 is deposited, the LED precursor is planarized. Planarizing the LED precursor provides a surface suitable for bonding to a backplane electronic substrate. According to the first method, the LED precursor is planarized using a chemical mechanical polishing (CMP) process. Figure 10 It shows Figure 9 A schematic diagram of an LED precursor undergoing CMP treatment. (See diagram below.) Figure 10 As shown, the portion of the LED mask layer extending beyond the anode contact layer 50 in the direction perpendicular to the first semiconductor layer has been removed. Therefore, the CMP process removes a second portion of the LED mask layer from its top surface, leaving the remaining first portion of the LED mask layer planarized with the top surface of the monolithic LED stack. Thus, after the CMP process, the top surface of the LED mask layer 30 forms a substantially continuous plane with the top surface 52 of the anode contact layer 50 (i.e., the top surface of the monolithic LED stack 40).
[0112] The chemical mechanical polishing process can be any known CMP process suitable for use with group III nitrides, etc.
[0113] Once the planar surface is formed, the LED precursor can be bonded to the backplane electronic substrate 60. Figure 1 Step 106). Figure 11 An example is shown where a backplane electronics substrate 60 is aligned with an LED precursor for substrate bonding. The backplane electronics substrate includes multiple contact pads 62 and a dielectric bonding layer 64.
[0114] Contact pads 62 can be disposed on the backplane electronic substrate in a manner corresponding to the arrangement of the anode contact / monochip LED stack 40 on the first semiconductor layer 20. Contact pads 62 are configured to form an electrical connection between the backplane electronic substrate 60 and the anode contact 50. During the bonding process, contact pads 60 can be arranged to form diffusion bonding, direct bonding, or eutectic bonding with the anode contact 50.
[0115] A dielectric bonding layer 64 is disposed around contact pads 62 on the backplane electronic substrate 60. During bonding, the dielectric bonding layer can be configured to bond with the LED mask layer 30, thereby forming a hybrid substrate bond. Further information regarding suitable hybrid bonding processes is described at least in GB 1917182.6.
[0116] Substrates can be bonded together by applying pressure and / or temperature. For example, in some embodiments, after alignment, the substrates can be pressed together in a press at a temperature of at least 100°C. In some embodiments, a pressure of at least 10 kN can be applied. In some embodiments, a compressive force of at least 20 kN, 30 kN, or 40 kN can be applied. Applying a greater compressive force to the substrates to be bonded can improve the reliability of bonding between the substrates. In some embodiments, the press can apply a compressive force of no more than 45 kN to reduce the risk of substrate breakage and the risk of undesirable deformation of the contact pads 62 and anode contacts 50 during bonding.
[0117] Once the LED precursor is bonded to the backplane electronic substrate 60, the substrate 10 can be removed. Figure 1 Step 107 in the middle. Figure 12 A schematic diagram is shown of the light-emitting surface 28 of the first semiconductor layer 20, which is exposed by removing the substrate 10.
[0118] After removing the substrate, further processing steps can be performed on the light-emitting surface 28 of the first semiconductor layer 20. For example, in Figure 13 In this embodiment, a common cathode contact 70 is formed on the first semiconductor layer 20. Since the common cathode contact 70 is formed on the light-emitting surface 28, the common cathode in this embodiment comprises a material transparent to visible light. For example, the common cathode contact 70 may comprise indium tin oxide, or any other suitable transparent conductive oxide. It should be understood, of course, that... Figure 13 This is just one example of a possible arrangement of the common cathode contact 70. In other embodiments, electrical contacts with the first semiconductor layer 20 may extend through the LED mask layer 30 to the backplane electronic substrate 60.
[0119] like Figure 13 As shown, an additional optical guide structure 80 can be formed after the substrate is removed. Figure 13 In this configuration, a light guide structure 80 is formed around each monolithic LED stack 40 to prevent crosstalk between LEDs. For example, the light guide structure may include Al, Ag, Au, or any other suitable metal. In some embodiments, the light guide structure may include a reflector, such as a distributed Bragg reflector (DBR). Therefore, it should be understood that the LED array can be formed according to the first method outlined above.
[0120] According to the second method, LED arrays can also be provided. The second method is as follows: Figures 14-18 As shown.
[0121] like Figure 14 As shown, the LED mask layer 30 can be selectively removed after the monolithic LED stack 40 is formed. Figure 14 In this implementation, essentially all of the LED mask layers 30 are removed. Therefore, the LED stack sidewalls 47 are... Figure 14 The intermediate processing steps shown are exposed during this period.
[0122] Contacts can be formed between the p-type semiconductor layer 46 and the first semiconductor layer 20. For example... Figure 14 As shown, the anode contact 50 can be formed on the top surface of the p-type semiconductor layer 46. The anode contact 50 can comprise a material similar to the anode contact 50 discussed above for the first method.
[0123] A cathode contact 71 can also be formed, configured to make electrical contact with the first semiconductor layer 20. For example... Figure 14 As shown, an insulating layer 74 may be provided on at least a portion of the monolithic LED stack to provide electrical isolation between the cathode contact 71 and the monolithic LED stack 40.
[0124] After the contacts (anode contact 50 and cathode contact 71) are formed, a gap-filling insulator 90 can be formed in the gaps between the monolithic LED stack 40. Thus, the gap-filling insulator fills the remaining gaps left after the removal of the LED mask layer. The depositable gap-filling insulator includes a top insulator surface 92 that forms a substantially continuous planar surface (i.e., a flat surface) with the top surfaces 52, 72 of the anode contact 50 and cathode contact 71, respectively.
[0125] After removing the LED mask layer 30, a gap-filling insulator can be configured to fill the gaps between the monolithic LED stacks 40. The gap-filling insulator includes an insulating material to ensure that each monolithic LED stack does not short-circuit together. The gap-filling insulator also serves as a passivation layer for the LED stack sidewalls 47 of each monolithic LED stack 40. The gap-filling insulator 90 may include SiO2, SiN, etc. x Or any other suitable insulator. For example, the gap-filling insulator 90 can be formed by chemical vapor deposition or other suitable deposition techniques.
[0126] Once the planarized surface is formed, the LED precursor can be bonded to the backplane electronic substrate 60. Figure 1 Step 106 in the process. Figure 16 The diagram schematically illustrates a method for bonding an LED precursor to a backplane substrate. Figure 16 In this configuration, the backplane electronic substrate 60 is aligned with the anode and cathode contacts on the first semiconductor layer 20. The method for bonding the two substrates together can be performed in a manner similar to that described above.
[0127] After bonding the substrate, the substrate 10 can be removed from the first semiconductor layer 20. Figure 1 Step 107 in the middle. Figure 17 A schematic diagram of this process is shown. The steps for performing this step are substantially the same as those described above for the first method. After removing the substrate 10, the remaining structure comprises an array of LEDs (i.e., an LED array).
[0128] exist Figure 18 In this process, an additional light-guiding structure (i.e., lens 84) can be formed on the light-emitting surface of the first semiconductor layer 20. For example, the light-emitting surface of the first semiconductor layer can be further patterned or shaped. The light-guiding structure 84 may include a collimation structure such as lens 84 to improve light extraction from the LED.
[0129] exist Figure 19 middle, Figure 18 The implementation is further processed to include a light guide structure 80 to reduce crosstalk (i.e., a crosstalk reduction structure). A crosstalk reduction structure can be provided around each LED to reduce or prevent crosstalk between LEDs. The light guide structure 80 can be provided in a manner consistent with... Figure 13 The optical guide structure is similar.
[0130] Therefore, according to the method of this disclosure, an LED array can be formed from an LED precursor array.
Claims
1. A method for forming a monolithic LED precursor, the method comprising: (a) Providing a substrate having a top surface; (b) A first semiconductor layer comprising a group III nitride is formed on the top surface of the substrate; (c) Selectively masking the first semiconductor layer with an LED mask layer, the LED mask layer including an aperture defining an LED well through the thickness of the LED mask layer to an unmasked portion of the first semiconductor layer, the LED well including an LED well sidewall extending from the top surface of the first semiconductor layer to the top surface of the LED mask layer; (d) Selectively forming a monolithic LED stack within an LED well on the unmasked portion of the first semiconductor layer, the monolithic LED stack comprising: An n-type semiconductor layer, comprising a group III nitride, is formed on the first semiconductor layer; An active layer is formed on the first semiconductor layer, the active layer includes one or more quantum well sublayers, and the active layer contains a group III nitride; A p-type semiconductor layer comprising a group III nitride is formed on the active layer; Wherein, the LED stack sidewalls extending from the top surface of the first semiconductor layer of the monolithic LED stack are consistent with the LED well sidewalls of the LED mask layer; The collimated portion of the sidewall of each LED well, extending from the first semiconductor layer, extends in a direction substantially perpendicular to the first semiconductor layer. The tapered portion of each LED well sidewall extending between the collimation portion and the top surface of the LED mask layer is inclined such that, in a plane parallel to the top surface of the first semiconductor layer, the cross-sectional area of the LED well decreases in the direction from the top surface of the first semiconductor layer toward the top surface of the LED mask layer.
2. The method according to claim 1, wherein: Selectively masking the first semiconductor layer with an LED mask layer includes depositing the LED mask layer on the top surface of the first semiconductor layer and selectively removing a first portion of the LED mask layer by means of the thickness of the LED mask layer to form the LED well.
3. The method according to claim 1 or 2, wherein: The LED well sidewalls extend in a direction substantially perpendicular to the top surface of the first semiconductor layer.
4. The method according to claim 1 or 2, wherein: A portion of the LED well sidewall extending between the top surfaces of the first semiconductor layer and the LED mask layer is inclined relative to a direction perpendicular to the top surface of the first semiconductor layer.
5. The method according to claim 1, further comprising: (f) Remove a second portion of the LED mask layer from the top surface of the LED mask layer, such that the LED mask layer and the top surface of the monolithic LED stack form a planar surface.
6. The method according to claim 5, wherein, The second portion of the LED mask layer is removed using a polishing process.
7. The method according to claim 1, further comprising: (f) Selectively remove all LED mask layers after the monolithic LED stack is formed.
8. The method of claim 7, further comprising: A gap-filling insulator is deposited on the top surface of the first semiconductor layer surrounding the monolithic LED stack, the gap-filling insulator forming a planarized surface with the top surface of the monolithic LED stack.
9. The method according to claim 5, 6 or 8, further comprising: (g) Bond the planarized surface of the LED precursor to another substrate including backplane electronics.
10. The method of claim 9, further comprising: (h) Remove the substrate from the first semiconductor layer.
11. The method according to claim 1 or 2, wherein, The LED mask layer includes a dielectric.
12. The method according to claim 1 or 2, wherein, The cross-sectional area of the LED well on the first semiconductor layer is no greater than 100 μm × 100 μm.
13. A method for forming an LED array precursor, comprising: According to the method of claim 1, a plurality of LED precursors are formed on a substrate.