Group-III nitride multi-wavelength LED array

Abstract

An LED array includes a first mesa that includes a top surface, at least one first LED, and a tunnel junction. The at least one first LED includes a first p-type layer, a first n-type layer, and a first color active region. The tunnel junction is on the first LED, and a second n-type layer is on the tunnel junction. The LED array further includes an adjacent mesa that includes a top surface, a first LED, and a second LED. The second LED includes a second n-type layer, a second p-type layer, and a second color active region. A first trench separates the first mesa and the adjacent mesa. A cathode metallization is in the first trench and is in electrical contact with the first and second color active regions of the adjacent mesa, and an anode metallization contact is on the n-type layer of the first mesa and on the anode layer of the adjacent mesa. The device and its manufacturing method include a thin film transistor (TFT).

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to arrays of light emitting diode (LED) devices and methods of manufacturing the same. More particularly, embodiments relate to arrays of light emitting diode devices including group III nitride layers on a wafer, which provide microLEDs including tunnel junctions. Background Art

[0002] A light emitting diode (LED) is a semiconductor light source that emits visible light when current flows through it. A light emitting diode combines a P-type semiconductor and an N-type semiconductor. LEDs typically use group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on a substrate formed of sapphire or silicon carbide (SiC).

[0003] Various emerging display applications - including wearable devices, head-mounted displays, and large area displays - require miniaturized chips composed of high-density microLED (µLED or uLED) arrays with lateral dimensions as low as less than 100 µm × 100 µm. The diameter or width of a microLED (uLED) is typically about 50 µm or less, which is used to fabricate a color display by closely arranging microLEDs including red, blue, and green wavelengths. Generally, two methods are used to assemble a display composed of individual microLED dies. The first is the pick-and-place method, which includes picking up each individual blue, green, and red wavelength microLED and then aligning and attaching each individual blue, green, and red wavelength microLED to a backplane, and then electrically connecting the backplane to a driver integrated circuit. Due to the small size of each microLED, this assembly sequence is slow and prone to manufacturing errors. In addition, as the die size is reduced to meet the increasing resolution requirements of the display, an increasing number of dies must be transferred in each pick-and-place operation to fill a display of the required size.

[0004] Alternatively, to avoid the complex pick-and-place mass transfer process, various monolithic fabrication methods have been proposed to implement microLED displays. It would be desirable to provide an LED device and a method of manufacturing an LED device that provide a monolithic fabrication method. Summary of the Invention

[0005] Embodiments of the present disclosure are directed to LED arrays and methods of fabricating LED arrays. In a first embodiment, a light emitting diode (LED) array includes: a first mesa including a top surface, at least one first LED, and a first tunnel junction, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region, the first tunnel junction being on the first LED, the top surface of the first mesa including a second n-type layer on the first tunnel junction; an adjacent mesa including a top surface, a first LED, and a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region; a second tunnel junction on the second LED of the adjacent mesa, and a third n-type layer on the second tunnel junction of the adjacent mesa; a first trench separating the first mesa and the adjacent mesa; and an anode contact on the second n-type layer of the first mesa and on the top surface of the adjacent mesa. The LED array further includes a TFT driver including a driving transistor having a second electrode and a first electrode connected to a V DD line, a capacitor connected to the second electrode of the driving transistor, and a first electrode connected to a selection transistor, and the selection transistor having a first electrode and a second electrode, the second electrode of the selection transistor being connected to a data line, wherein the selection transistor is configured to be controlled by a selection line, and wherein the second electrode of the driving transistor is connected to one of the anode contacts

[0006] In a second embodiment, the first embodiment is modified such that the top surface of the adjacent mesa includes a third n-type layer.

[0007] In a third embodiment, the first embodiment further includes: a third color active region on the n-type layer of the adjacent mesa, and the adjacent mesa including a top surface including a third p-type layer; a third mesa including a first LED, a second LED, a second tunnel junction, and a third n-type layer on the second tunnel junction; a second trench separating the adjacent mesa and the third mesa; a cathode metallization in the first trench and in electrical contact with the first and second color active regions of the adjacent mesa; a cathode metallization in the second trench and in electrical contact with the first and second color active regions of the third mesa, and a cathode metallization in the first trench and in electrical contact with the first, second, and third color active regions of the adjacent mesa; and an anode contact on the third n-type layer of the third mesa.

[0008] In a fourth embodiment, the third embodiment includes the following features: the third p-type layer of the adjacent mesa is a non-etched p-type layer. In a fifth embodiment, the third or fourth embodiment is modified, wherein the first color active region is a blue active region, and the second color active region is a green active region. In a sixth embodiment, the third or fourth embodiment is modified, wherein the first color active region is a blue active region, the second color active region is a green active region, and the third color active region is a red active region.

[0009] In the seventh embodiment, any one of the first to sixth embodiments is modified such that the first p-type layer, the second p-type layer, the first n-type layer, and the second n-type layer include group-III nitride materials. In the eighth embodiment, the seventh embodiment includes the following feature: the group-III nitride material includes GaN. In the ninth embodiment, any one of the third to sixth embodiments includes the following feature: the first p-type layer, the second p-type layer, the third p-type layer, the first n-type layer, the first n-type layer, the second n-type layer, and the third n-type layer include group-III nitride materials. In the tenth embodiment, the ninth embodiment makes the group-III nitride material include GaN.

[0010] In the eleventh embodiment, any one of the first to tenth embodiments includes the following feature: the first mesa has sidewalls and an adjacent mesa has sidewalls, and the sidewalls of the first mesa and the adjacent mesa form an angle in the range from 60 degrees to less than 90 degrees with the top surface of the substrate on which the mesas are formed.

[0011] Another aspect of the present disclosure relates to an electronic system, and in the twelfth embodiment, the electronic system includes the LED array of any one of the first to eleventh embodiments and a driver circuit configured to provide an independent voltage to one or more anode contacts. In the thirteenth embodiment, the twelfth embodiment includes the following feature: wherein the electronic system is selected from the group consisting of LED-based lamps, light bars, light emitting sheets, optical displays, and microLED displays.

[0012] Another aspect relates to a method of manufacturing an LED array. In the fourteenth embodiment, a method includes: forming a first mesa that includes a top surface, at least one first LED, and a first tunnel junction, the at least one first LED includes a first p-type layer, a first n-type layer, and a first color active region, the first tunnel junction is on the first LED, and the top surface includes a second n-type layer on the first tunnel junction; forming an adjacent mesa that includes a first LED and a second LED, the second LED includes a second n-type layer, a second p-type layer, and a second color active region; forming a second tunnel junction on the second LED of the adjacent mesa and forming a third n-type layer on the second tunnel junction of the p-type layer of the adjacent mesa; forming a first trench that separates the first mesa and the adjacent mesa; and forming anode contacts on the second n-type layer of the first mesa and on the third n-type layer of the adjacent mesa.

[0013] In a fifteenth embodiment, the fourteenth embodiment further includes forming a top surface of an adjacent mesa including a third n-type layer. In a sixteenth embodiment, the fourteenth or fifteenth embodiment further includes forming a third color active region on the n-type layer of the adjacent mesa, and the adjacent mesa includes a top surface including a third p-type layer; forming a third mesa that includes a top surface, a first LED, a second LED, a second tunnel junction, and includes a third n-type layer on the second tunnel junction; and a third color active region, the top surface of the third mesa includes a third n-type layer; forming a second trench that separates the adjacent mesa and the third mesa; forming a cathode metallization in the first trench that is in electrical contact with the first color active region and the second color active region of the adjacent mesa; forming a cathode metallization in the second trench that is in electrical contact with the first color active region and the second color active region of the third mesa, and forming an n-type metallization in the first trench that is in electrical contact with the first color active region, the second color active region, and the third color active region of a second adjacent mesa, and forming a cathode metallization in the first trench that is in electrical contact with the third color active region; and forming an anode contact on the third n-type layer of the third mesa. The method further includes forming a TFT driver that includes a driving transistor having a second electrode and a first electrode connected to a V DD line, a capacitor connected to the second electrode of the driving transistor, and a first electrode connected to a selection transistor, and the selection transistor has a first electrode and a second electrode, the second electrode of the selection transistor is connected to a data line, wherein the selection transistor is configured to be controlled by a selection line, and wherein the second electrode of the driving transistor is connected to one of the anode contacts.

[0014] In a seventeenth embodiment, the sixteenth embodiment enables each of the first LED, the second LED, and the third LED to include an epitaxially deposited group III nitride material. In an eighteenth embodiment, the first LED, the second LED, and the third LED are formed on a substrate. In a nineteenth embodiment, the eighteenth embodiment enables the first trench and the second trench to be formed by etching the trenches to form the first mesa, the adjacent mesa, and the third mesa. In a twentieth embodiment, the eighteenth or nineteenth embodiment enables the group III nitride material to include GaN. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a more particular description of the above-listed features of the present disclosure for easy and detailed understanding, reference may be made to the embodiments in which the present disclosure briefly outlined above is described in more specific detail, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure and should not be considered to limit its scope, as the present disclosure may admit other equivalent embodiments. The embodiments described herein are shown in the various figures of the drawings by way of example and not limitation, in which like reference numerals indicate like elements.

[0016] Figure 1 Shows a cross-sectional view of a red, green, and blue LED device including multiple quantum wells according to one or more embodiments;

[0017] Figure 2 Shows a sacrificial layer and an etch mask formed on the LED device of Figure 1 ;

[0018] Figure 3 Shows Figure 2 The device of provides three mesa surfaces after the etching process to form an LED array;

[0019] Figure 4 Shows Figure 3 The conformal dielectric layers on the three mesa surfaces of the LED array in;

[0020] Figure 5 Shows after etching openings in the dielectric layer of the device of Figure 4 ; Figure 4 The LED array of;

[0021] Figure 6 Shows the LED array after depositing cathode metallization in the openings of Figure 5 ;

[0022] Figure 7 Shows the LED array after electro-depositing conductive metal of Figure 6 ;

[0023] Figure 8A Shows the LED array including a first mesa surface and a second mesa surface after anode formation;

[0024] Figure 8B Shows the LED array after p-contact formation of Figure 7 ;

[0025] Figure 9 Shows the LED array of connected to a backplane of Figure 7 ;

[0026] Figure 10 Shows a top view of an electronic device including an LED array configured to emit two or more colors according to an embodiment;

[0027] Figure 11 Shows Figure 10 Partition A of;

[0028] Figure 12 Shows a side view of an electronic device including an LED array and one or more TFT drivers according to an embodiment;

[0029] Figure 13Describes embodiments of an electronic device including an LED array and a TFT driver; and

[0030] Figure 14 Shows Figure 13 Partition B of Detailed Description

[0031] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0032] According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers only to a portion of the substrate, unless the context clearly indicates otherwise. Further, according to some embodiments, reference to depositing on a substrate includes depositing on a bare substrate or on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

[0033] In one or more embodiments, "substrate" means any substrate or the surface of a material formed on a substrate on which film processing is performed during a fabrication process. In an exemplary embodiment, depending on the application, the substrate surface on which processing is performed includes materials such as: silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, silicon oxide doped with carbon, germanium, gallium arsenide, glass, sapphire, and any other suitable material (such as metals, metal nitrides, group III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials). Substrates include, but are not limited to, light-emitting diode (LED) devices. In some embodiments, the substrate is exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV-cure, electron-beam-cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps are also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0034] In the present disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer serves as the substrate on which the LED devices described herein are formed.

[0035] The embodiments described herein relate to an array of LED devices and a method of forming an array of LED devices (or LED array). In particular, the present disclosure describes LED devices and a method of fabricating LED devices that emit multiple colors or wavelengths from a single wafer. The position and size of the LED devices that emit multiple colors or wavelengths are controlled by adjusting the lithography steps and the etching depth after the epitaxial deposition of the materials for forming the LED devices. In some embodiments, adjacent LED devices that emit multiple colors or wavelengths share a common n-type electrical contact. In some embodiments, the LED can be formed by using a process that does not require removal of the substrate. One or more embodiments of the present disclosure can be used to fabricate microLED displays.

[0036] In one or more embodiments, by utilizing the LED devices and their fabrication methods, integrating two or more active regions that emit different wavelengths on a single wafer provides a less complex microLED fabrication process. The devices and methods described according to one or more embodiments utilize group III nitride materials, such as materials in the AlInGaN material system, which can be fabricated to form blue, green, and red LEDs. The embodiments described herein provide a multicolor device (such as a chip) that can be used in a microLED display. In one or more embodiments, multiple layers are stacked during a single epitaxial growth process, and the multiple layers are configured to emit at different wavelengths. Devices are provided that are configured such that the corresponding emission intensity ratios between emitters of different wavelengths can be varied.

[0037] According to one or more embodiments, the devices and methods provide multiple quantum wells (MQWs) that are configured to emit red, green, and blue light within a single active region - i.e., between the p-layer and the n-layer of a p-n junction. In one or more embodiments, two or more pixels of different wavelengths are formed in the same LED device, which includes several p-n junctions on the same epitaxial wafer. By using multiple steps of etching the mesa as further described herein, the embodiments provide for the formation of independent electrical contacts to each p-n junction. According to one or more embodiments, one or more emitter layers of different wavelengths are embedded in separate p-n junctions having separate current paths, such that the wavelength and radiation are independently controlled.

[0038] Figure 3An exemplary embodiment of an LED array is shown, which is configured to emit two or more different colors adjacent to each other on the same wafer. Several p-n junctions and active regions are stacked on top of each other, and in some embodiments, they are made in sequence by epitaxial growth, where unnecessary layers are removed by post-growth etching. In one or more embodiments, a method is provided for using dry etching to open trenches for contacting buried layers. However, it has been found that the dry etching process introduces atomic-level damage to the III-nitride crystal structure of the epitaxial layer, which changes the conductive type of the p-type layer to an n-type layer.

[0039] Due to this conversion of conductive type during dry etching, it is not possible to obtain a low-resistance ohmic contact with the buried p-type nitride surface that has been exposed by dry etching. Thus, in the LED array 109 of the type shown in Figure 3 , the dry etching process results in damage to the p-GaN surface, and the non-ohmic contact with the dry-etched p-GaN surface causes a forward voltage loss of one volt or more in the blue and green active regions. Even if the voltage loss is acceptable to the device manufacturer, the p-GaN layer must be grown much thicker than the optimal thickness in order to provide sufficient error tolerance when controlling the etching rate, thus ensuring that the etching stops within the p-GaN layer.

[0040] According to one or more embodiments, by incorporating a tunnel junction into the epitaxial layer, the functions shown in Figure 3 are achieved, but without the difficulties of attempting to make electrical contact with the etched p-GaN surface. In a particular embodiment, electrical contact is made to an n-type GaN layer, which can be grown to a relatively high thickness without damaging the active region or causing optical absorption losses. Embodiments of the lithography and etching methods described herein allow for the fabrication of LEDs configured to emit different colors at adjacent locations on the same wafer. A common n-type electrical contact is made to a group of different LED colors without the need to remove the substrate.

[0041] According to one or more embodiments, an LED array and its manufacturing process are provided. Compared with existing methods, the number of independent epitaxial recipes that must be fabricated to produce the source die for a microLED display can be reduced. The reduction in the number of epitaxial recipes lowers the cost and complexity of the epitaxial manufacturing stage of LED array fabrication. Existing methods require the generation of separate blue, green, and red epitaxial recipes. In one or more embodiments, the number of pick-and-place operations required to fill a display is reduced because pixel arrays can be transferred together rather than one pixel at a time. Fewer pick-and-place operations will result in cost and yield improvements in the display assembly stage. In some embodiments, the need for pick-and-place operations is eliminated entirely, and the embodiments instead allow for wafer-level transfer of pixels across the display because each wafer can contain all three required colors (red, blue, and green). In such embodiments, an entire processed wafer or a large chunk thereof can be directly incorporated into the display. According to one or more embodiments, the problem of having to make ohmic electrical contacts to an etched p-GaN surface is avoided, enabling lower operating voltages and higher wall-plug efficiency. In some embodiments, since all etched contacts in the tunnel junction are made to the n-GaN layer, which can be grown much thicker than the p-GaN layer while maintaining high LED efficiency, the restrictions on etch rate control are relaxed.

[0042] Accordingly, one or more embodiments provide III-nitride-based LEDs, such as GaN-based LED wafers, that include two or more independent active regions configured to emit different colors, the active regions being grown sequentially and connected by a tunnel junction. The embodiments provide a multi-level mesa etch process that allows for independent electrical contact to each individual active region, thereby producing two or three different colors of LEDs on the same wafer that are very close to each other. One or more embodiments include making n-type electrical contacts to the sidewalls of the etched mesa rather than to a planar n-type III-nitride (e.g., GaN) surface. A common n-contact made from the wafer side opposite the substrate side can be used for the entire array of red, green, and blue LED mesas.

[0043] One aspect of the present disclosure relates to a method of manufacturing an LED array. First, reference is made to Figure 1, an LED device 100 is fabricated by forming a plurality of group-III nitride layers on a substrate 101 to form a plurality of LEDs on the substrate including color active regions. The color active regions include a first color active region 124, a second color active region 114, and a third color active region 104. Although any order of stacking the different color active regions is within the scope of the present disclosure, in a specific embodiment, for a device emitting towards the substrate 101 on which these layers are formed, the color active region with the shortest emission wavelength is the first color active region grown in the order of forming two or more color active regions. Thus, in one or more embodiments, the first color active region 124 is first formed on the substrate and is a blue active region; then the second color active region 114 is formed, which is a green active region; and then the third color active region 104 is formed, which is a red active region. This order where the first color active region 124 is blue, the second color active region 114 is green, and the third color active region 104 is red avoids the emission from the blue active region 124 being internally absorbed by the color active regions with longer wavelengths.

[0044] Thus, according to certain specific embodiments, the LED device 100 includes a first LED, the first LED including a first n-type layer 126 formed on the substrate, a first p-type layer 122 formed on the first n-type layer 126, and a first color active region 124 located between the first n-type layer 126 and the first p-type layer 122. In one or more embodiments, the first color active region 124 is a blue active region. In the illustrated embodiment, there is a first tunnel junction 120 on the first LED - specifically, on the first p-type layer 122. A tunnel junction is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer under reverse bias. The location where the p-type layer and the n-type layer are adjacent to each other is referred to as the p / n junction. When electrons tunnel, holes are left in the p-type layer, thus generating carriers in both regions. Therefore, in a diode-like electronic device, only a small leakage current flows under reverse bias, and a large current can be carried across the tunnel junction under reverse bias. The tunnel junction includes a specific arrangement of the conduction band and the valence band at the p / n tunnel junction. This can be achieved by using very high doping (e.g., in a p++ / n++ junction). In addition, group-III nitride materials have an inherent polarization that generates an electric field at the heterointerface between different alloy components. This polarization field can also be used to achieve the energy band alignment for tunneling.

[0045] Still referring to Figure 1, the LED device 100 further includes a second LED, which includes a second n-type layer 116 on the first tunnel junction 120, a second p-type layer 112 formed on the second n-type layer 116, and a second color active region 114 between the second n-type layer 116 and the second p-type layer 112. In one or more embodiments, the second color active region 114 is a green active region. In the illustrated embodiment, there is a second tunnel junction 110 on the second LED - particularly on the second p-type layer 112. The LED device 100 further includes a third LED, which includes a third n-type layer 106 formed on the second tunnel junction 110, a third p-type layer 102 formed on the third n-type layer 106, and a third color active region 104 between the third n-type layer 106 and the third color active region. In one or more embodiments, the third color active region 104 is a green active region.

[0046] The substrate 101 can be any substrate known to those skilled in the art and is configured for the formation of III-nitride LED devices. In one or more embodiments, the substrate includes one or more of sapphire, silicon carbide, silicon dioxide (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In a particular embodiment, the substrate 101 includes sapphire. In one or more embodiments, the substrate 101 is not patterned before forming the LED on the top surface 101t of the substrate 101. Thus, in some embodiments, the substrate 101 is not patterned and can be considered flat or substantially flat. In other embodiments, the substrate 101 is a patterned substrate.

[0047] In one or more embodiments, the n-type layer and the p-type layer of each of the first LED, the second LED, and the third LED each include a III-nitride material layer. In some embodiments, the III-nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the n-type layer and the p-type layer of each LED include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a particular embodiment, the n-type layer and the p-type layer of the corresponding LED include n-type doped and p-type doped GaN.

[0048] In one or more embodiments, the group III nitride material layers forming the first LED, the second LED, and the third LED are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0049] As used herein, "sputter deposition" refers to a physical vapor deposition (PVD) method of depositing a thin film by sputtering. In sputter deposition, a material such as a group III nitride is ejected from a target as a source onto a substrate. This technique is based on ion bombardment of the source material (target). Due to the purely physical process, i.e., sputtering of the target material, ion bombardment generates vapor.

[0050] According to some embodiments herein, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique for depositing a thin film on a substrate surface. The ALD process involves exposing the substrate surface or a portion of the substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to the alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into the reaction zone of the processing chamber, and the substrate or a portion of the substrate is exposed to the precursors individually.

[0051] According to some embodiments, "chemical vapor deposition" as used herein refers to the process of depositing a thin film of material from the gas phase by decomposition of chemical substances on a substrate surface. In CVD, the substrate surface is exposed to the precursor and / or co-reactant simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" means that most of the exposure of the precursor and the flow or presence overlap.

[0052] According to some embodiments, "plasma enhanced atomic layer deposition (PEALD)" as used herein refers to a technique for depositing a thin film on a substrate. In some examples of the PEALD process relative to the thermal ALD process, the material can be formed from the same chemical precursors, but at a higher deposition rate and lower temperature. Generally, the PEALD process sequentially introduces a reactive gas and a reactive plasma into a process chamber having a substrate therein. The first reactive gas is pulsed in the processing chamber and adsorbed onto the substrate surface. Thereafter, the reactant plasma is pulsed into the processing chamber and reacts with the first reactant gas to form a deposited material, e.g., a thin film on the substrate. Similar to the thermal ALD process, a purge step can be performed between the delivery of each reactant.

[0053] According to one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" as used herein refers to a technique for depositing a thin film on a substrate. In the PECVD process, a source material in gaseous or liquid phase, such as a gaseous group III nitride material or a vapor of a liquid group III nitride material, which has been entrained in a carrier gas, is introduced into the PECVD chamber. A plasma-initiated gas is also introduced into the chamber. The generation of plasma in the chamber produces excited radicals. The excited radicals chemically bond to the surface of the substrate located in the chamber, forming the desired film thereon.

[0054] In one or more embodiments, the LED device 100 forming the LED array is fabricated by placing the substrate 101 in a metalorganic vapor phase epitaxy (MOVPE) reactor to epitaxially grow the LED device layers. The first n-type layer 126 includes one or more layers of semiconductor material having different compositions and doping concentrations. In a particular embodiment, the first n-type layer 126 is formed by growing an epitaxial layer of a group III nitride (e.g., n-GaN). The first p-type layer 122 includes one or more layers of semiconductor material having different compositions and doping concentrations. In a particular embodiment, the first p-type layer 122 is formed by growing an epitaxial layer of a group III nitride (e.g., p-GaN). In use, current is passed through the p-n junction in the first color active region 124, and the first color active region 124 emits light of a first wavelength determined in part by the bandgap energy of the material. In some embodiments, the first LED including the first n-type layer 126, the first p-type layer 122, and the first color active region 124 includes one or more quantum wells. In one or more embodiments, the first color active region 124 is configured to emit blue light.

[0055] In a particular embodiment, after the formation of the first p-type layer 122 of p-GaN layer including a blue LED is completed, the epitaxial growth conditions are then modified to grow the first tunnel junction 120. Then a second LED is formed, which includes a second n-type layer 116, a second p-type layer 112, and a second color active region 114 between the second n-type layer 116 and the second p-type layer 112. The second n-type layer 116 is formed by growing an epitaxial layer of group III nitride (such as n-GaN). The second p-type layer 112 includes one or more layers of semiconductor materials having different compositions and doping concentrations. In a particular embodiment, the second p-type layer 112 is formed by growing an epitaxial layer of group III nitride (such as p-GaN). In use, current is passed through the p-n junction in the second color active region 114, and the second color active region 114 generates light of a second wavelength determined in part by the bandgap energy of the material. In some embodiments, the second LED including the second n-type layer 116, the second p-type layer 112, and the second color active region 114 includes one or more quantum wells. In one or more embodiments, the second color active region 114 is configured to emit green light. According to some embodiments, the formation of the second LED includes changing the thickness and / or growth conditions of the second n-type layer 116.

[0056] In a particular embodiment, after the formation of the second p-type layer 112 of p-GaN layer including a green LED is completed, the epitaxial growth conditions are then modified to grow the second tunnel junction 110. Then a third LED is formed, which includes a third n-type layer 106, a third p-type layer 102, and a third color active region 104 between the third n-type layer 106 and the third p-type layer 102. The third n-type layer 106 is formed by growing an epitaxial layer of group III nitride (such as n-GaN). The third p-type layer 102 includes one or more layers of semiconductor materials having different compositions and doping concentrations. In a particular embodiment, the third p-type layer 102 is formed by growing an epitaxial layer of group III nitride (such as p-GaN). In use, current is passed through the p-n junction in the third color active region 104, and the third color active region 104 generates light of a third wavelength determined in part by the bandgap energy of the material. In some embodiments, the third LED including the third n-type layer 106, the third p-type layer 102, and the third color active region 104 includes one or more quantum wells. In one or more embodiments, the third color active region 104 is configured to emit red light. According to some embodiments, the formation of the third LED includes changing the thickness and / or growth conditions of the third n-type layer 106.

[0057] The present disclosure is not limited to any particular epitaxial design of the first tunnel junction 120 and the second tunnel junction 110 or the LED color active region. According to one or more embodiments, after the epitaxial growth of the first LED, the second LED, and the third LED, a series of photolithography and dry etching processes are utilized to form the LED array 109, as Figure 2 - shown in FIG. 8. The end result of the photolithography and dry etching processes is an array of mesa structures having different heights, as shown in FIG. 8. Quantum wells and p-n junctions that are not desired for a particular emission color are etched away in some of the mesa structures, which results in the mesa structures having different heights.

[0058] According to an embodiment, various options may be used in the photolithography and dry etching processes, as will be discussed below. Figure 2 - Conventional processing steps, such as photoresist exposure, development, lift-off, and cleaning steps, have been omitted in FIG. 8. In one embodiment of the etching process, a first sacrificial layer 125a is patterned on a portion of the third p-type layer 102 where a mesa structure with the maximum height is desired, as Figure 2 - shown. A second sacrificial layer 125b is patterned from a portion of the third type p-type layer 102 where the height of an adjacent mesa structure is greater than the height of the first mesa structure. The height of the first sacrificial layer 125a is greater than the height of the second sacrificial layer 125b.

[0059] After forming the first sacrificial layer 125a and the second sacrificial layer 125b, an etch mask layer 127 is deposited on the third p-type layer 102 that is not covered by the first sacrificial layer 125a and the second sacrificial layer, as well as on the first sacrificial layer 125a and the second sacrificial layer, as Figure 2As shown. In the illustrated embodiment, the materials forming the etch mask layer 127 and the materials forming the first sacrificial layer 125a and the second sacrificial layer 125b are not affected by dry etch chemistries. Thus, for an etch time long enough to etch through the etch mask layer 127 and / or the sacrificial layers, the depth etched into the epitaxial wafer depends on the thicknesses of the etch mask layer and the sacrificial layers. Then, by utilizing the thickness of the sacrificial layers and the differences in etch rates between the sacrificial layers, the etch mask layer, and the epitaxial formation layers of the first LED, the second LED, and the third LED, adjacent mesa having different heights can be obtained by a single dry etch step to control the height of each mesa. The first mesa 103 has a first height represented by H, the adjacent mesa 105 has a second height, and the third mesa 107 has a third height. In the illustrated embodiment, the first height H of the first mesa 103 is less than the second height of the adjacent mesa 105 and the third height of the third mesa 107. The second height of the adjacent mesa 105 is greater than the third height of the third mesa 107. Thus, the first mesa 103 is the shortest of the three mesas. The first trench 111 separates the first mesa 103 and the adjacent mesa 105, and the second trench 113 separates the adjacent mesa 105 and the third mesa 107. The first mesa 103 has sidewalls 103s, the adjacent mesa 105 has sidewalls 105s, and the third mesa 107 has sidewalls 107s. In one or more embodiments, the sidewalls 103s, 105s, and 107s are angled with respect to the top surface 101t of the substrate. The sidewalls 103s of the first mesa 103, the sidewalls 105s of the adjacent mesa 105, and the sidewalls 107s of the third mesa 107 each form an angle "a" in the range from 75 degrees to less than 90 degrees with the top surface 101t of the substrate 101.

[0060] In some embodiments to be discussed with reference to Figure 8A there are the first mesa 103 and the adjacent mesa 105. Thus, in such embodiments, during the manufacturing process, only the first sacrificial layer is utilized and only the first trench is formed.

[0061] At the first trench 111 and the second trench 113, the etch process effectively stops at the substrate 101 because the substrate is hardly affected by etching under the conditions for etching the group III nitride epitaxial layer. In one or more embodiments, the etch mask layer 127, the first sacrificial layer 125a, and the second sacrificial layer 125b are composed of the same material or different materials. Photoresist or dielectric materials such as silicon dioxide and silicon nitride can be used as suitable etch mask materials for the mask and etch processes.

[0062] In an alternative embodiment of the etching process, the first mesa 103, adjacent mesa 105, and third mesa 107, which have different heights respectively, are processed in separate dry etching steps. In the first etching step, mesas of the same height are produced. The first etching step is stopped, and some of the mesas are re-masked to prevent their heights from decreasing in subsequent etching steps. The mask layer is not completely etched during the process and includes, in some embodiments, a material that is not affected by the etching chemicals. This alternative embodiment shows a slower manufacturing throughput than the embodiment described in the previous paragraph, but shows less stringent control over parameters such as mask and sacrificial layer thicknesses and etching rate selectivity.

[0063] After Figure 3 the mesa etching process and the appropriate cleaning steps shown in, the activation of the buried p-type layer is achieved by laterally diffusing hydrogen through the etched sidewalls of the buried p-type layer. According to one or more embodiments, the mesa is annealed after mesa etching rather than early in the process because the space between the mesas allows an effective path for hydrogen to laterally diffuse and escape from the p-type layer. The annealing can be similar to that of a conventional LED or can use a higher temperature and / or a longer time.

[0064] Now referring Figure 4 , after the activation annealing of the p-type layer, a conformal coating of a dielectric layer 130 (such as silicon dioxide) is deposited on the mesa and its sidewalls using methods such as plasma-enhanced chemical vapor deposition, atomic layer deposition, or sputtering. The dielectric layer 130 electrically isolates the metal contacts that will be fabricated in later process steps.

[0065] As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes, but is not limited to, oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3); nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes silicon dioxide (SiO2). In some embodiments, the dielectric layer composition is non-stoichiometric with respect to the ideal chemical formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon dioxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)), and oxynitrides (e.g., silicon carbon oxynitride (SiNCO)).

[0066] In one or more embodiments, the dielectric layer 130 is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0067] Now referring to Figure 5 , subsequently, portions of the mesa are masked with a resist, and openings are dry-etched in the dielectric layer 130. As Figure 5 shown, the dielectric layer 130 only covers the sidewalls 105s of the adjacent mesas 105 and the third color active regions 104 (red active regions) of the adjacent mesas 105 at the third p-type layer 102 of the adjacent mesas 105. On the third mesa 107, the dielectric layer 130 only extends on the sidewalls 107s at the third n-type layer 106, the second tunnel junction 110, the second p-type layer 112, and the second color active region 114 (green active region). On the first mesa 103, the dielectric layer 130 only covers the sidewalls 103s at the second n-type layer 116, the first tunnel junction 120, the first p-type layer 122, and the first color active region 124 (blue active region).

[0068] Now referring to Figure 6 , a cathode metallization layer 132 is deposited on the Figure 5 open areas left by the dry-etching step shown. In one or more embodiments, the cathode metallization layer 132 includes an aluminum-containing metal layer and is deposited by physical vapor deposition and patterned as Figure 6 shown. The n-contact metallization layer 132 covers the sidewalls on the n-type layer 126 of the first mesa 103 and the adjacent mesas 105. The n-contact metallization layer 132 extends to and covers the sidewalls of the third n-type layer 106 of the adjacent mesas 105. The n-contact metallization layer 132 extends to and covers the sidewalls of the third mesa 107 to the second n-type layer 116.

[0069] Now referring to Figure 7 , the first trench 111 and the second trench 113 between adjacent mesas are partially filled by electrodepositing a solution of a metal (such as copper) that uses the previously deposited aluminum-containing metal as a seed layer. If desired, the electrodeposited metal can be planarized using chemical-mechanical planarization in a subsequent processing step.

[0070] Now referring to Figure 8B , after cleaning, the LED array 109 is masked again, a set of openings for the anode metallization contacts is patterned, and another set of openings is etched in the dielectric layer 130. Then, an anode metallization contact including a conductive metal (such as silver) is patterned into the openings as Figure 8B shown. Optionally, if different contact metals are desired for the electrode contacts on the third p-type layer 102 (red LED) on the first mesa 103 and the p-type metallization contacts 136 on the n-GaN tunnel junctions of the blue LED on the third mesa 107 and the green LED of the adjacent mesas 105, then it can be performed in separate lithography and deposition steps Figure 8BThe patterning shown in

[0071] In Figure 8B In it, the cathode metallization layer 132 of the third mesa 107 of the green LED also contacts the blue LED layer in the third mesa 107, and the cathode metallization layer 132 of the first mesa 103 of the red LED also contacts the green and blue LED layers in this mesa. However, this contact does not prevent the independent operation of adjacent LEDs sharing a common cathode. The bias voltage in typical applications does not exceed 4V, which is not sufficient to inject holes outside the active region closest to the anode, even if the cathode metal contacts deeper layers in the epitaxial structure. Figure 8B The dashed arrow 150 in

[0072] Another aspect of the present disclosure relates to Figure 8A and Figure 8B the LED array shown in Figure 8A In the first embodiment shown in Figure 8A , the LED array 109a includes a first mesa 103, the first mesa 103 includes a top surface 103t, at least one first LED, and a first tunnel junction 120, at least one first LED includes a first p-type layer 122, a first n-type layer 126 and a first color active region 124, the first tunnel junction 120 is on the p-type layer 122 of the first LED, and the top surface 103t of the first mesa 103 includes a second n-type layer 116 on the first tunnel junction 120. Still referring to Figure 8A In the embodiment shown in

[0073] Therefore, the LED array 109a shown in FIG. 8 includes a monochromatic (blue) LED formed by the first mesa 103 and a two-color LED formed by the adjacent mesa 105.

[0074] Figure 8BAnother embodiment of the LED array 109b is shown, which includes a first mesa 103 that includes a top surface 103t, at least one first LED, and a first tunnel junction 120. The at least one first LED includes a first p-type layer 122, a first n-type layer 126, and a first color active region 124. The first tunnel junction 120 is on the p-type layer 122 of the first LED. The top surface 103t of the first mesa 103 includes a second n-type layer 116 on the first tunnel junction 120. The adjacent mesa 105 includes a top surface 105t, a first LED, and a second LED. The second LED includes a second n-type layer 116, a second p-type layer 112, and a second color active region 114. There is a second tunnel junction 110 on the second LED of the adjacent mesa 105 (i.e., on the p-type layer 112), and there is a third n-type layer 106 on the second tunnel junction 110 of the adjacent mesa 105. There is a first trench 111 that separates the first mesa 103 and the adjacent mesa 105. There is an n-type metallization 134 in the first trench 111 that is in electrical contact with the first color active region 124 and the second color active region 114 of the adjacent mesa 104. There are p-type metallization contacts 136 on the second n-type layer of the first mesa and on the top surface 105t of the adjacent mesa 105.

[0075] Figure 8B The LED array 109b shown in also includes a third color active region 104 on the n-type layer 106 of the adjacent mesa 105, and the adjacent mesa includes a top surface 105t that includes a third p-type layer 102. The LED array 109b also includes a third mesa 107 that includes a first LED, a second LED, a second tunnel junction 110, and a third n-type layer 106 on the second tunnel junction 110. There is a second trench 113 that separates the adjacent mesa 105 and the third mesa 107. There is a cathode metallization 134 in the second trench 113 that is in electrical contact with the first color active region 124 and the second color active region 114 of the third mesa 107, and there is a cathode metallization 134 in the first trench 111 that is in electrical contact with the first color active region 124, the second color active region 114, and the third color active region 104 of the adjacent mesa 105. In addition, there is an anode metallization contact 136 on the third n-type layer 106 of the third mesa 107.

[0076] In some embodiments, the third p-type layer 102 of the adjacent mesa 105 is a non-etched p-type layer. In some embodiments, the first color active region 124 is a blue active region, and the second color active region 114 is a green active region. In some embodiments, the first color active region 124 is a blue active region, the second color active region 114 is a green active region, and the third color active region 104 is a red active region.

[0077] In an embodiment where light is emitted toward the substrate side of the structure, the height of the mesa increases in the order of increasing emission wavelength (in this example, red > green > blue).

[0078] Referring now to Figure 9 , the electronic system or device 200 shown includes the LED array 109 of FIG. 8, and a driver circuit configured to provide independent voltages to one or more anode contacts 136 of the first mesa 103, the adjacent mesa 105, and the third mesa. This can be achieved through a backplane 190, such as a CMOS backplane 190 connected to the anode contacts 136 through metal 192 (such as metal solder bumps). In one or more embodiments, the electronic system is selected from the group consisting of LED-based lighting fixtures, light bars, light sheets, optical displays, and microLED displays.

[0079] Referring now to Figures 10 to 1 5, the electronic device 800 shown including a thin-film transistor (TFT) driver circuit includes an LED array 809 integrated with one or more TFT drivers 850. In one or more embodiments, the TFT driver circuit including one or more TFT drivers 850 is combined with any embodiment of the LED array described herein.

[0080] Figure 10 A partial top view of the LED array 809 configured to emit two or more colors is shown. Figure 10 The partial top view of shows the LED array 809, which includes a partition of a TFT matrix grid 802 having a plurality of rows and a plurality of columns. In the embodiment shown, the partition of the grid 802 has three rows and three columns, a total of nine cells, with three cells in each row arranged in a pattern of a blue (854B) column, a red (854R) column, and a green (854G) column of LEDs to provide a plurality of rows (top row 855A, middle row 855B, and bottom row 855C). Each cell includes an electrode contact 853 electrically connected to an anode metallization contact 836 (shown in the cross-section of Figures 12 - 14 ), and the anode metallization contact 836 is disposed on the mesa of the LED in any embodiment described herein. Each electrode contact 853 of each cell is surrounded by an n-type material 852 (e.g., n-type GaN).

[0081] The grid 802 further includes at least a plurality of select lines 856 extending parallel to each row 855A, 855B, 855C, and a plurality of V DD lines 858 and a plurality of data lines 860 extending perpendicular to each row. The plurality of V DD lines 858 and the plurality of data lines 860 are deposited on at least one layer above the select lines 856, as described in further detail below. In one or more embodiments, the plurality of V DDEach of the lines 858 provides a constant voltage above the threshold "on" voltage for each LED. Each row of the display has a select line 856, and each display column has a V DD line 858, but all are connected to a common external power supply. For each column driver connected to an external CMOS column driver (on each display column), there is a data line 860. The LED common cathode is connected to ground external to the device, such as the display.

[0082] Figure 11 A schematic diagram of one or more TFT drivers 850 is shown, as indicated by partition A depicted by the dashed line in Figure 10 For clarity, the insulator material is not drawn. As shown, each TFT driver 850 includes at least two transistors, a capacitor, a select line 856, a V DD line 858, and a data line 860. The V DD line 858 is connected to the first electrode 868 of the driving transistor 865, which is configured as the gate of the device. The driving transistor 865 is connected to the capacitor 864, which in turn is connected to the first electrode 867 of the select transistor 863. The second electrode 869 of the select transistor 863 is connected to the data line 860. The second electrode 866 of the driving transistor 865 is connected to the anode metallization contact 836 of each mesa that powers the LED ( Figures 12 - 14 as shown in).

[0083] According to one or more embodiments, the V DD line 858 is configured as the source, which provides a constant supply voltage above the turn-on threshold of each LED; and the select line 856 is configured as the drain. The data line 860 is configured to charge the capacitor 864 to a desired voltage, and the select line 856 is configured to turn off the driving transistor 865. In operation, the V DD line 858 provides a constant supply voltage. The cyclic voltage to the select line 856 turns off the select transistor 863, and the voltage to the data line 860 charges the capacitor 864. The current through each LED is controlled by the voltage stored in the capacitor 864. In one or more embodiments, an exemplary voltage is 3.5V.

[0084] Figure 12 Shown in connection with Figure 8BAn LED array 809 similar to the LED array shown in [reference], which includes a first mesa 803. The first mesa 803 includes a top surface 803t, at least one first LED, and a first tunnel junction 820. The at least one first LED includes a first p-type layer 822, a first n-type layer 826, and a first color active region 824. The first tunnel junction 820 is on the p-type layer 822 of the first LED. The top surface 803t of the first mesa 803 includes a second n-type layer 816 on the first tunnel junction 820. The adjacent mesa 805 includes a top surface 805t, a first LED, and a second LED. The second LED includes a second n-type layer 816, a second p-type layer 812, and a second color active region 814. There is a second tunnel junction 810 on the second LED of the adjacent mesa 805 - that is, on the p-type layer 812 - and there is a third n-type layer 806 on the second tunnel junction 810 of the adjacent mesa 805. There is a first trench separating the first mesa 803 and the adjacent mesa 805. There is an n-type metallization 834 in the first trench and in electrical contact with the first color active region 824 and the second color active region 814 of the adjacent mesa 804. There are anode metallization contacts 836 on the second n-type layer of the first mesa and on the top surface 805t of the adjacent mesa 805. A common ground electrode 847 is deposited above the first and second trenches and is in contact with the cathode metallization 834.

[0085] Using methods such as plasma-enhanced chemical vapor deposition, atomic layer deposition, or sputtering, a conformal coating of a dielectric layer 830 (such as silicon dioxide) is deposited on the mesa and its sidewalls. The dielectric layer 830 isolates the metal contacts from each other, which will be fabricated in subsequent process steps. A planarization material 845 (including a dielectric material in some embodiments) is deposited above the dielectric layer 830, the mesa, and the common ground electrode 847. Electrical contacts extend through the planarization material 845, which connect the p-type metallization contacts 836 of the first mesa 803, the adjacent mesa 805, and the third mesa 807 to the second electrode 866 of a driving transistor 865 of one or more TFT drivers 850, thereby powering the LEDs.

[0086] Figure 13 and Figure 14 A stacked layer including one or more TFT drivers 850 is shown, where Figure 14 The stacked layer is shown in more detail, as Figure 13 indicated by the dashed line B in [reference]. For ease of reference, all details of the LEDs Figure 12 are not repeated in [[reference]] Figure 13 and Figure 14 It will be appreciated that Figure 12 the capacitor 864 shown in [[reference]] Figure 13 and Figure 14Invisible in the cross-sectional view shown. Deposited on the planarized material 845 is the lower TFT dielectric layer 870, which, in some embodiments, serves as the insulator for the capacitor and gate of the select transistor 863. There is also a lower level TFT metallization layer 872, which includes a first portion 872a, a second portion 872b, and a third portion 872c. In some embodiments, these first, second, and third portions of the lower TFT metallization layer 872 serve as the gate of the select transistor 863 and the source and drain of the drive transistor 865. As Figure 13 and Figure 14 shown, the select transistor 863 includes semiconductor material 863S on the lower TFT dielectric layer 870. The drive transistor 865 includes semiconductor material 865S on the second portion 872b and the third portion 872c of the lower TFT metallization layer 872. There is an upper level TFT metallization layer 877, which includes a first portion 877a, a second portion 877b, and a third portion 877c, which, in some embodiments, serve as the gate of the select transistor and the source and drain of the drive transistor 865, respectively. On the semiconductor material 865S of the drive transistor 865 is the upper TFT dielectric layer 879, which, in some embodiments, serves as the insulator for the gate of the drive transistor 865. There is also an upper TFT metallization layer 881, which includes a first portion 881a, a second portion 881b, and a third portion 881c, which, in some embodiments, serve as the source (881a) and drain (881b) of the select transistor 863 and the gate (881c) of the drive transistor 865, respectively. Although not shown in the Figure 13 and Figure 14 cross-section, the third portion 872c of the lower metallization layer is connected to the bottom of the capacitor 864, and the first portion 872a of the lower metallization layer is connected to the select line 856. The electronic device 800 includes an LED array 809 and a driver circuit configured to provide independent voltages to one or more of the anode metallization contacts 836 of the first mesa 803, the adjacent mesa 805, and the third mesa 807. This can be achieved by the TFT circuits shown and described herein according to one or more embodiments. In one or more embodiments, the electronic device 800 is selected from the group consisting of LED-based luminaires, light bars, light sheets, optical displays, and microLED displays.

[0087] According to embodiments provided herein, a CMOS gate and column driver acquire a video input signal and convert the video input signal into a voltage on a data line, and the data line programs the LEDs to emit the light levels required to generate an image. In the embodiments described herein, the operation of device 800 is divided between "program" and "display" cycles. During the "programming" cycle, a voltage disconnect edge to a select line turns on the select transistors of a designated row, and a voltage to the data line charges each capacitor on a column to a desired voltage. In one or more embodiments, device 800 is programmed one row at a time. During the "display" cycle, the current through each LED is controlled by the voltage stored on the capacitor during the "programming" cycle.

[0088] According to an embodiment, the transistor is an amorphous silicon N-channel transistor. The source contact and drain contact may be separately deposited amorphous silicon films with high n-type (phosphorus) doping. The non-source and non-drain semiconductor regions are amorphous Si with weak p-type conductivity. In some embodiments, an applied gate voltage inverses the p-type material under the gate to n-type, thus turning on the current in the lateral direction. In some embodiments, the dielectric material is SiN prepared by plasma enhanced chemical vapor deposition x , which is also the method for depositing amorphous Si. The metal of some embodiments is typically Cr or Mo and is deposited by electron beam evaporation or sputtering.

[0089] In one or more embodiments, semiconductor materials that can be used to fabricate TFTs - whose processing temperatures are suitable for LED wafers - include amorphous silicon, laser-crystallized polysilicon, amorphous conductive oxides (such as indium gallium zinc oxide), or II-VI compounds (such as CdS). Generally, the TFT can be N-channel or P-channel, but amorphous Si transistors are always N-channel (due to low hole mobility). In some embodiments, polysilicon can allow for smaller physical dimensions of the TFT, thus allowing for smaller pixel pitches. Additionally, polysilicon has better long-term reliability and can improve the electrical efficiency of the display.

[0090] Simpler embodiments of the present disclosure include an epitaxial growth sequence characterized by only one tunnel junction (instead of two tunnel junctions) and only two colors (instead of three colors) in the active region. Although the drawings show an architecture in which the substrate remains attached in the finished device, in some embodiments, a laser lift-off or other epitaxial film separation process can be applied such that the substrate is removed in the finished device. Photoelectrochemical etching can be applied after removing the substrate to roughen the exposed GaN surface and improve the light extraction efficiency. Embodiments

[0091] The following lists various embodiments. It will be understood that, within the scope of the present invention, the embodiments listed below can be combined with all aspects and other embodiments.

[0092] Example (a). A light-emitting diode (LED) array includes: a first mesa including a top surface, at least one first LED, and a first tunnel junction, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region, the first tunnel junction being on the first LED, the top surface of the first mesa including a second n-type layer on the first tunnel junction; an adjacent mesa including a top surface, a first LED, and a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region; a second tunnel junction on the second LED of the adjacent mesa, and a third n-type layer on the second tunnel junction of the adjacent mesa; and a first trench separating the first mesa and the adjacent mesa; an anode metallization contact on the second n-type layer of the first mesa and on the top surface of the adjacent mesa.

[0093] Example (b). The LED array according to example (a) further includes a thin-film transistor (TFT) driver including a driving transistor having a second electrode and a first electrode connected to a V DD line, a capacitor connected to the second electrode of the driving transistor, and a first electrode connected to a selection transistor, and the selection transistor having a first electrode and a second electrode, the second electrode of the selection transistor being connected to a data line, wherein the selection transistor is configured to be controlled by a selection line, and wherein the second electrode of the driving transistor is connected to one of the anode metallization contacts.

[0094] Example (c). The LED array according to example (a) or example (b), wherein the top surface of the adjacent mesa includes a third n-type layer.

[0095] Example (d). The LED array according to any one of examples (a) to (c) further includes: a third color active region on the n-type layer of the adjacent mesa, and the adjacent mesa including a top surface including a third p-type layer; a third mesa including a first LED, a second LED, a second tunnel junction, and a third n-type layer on the second tunnel junction; a second trench separating the adjacent mesa and the third mesa; a cathode metallization in the first trench and in electrical contact with the first and second color active regions of the adjacent mesa; a cathode metallization in the second trench and in electrical contact with the first and second color active regions of the third mesa, and a cathode metallization in the first trench and in electrical contact with the first, second, and third color active regions of the adjacent mesa; and an anode metallization contact on the third n-type layer of the third mesa.

[0096] Example (e). The LED array according to example (d), wherein the third p-type layer of the adjacent mesa is a non-etched p-type layer.

[0097] Embodiment (f). The LED array according to embodiment (d), wherein the first color active region is a blue active region and the second color active region is a green active region.

[0098] Embodiment (g). The LED array according to embodiment (d), wherein the first color active region is a blue active region, the second color active region is a green active region, and the third color active region is a red active region.

[0099] Embodiment (h). The LED array according to any one of embodiments (a) to (g), wherein the first p-type layer, the second p-type layer, the first n-type layer, and the second n-type layer comprise group III nitride materials.

[0100] Embodiment (i). The LED array according to embodiment (h), wherein the group III nitride material comprises GaN.

[0101] Embodiment (j). The LED array according to embodiment (d), wherein the first p-type layer, the second p-type layer, the third p-type layer, the first n-type layer, the first n-type layer, the second n-type layer, and the third n-type layer comprise group III nitride materials.

[0102] Embodiment (k). The LED array according to embodiment (j), wherein the group III nitride material comprises GaN.

[0103] Embodiment (l). The LED array according to any one of embodiments (a) to (k), wherein the first mesa has sidewalls and the adjacent mesa has sidewalls, and the sidewalls of the first mesa and the adjacent mesa form an angle in the range from 60 degrees to less than 90 degrees with the top surface of the substrate on which the mesas are formed.

[0104] Embodiment (m). An electronic system, comprising: the LED array according to embodiment (b); and a driver circuit configured to provide independent voltages to one or more anode contacts.

[0105] Embodiment (n). The electronic system according to embodiment (m), wherein the electronic system is selected from the group consisting of LED-based lamps, light-emitting strips, light-emitting sheets, optical displays, and microLED displays.

[0106] Embodiment (o). A method of manufacturing an LED array, the method comprising: forming a first mesa that includes a top surface, at least one first LED, and a first tunnel junction, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region, the first tunnel junction being on the first LED, the top surface including a second n-type layer on the first tunnel junction; forming an adjacent mesa that includes a first LED and a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region; forming a second tunnel junction on the second LED of the adjacent mesa and forming a third n-type layer on the second tunnel junction of the p-type layer of the adjacent mesa; forming a first trench that separates the first mesa and the adjacent mesa; and forming an anode metallization contact on the second n-type layer of the first mesa and on the third n-type layer of the adjacent mesa.

[0107] Embodiment (p). The method according to embodiment (o), further comprising forming a thin-film transistor (TFT) driver that includes a driving transistor having a second electrode and a first electrode connected to a V DD line, a capacitor connected to the second electrode of the driving transistor, and a selection transistor having a first electrode and a second electrode, the second electrode of the selection transistor being connected to a data line, wherein the selection transistor is configured to be controlled by a selection line, and wherein the second electrode of the driving transistor is connected to one of the anode metallization contacts.

[0108] Embodiment (q). The method according to embodiment (o) or embodiment (p), further comprising forming a top surface of an adjacent mesa that includes a third n-type layer.

[0109] Embodiment (r). The method according to any one of embodiments (o) to (q), further comprising: forming a third color active region on the n-type layer of the adjacent mesa, and the adjacent mesa including a top surface that includes a third p-type layer; forming a third mesa that includes a top surface, a first LED, a second LED, a second tunnel junction, and includes a third n-type layer on the second tunnel junction; and a third color active region, the top surface of the third mesa including a third n-type layer; forming a second trench that separates the adjacent mesa and the third mesa; forming a cathode metallization in the first trench that is in electrical contact with the first color active region and the second color active region of the adjacent mesa; forming a cathode metallization in the second trench that is in electrical contact with the first color active region and the second color active region of the third mesa, and forming a cathode metallization in the first trench that is in electrical contact with the first color active region, the second color active region, and the third color active region of a second adjacent mesa, and forming an n-type metallization in the first trench that is in electrical contact with the third color active region; and forming an anode metallization contact on the third n-type layer of the third mesa.

[0110] Embodiment(s). The method according to embodiment (r), wherein each of the first LED, the second LED, and the third LED comprises an epitaxially deposited group III nitride material.

[0111] Embodiment (t). The method according to embodiment (s), wherein the first LED, the second LED, and the third LED are formed on a substrate, and wherein the first trench and the second trench are formed by etching trenches to form a first mesa, an adjacent mesa, and a third mesa.

[0112] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "a," "an," "the," and similar references should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the recitation of ranges of values herein is merely intended to serve as a shorthand method for individually referring to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated herein or clearly contradicted by the context in some other way, all methods described herein can be performed in any suitable order. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illuminate the materials and methods and does not impose a limitation on the scope unless otherwise claimed. No language in this specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0113] Throughout this specification, references to the terms first, second, third, etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0114] Throughout this specification, references to a layer, region, or substrate being "on" or extending "onto" another element mean that it can be directly on or directly extend onto the other element, or there may also be intervening elements. When an element is referred to as being "directly on" or "directly extending onto" another element, there may be no intervening element present. Additionally, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intervening element present between the element and the other element. It will be understood that these terms are intended to cover different orientations of the elements in addition to any orientation depicted in the various figures.

[0115] Relative terms such as "below", "above", "upper", "lower", "horizontal", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the various figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the various figures.

[0116] Throughout this specification, reference to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" throughout this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0117] Although the present disclosure has been described with reference to particular embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that the present disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode (LED) array, comprising: A first mesa, the first mesa including a top surface, at least one first LED, and a first tunnel junction, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region, the first tunnel junction being on the first LED, and the top surface of the first mesa including a second n-type layer on the first tunnel junction; An adjacent mesa, the adjacent mesa including a top surface, a first LED, and a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region; A second tunnel junction on the second LED of the adjacent mesa, and a third n-type layer on the second tunnel junction of the adjacent mesa; A first trench separating the first mesa and the adjacent mesa; An anode metallization contact on the second n-type layer of the first mesa and on the top surface of the adjacent mesa; A third color active region on the n-type layer of the adjacent mesa, and the adjacent mesa including a top surface including a third p-type layer; A third mesa, the third mesa including a first LED, a second LED, a second tunnel junction, and a third n-type layer on the second tunnel junction; A second trench separating the adjacent mesa and the third mesa; A cathode metallization in the first trench in direct electrical contact with the first n-type layer of the first mesa via a cathode metallization layer in the first trench; A cathode metallization in the second trench in direct electrical contact with the first n-type layer and the second n-type layer of the third mesa via a cathode metallization layer in the second trench; A cathode metallization in the first trench in direct electrical contact with the first n-type layer, the second n-type layer, and the third n-type layer of the adjacent mesa via a cathode metallization layer in the first trench; and An anode metallization contact on the third n-type layer of the third mesa.

2. The LED array according to claim 1 further includes a thin film transistor (TFT) driver, the thin film transistor driver including a driving transistor having a second electrode and a first electrode connected to the V DD -line, a capacitor connected to the second electrode of the driving transistor, and a connection to the first electrode of a selection transistor, and the selection transistor having a first electrode and a second electrode, the second electrode of the selection transistor being connected to a data line, wherein the selection transistor is configured to be controlled by a selection line, and wherein the second electrode of the driving transistor is connected to one of the anode metallization contacts.

3. The LED array according to claim 1, wherein the top surface of the adjacent mesa includes the third n-type layer.

4. The LED array according to claim 1, wherein the third p-type layer of the adjacent mesa is a non-etched p-type layer.

5. The LED array according to claim 1, wherein the first color active region is a blue active region, and the second color active region is a green active region.

6. The LED array according to claim 1, wherein the first color active region is a blue active region, the second color active region is a green active region, and the third color active region is a red active region.

7. The LED array according to claim 1, wherein the first p-type layer, the second p-type layer, the first n-type layer, and the second n-type layer include group III nitride materials.

8. The LED array according to claim 7, wherein the group III nitride materials include GaN.

9. The LED array according to claim 1, wherein the first p-type layer, the second p-type layer, the third p-type layer, the first n-type layer, the first n-type layer, the second n-type layer, and the third n-type layer include group III nitride materials.

10. The LED array according to claim 9, wherein the group III nitride material comprises GaN.

11. The LED array according to claim 1, wherein the first mesa has sidewalls and the adjacent mesa has sidewalls, and the sidewalls of the first mesa and the sidewalls of the adjacent mesa form an angle in the range from 60 degrees to less than 90 degrees with the top surface of the substrate on which the mesas are formed.

12. An electronic system, comprising: The LED array according to claim 2; and A driver circuit configured to provide independent voltages to one or more anode contacts.

13. The electronic system according to claim 12, wherein the electronic system is selected from the group consisting of LED-based lamps, light bars, light sheets, optical displays, and microLED displays.

14. A method of manufacturing an LED array, the method comprising: Forming a first mesa, the first mesa comprising a top surface, at least one first LED, and a first tunnel junction, the at least one first LED comprising a first p-type layer, a first n-type layer, and a first color active region, the first tunnel junction being on the first LED, the top surface comprising a second n-type layer on the first tunnel junction; Forming an adjacent mesa, the adjacent mesa comprising a first LED and a second LED, the second LED comprising a second n-type layer, a second p-type layer, and a second color active region; Forming a second tunnel junction on the second LED of the adjacent mesa and forming a third n-type layer on the second tunnel junction of the p-type layer of the adjacent mesa; Forming a first trench separating the first mesa and the adjacent mesa; Forming anode metallization contacts on the second n-type layer of the first mesa and on the third n-type layer of the adjacent mesa; Forming a third color active region on the n-type layer of the adjacent mesa, and the adjacent mesa comprising a top surface including a third p-type layer; Forming a third mesa, the third mesa comprising a first LED, a second LED, a second tunnel junction, and a third n-type layer on the second tunnel junction; Forming a second trench separating the adjacent mesa and the third mesa; Forming a cathode metallization in the first trench that is in direct electrical contact with the first n-type layer of the first mesa via a cathode metallization layer in the first trench; Forming a cathode metallization in the second trench that is in direct electrical contact with the first n-type layer and the second n-type layer of the third mesa via a cathode metallization layer in the second trench; Forming a cathode metallization in the first trench that is in direct electrical contact with the first n-type layer, the second n-type layer, and the third n-type layer of the adjacent mesa via a cathode metallization layer in the first trench; and Forming an anode metallization contact on the third n-type layer of the third mesa.

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