A successive approximation analog-to-digital converter and a method for mismatch voltage detection

Abstract

A SAR ADC and a method for mismatch voltage detection. When performing a capacitor mismatch detection, a SAR control circuit is configured to control a CDAC to output a mismatch voltage according to a first control signal. A variable capacitor array is configured to provide a detection voltage. A comparator is configured to generate a comparison result according to the mismatch voltage and the detection voltage. A correction control circuit is configured to generate the first control signal and generate a second control signal according to the comparison result. An RDAC is configured to output an analog voltage according to the second control signal and charge the variable capacitor array to generate the detection voltage. In the foregoing capacitor mismatch detection process, due to the adjustable size of the capacitors of the variable capacitor array, a variable voltage range is provided. When the capacitors of the variable capacitor array are small, a small voltage range is provided. Since the voltage range is small, the accuracy is high, and therefore a detection voltage with sufficient accuracy can be provided based on the voltage range to accurately measure the mismatch amount of the low-bit capacitors in the CDAC.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and more particularly to a successive approximation register analog-to-digital converter (SAR ADC) and a method for mismatch voltage detection. Background Technology

[0002] The digital-to-analog converter (DAC) in a SAR ADC typically consists of a binary weighted capacitor array. This array contains multi-bit capacitors, with the capacitance value of each capacitor increasing exponentially with the number of bits. In practical applications, there will be a certain deviation between the capacitance value of each capacitor and the ideal design value, known as capacitor mismatch. To ensure the performance of the SAR ADC, it is necessary to correct the capacitor mismatch.

[0003] A commonly used capacitor mismatch correction technique is the digital domain back-end correction technique. This technique can correct the mismatch of each capacitor in the DAC bit by bit. Accurately measuring the mismatch of each capacitor is particularly important. Specifically, this technique controls the switching of each capacitor in the DAC to generate a mismatch voltage corresponding to the capacitor under test. This voltage reflects the mismatch of the capacitor under test. Then, a detection voltage is injected into the DAC, causing the detection voltage to cancel out the mismatch voltage. Since the magnitude of the detection voltage is known, the mismatch of the capacitor under test can be determined by its magnitude.

[0004] This technology typically pre-sets a fixed voltage range, within which different detection voltages can be provided. Since the mismatch voltage corresponding to the highest capacitor is relatively large, the voltage range usually needs to be set large enough. However, when the voltage range is too large, its accuracy is low, making it impossible to accurately measure the mismatch of the lower capacitors. Summary of the Invention

[0005] This application provides a method for successive approximation analog-to-digital converters and mismatch voltage detection, which can accurately measure the capacitance mismatch of the low-order capacitors in the RDAC.

[0006] The first aspect of this application provides a successive approximation analog-to-digital converter, including: a capacitor digital-to-analog converter (CDAC), a SAR control circuit, a variable capacitor array, a comparator, a correction control circuit, and a resistance digital-to-analog converter (RDAC).

[0007] When performing capacitor mismatch detection of CDAC, the SAR control circuit is used to control the CDAC to output a first voltage according to the first control signal, wherein the first voltage is the mismatch voltage, which is related to the capacitor mismatch of CDAC.

[0008] A variable capacitor array is used to provide a second voltage, which is a detection voltage used to detect the magnitude of the first voltage;

[0009] The comparator is used to compare the first voltage and the second voltage to generate a comparison result;

[0010] The correction control circuit is used to generate a first control signal and a second control signal based on the comparison result;

[0011] The RDAC is used to output an analog voltage according to the second control signal and charge the variable capacitor array to generate the second voltage;

[0012] The capacitance value of the variable capacitor array is adjustable.

[0013] In the aforementioned successive approximation analog-to-digital converter, a variable voltage range is provided because the capacitance value of the variable capacitor array used to provide the second voltage is adjustable. When the capacitance value of the variable capacitor array is small, a smaller voltage range can be provided. Since the voltage range is small, its accuracy is high. Therefore, based on this voltage range, a detection voltage with sufficient accuracy can be provided to accurately measure the capacitance mismatch of the low-order capacitors in the RDAC.

[0014] In conjunction with the first aspect of the embodiments of this application, in a first implementation of the first aspect of the embodiments of this application, the correction control circuit is further configured to generate a third control signal to control the variable capacitor array to adjust the capacitance value.

[0015] In the above implementation, a third control signal is generated by the correction control circuit to adjust the capacitance value of the variable capacitor array, thereby improving the flexibility and selectivity of the solution.

[0016] In conjunction with the first implementation of the first aspect of the present application, in the second implementation of the first aspect of the present application, the correction control circuit includes: a state machine, which is used to output a third control signal to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor to be measured.

[0017] In the above implementation, a third control signal is generated by the state machine in the correction control circuit to adjust the capacitance value of the variable capacitor array, so that the adjusted capacitance value of the variable capacitor array matches the mismatch of the capacitor under test, thereby improving the flexibility and selectivity of the solution.

[0018] In conjunction with the first or second implementation of the first aspect of the embodiments of this application, in the third implementation of the first aspect of the embodiments of this application, the variable capacitor array includes multiple parallel capacitor branches, and each capacitor branch includes a capacitor and a switch connected in series.

[0019] In the above implementation, a variable capacitor array is formed by multiple parallel capacitor branches, which improves the flexibility and selectivity of the solution.

[0020] In conjunction with the third implementation of the first aspect of the present application, in the fourth implementation of the first aspect of the present application, the variable capacitor array is used to: control the switching of at least one capacitor branch according to the third control signal.

[0021] In the above implementation, after receiving the third control signal sent by the correction control circuit, the variable capacitor array can control the switch in at least one capacitor branch to switch according to the third control signal, thereby adjusting its own capacitance value so that the adjusted capacitance value can match the mismatch of the capacitor under test in RDCA, so as to accurately detect the capacitance mismatch of the capacitor under test.

[0022] In conjunction with the first aspect of the embodiments of this application and any one of the first to fourth implementations of the first aspect of the embodiments of this application, in the fifth implementation of the first aspect of the embodiments of this application, the SAR control circuit is used to: control the capacitor array in the CDAC to switch according to the first control signal so as to output a first voltage.

[0023] In the above implementation, after receiving the first control signal sent by the correction control circuit, the SRA control circuit can switch the capacitor array in the CDAC based on the first control signal so that the CDAC outputs the first voltage, which improves the flexibility and selectivity of the solution.

[0024] In conjunction with the fifth implementation of the first aspect of the present application, in the sixth implementation of the first aspect of the present application, the SAR control circuit is used to: control the switching of the capacitor under test in the capacitor array of the CDAC, and the switching of the low-order capacitors whose median value is lower than that of the capacitor under test, so as to output a first voltage, the first voltage being associated with the mismatch of the capacitor under test.

[0025] In the above implementation, after receiving the first control signal sent by the correction control circuit, the SRA control circuit can switch the switching of the capacitor to be tested in the capacitor array of the CDAC, as well as the switching of the low-order capacitors whose median value is lower than that of the capacitor to be tested, so that the CDAC outputs the first voltage, thereby improving the flexibility and selectivity of the solution.

[0026] A second aspect of this application provides a method for mismatch voltage detection. This method is applied to a successive approximation analog-to-digital converter (ADC), which includes a CDAC, a comparator, a SAR control circuit, an RDAC, a variable capacitor array, and a correction control circuit. The capacitance value of the variable capacitor array is adjustable. The method includes:

[0027] The first control signal is generated by the calibration control circuit;

[0028] The SAR control circuit controls the CDAC to output a first voltage according to the first control signal;

[0029] The comparator generates a comparison result based on the first voltage and the second voltage.

[0030] The calibration control circuit generates a second control signal based on the comparison result.

[0031] The RDAC outputs an analog voltage based on the second control signal and charges the variable capacitor array to generate the second voltage.

[0032] In the above-described method for detecting mismatch voltage, since the capacitance value of the variable capacitor array used to provide the second voltage is adjustable, a variable voltage range is provided. When the capacitance value of the variable capacitor array is small, a smaller voltage range can be provided. Because the voltage range is small, its accuracy is high. Therefore, based on this voltage range, a detection voltage with sufficient accuracy can be provided to accurately measure the capacitance mismatch of the low-order capacitors in the RDAC.

[0033] In conjunction with the second aspect of the embodiments of this application, in a first implementation of the second aspect of the embodiments of this application, the method further includes: generating a third control signal through a correction control circuit to control the variable capacitor array to adjust the capacitance value.

[0034] In the above implementation, a third control signal is generated by the correction control circuit to adjust the capacitance value of the variable capacitor array, thereby improving the flexibility and selectivity of the solution.

[0035] In conjunction with the first implementation of the second aspect of this application, in the second implementation of the second aspect of this application, the correction control circuit includes: a state machine, which generates a third control signal to control the variable capacitor array to adjust the capacitance value, including:

[0036] The state machine outputs a third control signal to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor under test.

[0037] In the above implementation, a third control signal is generated by the state machine in the correction control circuit to adjust the capacitance value of the variable capacitor array, so that the adjusted capacitance value of the variable capacitor array matches the mismatch of the capacitor under test, thereby improving the flexibility and selectivity of the solution.

[0038] In conjunction with the first or second implementation of the second aspect of this application, in the third implementation of the second aspect of this application, the variable capacitor array includes multiple parallel capacitor branches, and each capacitor branch includes a capacitor and a switch connected in series. Controlling the variable capacitor array to adjust the capacitance value includes:

[0039] The switches in at least one capacitor branch are switched by a variable capacitor array according to a third control signal.

[0040] In the above implementation, after receiving the third control signal sent by the correction control circuit, the variable capacitor array can control the switch in at least one capacitor branch to switch according to the third control signal, thereby adjusting its own capacitance value so that the adjusted capacitance value can match the mismatch of the capacitor under test in RDCA, so as to accurately detect the capacitance mismatch of the capacitor under test.

[0041] In conjunction with the second aspect of the embodiments of this application and any one of the first to third implementations of the second aspect of the embodiments of this application, in the fourth implementation of the first aspect of the embodiments of this application, controlling the CDAC to output a first voltage according to the first control signal by the SAR control circuit includes:

[0042] The SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal in order to output the first voltage.

[0043] In the above implementation, after receiving the first control signal sent by the correction control circuit, the SRA control circuit can switch the capacitor array in the CDAC based on the first control signal so that the CDAC outputs the first voltage, which improves the flexibility and selectivity of the solution.

[0044] In conjunction with the fourth implementation of the second aspect of the embodiments of this application, in the fifth implementation of the second aspect of the embodiments of this application, the SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal to output the first voltage, including:

[0045] The SAR control circuit controls the switching of the capacitor under test in the capacitor array of the CDAC, as well as the switching of the low-order capacitors in the capacitor array whose median value is lower than that of the capacitor under test, to output a first voltage, which is related to the mismatch of the capacitor under test.

[0046] In the above implementation, after receiving the first control signal sent by the correction control circuit, the SRA control circuit can switch the switching of the capacitor to be tested in the capacitor array of the CDAC, as well as the switching of the low-order capacitors whose median value is lower than that of the capacitor to be tested, so that the CDAC outputs the first voltage, thereby improving the flexibility and selectivity of the solution.

[0047] A third aspect of the embodiments of this application also provides a communication chip, including an antenna, a radio frequency front end, a digital processing circuit, and a successive approximation analog-to-digital converter as described in the first aspect, or any one of the first to sixth implementations of the first aspect;

[0048] Antenna, used to receive analog signals;

[0049] The radio frequency front end is used to down-convert analog signals to obtain down-converted analog signals.

[0050] A successive approximation analog-to-digital converter is used to convert down-frequency analog signals into digital signals.

[0051] Digital processing circuits are used to encode and decode digital signals.

[0052] This application provides a SAR ADC and a method for detecting capacitance mismatch voltage. The SAR ADC includes a capacitor deactivation array (CDAC), a comparator, a SAR control circuit, an analog capacitor deactivation array (RDAC), a variable capacitor array, and a correction control circuit. During capacitance mismatch detection, the SAR control circuit controls the CDAC to output a first voltage based on a first control signal. This first voltage is associated with the capacitance mismatch of the CDAC. The variable capacitor array provides a second voltage, which is used to detect the magnitude of the first voltage. The comparator generates a comparison result based on the first and second voltages. The correction control circuit generates a first control signal and a second control signal based on the comparison result. The RDAC outputs an analog voltage based on the second control signal and charges the variable capacitor array to generate the second voltage. In the aforementioned capacitance mismatch detection process, since the capacitance of the variable capacitor array is adjustable, a variable voltage range is provided. When the capacitance of the variable capacitor array is small, a smaller voltage range can be provided. Because the voltage range is small, its accuracy is high. Therefore, based on this voltage range, a second (detection) voltage with sufficient accuracy can be provided to accurately measure the capacitance mismatch of the lower capacitor in the CDAC. Attached Figure Description

[0053] Figure 1 A schematic diagram of the structure of a SAR ADC provided in an embodiment of this application;

[0054] Figure 2 This is a schematic diagram of the CDAC structure;

[0055] Figure 3 A schematic diagram of the capacitor switching state of the CDAC;

[0056] Figure 4 Another schematic diagram showing the capacitor switching state of the CDAC;

[0057] Figure 5 Another schematic diagram showing the capacitor switching state of the CDAC;

[0058] Figure 6 Another schematic diagram showing the capacitor switching state of the CDAC;

[0059] Figure 7 This is a schematic diagram of a variable capacitor array. Detailed Implementation

[0060] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0061] Figure 1 For a schematic diagram of the SAR ADC provided in the embodiments of this application, please refer to [link / reference]. Figure 1 The SAR ADC includes a main circuit for analog-to-digital conversion and a correction circuit for capacitor mismatch correction.

[0062] The main circuit includes a CDAC, a comparator, and a SAR control circuit. The output of the CDAC is coupled to the input of the comparator, the output of the comparator is coupled to the input of the SAR control circuit, and the output of the SAR control circuit is coupled to the capacitor switch of the CDAC. When the SAR ADC is in analog-to-digital conversion mode, the CDAC first samples and quantizes the input analog signal. The comparator then compares the results of the sampling and quantization. Finally, the SAR control circuit outputs a digital signal based on the comparison result, thus completing the conversion between analog and digital signals.

[0063] A CDAC can be constructed from a binary weighted capacitor array. For ease of understanding, the following will combine... Figure 2 The structure of CDAC will be described in detail. Figure 2 A schematic diagram of the CDAC structure, as shown below. Figure 2 As shown, the CDAC has a total capacitance of 2 N It consists of multiple capacitors, with the highest capacitor having a capacitance of 2. N-1 C, the capacitance value of the second highest capacitor is 2. N-2C, and so on, with the capacitance value of the least significant capacitor being 1C. However, in practical applications, the actual capacitance value of each capacitor may deviate from the ideal capacitance value. For example, the ideal capacitance value of the least significant capacitor may be 1C, while the actual capacitance value may be 0.8C, indicating a capacitance mismatch. Therefore, correcting the capacitance mismatch of the CDAC is particularly important. The most critical step is measuring the capacitance mismatch, which can be done by measuring the capacitance mismatch of each capacitor through a correction circuit.

[0064] The calibration loop includes an RDAC, a variable capacitor array, and a calibration control circuit. The output of the RDAC is coupled to the input of a comparator via the variable capacitor array. The output of the comparator is coupled to the input of the calibration control circuit. The output of the calibration control circuit is coupled to the input of the RDAC. The output of the calibration control circuit is coupled to the variable capacitor array. The output of the calibration control circuit is coupled to the input of the SAR control circuit. When the SAR ADC is in capacitor mismatch correction mode, capacitor mismatch detection can be performed first through the calibration loop.

[0065] During capacitor mismatch detection, the correction control circuit first generates a first control signal and sends it to the SAR control circuit. The SAR control circuit then controls the CDAC to output a first voltage (i.e., the mismatch voltage) based on the first control signal. This first voltage is associated with the capacitor mismatch amount of the CDAC. In one possible implementation, the SAR control circuit controls the switching of the capacitor array in the CDAC according to the first control signal, so that the CDAC outputs the first voltage. Furthermore, the SAR control circuit controls the switching of the capacitor under test in the capacitor array of the CDAC, as well as the switching of all low-order capacitors in the capacitor array whose median value is lower than that of the capacitor under test, to output the first voltage. This first voltage is associated with the mismatch amount of the capacitor under test, meaning it reflects the magnitude of the capacitor mismatch.

[0066] Specifically, the first control signal generated by the calibration control circuit is used to indicate the capacitor to be measured in the CDAC. After receiving the first control signal, the SAR control circuit can determine which capacitor in the CDAC is the capacitor to be measured, and generate a fourth control signal based on the first control signal and send it to the CDAC. The fourth control signal is used to control the switching of the capacitor to be measured and the switching of all lower-order capacitors with a lower number of bits. Therefore, after receiving the fourth control signal, the CDAC can switch the switching of the capacitor to be measured and the switching of all capacitors with a lower number of bits according to the fourth control signal, so that the CDAC outputs a first voltage corresponding to the capacitor to be measured. This first voltage reflects the capacitance mismatch of the capacitor to be measured.

[0067] For ease of understanding, the following is combined with Figure 3 , Figure 4 , Figure 5 and Figure 6 The capacitor switching process in the CDAC described above will be further explained. Figure 3 A schematic diagram of the capacitor switching state of the CDAC, as shown below. Figure 3 As shown, the capacitor under test is assumed to be the highest-order capacitor. At this time, the CDAC capacitors are in the normal power-on state, and the first switch of all capacitors (hereinafter referred to as the common terminal) is connected to the common-mode voltage V. CM The highest bit capacitor C of the CDAC MSB (Capacitance value is 2) N-1 The second switch (hereinafter referred to as the free end) of C) is grounded, and the remaining capacitors C MSB’ The second switch (hereinafter referred to as the free terminal) of (the equivalent capacitance of all remaining bits below the highest bit capacitance) is connected to the reference voltage V. DD In order to measure the highest bit capacitance C MSB The capacitance mismatch can change the state of the switch. Figure 4 Another schematic diagram of the capacitor switching state of the CDAC, as shown below. Figure 4 As shown, at this point, CDAC switches the capacitors based on the fourth control signal. Specifically, the common terminal of all capacitors is not connected to the common-mode voltage V. CM The highest bit capacitor C of the CDAC MSB The free end is connected to the reference voltage V DD The remaining capacitors C MSB’ Since the free end is grounded, a first voltage V is generated at the common end. RES The first voltage V RES The size of the value can reflect the capacitance mismatch of the highest-order capacitor.

[0068] Similarly, Figure 5 Another schematic diagram of the capacitor switching state of the CDAC, as shown below. Figure 5 As shown, the capacitor to be measured is the second highest capacitor. At this time, the CDAC capacitors are in the normal power-on state, and the common terminal of all capacitors is connected to the common-mode voltage V. CM The highest bit capacitor C of the CDAC MSB (Capacitance value is 2) N-1 C) and the second highest capacitor C MSB-1 (Capacitance value is 2) N-2 C) has its free end grounded, and the remaining terminals are capacitors C. MSB-1’ The free-terminal reference voltage V of (the equivalent capacitance of all remaining bits below the second-highest bit capacitance) DD In order to measure the second highest capacitance C MSB-1 The capacitance mismatch can change the state of the switch. Figure 6 Another schematic diagram of the capacitor switching state of the CDAC, as shown below. Figure 6As shown, at this point, CDAC switches the capacitors based on the fourth control signal. Specifically, the common terminal of all capacitors is not connected to the common-mode voltage V. CM The highest bit capacitor C of the CDAC MSB The free end remains unchanged, and the second highest capacitance C MSB-1 (Capacitance value is 2) N-2 C) Free-terminated reference voltage V DD The remaining capacitors C MSB-1’ Since the free end is grounded, a first voltage V is generated at the common end. RES-1 The first voltage V RES-1 The magnitude of this value reflects the capacitance mismatch of the second-highest capacitor. Similarly, if it is necessary to measure the capacitance mismatch of the remaining capacitors, the same operation as described above can be performed, which will not be repeated here.

[0069] Once the CDAC generates a first voltage corresponding to the capacitor under test, the capacitance value of the variable capacitor array can be adjusted. In one possible implementation, the calibration control circuit can generate a third control signal and send it to the variable capacitor array to control the variable capacitor array to adjust its capacitance value. Furthermore, the calibration control circuit includes a state machine that outputs the third control signal to control the variable capacitor array to adjust its capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor under test.

[0070] In practical applications, there are various ways to adjust the capacitance value of a variable capacitor array using a third control signal. The specific method depends on the structure of the variable capacitor array. In one possible implementation, the variable capacitor array includes multiple parallel capacitor branches, and each capacitor branch includes a capacitor and a switch connected in series. For ease of understanding, the following describes a combination of... Figure 7 The structure of the variable capacitor array will be described in detail. Figure 7 This is a schematic diagram of a variable capacitor array, as shown below. Figure 7As shown, the variable capacitor array consists of multiple capacitors connected in parallel. The capacitance value of each capacitor can be set according to actual needs, and no specific restrictions are imposed here. Each branch containing a capacitor has a switch, controlled by a third control signal generated by the calibration control circuit. When a switch is set to "1", it indicates that the corresponding capacitor is in the connected state; when the switch is set to "0", it indicates that the corresponding capacitor is out of the connected state. Therefore, by controlling the switching state of the capacitor branches, the total capacitance value of the variable capacitor array can be changed. Since one capacitance value corresponds to a fixed voltage range, the variable capacitor array provides a variable voltage range. When the capacitance of the variable capacitor array is large, it can provide a large voltage range, which provides a sufficiently large detection voltage to accurately measure the capacitance mismatch of the high-order capacitors in the DAC. When the capacitance of the variable capacitor array is small, it can provide a small voltage range. Because the voltage range is small, its accuracy is high, thus providing a sufficiently accurate detection voltage to accurately measure the capacitance mismatch of the low-order capacitors in the DAC.

[0071] Furthermore, the variable capacitor array can control the switching of switches in at least one capacitor branch according to a third control signal to adjust its own capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor under test. Specifically, the calibration control circuit can generate a third control signal and send it to the variable capacitor array so that the variable capacitor array adjusts its capacitance according to the third control signal. The third control signal contains information for adjusting the capacitance value of the variable capacitor array itself. It is worth noting that the calibration control circuit has a pre-set correspondence between the capacitance value of the variable capacitor array and the capacitance mismatch of the capacitor under test. For example, when the calibration control circuit determines that the capacitor under test is the highest-order capacitor (its corresponding capacitance mismatch is the largest), it can set the capacitance value of the variable capacitor array to the maximum value through the third control signal. When the calibration control circuit determines that the capacitor under test is a low-order capacitor (its corresponding capacitance mismatch is smaller), it can reduce the capacitance value of the variable capacitor array through the third control signal, and so on. After adjustment, the variable capacitor array can be equivalent to a capacitor with a fixed capacitance value. The calibration control circuit can charge the variable capacitor array through the RDAC. If the capacitance value of the variable capacitor array is large, the maximum voltage that the RDAC can generate on the variable capacitor array is also large, that is, it provides a large voltage range. If the capacitance value of the variable capacitor array is small, the maximum voltage that the RDAC can generate on the variable capacitor array is small, that is, it provides a small voltage range, but its accuracy is high. Therefore, after the variable capacitor array is adjusted by the calibration control circuit, it is equivalent to providing a voltage range. The calibration control circuit can select a certain second voltage (detection voltage) within this voltage range to detect the mismatch voltage corresponding to the capacitor under test, and thus determine the capacitance mismatch of the capacitor under test.

[0072] Once the capacitance value of the variable capacitor array is adjusted, the correction control circuit can generate a second control signal based on the comparison result output by the comparator, and send the second control signal to the RDAC, so that the RDAC outputs an analog voltage based on the second control signal, and charges the variable capacitor array based on the analog voltage to generate a second voltage on the variable capacitor array.

[0073] Specifically, when the variable capacitor array has just finished adjusting, the comparator's input is connected to the CDAC's output and the variable capacitor array. Therefore, the comparator's input signal is the difference between the mismatch voltage corresponding to the capacitor under test and the second voltage (at this time, since the RDAC has not yet received the second control signal, the variable capacitor array has not yet been charged, i.e., the second voltage is zero). Figure 2 V in X =|V RES The second voltage is determined by the comparator upon receiving the input signal. It compares the input signal to determine its sign and then sends the comparison result to the correction control circuit. The comparison result indicates that the difference between the mismatch voltage and the detection voltage is not zero (for example, a comparison result of 111111…11 or 000000…00 indicates that the difference between the two voltages is always greater than or never less than zero, thus indicating a certain difference from zero). The correction control circuit then generates a second control signal based on the comparison result, causing the RDAC to charge the variable capacitor array, generating a second voltage of a certain magnitude on the variable capacitor array. If the comparison result output by the comparator still indicates that the difference between the mismatch voltage and the detection voltage is not zero, the correction control circuit can continue to generate a second control signal based on the comparison result to adjust the magnitude of the second voltage on the variable capacitor array until the comparison result output by the comparator indicates that the difference between the mismatch voltage and the detection voltage is close to zero (for example, if the comparison result is 101010101010……10, it means that the difference between the two voltages is switching between greater than zero and less than zero, which can be considered as the difference being approximately equal to zero). Then the correction control circuit can determine that the magnitude of the second voltage is the magnitude of the first voltage. At this time, the second voltage reflects the capacitance mismatch of the capacitor under test, thus completing the capacitance mismatch detection of the capacitor under test.

[0074] It is worth noting that the second control signal includes codeword information for adjusting the RDAC and estimated information for the first voltage corresponding to the capacitor under test. Specifically, the codeword information of the RDAC is the voltage step size for charging the variable capacitor array. The RDAC can adjust the voltage of the variable capacitor array (i.e., the second voltage) as needed. For example, when detecting the first voltage corresponding to the highest-order capacitor, the voltage step size can be set to 0.1V, allowing the RDAC to adjust the voltage of the variable capacitor array with an accuracy of 0.1V. Similarly, when detecting the first voltage corresponding to the lowest-order capacitor, the voltage step size can be set to 0.01V, allowing the RDAC to adjust the voltage of the variable capacitor array with an accuracy of 0.01V. Therefore, the calibration control circuit can control the accuracy of adjusting the second voltage by adjusting the codeword information in the second control signal. Furthermore, the correction control circuit has pre-set estimated information for the mismatch voltage corresponding to each capacitor of the CDAC. For example, in the CDAC, the actual first voltage corresponding to the highest-order capacitor is 0.81V, and the actual first voltage corresponding to the lowest-order capacitor is 0.0088V. Therefore, the correction control circuit has corresponding estimated information: the estimated first voltage corresponding to the highest-order capacitor is 0.80V, and the estimated first voltage corresponding to the lowest-order capacitor is 0.0090V. Thus, by adjusting the estimated mismatch voltage information in the second control signal, the correction control circuit can adjust the magnitude of the second voltage generated by the RDAC on the variable capacitor array.

[0075] As in the example above, when the correction control circuit measures the first voltage corresponding to the highest-order capacitor, it generates a second control signal containing a codeword of 0.01V and an estimated first voltage (0.80V) for the highest-order capacitor. After receiving the second control signal, the RDAC adjusts the second voltage generated by the variable capacitor array with an accuracy of 0.01V until the second voltage is approximately 0.80V (e.g., fluctuating between 0.79V and 0.82V). At this point, the second voltage generated by the variable capacitor array is almost equal to the first voltage corresponding to the highest-order capacitor. The comparator receives the input signal consisting of the difference between the two voltages and compares them. It then outputs a comparison result to indicate to the correction control circuit that the difference between the two voltages is close to zero, meaning that the second voltage can correctly measure the first voltage corresponding to the highest-order capacitor. Based on this second voltage, the capacitance mismatch of the highest-order capacitor can be determined.

[0076] After determining the capacitance mismatch of the current capacitor under test, the detection of the capacitance mismatch of the next capacitor can proceed. At this point, the correction control circuit can control the RDAC to reset, thus putting the variable capacitor array in an uncharged state. Then, it controls the CDAC to output the first voltage corresponding to the next capacitor, adjusts the capacitance value of the variable capacitor array, and charges the adjusted variable capacitor array to generate a second voltage. The magnitude of the second voltage is adjusted through feedback, and the capacitance mismatch of the next capacitor is determined by the comparison result of the comparator. This process can be referred to the relevant content mentioned above, and will not be elaborated here. After determining the capacitance mismatch of each capacitor in the CDAC, the capacitance mismatch of each capacitor can be corrected step by step.

[0077] In the SAR ADC provided in this application embodiment, since the capacitance of the variable capacitor array is adjustable, a variable voltage range is provided. When the capacitance of the variable capacitor array is small, a smaller voltage range can be provided. Since the voltage range is small, its accuracy is high. Therefore, based on this voltage range, a detection voltage with sufficient accuracy can be provided to accurately measure the mismatch of the low-order capacitors in the CDAC.

[0078] The above is a detailed description of the SAR ADC provided in the embodiments of this application. The following will describe the mismatch voltage detection method provided in the embodiments of this application, which is applied to... Figure 1 The corresponding SAR ADC, the method includes:

[0079] S1: Generate the first control signal through the calibration control circuit;

[0080] S2: The SAR control circuit controls the CDAC to output a first voltage according to the first control signal;

[0081] S3: The comparator generates a comparison result based on the first voltage and the second voltage;

[0082] S4: The calibration control circuit generates a second control signal based on the comparison result;

[0083] S5: The RDAC outputs an analog voltage according to the second control signal and charges the variable capacitor array to generate the second voltage.

[0084] It should be noted that detailed explanations of steps S1 to S5 can be found in [reference needed]. Figure 1 The relevant explanatory sections in the corresponding embodiments will not be repeated here.

[0085] Optionally, the method further includes: generating a third control signal through a calibration control circuit to control the variable capacitor array to adjust the capacitance value.

[0086] Optionally, the correction control circuit includes: a state machine that generates a third control signal to control the variable capacitor array to adjust the capacitance value, including:

[0087] The state machine outputs a third control signal to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor under test.

[0088] Optionally, the variable capacitor array includes multiple parallel capacitor branches, and each capacitor branch includes a capacitor and a switch connected in series. Controlling the variable capacitor array to adjust the capacitance value includes:

[0089] The switches in at least one capacitor branch are switched by a variable capacitor array according to a third control signal.

[0090] Optionally, controlling the CDAC output of a first voltage according to the first control signal via the SAR control circuit includes:

[0091] The SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal in order to output the first voltage.

[0092] Optionally, the SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal to output a first voltage, including:

[0093] The SAR control circuit controls the switching of the capacitor under test in the capacitor array of the CDAC, as well as the switching of the low-order capacitors in the capacitor array whose median value is lower than that of the capacitor under test, to output a first voltage, which is related to the mismatch of the capacitor under test.

[0094] It should be noted that detailed descriptions of the various optional embodiments described above can be found in [reference needed]. Figure 1 The relevant explanatory sections in the corresponding embodiments will not be repeated here.

[0095] Furthermore, after completing the capacitor mismatch detection for each capacitor in the CDAC, capacitor mismatch correction can be performed on the CDAC. The capacitor mismatch correction process for the CDAC is as follows:

[0096] (1) Activate capacitor mismatch correction mode;

[0097] (2) Start the correction from the highest-order capacitor of the CDAC, control the switch of the CDAC to switch so that the output of the CDAC is the mismatch voltage corresponding to the highest-order capacitor;

[0098] (3) Control the capacitor switches of the variable capacitor array to switch, so as to control the capacitance of the variable capacitor array;

[0099] (4) Adjust the code word information of RDAC so that RDAC charges the variable capacitor array and generates a detection voltage;

[0100] (5) Read the comparison result of the comparator, adjust the magnitude of the detection voltage or perform capacitance mismatch detection for the next capacitor;

[0101] (6) Correct the capacitance mismatch of each CDAC capacitor sequentially from the high bit to the low bit.

[0102] This application also relates to a communication chip, which can be, for example, an information transceiver chip in an optical communication system, or a data acquisition chip in a medical imaging system, an industrial process control system, etc. The communication chip includes: an antenna, a radio frequency front-end, a digital processing circuit, and an interface... Figure 1 The corresponding SAR ADC.

[0103] The system includes: an antenna for receiving analog signals; an RF front-end for down-converting the analog signals; a SAR ADC for converting the down-converted analog signals to digital signals; and a digital processing circuit for encoding and decoding the digital signals.

[0104] In the aforementioned chip, the SAR ADC includes a main circuit for analog-to-digital conversion and a correction circuit for capacitor mismatch correction. The correction circuit has an adjustable variable capacitor array, which can accurately measure the mismatch of the low-order capacitor of the CDAC in the main circuit and realize capacitor mismatch correction. This can effectively improve the performance of the communication chip to meet the higher requirements of practical applications.

Claims

1. A successive approximation analog-to-digital converter, characterized by, include: Capacitor-to-Digital Converter (CDAC); The successive approximation SAR control circuit is used to control the capacitor array in the CDAC to switch on and off according to the first control signal in order to output the first voltage; A variable capacitor array is used to provide a second voltage; A comparator is used to generate a comparison result based on the first voltage and the second voltage; A calibration control circuit is used to generate the first control signal and generate a second control signal based on the comparison result; A resistor-to-digital converter (RDAC) is used to output an analog voltage according to the second control signal and charge the variable capacitor array to generate the second voltage; The capacitance value of the variable capacitor array is adjustable.

2. The successive approximation analog-to-digital converter of claim 1, wherein, The correction control circuit is also used to generate a third control signal to control the variable capacitor array to adjust the capacitance value.

3. The successive approximation analog-to-digital converter of claim 2, wherein, The correction control circuit includes a state machine, which outputs the third control signal to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor to be measured.

4. A successive approximation analog-to-digital converter according to claim 2 or 3, characterized in that, The variable capacitor array includes multiple parallel capacitor branches, and each capacitor branch includes a capacitor and a switch connected in series.

5. The successive approximation analog-to-digital converter of claim 4, wherein, The variable capacitor array is used to control the switching of at least one switch in the capacitor branch according to the third control signal.

6. The successive approximation analog-to-digital converter of claim 5, wherein, The SAR control circuit is used to control the switching of the capacitor under test in the capacitor array of the CDAC, and to switch the switching of the low-order capacitors in the capacitor array whose median value is lower than that of the capacitor under test, so as to output the first voltage, which is associated with the mismatch of the capacitor under test.

7. A method of mismatch voltage detection, the method comprising: An application is made to a successive approximation analog-to-digital converter (ADC), the successive approximation ADC comprising: a CDAC, a comparator, a SAR control circuit, an RDAC, a variable capacitor array, and a correction control circuit, wherein the capacitance value of the variable capacitor array is adjustable, and the method includes: The first control signal is generated by the correction control circuit; The SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal in order to output the first voltage; The comparator generates a comparison result based on the first voltage and the second voltage. The correction control circuit generates a second control signal based on the comparison result. The RDAC outputs an analog voltage according to the second control signal and charges the variable capacitor array to generate the second voltage.

8. The method of claim 7, wherein, The method further includes generating a third control signal through the correction control circuit to control the variable capacitor array to adjust the capacitance value.

9. The method of claim 8, wherein, The correction control circuit includes a state machine, and the step of generating a third control signal through the correction control circuit to control the variable capacitor array to adjust the capacitance value includes: The state machine outputs the third control signal to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch of the capacitor to be measured.

10. The method according to claim 8 or 9, characterized in that, The variable capacitor array includes multiple parallel capacitor branches, and each capacitor branch includes a capacitor and a switch connected in series. Controlling the variable capacitor array to adjust the capacitance value includes: The variable capacitor array controls the switching of at least one switch in the capacitor branch according to the third control signal.

11. The method of claim 10, wherein, The step of controlling the capacitor array in the CDAC to switch on and off according to the first control signal via the SAR control circuit to output the first voltage includes: The SAR control circuit controls the switching of the capacitor under test in the capacitor array of the CDAC, as well as the switching of the low-order capacitors in the capacitor array whose median value is lower than that of the capacitor under test, to output the first voltage, which is associated with the mismatch of the capacitor under test.

12. A communication chip, comprising: Includes an antenna, a radio frequency front-end, digital processing circuitry, and a successive approximation analog-to-digital converter as described in any one of claims 1 to 6; The antenna is used to receive analog signals; The radio frequency front end is used to down-frequency the analog signal to obtain a down-frequency analog signal; The successive approximation analog-to-digital converter is used to perform analog-to-digital conversion on the down-frequency analog signal to obtain a digital signal. The digital processing circuit is used to encode and decode the digital signal.

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