In-die clock network delay test method and test circuit

Abstract

The application relates to a chip clock network delay test method and a test circuit, and relates to integrated circuit technology. The test method comprises the following steps: 1) a clock management circuit module in a chip provides a control clock signal and N test clock signals, the phases of the test clock signals are the same, and N is an integer greater than 2; 2) N test branches are constructed, each test branch comprises a clock network path and a flip-flop connected to the clock network path, and the test branches and the test clock signals are one-to-one corresponding; 3) the control clock signal is connected to the flip-flop area in the chip through the same path, and then is branched to each flip-flop, so that the control clock signal is used as the control clock of each flip-flop; 4) the phase of the control clock signal is adjusted in a waveform sliding mode through the clock management circuit module, and the output of each flip-flop is recorded; and 5) the phase difference of the output signals of the flip-flops is used to judge the delay difference between the test branches. The application has low test cost and high precision.

Description

Technical Field

[0001] This invention relates to integrated circuit technology, and particularly to integrated circuit testing technology. Background Technology

[0002] FPGA (Field-Programmable Logic Array) devices contain complex clock networks, through which clock signals are transmitted from the transmitting circuit to the receiving circuit. The varying signal transmission delays of different clock network paths affect the timing relationships of the internal logic circuits. Furthermore, the signal transmission delay parameters of the clock network are related to factors such as power supply voltage, chip junction temperature, and chip manufacturing process. Therefore, research on testing methods for clock network delay parameters has significant engineering value.

[0003] Traditional clock network delay parameter testing selects certain I / O interfaces of the FPGA chip under test as signal input and output terminals. Then, an oscilloscope or other test equipment is used to measure the timing delay between the input and output signals, and the signal transmission delay of the signal transmission channel on the test board is subtracted. This testing method is highly dependent on the test ports, has low testing flexibility, and is easily affected by external test conditions. Especially for certain special clock network paths within the FPGA chip, it is difficult to test them through I / O input / output ports. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a test technology for FPGA on-chip clock network that does not rely on dedicated test instruments and equipment, including on-chip clock network delay test method and on-chip clock network delay test circuit.

[0005] The technical solution adopted by the present invention to solve the aforementioned technical problem is an on-chip clock network delay testing method, characterized by comprising the following steps:

[0006] 1) The internal clock management circuit module of the chip provides control clock signals and N test clock signals. The phase of each test clock signal is the same, and N is an integer greater than 2.

[0007] 2) Construct N test branches, each test branch including a clock network path and a flip-flop connected to it, and the test branches and test clock signals are connected in a one-to-one correspondence;

[0008] 3) The control clock signal is connected to the on-chip flip-flop area through the same path, and then split to each flip-flop, so that the control clock signal is used as the control clock for each flip-flop;

[0009] 4) The phase of the control clock signal is adjusted by waveform sliding through the clock management circuit module, and the output of each flip-flop is recorded;

[0010] 5) Determine the time delay difference between each test branch by measuring the phase difference of the output signals of each trigger.

[0011] In step 4), after the clock management circuit module outputs the control clock signal for the first time, the phase of each output control clock signal is delayed by a preset time unit compared to the phase of the previous output control clock signal.

[0012] The frequency of the control clock signal is an even multiple of the frequency of the test clock signal.

[0013] The on-chip clock network delay test circuit provided by the present invention includes a clock management circuit module, a control clock signal branch and N test branches. Each test branch includes a clock network path and a flip-flop connected thereto. The output of each flip-flop is connected to a control / storage module, and the control / storage module is connected to an external output interface.

[0014] The control / storage module is connected to the clock management circuit module;

[0015] The test clock signal port of the clock management circuit module is connected to the sampling signal input terminal of the trigger of each test branch through the clock network path in each test branch;

[0016] The control clock signal port of the clock management circuit module is connected to the clock terminals of each flip-flop through the control clock signal branch.

[0017] Furthermore, the control / storage module includes a phase shift control module, which generates signals with progressively increasing durations between adjacent trigger points. The trigger point refers to a characteristic point in the signal that serves as a trigger, such as a rising edge or a falling edge.

[0018] The testing method of the present invention has a simple working principle, is easy to apply, has low testing cost, and high testing accuracy (accuracy can reach 25ps). Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the built-in test architecture for signal transmission delay of the clock network of the present invention.

[0020] Figure 2 This is an example diagram showing the initial phase relationship of each output clock of the clock management circuit module at the source end.

[0021] Figure 3 This is an example diagram showing the phase relationship of each output clock of the clock management circuit module after reaching the flip-flop through different clock networks.

[0022] Figure 4 This is a diagram showing the address allocation of the storage section of the control / storage module.

[0023] Figure 5 This is a schematic diagram of Example 1.

[0024] Figure 6 This is a schematic diagram of Example 2. Detailed Implementation

[0025] This invention proposes a method for testing the signal transmission delay parameters of a clock network based on built-in chip testing. Since chip testing involves numerous stages, the testing method described in this invention is primarily applicable to board-level testing of finished chips. That is, without relying on dedicated testing equipment, the clock network is tested using the internal functional circuitry of an FPGA chip, and the raw test data is uploaded to a computer for later data statistics and analysis.

[0026] This invention combines the clock management module with dynamic phase shift adjustment function inside the FPGA chip with the clock network under test. Through the built-in test method, the signal transmission delay test of some internal clock networks of the chip can be realized.

[0027] The on-chip clock network delay testing method of the present invention includes the following steps:

[0028] 1) The internal clock management circuit module of the chip provides control clock signals and N test clock signals. The phase of each test clock signal is the same, and N is an integer greater than 2.

[0029] 2) Construct N test branches, each test branch including a clock network path and a flip-flop connected to it, and the test branches and test clock signals are connected in a one-to-one correspondence;

[0030] 3) The control clock signal is connected to the on-chip flip-flop area through the same path, and then split to each flip-flop, so that the control clock signal is used as the control clock for each flip-flop;

[0031] 4) The phase of the control clock signal is adjusted by waveform sliding through the clock management circuit module, and the output of each flip-flop is recorded;

[0032] 5) Determine the time delay difference between each test branch by measuring the phase difference of the output signals of each trigger.

[0033] In step 4), after the clock management circuit module outputs the control clock signal for the first time, the phase of each output control clock signal is delayed by a preset time unit compared to the phase of the previous output control clock signal.

[0034] The frequency of the control clock signal is an even multiple of the frequency of the test clock signal.

[0035] The on-chip clock network delay test circuit includes a clock management circuit module 100, a control clock signal branch 105, and N test branches. Each test branch includes a clock network path and a flip-flop connected to it. The output of each flip-flop is connected to the control / storage module, and the control / storage module is connected to the external output interface. Figure 1 The case with 4 test branches is shown as 101, 102, 103 and 104 respectively.

[0036] The control / storage module is connected to the clock management circuit module;

[0037] The test clock signal port of the clock management circuit module is connected to the sampling signal input terminal of the trigger of each test branch through the clock network path in each test branch;

[0038] The control clock signal port of the clock management circuit module is connected to the clock terminals of each flip-flop through the control clock signal branch.

[0039] The control / storage module includes a phase-shift control module, which generates signals with progressively increasing durations between adjacent trigger points. A trigger point refers to a characteristic point in the signal that triggers the output, such as a rising or falling edge. The clock management circuit module uses these trigger points as the trigger signals for outputting the phase-shifted clock.

[0040] Specifically, the testing system, such as Figure 1 As shown, the FPGA chip under test is mounted on a board-level test board and connected to a PC via a JTAG interface. The board-level test board provides the FPGA chip under test with power supply, clock signal source, power-on reset, and other peripheral functional circuits.

[0041] The core of the built-in test circuit of the clock network mainly includes the clock management circuit module, each clock network path, flip-flops, and the built-in test data storage module.

[0042] The main function of the clock management circuit module is to output multiple clock signals, taking 5 output clocks as an example; clock network paths NO.1~5 are different clock network paths; flip-flops are used to sample the logic state of the clock network signals; the built-in test control and storage module is used to control the working state of the clock management circuit module, store the logic level collected by the flip-flops, and upload the collected test data under the control of the PC computer.

[0043] The clock management circuit module can have multiple output clocks. Output clock 5 operates in a dynamic phase-shift state, meaning its phase relative to output clocks 1-4 can be dynamically adjusted; while the phases of output clocks 1-4 are fixed. For ease of later data analysis, the frequency (fclk) and duty cycle of output clocks 1-4 are preferably set to the same value. The frequency (fs) of output clock 5 can be equal to fclk or an even multiple of fclk.

[0044] like Figure 2 As shown, taking output clocks 1-5 as an example where the output frequencies are the same and the duty cycle is 50%, the relative phase relationship of each output clock at the source end remains consistent after the clock management circuit module is reset and stabilized.

[0045] Because clock network paths NO.1 to NO.4 are different, their signal transmission delay characteristics differ. If the signal transmission delay of clock network path NO.2 is greater than that of path NO.1, let the difference in transmission delay be ΔT21. Since output clocks 1 and 2 have the same phase at the source, the relative phases change when the clock signals output by the clock management circuit unit reach the inputs of flip-flops 1 and 2 respectively. The D input signal of flip-flop 2 lags behind that of flip-flop 1.

[0046] Because the frequencies of output clock 5 and output clocks 1-4 are divided by an equal or even multiple, the output logic of the flip-flop is fixed for any single sampling clock trigger edge (Note: this excludes cases where the sampling clock edge and the input signal edge of flip-flop D occur adjacently, in which case the output logic of the flip-flop is random). Therefore, using this testing method, the frequency setting of output clock 5 is more flexible, allowing for frequency division to a lower range to suit the operating frequency range of the logic and memory circuits of the FPGA chip under test.

[0047] Based on this, the phase of output clock 5 relative to output clocks 1-4 can be dynamically and continuously adjusted, such as... Figure 3 As shown, each phase adjustment step corresponds to the phase delay of Ts, and the value of Ts is a known parameter that can be configured through the built-in test control program.

[0048] Flip-flops 1-4 can be used to obtain the logic level of each clock network under test under each phase condition, and the data can be stored in the corresponding memory address in the data storage circuit inside the FPGA chip under test. For example... Figure 4 As shown, the data is then transferred to a PC via JTAG or another data bus interface, which allows the data to be recovered as shown. Figure 3 The phase relationship between the D input signals of flip-flops 1-4 is shown. Figure 3For example, the D input signals of flip-flops 1 and 2 differ by 3 phase adjustment steps, or 3 × Ts. That is, the measured value of the signal transmission delay between clock network paths No. 1 and 2 is 3 × Ts. Example

[0049] like Figure 5 As shown, the clock networks under test 1-4 are all BUFH horizontal clock networks within the FPGA chip (the FPGA's internal space can be divided into multiple clock domains based on different physical locations, and the paths of the BUFH horizontal clock networks are only distributed within their corresponding clock domains. Theoretically, the design goal of the BUFH horizontal clock network is to ensure that the signal transmission delay of all BUFH horizontal clock networks within the same clock domain to the same load circuit is equivalent). Using the architecture of this embodiment, the difference in signal transmission delay between different BUFH horizontal clock networks within the same clock domain can be tested. Example

[0050] like Figure 6 As shown, the clock networks under test 1 and 2 are the BUFH horizontal clock network and a BUFG global clock network inside the FPGA chip under test, respectively. The BUFG global clock network has a longer signal transmission path and a greater signal transmission delay. This test architecture allows us to obtain the difference in signal transmission delay between the BUFH and BUFG clock network paths.

[0051] MMCM: Clock Management Circuit Module

[0052] BUFH: Horizontal Clock Network

[0053] FDCE: Trigger

[0054] Detect: Detector

[0055] BRAM: Data Memory

[0056] The instructions and accompanying drawings clearly illustrate the principles and working process of this invention, enabling those skilled in the art to implement it. The clock management circuit module, control / storage module, and other functional modules are internal FPGA modules, which are readily understood by those skilled in the art; their specific structures will not be elaborated further.

Claims

1. A method for testing the latency of an on-chip clock network, characterized in that, Includes the following steps: 1) The internal clock management circuit module of the chip provides control clock signals and N test clock signals. The phase of each test clock signal is the same, and N is an integer greater than 2. 2) Construct N test branches, each test branch including a clock network path and a flip-flop connected to it, and the test branches and test clock signals are connected in a one-to-one correspondence; 3) The control clock signal is connected to the on-chip flip-flop area through the same path, and then split to each flip-flop, so that the control clock signal is used as the control clock for each flip-flop; 4) The phase of the control clock signal is adjusted by waveform sliding through the clock management circuit module, and the output of each flip-flop is recorded; 5) Determine the time delay difference between each test branch by measuring the phase difference of the output signals of each trigger.

2. The on-chip clock network delay testing method as described in claim 1, characterized in that, In step 4), after the clock management circuit module outputs the control clock signal for the first time, the phase of each output control clock signal is delayed by a preset time unit compared to the phase of the previous output control clock signal.

3. The on-chip clock network delay testing method as described in claim 1, characterized in that, The frequency of the control clock signal is an even multiple of the frequency of the test clock signal.

4. An on-chip clock network delay test circuit, characterized in that, It includes a clock management circuit module, a control clock signal branch, and N test branches. Each test branch includes a clock network path and a flip-flop connected to it. The output of each flip-flop is connected to the control and storage module, and the control and storage module is connected to the external output interface. The control and storage module is connected to the clock management circuit module; The test clock signal port of the clock management circuit module is connected to the sampling signal input terminal of the trigger of each test branch through the clock network path in each test branch; The control clock signal port of the clock management circuit module is connected to the clock terminals of each flip-flop through the control clock signal branch; the control and storage module stores the logic level of each clock network under test under each phase condition, and then transmits the data to the PC computer to recover the phase relationship between the D input signals of the flip-flops in each test branch, and obtains the signal transmission delay value through the phase relationship.

5. The on-chip clock network delay test circuit as described in claim 4, characterized in that, The control and storage module includes a phase shift control module, which generates signals with equally increasing durations between two adjacent trigger points.

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