A method for preparing a solder for bump structure eutectic bonding

Abstract

The present application relates to a method for preparing solder for eutectic bonding of protruding structures, which can selectively form solder on the bonding surface of the protruding structures by electroplating, while the sidewalls of the protruding structures are wrapped with a non-conductive parylene layer, so that metal solder is prevented from forming on the sidewalls of the protruding structures during electroplating.

Description

Technical Field

[0001] This invention relates to the field of microelectronic processing, and more specifically to a method for preparing solder for eutectic bonding of protrusion structures. Background Technology

[0002] In the field of electronic devices, it is often necessary to bond wafers with raised structures to another substrate. Currently, the main bonding processes include silicon-silicon bonding, anodic bonding, and eutectic bonding. However, silicon-silicon bonding requires high temperatures, resulting in significant thermal stress on the surface of the bonded wafer, which affects the bonding quality. Anodic bonding requires high surface quality and high pressure, making it prone to stress problems. Eutectic bonding, due to its lower temperature requirements, has become the more commonly used bonding method.

[0003] However, when the adhesion layer and seed layer of eutectic bonding solder are prepared on the top of the protrusion structure of the wafer, metal will also be sputtered on the sidewall of the protrusion structure. This will cause metal solder to grow on the sidewall when the metal solder is formed by electroplating, which will result in a smaller spacing between adjacent protrusion structures, or even a connection between the sidewalls of adjacent protrusion structures.

[0004] Therefore, there is a need to develop a method for preparing solder for eutectic bonding of protrusion structures that can avoid the formation of metallic solder on the sidewalls of the protrusion structure. Summary of the Invention

[0005] The purpose of this invention is to provide a method for preparing solder for eutectic bonding of raised structures. This method can selectively form solder on the bonding surface of the raised structure by electroplating. Since the sidewalls of the raised structure are covered with a non-conductive parylene layer, the formation of metal solder on the sidewalls of the raised structure can be avoided during electroplating.

[0006] To achieve the above objectives, the present invention provides the following technical solution.

[0007] A method for preparing a solder for eutectic bonding, comprising:

[0008] A substrate is provided, the substrate having a protrusion structure, the top surface of the protrusion structure being a bonding surface;

[0009] An adhesive layer is formed to cover the protruding structure;

[0010] A seed layer and a parylene layer are sequentially formed on the adhesion layer;

[0011] Removing a portion of the parylene layer from the bonding surface, thereby exposing a portion of the seed layer and forming a window; and

[0012] Solder is formed at the window by electroplating.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] 1. The present invention provides a method for preparing solder for eutectic bonding of protruding structures. The method can selectively form solder on the bonding surface of the protruding structure by electroplating. Since the sidewall of the protruding structure is covered with a non-conductive parylene layer, the formation of metal solder on the sidewall of the protruding structure can be avoided during electroplating.

[0015] 2. This invention forms an adhesion layer and a seed layer through sputtering or ion beam evaporation, enabling the seed layer and adhesion layer to cover the raised structure and the entire substrate surface where the raised structure is located, thus making it possible to form solder on all bonding surfaces. Existing technology involves first sputtering a metal adhesion layer and a seed layer across the entire wafer surface, then etching away the metal in areas where solder growth is not desired, followed by etching the raised structure in these areas, and finally electroplating to grow solder. While this method avoids solder growth on the sidewalls of the raised structure, the formation of island structures in some areas after etching prevents electrons from reaching the metal seed layer on these island structures, thus preventing solder deposition in those areas during electroplating.

[0016] 3. The present invention forms a metal barrier layer on the sidewall of the protruding structure. Since the metal barrier layer has poor affinity with the molten metal solder, it solves the problem of the molten metal solder spreading along the area with metal on the sidewall of the protruding structure during the metal eutectic welding process, avoids the loss of metal solder in the eutectic bonding area, and improves the bonding effect; at the same time, it prevents the molten metal solder from flowing into the gap between the protruding structures (e.g., into the microchannel) and causing blockage. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0018] Figure 1-10 This is a partial structural diagram of the structure obtained in each step of the preparation method provided in the embodiments of the present invention.

[0019] Explanation of reference numerals in the attached figures

[0020] 100 is the silicon wafer, 200 is the microchannel, 201 is the spacer, 202 is the bonding surface, 300 is the adhesion layer, 400 is the seed layer, 500 is the metal barrier layer, 600 is the parylene layer, 700 is the solder, 800 is the cover plate, and 900 is the metal layer. Detailed Implementation

[0021] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0023] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0024] Because existing techniques for preparing the adhesion layer and seed layer of eutectic bonding solder on the top of a protruding structure also sputter metal onto the sidewalls of the protruding structure, metal solder also grows on the sidewalls during electroplating to form metal solder. To avoid the formation of metal solder on the sidewalls of the protruding structure, this invention provides an improved method for preparing solder for eutectic bonding, comprising the following steps.

[0025] First, a substrate is provided, the substrate having a raised structure, the top surface of the raised structure being a bonding surface.

[0026] The substrate of this invention can be a silicon wafer, a silicon-on-insulator wafer, a germanium-silicon wafer, a germanium wafer, a gallium nitride wafer, a SiC wafer, a quartz wafer, or a sapphire wafer. This invention does not impose any particular limitations on the substrate; any conventional substrate suitable for microfabrication processes can be used.

[0027] In some embodiments, a plurality of protrusions are provided on one surface of the substrate (e.g., the upper or lower surface). In other embodiments, a plurality of protrusions are provided on both the upper and lower surfaces of the substrate.

[0028] Preferably, the substrate and the protrusion structure are integrally formed.

[0029] In some embodiments, a method for fabricating a substrate with raised structures includes: providing an initial substrate; and photolithography and etching the initial substrate to obtain the substrate having the raised structures. The initial substrate may be a silicon wafer, a silicon-on-insulator wafer, a germanium-silicon wafer, a germanium wafer, a gallium nitride wafer, a SiC wafer, a quartz wafer, or a sapphire wafer. This invention does not impose any particular limitation on the initial substrate; any conventional substrate suitable for microfabrication processes can be used.

[0030] In some embodiments, the substrate with the raised structure is a substrate with embedded microchannels. The spacers of the embedded microchannels are raised structures, and the top surface of the spacers is a bonding surface. This substrate is commonly used in the heat dissipation field of electronic devices. In some specific embodiments, the method for fabricating a substrate with embedded microchannels includes: providing an initial substrate, and forming embedded microchannels on the initial substrate by photolithography and etching.

[0031] Then, an adhesive layer is formed to cover the raised structure.

[0032] Preferably, the adhesion layer is formed by magnetron sputtering or ion beam evaporation.

[0033] Preferably, the adhesive layer is a metal with good interlayer adhesion, such as titanium or chromium.

[0034] The thickness of the adhesion layer can be 10-1000nm (determined by the solder thickness; a thicker adhesion layer can be selected when the solder thickness is thicker). For example, when the solder thickness is 10-20μm (the thickness of the solder is related to the type of metal in the eutectic bonding), the thickness of the adhesion layer can be 20-200nm.

[0035] Subsequently, a seed layer and a parylene layer are formed sequentially on the adhesion layer.

[0036] Preferably, the seed layer is a metal with good conductivity, such as copper or gold. The thickness of the seed layer can be 100-1000 nm (determined by the solder thickness; a thicker seed layer can be selected when the solder thickness is thicker). For example, when the solder thickness is 10-20 μm, the thickness of the seed layer can be 100-300 nm.

[0037] Preferably, the thickness of the parylene layer is 1-10 μm (determined by the size of the protrusion structure; for example, the higher the height of the protrusion structure, the greater the thickness of the parylene layer).

[0038] Preferably, the seed layer is formed by sputtering or ion beam evaporation. The present invention forms an adhesion layer and a seed layer across the entire surface by sputtering or ion beam evaporation, enabling the seed layer and adhesion layer to cover the protrusion structure and the entire substrate surface where the protrusion structure is located, thereby making it possible to form solder on all bonding surfaces.

[0039] Preferably, the parylene layer is formed by chemical vapor deposition (CVD). The CVD includes plasma-enhanced CVD.

[0040] Next, the portion of the parylene layer on the bonding surface is removed, thereby exposing a portion of the seed layer and forming a window.

[0041] Preferably, the parylene layer portion on the bonded surface is removed by chemical mechanical polishing.

[0042] Preferably, a metal barrier layer is formed on the seed layer after the seed layer is formed and before the parylene layer is formed.

[0043] The metal barrier layer of the present invention is a metal with high hardness that does not chemically react with the polishing slurry used for chemical mechanical polishing. Preferably, the metal barrier layer is a metal such as aluminum or tantalum that does not readily react with the corresponding polishing slurry.

[0044] Preferably, the thickness of the metal barrier layer is 100-1000 nm (the thickness of the metal barrier layer is related to the type of metal in the metal barrier layer).

[0045] Preferably, the metal barrier layer is formed by sputtering or ion beam evaporation.

[0046] When the metal barrier layer is formed on the seed layer, in order to expose the seed layer on the bonding surface of the protruding structure, it is necessary to remove the portion of the metal barrier layer on the bonding surface after removing the portion of the parylene layer on the bonding surface, thereby exposing part of the seed layer and forming a window. Preferably, an etchant is used to remove the portion of the metal barrier layer on the bonding surface. The etchant only reacts chemically with the metal barrier layer and not with the seed layer. Preferably, the etchant is an aluminum etchant or a tantalum etchant, including but not limited to hydrochloric acid, nitric acid, phosphoric acid, sulfuric acid, or mixtures thereof.

[0047] This invention forms a metal barrier layer on the seed layer located on the sidewall of the protruding structure. Because the metal barrier layer has poor affinity with molten metal solder, it solves the problem of molten metal solder spreading along the metal-bearing areas on the sidewall of the protruding structure during eutectic bonding, preventing solder loss from the eutectic bonding region and improving the bonding effect. Simultaneously, it prevents molten metal solder from flowing into the gaps between the protruding structures (e.g., into microchannels), causing blockage. This invention's method, by setting the metal barrier layer, can control the flow area of ​​the molten metal solder, resulting in better reliability and easier application in practical engineering.

[0048] Finally, solder is formed at the window by electroplating.

[0049] Preferably, the solder comprises one or more metal layers. Each metal layer is formed by electroplating or electron beam evaporation, and may be Cu, Sn, Pb, In, Au, Ag, or Sb. Preferably, the solder comprises multiple (e.g., 2-3) metal layers, and the metal layers are not identical to each other. Of course, the solder may include other metal layers suitable for eutectic bonding.

[0050] This invention uses an electroplating process to prepare solder, which, compared to other processes such as sputtering or evaporation, can form a thicker metallic solder. Preferably, the thickness of the solder is 10-20 μm.

[0051] During electroplating, the non-conductive parylene layer coating the sidewalls of the raised structure prevents the formation of metal solder on the sidewalls. In particular, when the substrate is a substrate with embedded microchannels, solder does not form on the inner walls of the microchannels, resulting in a larger flow rate and better heat dissipation during operation.

[0052] After the solder is formed, the remaining parylene layer can be removed depending on the actual application requirements. For example, when the substrate is a substrate with embedded microchannels, the low porosity of the parylene layer can prevent leakage of the cooling medium during microchannel operation, but the disadvantage is that it is difficult to withstand high-temperature processes.

[0053] In some embodiments, after the solder is formed, the remaining parylene layer is removed. Preferably, the remaining parylene layer can be removed by dry etching. The dry etching includes oxygen plasma etching.

[0054] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0055] Example 1

[0056] First, a silicon wafer 100 is provided. Then, microchannels 200 are formed on the upper surface of the silicon wafer 100 by photolithography and etching. A partial structural diagram of the resulting structure is shown below. Figure 1 As shown, 201 is the partition wall of the microchannel 200, and 202 is the bonding surface on the top of the partition wall 201.

[0057] Then, an adhesion layer 300 is formed by sputtering to cover the bonding surface 202 and the inner wall of the microchannel 200, wherein the adhesion layer 300 is titanium and has a thickness of 100 nanometers.

[0058] Subsequently, a seed layer 400 is formed on the upper surface of the adhesion layer 300 by sputtering. A partial structural diagram of the resulting structure is shown below. Figure 2 As shown, the seed layer 400 is made of gold and has a thickness of 200 nanometers.

[0059] Next, a metal barrier layer 500 is formed on the upper surface of the seed layer 400 by sputtering. A partial structural diagram of the resulting structure is shown below. Figure 3 As shown, the metal barrier layer 500 is made of aluminum and has a thickness of 200 nanometers.

[0060] Then, a parylene layer 600 is formed on the upper surface of the metal barrier layer 500 by plasma-enhanced chemical vapor deposition. A partial structural schematic diagram of the resulting structure is shown below. Figure 4 As shown, the thickness of the parylene 600 layer is 5 micrometers.

[0061] Subsequently, a portion of the parylene layer 600 on the bonding surface 202 is removed by chemical mechanical polishing, thereby exposing the metal barrier layer 500 on the bonding surface 202. A partial structural diagram of the resulting structure is shown below. Figure 5 As shown.

[0062] Next, the exposed metal barrier layer 500 is removed using an aluminum etching solution, thereby exposing part of the seed layer 400 and forming a window. A partial structural diagram of the resulting structure is shown below. Figure 6 As shown. Since the metal barrier layer 500 is very thin, after removing the exposed portion of the metal barrier layer 500, the seed layer 400 and the top surface of the parylene layer 600 can be considered to be on the same horizontal plane.

[0063] Then, solder 700 is formed at the window by electroplating, and a partial structural schematic diagram of the resulting structure is shown below. Figure 7 As shown, solder 700 is Sn with a thickness of 10 micrometers.

[0064] Subsequently, the remaining parylene layer 600 was removed by oxygen plasma etching, and a partial structural diagram of the resulting structure is shown below. Figure 8 As shown.

[0065] Next, a cover plate 800 is provided, and an adhesion layer 300 is formed on its lower surface by sputtering. Then, a 3-micrometer-thick Ni layer, a 1-micrometer-thick Au layer, and a 10-micrometer-thick Sn layer are sequentially formed from top to bottom on the lower surface of the adhesion layer 300 by electroplating. These three layers are collectively referred to as the metal layer 900. A partial structural schematic diagram of the resulting structure is shown below. Figure 9 As shown.

[0066] Finally, at a temperature above the solder melting point, in a nitrogen atmosphere, pressure is applied to... Figure 8 The structure shown and as Figure 9 The structure shown is bonded, and a partial structural diagram of the resulting structure is shown below. Figure 10 As shown. Because the inner wall of the microchannel 200 is wrapped with a metal barrier layer 500, the molten metal solder 700 during eutectic bonding will not flow into the interior of the microchannel 200.

[0067] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for preparing solder for eutectic bonding, characterized in that, include: A substrate is provided, the substrate having a protrusion structure, the top surface of the protrusion structure being a bonding surface; An adhesive layer is formed to cover the protruding structure; A seed layer and a parylene layer are sequentially formed on the adhesion layer; after the formation of the seed layer and before the formation of the parylene layer, a metal barrier layer is formed on the seed layer; the metal barrier layer is aluminum or tantalum; the thickness of the parylene layer is 1~10 μm; Removing a portion of the parylene layer from the bonding surface, removing a portion of the metal barrier layer from the bonding surface, thereby exposing a portion of the seed layer to form a window; and Solder is formed at the window by electroplating, and the solder is Cu, Sn, Pb, In, Au, Ag or Sb; After the solder is formed, the remaining parylene layer is removed.

2. The preparation method according to claim 1, characterized in that, The adhesion layer and the seed layer are formed by magnetron sputtering or ion beam evaporation processes.

3. The preparation method according to claim 1, characterized in that, The metal barrier layer is formed by sputtering or ion beam evaporation; The metal barrier layer is removed using an etchant.

4. The preparation method according to claim 1 or 2, characterized in that, The parylene layer was formed by chemical vapor deposition.

5. The preparation method according to claim 1 or 2, characterized in that, The parylene layer on the bonded surface is removed by chemical mechanical polishing.

6. The preparation method according to claim 1, characterized in that, The remaining parylene layer was removed by dry etching.

7. The preparation method according to claim 1 or 2, characterized in that, The method for fabricating the substrate having the protrusion structure includes: providing an initial substrate; and photolithography and etching the initial substrate to obtain the substrate having the protrusion structure.

8. The preparation method according to claim 1 or 2, characterized in that, The adhesive layer is made of titanium or chromium; The seed layer is made of copper or gold; The substrate is a silicon wafer, a silicon-on-insulator wafer, a germanium-silicon wafer, a germanium wafer, a gallium nitride wafer, a SiC wafer, a quartz wafer, or a sapphire wafer.

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