Gray area prevention circuit with indirect signal monitoring

Abstract

The present disclosure relates to a gray zone prevention circuit with indirect signal monitoring. For example, a gray zone prevention circuit includes a first gain stage circuit including a first input terminal and a first output terminal, the first gain stage circuit amplifying a feedback signal received at the first input terminal and generating an amplified signal at the first output terminal; a second gain stage circuit including a terminal coupled to the first output terminal for receiving the amplified signal and a second output terminal, wherein the second gain stage circuit is configured to generate a monitored signal based on the amplified signal; a feedback circuit coupled between the second output terminal and the first input terminal and configured to convert the monitored signal to the feedback signal; and a comparator circuit including a monitoring node coupled to the first output terminal for receiving the amplified signal, wherein the comparator circuit is configured to indirectly monitor the monitored signal via the amplified signal.

Description

Technical Field

[0001] This disclosure generally relates to the field of electronic circuits, and more specifically, to gray area prevention circuits with indirect signal monitoring. Background Technology

[0002] In integrated circuits, it is often necessary to detect whether an internal signal is within a specified range (i.e., a critical range) or within a tolerance window defined by an upper and lower limit of the range. In this setup, it is desirable for the internal signal to remain within the boundaries of the specified range and not enter a gray area. Two comparators can be used to observe the internal signal, one monitoring an upper reference threshold (e.g., upper reference) and the other monitoring a lower reference threshold (e.g., lower reference).

[0003] However, to ensure that violations of the specified range can be detected, the reference thresholds "upper reference" and "lower reference" must be within the specified range. In other words, the two reference thresholds are not set as the upper and lower limits of the specified range respectively, but rather within that specified range. Therefore, the upper reference threshold is less than the upper limit of the range, and the lower reference threshold is greater than the lower limit of the range. The need to set the reference (comparator) thresholds within the specified range stems from the manufacturing tolerances of the two comparators in mass production. These manufacturing tolerances need to be considered to ensure that the comparator does not monitor values ​​outside the specified range (this results in a "gray area"). In other words, if the comparator threshold is outside the critical range, the range outside the critical range can be defined as the gray area. Therefore, the gray area refers to the situation where a signal exceeds its critical range, but the comparator is not triggered because the signal has not reached its threshold. Thus, if the comparator threshold is outside the allowable critical range of the monitored signal, the gray area is the area between the upper / lower range critical limits of the signal and the upper / lower comparator threshold. Ensuring that the comparator does not monitor values ​​outside the specified critical range places strict precision requirements on the comparator and the reference thresholds "upper reference" and "lower reference," which in turn results in a larger chip area (for matching reasons).

[0004] Therefore, an improved monitoring device is expected that can achieve less stringent accuracy requirements for comparator precision. Such a monitoring device could further allow for the use of smaller comparators, saving chip area and cost. Summary of the Invention

[0005] An embodiment provides a gray area prevention circuit, comprising: a first gain stage circuit including a first input terminal and a first output terminal, wherein the first gain stage circuit amplifies a feedback signal received at the first input terminal and generates an amplified signal at the first output terminal; a second gain stage circuit including a terminal and a second output terminal, wherein the terminal is coupled to the first output terminal for receiving the amplified signal, wherein the second gain stage circuit is configured to generate a monitored signal at the second output terminal based on the amplified signal; a feedback circuit coupled between the second output terminal and the first input terminal and configured to convert the monitored signal into a feedback signal; and a comparator circuit including a monitoring node coupled to the first output terminal for receiving the amplified signal, wherein the comparator circuit is configured to indirectly monitor the monitored signal via the amplified signal.

[0006] The embodiment also provides a method for preventing a monitored signal from entering a gray area. The method includes: amplifying a feedback signal via a first gain stage circuit to generate an amplified signal; generating a monitored signal based on the amplified signal via a second gain stage circuit; converting the monitored signal into a feedback signal to be provided to the first gain stage circuit via a feedback circuit; and indirectly monitoring the monitored signal via the amplified signal through a comparator circuit. Attached Figure Description

[0007] This document describes embodiments with reference to the accompanying drawings.

[0008] Figure 1 It is a schematic diagram of a signal monitoring circuit according to one or more embodiments;

[0009] Figure 2A It is a schematic diagram of a signal monitoring circuit according to one or more embodiments;

[0010] Figure 2B It shows in Figure 2A Signal diagrams of various voltages taken within the signal monitoring circuit; and

[0011] Figure 3 This is a schematic diagram of a signal monitoring circuit according to one or more embodiments. Detailed Implementation

[0012] In the following sections, details are set forth to provide a more thorough explanation of exemplary embodiments. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In other instances, known structures and devices are shown in block diagrams or schematic representations rather than in detail to avoid obscuring the embodiments. Furthermore, unless otherwise specifically stated, features of the different embodiments described below may be combined with each other.

[0013] Furthermore, in the following description, equivalent or similar reference numerals are used to denote equivalent or similar elements or elements having equivalent or similar functions. Since identical or functionally equivalent elements have the same reference numerals in the drawings, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals can be interchanged.

[0014] It should be understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there is no intermediate element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" vs. "directly between", "adjacent" vs. "directly adjacent", etc.).

[0015] In the embodiments described herein or illustrated in the accompanying drawings, any direct electrical connection or coupling (i.e., any connection or coupling without additional intermediate elements) may also be implemented by indirect connection or coupling (i.e., connection or coupling with one or more additional intermediate elements), and vice versa, as long as the general purpose of the connection or coupling is substantially maintained, such as transmitting a signal or transmitting information. Features from different embodiments may be combined to form further embodiments. For example, unless otherwise stated, variations or modifications described with respect to one embodiment may also be applicable to other embodiments.

[0016] The term "substantially" may be used herein to describe small manufacturing tolerances (e.g., within 5%) that are considered acceptable in the industry without departing from the aspects of the embodiments described herein.

[0017] In this disclosure, the use of designations including serial numbers (such as "first," "second," etc.) can modify various elements. However, these elements are not limited by the foregoing designations. For example, the foregoing designations do not limit the order and / or importance of elements. The foregoing designations are only used to distinguish one element from other elements. For example, the first box and the second box represent different boxes, although they are both boxes. For example, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element, without departing from the scope of this disclosure.

[0018] One or more aspects of this disclosure can be implemented as a non-transitory computer-readable recording medium having a program thereon containing a embodied method / algorithm for instructing a processor to execute the method / algorithm. Therefore, the non-transitory computer-readable recording medium may have electrically readable control signals stored thereon that cooperate (or are capable of cooperating with) a programmable computer system to execute the corresponding method / algorithm. For example, the non-transitory computer-readable recording medium may be a CD-ROM, DVD, Blu-ray disc, RAM, ROM, PROM, EPROM, EEPROM, flash memory, or an electrical storage device.

[0019] Each element of this disclosure can be configured to perform the function of any component or combination thereof by implementing dedicated hardware or software programs on the memory of a control processor. Any component can be implemented as a central processing unit (CPU) or other processor that reads and executes software programs from a recording medium such as a hard disk or semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuits.

[0020] Therefore, the term "processor" is used herein to refer to any of the foregoing structures or any other structures suitable for implementing the techniques described herein. Thus, the techniques described in this disclosure can be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, aspects of the techniques can be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuits, and any combination of such components.

[0021] The controller, including hardware, can also perform one or more of the techniques disclosed herein. A controller including one or more processors can use electrical signals and digital algorithms to perform its receiving, analyzing, and controlling functions, which may further include correction functions. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described herein. The software may be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes program code or program algorithms stored thereon, which, when executed, cause the controller to perform the steps of the method via a computer program.

[0022] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals from one or more components and perform signal conditioning or processing on them. As used herein, signal conditioning refers to processing a signal in a manner that meets the requirements of further processing in the next stage. Signal conditioning may include analog-to-digital conversion (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for post-conditioning processing.

[0023] Therefore, signal processing circuitry may include an analog-to-digital converter (ADC), which converts analog signals from one or more sensor elements into digital signals. Signal processing circuitry may also include a digital signal processor (DSP) that performs some processing on the digital signals.

[0024] Figure 1 This is a schematic diagram of a signal monitoring circuit 100 according to one or more embodiments. In this example, the signal monitoring circuit 100 is used to indirectly monitor a monitored voltage Vmon. The signal monitoring circuit 100 includes a first gain stage 10 and a second gain stage 12 electrically coupled together. The first gain stage 10 has a first gain A1, and the second gain stage 12 has a second gain A2, which may be different from the first gain A1. Specifically, the first gain A1 may be greater than the second gain A2. For example, the first gain A1 may be at least one order of magnitude larger than the second gain A2, may be at least two orders of magnitude larger than the second gain A2, and may be at least three orders of magnitude larger than the second gain A2. The larger the difference between gains A1 and A2, the less demanding the accuracy requirements of comparators 16 and 18 are, as will be discussed below. However, more generally, the higher the gain A1, the less accurate comparators 16 and 18 may be. In this sense, the gain value of A2 can be ignored because the second gain stage 12 is not in the detection feedback loop. Thus, the value of gain A1 works in conjunction with the accuracy of comparators 16 and 18. It can be said that the value of gain A1 is inversely related to (e.g., inversely proportional to) the accuracy of comparators 16 and 18. When gain A1 is low, the accuracy requirement of comparators 16 and 18 increases. When gain A1 is high, the accuracy requirement of comparators 16 and 18 decreases.

[0025] The second gain stage 12 generates the monitored voltage Vmon at its output terminal. Specifically, the monitored voltage Vmon is generated and regulated by a feedback loop. Therefore, the signal monitoring circuit 100 includes two different gain stages 10 and 12 that generate an output voltage (i.e., the monitored voltage Vmon) regulated by the feedback loop. Thus, the signal monitoring circuit 100 is suitable for circuits that generate signals by feedback loops, such as voltage regulators and bandgap circuits.

[0026] The feedback loop includes a feedback (fb) circuit device 14 arranged on the feedback path, which generates, converts, or otherwise obtains a feedback voltage Vfb based on the monitored voltage Vmon. The feedback (fb) circuit device 14 receives the monitored voltage Vmon at its input terminal and outputs the feedback voltage Vfb at its output terminal. The feedback (fb) circuit device 14 extracts a voltage Vfb = βVmon from the monitored voltage Vmon of the second gain stage 12, where β is a function of the feedback (fb) circuit device 14 and may be referred to as the feedback ratio.

[0027] The first gain stage 10 can be a high-gain device, such as a negative feedback amplifier, which includes two input terminals and one output terminal. As a more specific example, the first gain stage 10 can be an operational amplifier (op amp). One input terminal of the first gain stage 10 (e.g., an inverting input) is configured to receive a feedback voltage Vfb, while the other input terminal (e.g., a non-inverting input) is configured to receive a reference voltage Vref3. The first gain stage 10 generates an amplified voltage VA based on the feedback voltage Vfb and the reference voltage Vref3.

[0028] For example, if the feedback voltage Vfb is greater than the reference voltage Vref3, the first gain stage 10 generates the amplifier voltage VA by amplifying the feedback voltage Vfb according to its gain A1. However, since the feedback voltage Vfb is greater than the reference voltage Vref3, the amplifier voltage VA becomes more negative and shifts towards the negative supply voltage V- (e.g., ground or 0V) supplied to the first gain stage 10. Similarly, if the feedback voltage Vfb is less than the reference voltage Vref3, the first gain stage 10 generates the amplifier voltage VA by amplifying the feedback voltage Vfb according to its gain A1. However, since the feedback voltage Vfb is less than the reference voltage Vref3, the amplifier voltage VA becomes more positive and shifts towards the positive supply voltage V+ (e.g., VDD) supplied to the first gain stage 10.

[0029] Due to the negative feedback loop and the high gain A1 of the first gain stage 10, small changes in the monitored voltage Vmon cause large changes in the output of the first gain stage 10 (i.e., the amplifier voltage VA). The high gain A1 of the first gain stage 10 can be designed to drive the amplifier voltage VA to a positive supply voltage V+ (e.g., VDD) or a negative supply voltage V- (e.g., ground or 0V) in response to any deviation of the monitored voltage Vmon from a predetermined value or a predetermined range.

[0030] A window comparator circuit is electrically connected to a monitoring node Nmon located between the output of the first gain stage 10 and the terminals of the second gain stage 12 (in some cases directly between the two). Thus, the amplifier voltage VA is received by the second gain stage 12 and used to generate the monitored voltage Vmon. The second gain stage 12 can be a high-ohm regulating device, such as a transistor. The second gain stage 12 can be a pass device with a gain A2 of 1 or substantially 1. The second gain stage 12 can be a power device, such as a power transistor that conducts the load current supplied to the node. In the case that the second gain stage 12 is a transistor, the terminal receiving the amplifier voltage VA and coupled to the monitoring node Nmon can be a control terminal (such as a gate terminal), and the amplifier voltage VA can be the gate voltage (i.e., the control voltage) of the second gain stage 12, which regulates the current flowing through the second gain stage 12 (e.g., through the transistor).

[0031] The window comparator circuit includes two comparators, 16 and 18, which define a tolerance window for comparison with the amplifier voltage VA. For example, the tolerance window is defined by an upper reference value defined by a reference voltage Vref1 and a lower reference value defined by a reference voltage Vref2. Reference voltages Vref1, Vref2, and Vref3 are fixed at predetermined values. It should be understood that if it is desired to monitor overvoltage only via comparator 16 or undervoltage via comparator 18, a single comparator (i.e., comparator 16 or 18) can be used instead of the window comparator.

[0032] Comparator 16 is configured to receive a reference voltage Vref1 and an amplifier voltage VA at its two inputs, and to generate an error signal (e.g., an error voltage) Verr1 in response to an amplifier voltage VA being greater than the reference voltage Vref1. For example, comparator 16 may be configured to generate a low voltage value when the amplifier voltage VA is equal to or less than the reference voltage Vref1, indicating that there is no error at the monitored voltage Vmon. Conversely, comparator 16 may be configured to generate a high voltage value Verr1 when the amplifier voltage VA is greater than the reference voltage Vref1, indicating that there is an error at the monitored voltage Vmon. Therefore, comparator 16 can be considered an overvoltage comparator.

[0033] Comparator 18 is configured to receive a reference voltage Vref2 and an amplifier voltage VA at its two inputs, and to generate an error signal (e.g., an error voltage) Verr2 in response to an amplifier voltage VA being less than the reference voltage Vref2. For example, comparator 18 may be configured to generate a low voltage value when the amplifier voltage VA is equal to or greater than the reference voltage Vref2, indicating that there is no error at the monitored voltage Vmon. Conversely, comparator 18 may be configured to generate a high voltage value Verr2 when the amplifier voltage VA is less than the reference voltage Vref2, indicating that there is an error at the monitored voltage Vmon. Therefore, comparator 18 can be considered an undervoltage comparator.

[0034] As described above, a small change in the monitored voltage Vmon results in a large change in the amplifier voltage VA. The high-gain A1 of the first gain stage 10 can be designed to drive the amplifier voltage VA to either the positive supply voltage V+ or the negative supply voltage V- (e.g., ground) in response to a deviation of the monitored voltage Vmon from a predetermined target value. The deviation can be "any" deviation from the predetermined target value, or it can be a predetermined amount of deviation from the predetermined target value. The reference voltages Vref1 and Vref2 of the window comparator circuit are set within limits of the supply voltages V+ and V-. In other words, the reference voltage Vref1 is set to be less than the supply voltage V+, and the reference voltage Vref2 is set to be greater than the supply voltage V-.

[0035] Therefore, the deviation between the monitored voltage Vmon and the predetermined target value causes the first-stage amplifier 10 to drive the amplifier voltage VA to a saturation value of V+ or V-, exceeding the limit of the tolerance window defined by the reference voltages Vref1 and Vref2, thereby generating one of the error signals Verr1 or Verr2. Thus, the window comparator circuit is configured to indirectly monitor the monitored signal Vmon via the amplifier signal VA.

[0036] It is understandable that the monitored voltage Vmon changes only slightly, but the amplifier voltage VA signal changes significantly due to the high open-loop gain of the first gain stage 10 (e.g., an operational amplifier). Comparators 16 and 18 of the window comparator circuit that checks for changes in the amplifier voltage VA can have more relaxed accuracy requirements. In other words, although both comparators are still used for window tolerance monitoring, their area is much smaller due to their relaxed accuracy requirements.

[0037] Furthermore, an error is detected while the monitored signal Vmon remains entirely within the acceptable tolerance window (i.e., before it enters the gray area). In other words, although the monitored signal Vmon may have deviated from a predetermined value that can be considered the optimal or target value, the monitored signal Vmon is still generally within the acceptable operating limits of the system. However, the error indications of error signals Verr1 or Verr2 can provide advance indication or warning, requiring continued monitoring to ensure that the monitored signal Vmon does not exceed the acceptable operating limits and / or to activate additional monitoring and fault detection measures to perform additional monitoring of the monitored signal Vmon or its system circuitry.

[0038] Figure 2A This is a schematic diagram of a signal monitoring circuit 200 according to one or more embodiments. Figure 2B The diagram shows signal graphs of various voltages taken within the signal monitoring circuit 200. Specifically, Figure 2A A voltage regulator circuit with a first gain stage 10 as an operational amplifier is shown, having a gain A1 of 1000 and a reference voltage Vref3 of 1.2V. Figure 2A A second gain stage 12, acting as a transistor, is also shown, having a gain A2 of 1, outputting the monitored voltage Vmon at 1.5V under optimal conditions, and at 1.49V when leakage current may exist due to a defect causing a slight voltage drop. It should be understood that the monitored voltage Vmon can also be increased from 1.5V due to another type of defect. The feedback circuit 14 is a voltage divider comprising two resistors R1 and R2, which generates a feedback voltage Vfb based on the monitored voltage Vmon. In this example, the reference voltages Vref1 and Vref2 of the window comparator circuit are set to 2.1V and 0.9V, respectively. The supply voltages V+ and V- of the operational amplifier 10 are set to 2.4V and 0V, respectively. It should be understood that the above values ​​are for illustrative purposes and not for limitation.

[0039] Figure 2B The monitored voltage Vmon, as the monitored signal, is shown, fluctuating between 1.5V and 1.49V and 1.51V. Furthermore, Figure 2BThe effect of the monitored voltage Vmon on the amplifier voltage VA is shown. Specifically, when the monitored voltage Vmon is at its target regulation value of 1.5V, the amplifier voltage VA is approximately 1.8V, clearly within the boundaries defined by the reference voltages Vref1 and Vref2. However, when the monitored voltage Vmon drifts to 1.49V, this change causes the amplifier voltage VA to be driven to 2.4V (i.e., the supply voltage V+ of operational amplifier 10), which exceeds (i.e., is greater than) the reference voltage Vref1. On the other hand, when the monitored voltage drifts to 1.51V, this change causes the amplifier voltage VA to be driven to 0V (i.e., the supply voltage V- of operational amplifier 10), which exceeds (i.e., is less than) the reference voltage Vref2.

[0040] When the monitored voltage Vmon drops by (e.g.) 10mV due to a defect on the die, the feedback voltage drops by 8mV via a resistor divider. Operational amplifier 10 now sees an 8mV differential input voltage across its input terminals. For example, if its gain is 1000, this 8mV will result in a voltage change of 8V at VA. In other words, due to saturation, VA will reach the supply voltage V+ of operational amplifier 10. Similarly, if the monitored voltage Vmon is forced to rise by 10mV, operational amplifier 10 will attempt to correct it; if it fails, voltage VA will ground.

[0041] It can be seen that the monitored voltage Vmon is forced to change by only a slight amount, but due to the high open-loop gain of operational amplifier 10, the amplifier voltage VA signal changes significantly. Comparators 16 and 18, which check the change in amplifier voltage VA, have more relaxed accuracy requirements compared to directly monitoring the monitored voltage Vmon. Figure 2B The dashed lines in the diagram represent the optimal comparator thresholds for upper and lower limit violations, respectively. Furthermore, a defect is detected when the monitored signal is still entirely within the specification (still within the critical lower and upper limits defining the boundaries of the corresponding gray areas) (e.g., it is 1.49V, but the critical lower limit for Vmon can be 1.35V). As a result of this monitoring, even with the relaxed accuracy requirements of comparators 16 and 18, early error detection can prevent the monitored voltage Vmon from entering the gray area.

[0042] Figure 3 This is a schematic diagram of a signal monitoring circuit 300 according to one or more embodiments. Specifically, Figure 3A bandgap voltage reference circuit 300 is shown, which generates a fixed bandgap voltage (i.e., the monitored voltage Vmon) regardless of power supply variations, temperature variations, and circuit loads from the device. The bandgap voltage reference circuit 300 includes a first gain stage 10, which functions as an operational amplifier with a gain A1 of 1000. It receives a reference voltage Vref3 at its non-inverting terminal and a feedback voltage Vfb at its inverting terminal. The operational amplifier is again configured as a negative feedback amplifier. Figure 3 A second gain stage 12, acting as a transistor, is also shown, having a gain A2 of 1, which outputs the monitored voltage Vmon at the target voltage. The monitored voltage Vmon may deviate from the target voltage due to defects in the circuit.

[0043] Feedback circuit 14 is the remainder of bandgap voltage reference circuit 300, including resistors R1 and R2 that conduct currents mI and I, respectively, where "m" is a multiplication factor. Feedback circuit 14 also includes a temperature-dependent (PTAT) current I. PTAT PTAT resistor R PTAT Each parallel branch of the feedback circuit 14 includes transistors Q1 and Q2, wherein the reflector area nA of transistor Q2 is "n" times larger than the emitter area A of transistor Q1.

[0044] The bandgap voltage reference circuit 300 also includes a window comparator comprising comparators 16 and 18, which operate in a similar manner as described above. That is, comparators 16 and 18 receive the amplifier voltage VA output from the first gain stage 10 and generate error voltages Verr1 and Verr2 based on the comparison results of the amplifier voltage VA with reference voltages Vref1 and Vref2.

[0045] The deviation of the monitored voltage Vmon from its target voltage result is a significant change in the amplifier voltage VA, more specifically, causing the amplifier voltage VA to be driven to either the operational amplifier supply voltage V+ or V-. Reference voltages Vref1 and Vref2 are pre-configured such that the operational amplifier supply voltage V+ or V- is outside their defined windows. Therefore, driving the amplifier voltage VA to either the operational amplifier supply voltage V+ or V- triggers one of the error signals Verr1 or Verr2. As described above, error signals Verr1 and Verr2 serve as advance indications that further monitoring action is needed to prevent the monitored voltage Vmon from deviating from a critical range (i.e., to prevent Vmon from entering the gray area). As a result of this monitoring, even with the relaxed accuracy requirements of comparators 16 and 18, early error detection can prevent the monitored voltage Vmon from entering the gray area.

[0046] The accuracy requirements for comparators 16 and 18, which check for changes in amplifier voltage VA, are much less stringent than those for comparators that directly monitor the monitored voltage Vmon. Furthermore, defects are detected while the monitored signal remains fully within specifications (still within the boundaries of its critical lower and upper limits). That is, it does not enter the gray area.

[0047] While various embodiments have been described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of this disclosure. Therefore, the invention is not limited except as provided in the appended claims and their equivalents.

[0048] For the various functions performed by the aforementioned components or structures (components, devices, circuits, systems, etc.), unless otherwise stated, the terminology used to describe such components (including references to “means”) is intended to correspond to any component or structure that performs the specified function of said component (i.e., functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of the invention shown herein.

[0049] Furthermore, the following claims are incorporated herein in detail, each of which may stand alone as a separate exemplary embodiment. While each claim may stand alone as a separate exemplary embodiment, it should be noted that although dependent claims may refer in the claims to a particular combination with one or more other claims, other exemplary embodiments may also include combinations of the subject matter of the dependent claim with each of the other dependent or independent claims. Such combinations are suggested herein unless it is stated that a particular combination is not intended. Furthermore, features of a claim may be incorporated into any other independent claim, even if the claim is not directly dependent on that independent claim.

[0050] It should also be noted that the methods disclosed in the specification or claims can be implemented by means having each corresponding action of these methods.

[0051] Furthermore, it should be understood that the disclosure of multiple actions or functions in the specification or claims should not be construed as being in a particular order. Therefore, the disclosure of multiple actions or functions does not limit them to a specific order unless such actions or functions are not interchangeable for technical reasons. Additionally, in some embodiments, a single action may include multiple sub-actions or may be decomposed into multiple sub-actions. Unless expressly excluded, such sub-actions may be included as part of the disclosure of a single action.

[0052] In summary, although various exemplary embodiments have been disclosed, those skilled in the art will understand that various changes and modifications can be made to achieve some of the advantages of the disclosed concepts without departing from the spirit and scope of the invention. Those skilled in the art will understand that other components performing the same function can be appropriately replaced. It should be understood that other embodiments can be utilized, and structural or logical changes can be made without departing from the scope of the invention. It should be mentioned that features interpreted with reference to specific drawings may be combined with features in other drawings, even if not explicitly mentioned. The appended claims and their legal equivalents cover such modifications to the general inventive concept.

Claims

1. A gray area prevention circuit, comprising: A first gain stage circuit includes a first input terminal and a first output terminal, wherein the first gain stage circuit amplifies the feedback signal received at the first input terminal and generates an amplified signal at the first output terminal; The second gain stage circuit includes a terminal and a second output terminal, wherein the terminal is coupled to the first output terminal for receiving the amplified signal, and wherein the second gain stage circuit is configured to generate a monitored signal at the second output terminal based on the amplified signal. A feedback circuit, coupled between the second output terminal and the first input terminal, is configured to convert the monitored signal into the feedback signal; as well as A comparator circuit includes a monitoring node coupled to the first output terminal for receiving the amplified signal, wherein the comparator circuit is configured to indirectly monitor the monitored signal via the amplified signal. The second gain stage circuit is configured to generate the monitored signal at the target value. The comparator circuit mentioned above includes at least one of a first comparator and a second comparator. The first comparator is configured to generate a first error signal in response to the monitored signal being larger than the target value, and The second comparator is configured to generate a second error signal in response to the monitored signal being smaller than the target value.

2. The gray area prevention circuit according to claim 1, wherein: The first gain stage circuit amplifies the feedback signal using a first gain to generate the amplified signal, and The second gain stage circuit uses a second gain to generate the monitored signal. The first gain is greater than the second gain.

3. The gray area prevention circuit according to claim 1, wherein: The comparator circuit is a window comparator circuit that includes the first comparator and the second comparator. The first comparator is configured to generate the first error signal in response to the monitored signal being larger than the target value by a first predetermined amount, and The second comparator is configured to generate the second error signal in response to the monitored signal being smaller than the target value by a second predetermined amount.

4. The gray area prevention circuit according to claim 3, wherein the feedback circuit is arranged on a negative feedback path, the negative feedback path extending between the second output terminal and the first input terminal.

5. The gray area prevention circuit according to claim 4, wherein: The first gain stage circuit is an operational amplifier, configured to provide a first power supply potential and a second power supply potential. The first gain stage circuit is configured to amplify the feedback signal using a first gain to generate the amplified signal. The first gain is sufficient to drive the amplified signal to the first power supply potential in response to the monitored signal being smaller than the target value by a second predetermined amount, and The first gain is sufficient to drive the amplified signal to the second power supply potential in response to the monitored signal being larger than the target value by a first predetermined amount.

6. The gray area prevention circuit according to claim 5, wherein the second gain stage circuit is a transistor, and the terminal of the second gain stage circuit that receives the amplified signal is the control terminal of the transistor.

7. The gray area prevention circuit according to claim 6, wherein the monitoring node is coupled to the control terminal.

8. The gray area prevention circuit according to claim 5, wherein the second gain stage circuit is a high-ohm adjustment device.

9. The gray area prevention circuit according to claim 5, wherein the second power supply potential is ground potential.

10. The gray area prevention circuit according to claim 5, wherein: The first comparator includes a first comparator input configured to receive a first reference value and a second comparator input configured to receive the amplified signal, and the first comparator is configured to generate the first error signal when the value of the amplified signal is greater than the first reference value. The second comparator includes a third comparator input configured to receive a second reference value and a fourth comparator input configured to receive the amplified signal, and the second comparator is configured to generate the second error signal when the value of the amplified signal is less than the second reference value.

11. The gray area prevention circuit according to claim 10, wherein: The first reference value is greater than the second reference value and less than the first power supply potential of the operational amplifier, and The second reference value is greater than the second power supply potential of the operational amplifier.

12. The gray area prevention circuit according to claim 3, wherein: The first comparator includes a first comparator input configured to receive a first reference value and a second comparator input configured to receive the amplified signal, and the first comparator is configured to generate the first error signal when the value of the amplified signal is greater than the first reference value. The second comparator includes a third comparator input configured to receive a second reference value and a fourth comparator input configured to receive the amplified signal, and the second comparator is configured to generate the second error signal when the value of the amplified signal is less than the second reference value.

13. The gray area prevention circuit according to claim 1, wherein: The first gain stage circuit is an operational amplifier, configured to provide a first power supply potential and a second power supply potential. The first gain stage circuit is configured to amplify the feedback signal using a first gain to generate the amplified signal. The first gain is sufficient to drive the amplified signal to the second power supply potential in response to the monitored signal being larger than the target value by a first predetermined amount, and The first gain is sufficient to drive the amplified signal to the first power supply potential in response to the monitored signal being smaller than the target value by a second predetermined amount.

14. The gray area prevention circuit according to claim 1, wherein: The comparator circuit is a window comparator circuit that includes the first comparator and the second comparator.

15. The gray area prevention circuit according to claim 1, further comprising: The feedback loop includes the feedback circuit and the first gain stage circuit, wherein the feedback loop is configured to regulate the monitored signal.

16. The gray area prevention circuit according to claim 1, wherein the feedback circuit is a resistor divider.

17. The gray area prevention circuit of claim 1, wherein the feedback circuit is part of a bandgap voltage reference circuit.

18. The gray area prevention circuit according to claim 1, wherein: The first gain stage circuit provides a first power supply potential and a second power supply potential. The first gain stage circuit is configured to amplify the feedback signal using a first gain to generate the amplified signal. The first gain is sufficient to drive the amplified signal to the second power supply potential in response to the monitored signal being larger than the target value by a first predetermined amount, and The first gain is sufficient to drive the amplified signal to the first power supply potential in response to the monitored signal being smaller than the target value by a second predetermined amount.

19. The gray area prevention circuit according to claim 18, wherein: The second gain stage circuit uses a second gain to generate the monitored signal, and The first gain is at least two orders of magnitude greater than the second gain.

20. A method for preventing monitored signals from entering a gray area, the method comprising: The feedback signal received at the first input terminal of the first gain stage circuit is amplified to generate an amplified signal. The monitored signal is generated at the target value based on the amplified signal through the second gain stage circuit, wherein the terminals of the second gain stage circuit are coupled to the first output terminal of the first gain stage circuit to receive the amplified signal; The monitored signal is converted into the feedback signal through a feedback circuit, and the feedback signal is provided to the first input terminal of the first gain stage circuit, wherein the feedback circuit is coupled between the output terminal of the second gain stage circuit and the first input terminal. as well as The amplified signal is received via a comparator circuit through a monitoring node coupled to the first output terminal, thereby indirectly monitoring the monitored signal. The comparator circuit mentioned above includes at least one of a first comparator and a second comparator. The first comparator generates a first error signal in response to the monitored signal being larger than the target value, and The second comparator generates a second error signal in response to the monitored signal being smaller than the target value.

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