Data processing circuit, method and semiconductor memory

Abstract

The application provides a data processing circuit, a method and a semiconductor memory, and relates to the technical field of storage. The circuit comprises a data selection module, which is used for receiving write data and outputting the write data when a received write control command is in a first level state, and receiving read data and outputting the read data when a received read control command is in the first level state; a check module, which is used for receiving the write data or the read data, performing check processing on the write data or the read data to obtain write check data or read check data, and outputting the write check data or the read check data; and a data output module, which is used for receiving the write check data or the read check data, outputting the write check data when the write control command is in the first level state, and outputting the read check data when the read control command is in the first level state. According to the embodiment of the application, the size of the semiconductor memory and the data read-write reliability can be considered.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data processing circuit, method, and semiconductor memory. Background Technology

[0002] With the rapid development of semiconductor storage technology, issues such as the integration level of semiconductor memory and the reliability of writing and reading data have become one of the research directions of semiconductor storage technology.

[0003] At present, in the process of shrinking the size of semiconductor memory, there is a lack of technical solutions that can effectively ensure the reliability of data reading and writing.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This application provides a data processing circuit, method, and semiconductor memory, which at least to some extent overcomes the problem in the related art that it is impossible to balance the size of semiconductor memory and the reliability of data read and write.

[0006] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0007] According to one aspect of this application, a data processing circuit is provided, comprising:

[0008] The data selection module is used to receive and output write data when the received write control command is in the first level state; and to receive and output read data when the received read control command is in the first level state.

[0009] The verification module is used to receive written data or read data; perform verification processing on the written data or read data to obtain written verification data or read verification data; and output written verification data or read verification data.

[0010] The data output module is used to receive written verification data or read verification data; it outputs written verification data when the write control command is in the first level state; and it outputs read verification data when the read control command is in the first level state.

[0011] According to another aspect of this application, a data processing method is provided, applied to the aforementioned data processing circuit, comprising:

[0012] When the received write control command is in the first level state, the data selection module receives and outputs write data; and when the received read control command is in the first level state, it receives and outputs read data.

[0013] The verification module receives written data or read data, performs verification processing on the written data or read data, obtains written verification data or read verification data, and outputs written verification data or read verification data.

[0014] The data output module receives written verification data or reads verification data. When the write control command is in the first level state, it outputs written verification data, and when the read control command is in the first level state, it outputs read verification data.

[0015] According to another aspect of this application, a semiconductor memory is provided, comprising:

[0016] The data processing circuit described above;

[0017] Semiconductor memory cell array.

[0018] The data processing circuit, method, and semiconductor memory provided in this application can, when the write control command is in the first level state, receive write data through the data selection module, send it to the verification module for verification processing, and output the write verification data obtained from the verification processing using the data output module; or, when the read control command is in the first level state, receive read data through the data selection module, perform verification processing on it using the verification module, and output the read verification data obtained from the verification processing using the data output module. Since it is not necessary to use different data processing circuits to process the write data and read data separately, only one data processing circuit can select the write data or read data for verification processing according to the write control command and read control command. This data processing circuit generates write verification data for verifying the correctness of the write data or generates read verification data for verifying the correctness of the read data, thereby ensuring the reliability of data reading and writing while considering the size of the semiconductor memory.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 This diagram illustrates the structure of a data processing circuit according to an embodiment of this application.

[0022] Figure 2 A schematic diagram illustrating an exemplary data transmission process provided in an embodiment of this application is shown;

[0023] Figure 3 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown;

[0024] Figure 4 This illustration shows a structural diagram of a data selection submodule provided in an embodiment of this application;

[0025] Figure 5 This illustration shows a schematic diagram of the structure of an exemplary data selection submodule provided in an embodiment of this application;

[0026] Figure 6A This diagram illustrates the logic of the data selection module when transmitting and writing data.

[0027] Figure 6B This diagram illustrates the logic of the data selection module when transmitting read data.

[0028] Figure 7 This paper shows a schematic diagram of the structure of another data processing circuit provided in an embodiment of the present application;

[0029] Figure 8 This paper shows a schematic diagram of an exemplary data processing circuit provided in an embodiment of this application.

[0030] Figure 9A This diagram illustrates the logic of the data output module when outputting written verification data.

[0031] Figure 9B This diagram illustrates the logic of the data output module when outputting read verification data.

[0032] Figure 10 This invention provides a schematic diagram of the structure of another data processing circuit in an embodiment of this application.

[0033] Figure 11 A schematic diagram of the read / write command format is shown;

[0034] Figure 12 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown;

[0035] Figure 13 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown;

[0036] Figure 14 This paper shows a schematic diagram of the structure of a sequence adjustment subunit provided in an embodiment of this application;

[0037] Figure 15 This illustration shows a structural schematic diagram of a sequence adjustment unit provided in an embodiment of this application;

[0038] Figure 16 A schematic diagram of an exemplary sequence adjustment module provided in an embodiment of this application is shown;

[0039] Figure 17 A schematic diagram of the signals and data involved in an exemplary sequence adjustment circuit provided in an embodiment of this application is shown;

[0040] Figure 18 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown;

[0041] Figure 19 This invention illustrates a flowchart of a data processing method according to an embodiment of this application; and

[0042] Figure 20 A schematic diagram of the structure of a semiconductor memory provided in an embodiment of this application is shown.

[0043] The annotations in the attached figures are explained as follows:

[0044] Data selection module 10; data selection submodule 11; write data selection unit 111; write data control terminal 1111; write data input terminal 1112, write data output terminal 1113; read data selection unit 112; read data control terminal 1121; read data input terminal 1122; read data output terminal 1123; signal output unit 113; first input terminal 1131; second input terminal 1132; output terminal 1133;

[0045] Verification module 20;

[0046] Data output module 30; first output submodule 31; write control terminal 311; first verification data input terminal 312; write verification data output terminal 313; second output submodule 32; read control terminal 321; second verification data input terminal 322; read verification data output terminal 323;

[0047] Sequence adjustment module 40; Sequence adjustment submodule 41; Data input terminal 411; First output terminal 412; Second output terminal 413; Data processing unit 414; Input terminal 4141; First output terminal 4142; Second output terminal 4143; Control terminal 4144; Sequence adjustment unit 415; First input terminal 4151; Second input terminal 4152; First output terminal 4153; Second output terminal 4154; First control terminal 4155; Second control terminal 4156; Data selection subunit 4157; First input terminal 4157A; Second input terminal 4157B; First output terminal 4157C; Second output terminal 4157C; First output subunit 4158; Input terminal 4158A; Control terminal 4158B; Output terminal 4158C; Second output subunit 4159; Input terminal 4159A; Control terminal 4159B; Output terminal 4159C. Detailed Implementation

[0048] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0050] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0051] It should be noted that the concepts of "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0052] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0053] In the description of this application, it should be noted that, unless otherwise stated, "multiple" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. "Vertical" is not vertical in the strict sense, but within the allowable tolerance range. "Parallel" is not parallel in the strict sense, but within the allowable tolerance range.

[0054] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0055] At present, in the development of semiconductor memories such as Dynamic Random Access Memory (DRAM), the trend is often toward increasing the integration density of semiconductor memories.

[0056] However, in the process of this development, how to effectively improve the reliability of reading and writing data while taking into account the area occupied by the memory circuit has become one of the urgent problems to be solved.

[0057] The inventors discovered through research that the reliability of reading and writing data may be affected by storage errors during the data reading and writing process, or by link errors between the storage array and the storage controller.

[0058] Based on this, embodiments of this application provide a data processing circuit, method, and semiconductor memory that eliminate the need for separate data processing circuits to process written and read data. A single data processing circuit can perform verification processing on written or read data according to write control commands and read control commands, and generate write verification data for verifying the correctness of written data or read verification data for verifying the correctness of read data. This ensures the reliability of data reading and writing while taking into account the size of the semiconductor memory.

[0059] In some embodiments of this application, the data processing circuit may further include a sequence adjustment module. The sequence adjustment module may also perform a data transmission sequence adjustment operation on the written data or read data before the read data or write data is input into the sequence adjustment module according to the sequence adjustment control signal. After adjusting the data to the correct transmission sequence, the data is input into the verification module, which ensures the correctness of the written data or read data input into the verification module. This can improve the correctness of the output written verification data or read verification data, thereby further improving the reliability of data reading and writing.

[0060] Before introducing the technical solutions provided in the embodiments of this application, the technical terms involved in the embodiments of this application will be explained below.

[0061] Writing data can refer to data to be written to the array of memory cells in a semiconductor memory.

[0062] Reading data can refer to data that needs to be read from the array of memory cells in a semiconductor memory and sent to the outside.

[0063] A write control command, also known as a write command or write control signal, can be a signal used to instruct a semiconductor memory to write data. For example, a write control command can be a level signal that, when in a first level state, controls the semiconductor memory to write data, and when in a fourth level state, controls the semiconductor memory to stop writing data. One of the first and fourth level states is high, and the other is low.

[0064] A read control command, also known as a read command or read control signal, is a signal used to instruct a semiconductor memory to read data. The control methods for read control commands and write control commands are the same; please refer to the relevant explanation of write control commands above, which will not be repeated here.

[0065] After introducing the above concepts, the following detailed description of the exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0066] This application embodiment provides a data processing circuit, which will be described below. Figures 1-18 This needs to be explained.

[0067] Figure 1 This diagram illustrates the structure of a data processing circuit according to an embodiment of this application. Figure 1 As shown, the data processing circuit provided in this embodiment may include a data selection module 10, a verification module 20, and a data output module 30. The verification module 20 is connected to both the data selection module 10 and the data output module 30.

[0068] The data selection module 10, the verification module 20, and the data output module 30 will be described in turn.

[0069] The data selection module 10 can be used to receive write data and output write data when the received write control command is in the first level state; or to receive read data and output read data when the received read control command is in the first level state.

[0070] The first level state can be the level at which the data selection module 10 receives corresponding data (write data or read data). For example, the first level state can be a high level state or a low level state. For instance, if the first level state is high, then when the write control command is high, the data selection module 10 selects to receive the write data and transmits it to the verification module 20. And, when the read control command is in the first level state, the data selection module 10 selects to receive the read data and transmits it to the verification module 20.

[0071] In one example, read and write operations on a semiconductor memory may not be performed simultaneously; correspondingly, read and write control commands can be mutually exclusive signals.

[0072] For example, during a write operation, the write control command is in the first level state, and the read control command is in the fourth level state. Correspondingly, the data selection module 10 can receive and output the written data within the data transmission cycle under the control of the write control command. The data transmission cycle for processing the written data can be called the write cycle. For example, as... Figure 17 As shown, one data transmission cycle in which the write control command is in the first level state (high level) is one write cycle.

[0073] For example, during a read operation, the read control command is in the first level state, and the write control command is in the fourth level state. Accordingly, the data selection module 10 can receive and output read data within the data transmission cycle under the control of the read control command. The data transmission cycle for processing the read data can be called the read cycle. For example, as... Figure 17As shown, one data transmission cycle in which the read control command is in the first level state is one read cycle.

[0074] Regarding the data output method of the data selection module 10, in some embodiments, to improve data processing efficiency, the data selection module 10 can transmit read data or write data to the verification module 20 through n data lines. Correspondingly, the data selection module 10 can transmit read data or write data to the verification module 20 in n parallel lines. Specifically, the data selection module 10 can transmit write data in P data transmission cycles, or it can transmit read data in P data transmission cycles. Here, P can be a positive integer greater than or equal to 1.

[0075] In one data transmission cycle, each data line can serially transmit k bits of data. Both n and k can be positive integers greater than or equal to 1. The values ​​of n and k can be set according to actual conditions and specific requirements. For example, n can be 8, 16, etc., and k can be 2, 4, 8, 16, etc., without specific limitations.

[0076] For example, taking k = 2, in one data transmission cycle, the data selection module 10 can transmit 2n bits of data to the verification module 20 through n data lines. Specifically, bits (n+1) to 2n are transmitted in parallel, and bits 1 to n are transmitted in parallel. Furthermore, each data line can transmit 2 bits of data serially within one data transmission cycle. For instance, the i-th bit and the (i+n)-th bit in the 2n bits are transmitted serially using the same data line (e.g., the i-th data line). Here, i is a positive integer greater than or equal to 1 and less than or equal to n.

[0077] It should be noted that if 2n bits of data are written or read, bits 0 to (n-1) are transmitted first, followed by bits n to (2n-1), then the transmitted ith bit can be the (i-1)th bit of the written or read data, and the transmitted (i+n)th bit can be the (i+n-1)th bit of the written or read data. Conversely, if 2n bits of data are written or read, bits n to (2n-1) are transmitted first, followed by bits 0 to (n-1), then the transmitted ith bit can be the (i+n-1)th bit of the written or read data, and the transmitted (i+n)th bit can be the (i-1)th bit of the written or read data.

[0078] Regarding the number of data selection modules 10, in one embodiment, data can be transmitted to the verification module 20 in parallel by r data selection modules 10. It should be noted that r can be determined according to the actual transmission requirements of the memory chip and the specific transmission circuit, and can be an integer such as 4, 8 or 16, without specific limitation.

[0079] Next, taking r=8 and n=8 as an example, the above data transmission process will be explained.

[0080] In one example Figure 2 A schematic diagram illustrating an exemplary data transmission process provided in an embodiment of this application is shown. For example... Figure 2 As shown, the eight data selection modules 10 can transmit data to the verification module 20 in parallel. Each data selection module 10 transmits input / output data from one DQ port to the verification module 20. For example, the first data selection module 10 transmits input / output data from the first DQ port to the verification module 20. Similarly, the second data selection module 10 transmits input / output data from the second DQ port, and so on, until the eighth data selection module 10 transmits input / output data from the eighth DQ port to the verification module 20.

[0081] See also Figure 2 Each data selection module 10 and the verification module 20 can transmit data in parallel across eight channels. Specifically, the 8th to 15th bits of data transmitted by each data selection module (i.e., the first to 8th bits transmitted earlier) are transmitted in parallel to the verification module 20 via eight data lines. After the 8th to 15th bits, the 0th to 7th bits of data (i.e., the 9th to 16th bits transmitted later) are transmitted in parallel to the verification module 20 via eight data lines. Specifically, the first data line transmits the 0th and 8th bits serially; the second data line transmits the 1st and 9th bits serially; ...; and the 8th data line transmits the 7th and 15th bits serially. Accordingly, within one data transmission cycle, the eight data selection modules 10 can output 128 bits of data to the verification module 20.

[0082] After explaining the data transmission process described above, the structure of the data selection module corresponding to this data transmission process will be described next. It should be noted that since the structures and functions of the various data selection modules are similar, the following embodiments of this application will describe only one data selection module.

[0083] Accordingly, Figure 3 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown. Figure 3 As shown, the data selection module 10 may include n parallelly configured data selection sub-modules 11. Each of the n data selection sub-modules 11 can be connected to the verification module 20, for example, by connecting to the verification module 20 via n data lines L1-Ln.

[0084] Specifically, the i-th data selection submodule 11 can be used to output the i-th bit and the (i+n)-th bit of the received write data in each data transmission cycle when the write control command is in the first level state. For example, if each data transmission cycle includes a first time period and a second time period, the i-th bit can be transmitted in the first time period and the (i+n)-th bit can be transmitted in the second time period.

[0085] When the read control command is in the first level state, the i-th bit and i+n-th bit of the received read data in each data transmission cycle will be output.

[0086] In this embodiment, when n equals 1, ordered data transmission between the data selection module 10 and the verification module 20 can be achieved, ensuring the accuracy of data transmission and thus improving the reliability of data processing.

[0087] Furthermore, when n is greater than 1, this embodiment can use n data lines and n parallel data transmissions between the data selection module 10 and the verification module 20 in units of data transmission cycles to achieve fast and orderly transmission of written and read data. This enables accurate and fast transmission of written or read data to the verification module 20, thereby improving the data transmission speed and processing efficiency of the data processing circuit.

[0088] It should be noted that the data selection module 10 can also be implemented using other functional structures to multiplex the write data of the write cycle input and the read data of the read cycle input into a single signal input verification module. The input data of the verification module is selected via a control signal; when the write control command is at the first level, the write data input verification module is selected, and when the read control command is at the first level, the read data input verification module is selected. For example, the data selection module 10 can be one or more multiplexing modules, and each multiplexing module can include one or more multiplexers. No specific limitations are imposed in this regard.

[0089] After a preliminary introduction to the data selection submodule 11, the specific structure of the data selection submodule will be explained next. Since the structures of the n data selection submodules 11 can be the same, the following explanation will take the i-th data selection submodule 11 as an example to illustrate each data selection submodule.

[0090] In one embodiment, Figure 4 A schematic diagram of the structure of a data selection submodule provided in an embodiment of this application is shown. Figure 4As shown, the data selection submodule 11 may include a write data selection unit 111, a read data selection unit 112, and a signal output unit 113. The write data selection unit 111 and the read data selection unit 112 are respectively connected to the signal output unit 113. The components will be described in turn.

[0091] The write data selection unit 111 may include a write data control terminal 1111, a write data input terminal 1112, and a write data output terminal 1113.

[0092] Specifically, in the i-th data selection submodule 11, the write data control terminal 1111 can be used to receive write control commands. The write data input terminal 1112 can be used to receive the i-th write sub-data, wherein the i-th write sub-data is the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle of the write data. The i-th write data selection unit 111 can be used to respond to the write control command and output the i-th input sub-data at the write data output terminal 1113. For example, the write data selection unit 111 can be used to generate a first pulse signal based on the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle of the write data. The write data output terminal 1113 can be used to output the first pulse signal.

[0093] Specifically, the i-th written sub-data can be output when the write control command is in the first level state. For example, the output of the i-th written sub-data can also be stopped when the write control command is in the fourth level state; for instance, a low-level signal can be output when the write control command is in the fourth level state. For example, a high-level signal corresponds to the value of the i-th bit or the (i+n)-th bit of the i-th written sub-data, and a low-level signal corresponds to the value of the i-th bit or the (i+n)-th bit.

[0094] The read data selection unit 112 may include a read data control terminal 1121, a read data input terminal 1122, and a read data output terminal 1123.

[0095] Specifically, the read data control terminal 1121 can be used to receive read control commands; the read data input terminal 1122 can be used to receive the i-th read sub-data, which is the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle. The read data selection unit 112 can be used to respond to the read control command and output the i-th read sub-data at the read data output terminal 1123. For example, the read data selection unit 112 can be used to generate a second pulse signal based on the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle. The read data output terminal 1123 can be used to output this second pulse signal.

[0096] Specifically, the system can output read data when the read control command is in the first level state. Optionally, it can also output a low-level signal when the read control command is in the fourth level state.

[0097] The signal output unit 113 may include a first input terminal 1131, a second input terminal 1132, and an output terminal 1133.

[0098] Specifically, the first input terminal 1131 is connected to the write data output terminal 1113. The second input terminal 1132 is connected to the read data output terminal 1123. The pulse signal output terminal 1133 can be used to output the i-th write sub-data or the i-th read sub-data.

[0099] In other words, the signal output unit 113 can select to output read data during the read cycle (i.e., the data transmission cycle when the read control command is in the first level state) and select to output write data during the write cycle (i.e., the write control command is in the first level state).

[0100] It should be noted that the data selection submodule 11 can also adopt other functional structures, such as a multiplexing module. No specific limitations are imposed. For example, the multiplexing module may include one or more multiplexers.

[0101] In this embodiment, when the write control command is in the first level state, i.e., during the write cycle, the level signals of the i-th bit and i+n-th bit of the written data transmitted in each data transmission cycle are output. Similarly, when the read control command is in the first level state, i.e., during the read cycle, the i-th bit and i+n-th bit of the read data transmitted in each data transmission cycle are output. This allows the i-th data selection submodule to output the i-th bit and i+n-th bit of the written data during the write cycle, and the i-th bit and i+n-th bit of the read data during the read cycle. Furthermore, by including n parallel data selection subunits, the read data output during the read cycle and the write data output during the write cycle can be sequentially output to the same signal output unit 113 for processing. This achieves multiplexing of read and write data at the data input terminals (including the aforementioned write data input terminal 1112 and read data input terminal 1122), improving data processing efficiency.

[0102] In one example Figure 5 A schematic diagram of the structure of an exemplary data selection submodule provided in an embodiment of this application is shown.

[0103] like Figure 5As shown, the write data selection unit 111 may include a first AND gate AND1. The first AND gate AND1 includes a fifth input terminal B1, a sixth input terminal A1, and a third output terminal Y1. The fifth input terminal B1 serves as the write data input terminal 1112. The sixth input terminal A1 serves as the write data control terminal 1111. The third output terminal Y1 serves as the write data output terminal 1113.

[0104] The read data selection unit 112 may include a second AND gate AND2. The second AND gate AND2 includes a seventh input B2, an eighth input A2, and a fourth output Y2. The seventh input B2 serves as the read data input 1122. The eighth input A2 serves as the read data control terminal 1121. The fourth output Y2 serves as the read data output terminal 1123.

[0105] The signal output unit 113 may include a connected NOR gate (NOR1) and NOT gate (NOT1). The NOR gate (NOR1) may include a ninth input terminal A3, a tenth input terminal B3, and a fifth output terminal Y3. The ninth input terminal A3 serves as the first input terminal 1131 of the signal output unit. The tenth input terminal B3 serves as the second input terminal 1132 of the signal output unit. The NOT gate (NOT1) may include an eleventh input terminal A4 and a sixth output terminal Y4. The eleventh input terminal A4 is connected to the fifth output terminal Y3. The sixth output terminal Y4 serves as the output terminal 1133 of the signal output unit.

[0106] It should be noted that, Figure 6A The diagram illustrates the logic of the data selection module during data transmission. Figure 6B This diagram illustrates the logic of the data selection module during data transmission. Figure 6A and Figure 6B In this context, a logic value of "1" corresponds to a high level, and a logic value of "0" corresponds to a low level. Next, we will... Figure 6A and Figure 6B right Figure 5 The processing logic of the logic gate circuit shown is explained.

[0107] like Figure 6A As shown, during the write cycle, the control logic of the first AND gate AND1 is as shown in truth table T11. Specifically, the write control command of the sixth input terminal A1 is held at a high level, corresponding to the logic value "1". At this time, if the write data of the fifth input terminal B1 is 0, the third output terminal Y1 outputs the logic value "0". And if the write data of the fifth input terminal B1 is 1, the third output terminal Y1 outputs the logic value "1".

[0108] Furthermore, during the write cycle, the control logic of the second AND gate AND2 is shown in truth table T12. Specifically, the read control command and the write control command are mutually exclusive signals. When the write control command is held high, the read control command of the eighth input terminal A2 is held low, corresponding to a logic value of "0". At this time, regardless of whether the data read from the seventh input terminal B2 is 0 or 1, the logic value output by the fourth output terminal Y2 remains "0".

[0109] Furthermore, during the write cycle, the control logic of the NOR gate NOR1 is shown in truth table T13, and the control logic of the NOT gate NOT1 is shown in truth table T14. At this time, the logic value of the ninth input terminal A3 is either 0 or 1, and the logic value of the tenth input terminal B3 is 0. When the ninth input terminal A3 is writing data 0, the fifth output terminal Y3 outputs a logic value of 1. After being inverted by the NOT gate NOT1, the sixth output terminal Y4 outputs the written data 0. Similarly, when the ninth input terminal A3 is writing data 1, the fifth output terminal Y3 outputs a logic value of 0. After being inverted by the NOT gate NOT1, the sixth output terminal Y4 outputs the written data 1.

[0110] And, such as Figure 6B As shown, during the read cycle, the control logic of the first AND gate AND1 is as shown in truth table T21. Specifically, the write control command of the sixth input terminal A1 is kept at a low level, corresponding to the logic value "0". At this time, regardless of whether the data written to the fifth input terminal B1 is 0 or 1, the third output terminal Y1 will output the logic value "0".

[0111] Furthermore, during the read cycle, the control logic of the second AND gate AND2 is shown in truth table T22. Specifically, when the write control command is held low, the read control command of the eighth input A2 is held high, corresponding to a logic value of "1". At this time, when the read data at the seventh input B2 is 0, the logic value output by the fourth output Y2 is 0. When the read data at the seventh input B2 is 1, the logic value output by the fourth output Y2 is 1.

[0112] Furthermore, during the read cycle, the control logic of the NOR gate NOR1 is shown in truth table T23, and the control logic of the NOT gate NOT1 is shown in truth table T24. At this time, the logic value of the ninth input terminal A3 is 0, and the logic value of the tenth input terminal B3 is the read data 0 or 1. When the tenth input terminal B3 is the read data 0, the fifth output terminal Y3 outputs the logic value 1. After being inverted by the NOT gate NOT1, the read data 0 is output by the sixth output terminal Y4. Similarly, when the tenth input terminal B3 is the read data 1, the fifth output terminal Y3 outputs the logic value 0. After being inverted by the NOT gate NOT1, the read data 1 is output by the sixth output terminal Y4.

[0113] In summary, during the write cycle, the data to be written is input to the data selection submodule through the fifth input terminal B1. After a series of logical data processing steps, the written data can be output through the sixth output terminal Y4. Similarly, during the read cycle, the data to be read is input to the data selection submodule through the seventh input terminal B2. After a series of logical data processing steps, the read data can be output through the sixth output terminal Y4.

[0114] Accordingly, in this embodiment, write data and read data can be multiplexed at the data input terminal using logic gate circuits. Since the area of ​​the verification module 20 in the actual circuit is much larger than the volume of the logic gate circuit, this embodiment of the application can transmit write data and read data to the same verification module 20 for processing in different time periods by setting up logic gate circuits. Compared with the scheme of using two verification modules to verify and process read data and write data separately, the area of ​​the semiconductor memory can be reduced.

[0115] It should be noted that other connection methods of logic gate devices can also be used to implement the function of the above-mentioned data selection submodule in the embodiments of this application, and no specific limitation is made thereto.

[0116] Furthermore, it should be noted that if a line transmits more than 2 bits of data in each data transmission cycle, such as 4 bits or 8 bits of data, then each data selection submodule 11 can also serially transmit more than 2 bits of data. The specific transmission method is similar to that of transmitting 2 bits of data as described above. Please refer to the specific description of transmitting 2 bits of data in the above part of the embodiments of this application, which will not be repeated here.

[0117] After introducing the data selection module 10, the verification module 20 will be explained next.

[0118] The verification module 20 can be used to receive written data or read data; perform verification processing on the written data or read data to obtain written verification data or read verification data; and output written verification data or read verification data.

[0119] Verification module 20 can calculate verification data for verifying the correctness of data. In some embodiments, verification module 20 can be a CRC (Cyclic Redundancy Check) module. Exemplarily, a CRC verification module can be referred to as a CRC counter.

[0120] In one embodiment, when the write control command is in the first level state, the verification data 20 can receive the write data output by the data selection module 10, perform CRC calculation on the write data to obtain a CRC checksum, and output the CRC checksum as the write verification data. For example, the verification data 20 can receive 128 bits of write data transmitted by eight data selection modules 10 in one data transmission cycle, and then calculate 8-bit or 16-bit write verification data.

[0121] In another embodiment, when the read control command is at the first level, the verification data 20 can receive the read data output by the data selection module 10, and the verification data 20 can perform CRC calculation on the read data to obtain the CRC check code, and output the calculated CRC check code as the read verification data.

[0122] In one embodiment, if a write data or a read data needs to be transmitted over a data transmission cycle, a checksum can be calculated after each data transmission cycle. For example, for 16-bit read data, if the checksum module receives 16 bits of read data in a data transmission cycle, it can perform checksum processing after receiving the 16 bits of read data to obtain a read checksum. The calculation process for write data is similar to that for read data and will not be described further here.

[0123] Alternatively, within each data transmission cycle, after receiving all data transmitted by all data selection modules, the verification data corresponding to each data selection module can be calculated. For example, such as... Figure 2 As shown, in one data transmission cycle, one data selection module 10 can transmit 16 bits of read data to the verification module 20, and eight data selection modules 10 can transmit 128 bits of read data to the verification module 20. After receiving all 128 bits of read data transmitted by the eight data selection modules 10, the verification module can combine and calculate 8 or 16 bits of verification data, and allocate 1 or 2 bits of verification data to each 16-bit data transmitted by the data selection module. The calculation process for writing data is similar to that for reading data, and will not be described in detail here.

[0124] Alternatively, if a write or read operation requires transmission over multiple data transfer cycles, a verification result can be calculated after each data transfer cycle. For example, if 64-bit read data needs to be transmitted to the verification module over four data transfer cycles, with 16 bits transmitted per cycle, the verification module can perform verification processing after receiving the 64-bit read data through four data transfer cycles, obtaining a read verification result. The calculation process for write data is similar to that for read data and will not be elaborated further here.

[0125] It should be noted that a real-time receiving and real-time calculation method can also be used, and the verification calculation method in this application embodiment is not specifically limited.

[0126] It should be noted that, in the embodiments of this application, other verification methods besides CRC, such as ECC (Error Correcting Code), parity check, MD5 (Message-Digest Algorithm 5), etc., may be adopted according to the actual scenario and specific needs, and no specific limitation is made in this regard.

[0127] In some embodiments, after the verification module 20 receives the data sent by the data selection module in each data transmission cycle, since the data is transmitted in parallel through 8 data lines, the received data can be converted into serial data by serial-to-parallel conversion at the input of the verification module 20 before verification processing.

[0128] After introducing the verification module 20, the data output module 30 will be explained next.

[0129] The data output module 30 can be used to receive write verification data or read verification data; output write verification data when the write control command is in the first level state; and output read verification data when the read control command is in the first level state. For example, the data output module 30 can receive and output write verification data when the write control command is in the first level state, and can also receive and output read verification data when the read control command is in the first level state.

[0130] In some embodiments, Figure 7 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown. Figure 7 As shown, the data output module 30 may include a first output submodule 31 and a second output submodule 32. The first output submodule 31 and the second output submodule 32 are respectively connected to the verification module 20.

[0131] The first output submodule 31 may include a write control terminal 311, a first verification data input terminal 312, and a write verification data output terminal 313. The write control terminal 311 can be used to receive write control commands. The first verification data input terminal 312 can be used to receive write verification data or read verification data output by the verification module 20. Specifically, the first verification data input terminal 312 can receive write verification data output by the verification module 20 when the write control command is in the first level state, and can receive read verification data output by the verification module 20 when the read control command is in the first level state. The write verification data output terminal 313 can be used to output write verification data when the write control command is in the first level state.

[0132] The second output submodule 32 may include a read control terminal 321, a second verification data input terminal 322, and a read verification data output terminal 323. The read control terminal 321 can be used to receive read control commands. The second verification data input terminal 322 is connected to the first verification data input terminal 312 and can be used to receive write verification data or read verification data output by the verification module 20. Specifically, the second verification data input terminal 322 can receive write verification data output by the verification module 20 when the write control command is in the first level state, and can receive read verification data output by the verification module 20 when the read control command is in the first level state. The read verification data output terminal 323 can be used to output read verification data when the read control command is in the first level state.

[0133] In this embodiment, the first output submodule and the second output submodule can demultiplex the write verification data and read verification data processed and transmitted by the same verification module 20, and output them through different output terminals (i.e., the write verification data output terminal 313 and the read verification data output terminal 323). This facilitates different processing and use of the write verification data and read verification data in the future, and improves the performance of the data processing circuit.

[0134] It should be noted that the data output module 30 in this embodiment can also be other functional modules capable of separating or demultiplexing sequentially transmitted write data and read data, and no specific limitation is made thereto.

[0135] In one embodiment, Figure 8 A schematic diagram of an exemplary data processing circuit provided in an embodiment of this application is shown.

[0136] like Figure 8As shown, the first output submodule 31 may include a third AND gate AND3. The third AND gate AND3 includes a twelfth input B5, a thirteenth input A5, and a seventh output Y5. The twelfth input B5 serves as the first verification data input 312, the thirteenth input A5 serves as the write control input 311, and the seventh output Y5 serves as the write verification data output 313.

[0137] The second output submodule 32 may include a fourth AND gate AND4. The fourth AND gate AND4 includes a fourteenth input B6, a fifteenth input A6, and an eighth output Y6. The fourteenth input B6 serves as the second verification data input 322, the fifteenth input A6 serves as the read control input 321, and the eighth output Y6 serves as the read verification data output 323.

[0138] It should be noted that, Figure 9A The diagram shown illustrates the logic of the data output module when outputting written verification data. Figure 9B This diagram illustrates the logic of the data output module when outputting read verification data. Figure 9A and Figure 9B In this context, a logic value of "1" corresponds to a high level, and a logic value of "0" corresponds to a low level. Next, we will... Figure 9A and Figure 9B right Figure 5 The processing logic of the logic gate circuit shown is explained.

[0139] like Figure 9A As shown, during the write cycle, the control logic of the third AND gate AND3 is as shown in truth table T31. Specifically, the write control command at the thirteenth input A5 is held high, corresponding to the logic value "1". The twelfth input B5 receives the write verification data. If the write verification data is 0, the seventh output Y5 outputs the logic value "0". And if the write verification data is 1, the seventh output Y5 outputs the logic value "1".

[0140] Furthermore, the control logic of the fourth AND gate, AND4, is shown in truth table T32. Specifically, the read control command of the fifteenth input terminal A6 is kept at a low level, corresponding to a logic value of "0". When the fourteenth input terminal B6 receives the write verification data, regardless of whether the write verification data is 0 or 1, the logic value output by the eighth output terminal Y6 remains "0".

[0141] And, such as Figure 9BAs shown, during the read cycle, the control logic of the third AND gate AND3 is as shown in truth table T41. Specifically, the write control command of the thirteenth input terminal A5 is kept at a low level, corresponding to the logic value "0". The twelfth input terminal B5 receives the read verification data. At this time, regardless of whether the read verification data is 0 or 1, the seventh output terminal Y5 outputs the logic value "0".

[0142] Furthermore, the control logic of the fourth AND gate, AND4, is shown in truth table T42. Specifically, the read control command of the fifteenth input terminal A6 is held at a high level, corresponding to the logic value "1". The fourteenth input terminal B6 receives the read verification data. At this time, if the read verification data is 0, the eighth output terminal Y6 outputs the logic value "0", and if the read verification data is 1, the eighth output terminal Y6 outputs the logic value "1".

[0143] In summary, during the write cycle, the verification module 20 outputs the write verification data to the twelfth input B5 of the third AND gate AND3 and the fourteenth input B6 of the fourth AND gate AND4. At this time, since the logic value of the thirteenth input A5 of the third AND gate AND3 is 1, the write verification data can be output from the seventh output Y5 of the third AND gate. Similarly, during the read cycle, the verification module 20 outputs the read verification data to the twelfth input B5 of the third AND gate AND3 and the fourteenth input B6 of the fourth AND gate AND4. At this time, since the logic value of the fifteenth input A6 of the fourth AND gate AND4 is 1, the write verification data can be output from the eighth output Y6 of the third AND gate.

[0144] Accordingly, in this embodiment, the write verification data and read verification data can be demultiplexed at the data output terminal using logic gate circuits. Since the area of ​​the verification module 20 in an actual circuit is much larger than the volume of the logic gate circuit, this embodiment can separate the write verification data and read verification data from the data streams of the same verification module 20 by using logic gate circuits. Compared to using two separate verification modules to generate read verification data and write verification data, this reduces the area of ​​the semiconductor memory.

[0145] It should be noted that other connection methods of logic gate devices can also be used to implement the function of the above-mentioned data selection submodule in the embodiments of this application, and no specific limitation is made thereto.

[0146] The embodiments of this application are combined Figures 1 to 9BThe data processing circuit shown in any of the accompanying figures can, when the write control command is at the first level, receive the write data through the data selection module 10, send it to the verification module 20 for verification processing, and output the write verification data obtained from the verification processing through the data output module 30. Similarly, when the read control command is at the first level, after receiving the read data through the data selection module 10, the same verification module 20 can be used to perform verification processing on it, and the read verification data obtained from the verification processing can be output through the data output module 30. Since it is not necessary to use different data processing circuits to perform verification processing on the write and read data separately, only one data processing circuit can select the write or read data to perform verification processing based on the write control command and the read control command to generate write verification data or read verification data. Furthermore, under the control of the write control command and the read control command, the write verification data and read verification data can be output to different subsequent processing circuits through different output circuits, thereby ensuring the reliability of data reading and writing while considering the size of the semiconductor memory.

[0147] Furthermore, it should be noted that, through the embodiments of this application, by utilizing write control commands and read control commands, the output timing of the written verification data and read verification data can be synchronized with the read and write order of the semiconductor memory. Thus, a single verification module 20 can ensure data read and write reliability without affecting data read and write efficiency. Compared to existing technologies that fail to guarantee data read and write reliability while improving read and write efficiency, and vice versa, this approach achieves a reduction in semiconductor memory area while simultaneously considering both data read and write reliability and efficiency, thereby improving the performance of the semiconductor memory.

[0148] During data processing, the inventors also discovered that the order in which data is read and written can be incorrect. For example, if the order in which data is read is incorrect when reading data from a semiconductor memory, the order in which the data is read may be incorrect.

[0149] Based on this, the inventors also provided another data processing circuit. Figure 10 This diagram illustrates the structure of yet another data processing circuit according to an embodiment of this application. The embodiments of this application are optimizations based on the above embodiments, and can be combined with various optional solutions from one or more of the above embodiments.

[0150] and Figure 1 The difference shown in the data processing circuit is that, Figure 10The data processing circuit shown may further include a sequence adjustment module 40. The data selection module 10 can be connected to the verification module 20 via the sequence adjustment module 40. For example, when the number of data selection modules 10 is r, r sequence adjustment modules 40 may be included, wherein each data selection module 10 is connected to the verification module 20 via one sequence adjustment module 40. It should be noted that, since the sequence adjustment modules 40 are similar, the accompanying drawings and description of this application embodiment only describe one data selection module 10 and the sequence adjustment module 40 connected to it.

[0151] The sequence adjustment module 40 can receive write data or read data output by the data selection module 10, and perform data transmission order adjustment operation on the write data or read data according to the sequence adjustment control signal, adjusting the write data or read data to the correct transmission order before outputting it. Specifically, during the write cycle, the sequence adjustment module 40 can receive the write data transmitted by the data selection module 10 and adjust it to the correct transmission order before outputting it. Similarly, during the read cycle, the sequence adjustment module 40 can receive the read data transmitted by the data selection module 10 and adjust it to the correct transmission order before outputting it.

[0152] Accordingly, when the data processing circuit further includes a sequence adjustment module 40, the verification module 20 can be specifically used to: receive write data or read data that has been adjusted to the correct transmission order; perform verification processing on the write data or read data that has been adjusted to the correct transmission order to obtain write verification data or read verification data; and output the write verification data or read verification data. It should be noted that other aspects of the verification module 20 can be found in the relevant descriptions in the above sections of the embodiments of this application, and will not be repeated here.

[0153] Next, the sequence adjustment module 40 will be described through the sequence adjustment control signal, the data transmission sequence adjustment operation, and the specific structure of the sequence adjustment module 40.

[0154] The sequence adjustment control signal can be used to indicate whether the transmission order of the data (written data or read data) received by the sequence adjustment module 40 is correct.

[0155] In some embodiments, the sequence adjustment control signal can be determined based on the value of a preset bit in the burst sequence field, whereby the preset bit is used to characterize whether the data reading order is reversed. The preset bit can be a specific bit in the burst sequence field obtained by decoding the read / write command.

[0156] In one example Figure 11 A schematic diagram illustrating the format of read and write commands is shown. For example... Figure 11As shown, the burst sequence field can be the field corresponding to C0-C3. Among them, the preset bit can be C3.

[0157] In one example, taking a data selection module 10 transmitting 16 bits of correctly ordered data 0-F via 8 data lines, if bit C3 is 0, it indicates that the data transmission order is correct, that is, bits 0 to 7 (i.e.,...) Figure 11 (0-7) is first transmitted through 8 data lines, and the 8th to 15th bits of data (i.e. Figure 11 After bits 8, 9, and AF, data is transmitted via 8 data lines. Also, if bit C3 is 1, it indicates that the data transmission order is reversed, meaning bits 8 through 15 are transmitted first, followed by bits 0 through 7.

[0158] Similarly, if the correct transmission order is high-order bits first and low-order bits last, then the correct transmission order could be bits 8 through 15 first, followed by bits 0 through 7. This will not be elaborated further.

[0159] After a preliminary introduction to the sequence adjustment control signals, the data transmission sequence adjustment operation will now be explained.

[0160] The data transmission order adjustment operation can refer to the operation of adjusting the data received by the order adjustment module 40 to the correct transmission order. For example, if the transmission order of the data received by the order adjustment module 40 is correct, the transmission order of the received data can be maintained, and the data can be output to the subsequent verification module 20. As another example, if the transmission order of the received data is incorrect, it can be adjusted to the correct transmission order before being output to the subsequent verification module 20.

[0161] In some embodiments, if the data selection module 10 uses one data line to transmit one path of write data or read data in each data transmission cycle, the sequence adjustment module can adjust the data transmission order of multiple bit values ​​in that path of data.

[0162] In other embodiments, if the data selection module 10 uses multiple data lines to transmit multiple write data or read data in each data transmission cycle, the data selection module 10 can adjust the data transmission order of multiple bit values ​​in each data path.

[0163] After introducing the sequence adjustment control signal and the data transmission sequence adjustment operation, the specific structure of the sequence adjustment module 40 will be explained next.

[0164] In some embodiments, Figure 12 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown. Figure 12 As shown, in the case where the data selection module 10 transmits 2n bits of write or read data to the sequence adjustment module 40 through n data lines in one data transmission cycle, the sequence adjustment module 40 includes n parallel sequence adjustment sub-modules 41. The transmission method of the n data lines can be found in the above-described portion of the embodiments of this application. Figure 2 The relevant explanations will not be repeated here.

[0165] See also Figure 12 Each sequence adjustment submodule 41 may be provided with a data input terminal 411, a first output terminal 412, and a second output terminal 413. Each data input terminal 411 is connected to the data selection module 10, and each first output terminal 412 and each second output terminal 413 are connected to the verification module 20.

[0166] In one embodiment, when the data selection module 10 includes n parallelly configured data selection sub-modules 11... Figure 13 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown.

[0167] like Figure 13 As shown, when the data selection module 10 includes n parallel data selection sub-modules 11, each of the n parallel data selection sub-modules 11 is connected to a corresponding n parallel sequence adjustment sub-modules 41. That is, the first data selection sub-module 11 is connected to the first sequence adjustment sub-module 41, the second data selection sub-module 11 is connected to the second sequence adjustment sub-module 41, and so on, until the nth data selection sub-module 11 is connected to the nth sequence adjustment sub-module 41.

[0168] The following is a detailed explanation of the order adjustment submodule 41. Since the structure and function of the n order adjustment submodules 41 can be the same, we will take the i-th order adjustment submodule 41 as an example to explain each data selection submodule.

[0169] The data input terminal 411 of the i-th sequence adjustment submodule 11 is connected to the data selection module 10 and can be used to receive the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle. For example, the data input terminal 411 can receive the i-th bit and the (i+n)-th bit of the written data in a data transmission cycle for transmitting written data, and the i-th bit and the (i+n)-th bit of the read data in a data transmission cycle for transmitting read data. It should be noted that the data input terminal 411 can sequentially receive the i-th bit and the (i+n)-th bit in each data transmission cycle. For example, each data transmission cycle may include a first time period and a second time period; the data input terminal 411 can receive the i-th bit of the current data transmission cycle in the first time period and the (i+n)-th bit of the current data transmission cycle in the second time period.

[0170] The i-th order adjustment submodule 41 can be used to adjust the order of the i-th bit and the (i+n)-th bit in each data transmission cycle to the correct transmission order. In one embodiment, when the order adjustment control signal indicates that the data transmission order is reversed, the i-th order adjustment submodule 41 can swap the order of the i-th bit and the (i+n)-th bit received in each data transmission cycle. That is, the i-th bit before adjustment becomes the new (i+n)-th bit, and the (i+n)-th bit before adjustment becomes the new i-th bit. For example, taking the data 0-F transmitted when n=8 as an example, one set of data is "0-7" and another set of data is "8-F". The data transmission order can be adjusted between the two sets of data, while the transmission order between the data within each set is not adjusted. In another embodiment, when the order adjustment control signal indicates that the data transmission order is correct, the i-th order adjustment submodule 41 can keep the order of the i-th bit and the (i+n)-th bit received in each data transmission cycle unchanged.

[0171] The first output terminal 412 and the second output terminal 413 of the i-th order adjustment submodule 41 are respectively connected to the verification module 20. The first output terminal 412 and the second output terminal 413 can be used to output the i-th bit and the (i+n)-th bit, which have been adjusted to the correct transmission order, to the verification module 20, respectively. In one embodiment, the first output terminal 412 is used to output the i-th bit, and the second output terminal 413 can be used to output the (i+n)-th bit.

[0172] In this embodiment, when the data transmission order is reversed, the i-th order adjustment submodule 41 can adjust the transmission order of the received i-th bit and i+n-th bit, and output the adjusted i-th bit from the first output terminal 412 and the adjusted i+n-th bit from the second output terminal 413, thus ensuring the accuracy of the data received by the verification module 20 and improving the reliability of reading and writing data.

[0173] In one embodiment, Figure 14 A schematic diagram of the structure of a sequence adjustment subunit provided in an embodiment of this application is shown. Figure 14 As shown, the i-th order adjustment submodule 41 may include a data processing unit 414 and an order adjustment unit 415.

[0174] The data processing unit 414 may be provided with an input terminal 4141, a first output terminal 4142, a second output terminal 4143 and a control terminal 4144.

[0175] The input terminal 4141 of the data processing unit serves as the data input terminal 411 of the i-th sequence adjustment submodule. The input terminal 4141 of the data processing unit can be used to receive the i-th bit and the (i+n)-th bit transmitted serially in each data transmission cycle.

[0176] The control terminal 4144 of the data processing unit can be used to receive a first clock signal. In response to the control of the first clock signal, the data processing unit 414 can generate first transmission data and second transmission data to be transmitted in parallel, based on the i-th bit and the (i+n)-th bit received serially. The first transmission data includes the (i+n)-th bit obtained by sampling at the second trigger edge of the first clock signal. The second transmission data includes the i-th bit obtained by sampling at the second trigger edge of the first clock signal. The first output terminal 4142 and the second output terminal 4143 of the data processing unit are used to output the first transmission data and the second transmission data in parallel. That is, when the first output terminal 4142 outputs the first transmission data, the second output terminal 4143 can synchronously output the second transmission data.

[0177] For the first clock signal, the occurrence time of its first trigger edge can be later than or synchronized with the start transmission time of the i-th bit and earlier than the end transmission time of the i-th bit. The occurrence time of its second trigger edge can be later than or synchronized with the start transmission time of the (i+n)-th bit and earlier than the end transmission time of the (i+n)-th bit. Here, the start transmission time of any bit is the time when transmission of that bit begins, and the end transmission time of any bit is the time when transmission of that bit stops. For example, the trigger edge can be a rising edge or a falling edge.

[0178] Specifically, the first clock signal can correspond to either level triggering or edge triggering. For example, if the first clock signal corresponds to level triggering (high level triggering), the trigger edge is a rising edge. Accordingly, the falling edge corresponding to the first trigger edge occurs earlier than the end transmission time of the i-th bit, and the falling edge corresponding to the second trigger edge occurs earlier than the end transmission time of the (i+n)-th bit. As another example, if the first clock signal is low level triggering (low level triggering), the trigger edge is a falling edge. Accordingly, the rising edge corresponding to the first trigger edge occurs earlier than the end transmission time of the i-th bit, and the rising edge corresponding to the second trigger edge occurs earlier than the end transmission time of the (i+n)-th bit.

[0179] The sequence adjustment unit 415 may be provided with a first input terminal 4151, a second input terminal 4152, a first output terminal 4153, a second output terminal 4154, a first control terminal 4155, and a second control terminal 4156.

[0180] The first input terminal 4151 of the sequence adjustment unit is connected to the first output terminal 4142 of the data processing unit and can be used to receive the first transmitted data. The second input terminal 4152 of the sequence adjustment unit is connected to the second output terminal 4143 of the data processing unit and can be used to receive the second transmitted data. That is, while the first input terminal 4151 of the sequence adjustment unit is receiving the first transmitted data, the second input terminal 4152 of the sequence adjustment unit can simultaneously receive the second transmitted data.

[0181] The first output terminal 4153 of the sequence adjustment unit serves as the first output terminal 412 of the i-th sequence adjustment submodule. The second output terminal 4154 of the sequence adjustment unit serves as the second output terminal 413 of the i-th sequence adjustment submodule. The first control terminal 4155 of the sequence adjustment unit can be used to receive a sequence adjustment control signal. The second control terminal 4156 of the sequence adjustment unit can be used to receive a second clock signal.

[0182] The sequence adjustment unit 415 can be used to adjust the sequence of the first transmission data and the second transmission data according to the sequence adjustment control signal and the second clock signal.

[0183] In one example, when the sequence adjustment control signal indicates that the data transmission order is reversed, the sequence adjustment unit 415 can, when the second clock signal is at the trigger level, use the (i+n)th bit of the first transmitted data as the high-order bit data Q. n+i And output through the first output terminal 4153 of the sequence adjustment unit. And take the i-th bit of the second transmitted data when the second clock signal is at the trigger level as the low-order bit data Q. iAnd output through the second output terminal 4154 of the sequence adjustment unit. It should be noted that the high-order bit data Q output by the i-th sequence adjustment unit 415... n+i This can be the (n+i-1)th bit of the data from bit 0 to bit 2n-1 transmitted by the sequence adjustment module. Also, the low-order bit data Q output by the i-th sequence adjustment unit 415. i It can be used as the (i-1)th bit of the data from the 0th bit to the (2n-1)th bit of the data transmitted by the sequence adjustment module. It should be noted that the first output terminal 4153 in this embodiment can also be called the high-bit data output terminal (i.e., the output port used to output high-bit data), and the second output terminal 4154 can also be called the low-bit data output terminal (i.e., the output port used to output low-bit data).

[0184] For the second clock signal, the trigger level transition time can be the moment when the second clock signal transitions from a non-trigger level to a trigger level. The trigger level can be the level at which the trigger sequence adjustment module performs signal latching. In one example, if high-level latching occurs, the trigger level can be high, and correspondingly, the non-trigger level is low. Similarly, if low-level latching occurs, the trigger level can be low, and the non-trigger level can be high.

[0185] Furthermore, the trigger level flip time of the second clock signal can be aligned with the occurrence time of the second trigger edge of the first clock signal.

[0186] For example, if the second clock signal corresponds to edge triggering, and the trigger level flipping time of the second clock signal is later than the occurrence time of the second trigger edge of the first clock signal, and the trigger level flipping time of the second clock signal is earlier than the occurrence time of the third trigger edge of the first clock signal, it can be determined that the trigger level flipping time of the second clock signal is aligned with the occurrence time of the second trigger edge of the first clock signal.

[0187] It should be noted that, in this embodiment, the trigger level flipping time of the second clock signal is later than the occurrence time of the second trigger edge of the first clock signal, which avoids the impact of transmission delay on data reading during actual circuit transmission. This ensures that the first and second transmitted data can be accurately read using the second clock signal at the trigger level, thus improving the accuracy of data processing.

[0188] As another example, if the second clock signal corresponds to level triggering, when the occurrence time of the second trigger edge of the first clock signal is within the duration of the trigger level of the second clock signal, it can be determined that the trigger level flip time of the second clock signal is aligned with the occurrence time of the second trigger edge of the first clock signal. For example, the trigger level flip time of the second clock signal can be earlier than, equal to, or later than the occurrence time of the second trigger edge of the first clock signal, and earlier than the occurrence time of the third trigger edge of the first clock signal.

[0189] In another example, when the sequence adjustment control signal indicates that the data transmission sequence is correct, the sequence adjustment unit 415 can, when the second clock signal is at the trigger level, use the i-th bit in the second transmitted data as the high-order bit data Q. n+i And output through the first output terminal 4153 of the sequence adjustment unit, and take the (i+n)th bit of the first transmitted data when the second clock signal is at the trigger level as the low bit data Q. i The data is output through the second bit output terminal 4154 of the sequence adjustment unit. It should be noted that the high-order bit data Q output by the sequence adjustment unit 415... n+i and low-order bit data Q i For relevant details, please refer to the above descriptions in the embodiments of this application, which will not be repeated here.

[0190] In this embodiment, the data processing unit 414 can generate first transmission data and second transmission data to be transmitted in parallel. Since the first transmission data transmits the (i+n)th bit on the second trigger edge of the first clock signal and the second transmission data transmits the ith bit on the second trigger edge of the first clock signal, the sequence adjustment unit 415 can simultaneously receive the ith bit and the (i+n)th bit of the parallel transmission. Furthermore, by adjusting the output ports of the ith bit and the (i+n)th bit of the parallel transmission, the ith bit and the (i+n)th bit can be flexibly adjusted, thereby improving the transmission accuracy of written and read data.

[0191] In one example Figure 15 A schematic diagram of the structure of a sequence adjustment unit provided in an embodiment of this application is shown. Figure 15 As shown, the sequence adjustment unit 415 may include: a data selection subunit 4157, a first output subunit 4158, and a second output subunit 4159.

[0192] The data selection subunit 4157 may have a first input terminal 4157A, a second input terminal 4157B, a first output terminal 4157C, and a second output terminal 4157D. The first input terminal 4157A of the data selection subunit serves as the first input terminal 4151 of the sequence adjustment unit and can be used to acquire first transmitted data. The second input terminal 4157B of the data selection subunit serves as the second input terminal 4152 of the sequence adjustment unit and can be used to acquire second transmitted data. The data selection subunit 4157 can be used to select and output the first and second transmitted data at their corresponding output terminals according to a sequence adjustment control signal. Specifically, when the sequence adjustment control signal indicates that the data transmission order is reversed, the first transmitted data is output at the first output terminal 4157C, and the second transmitted data is output at the second output terminal 4157D. When the sequence adjustment control signal indicates that the data transmission order is correct, the second transmitted data is output at the first output terminal 4157C, and the first transmitted data is output at the second output terminal 4157D.

[0193] The first output subunit 4158 may include an input terminal 4158A, a control terminal 4158B, and an output terminal 4158C. The input terminal 4158A of the first output subunit is connected to the first output terminal 4157C of the data selection subunit and can be used to receive the transmission data selected and output by the first output terminal 4157C of the data selection subunit. The control terminal 4158B of the first output subunit can be used to receive a second clock signal. The output terminal 4158C of the first output subunit serves as the first output terminal 4153 of the sequence adjustment unit. The first output subunit 4158 can be used to output the transmission data received by the input terminal 4158A of the first output subunit through the output terminal 4158C when the second clock signal is at a trigger level.

[0194] The second output subunit 4159 may include an input terminal 4159A, a control terminal 4159B, and an output terminal 4159C. The input terminal 4159A of the second output subunit is connected to the second output terminal 4157D of the data selection subunit. The control terminal 4159B of the second output subunit is used to receive a second clock signal. For example, the second clock signal can be received by connecting the control terminal 4159B of the second output subunit to the control terminal 4158B of the first output subunit. The output terminal 4159C of the second output subunit serves as the second output terminal 4154 of the sequence adjustment unit. When the second clock signal is at a trigger level, the second output subunit 4159 outputs the transmitted data received at its input terminal 4159A through its output terminal 4159C.

[0195] The sequence adjustment control signal can be determined based on the value of a preset bit in the burst sequence field. The preset bit is used to characterize whether the data transmission order is reversed. The burst sequence field is obtained by decoding the read / write command. It should be noted that the sequence adjustment control signal can be found in the relevant descriptions in the above sections of the embodiments of this disclosure, and will not be repeated here.

[0196] Through the embodiments of this application, the first transmission data and the second transmission data can be transmitted to the corresponding output subunit through the data selection subunit according to whether the data is reversed. Under the control of the second clock signal, the first output subunit and the second output subunit output the bit data adjusted to the correct output order at the same trigger time, thereby realizing the correct parallel output of bit data and improving the accuracy of data transmission.

[0197] In an optional example, Figure 16 A schematic diagram of an exemplary sequence adjustment module provided in an embodiment of this application is shown. Figure 16 As shown, the data processing unit 414 may include a first D flip-flop D1 and a second D flip-flop D2.

[0198] The first D flip-flop D1 may have a third input terminal (the D port of the first D flip-flop D1), a third non-inverting output terminal (the Q port of the first D flip-flop D1), and a third inverting output terminal (the Q port of the first D flip-flop D1). Port), the fifth control terminal (the C port of the first D flip-flop D1).

[0199] The third input terminal serves as the input terminal of the data processing unit 414, and can be used to receive the i-th bit and the (i+n)-th bit serially transmitted in each data transmission cycle. The fifth control terminal can be used to receive the first clock signal CLK1. The third in-phase output terminal serves as the first output terminal 4142 of the data processing unit, and can be used to output the first transmitted data DATA1. For example, the first D flip-flop D1 can be used to adjust the i-th bit in each data transmission cycle to be transmitted on the first trigger edge of the first clock signal CLK1, and to adjust the (i+n)-th bit in each data transmission cycle to be transmitted on the second trigger edge of the first clock signal, to obtain the first transmitted data DATA1.

[0200] The second D flip-flop D2 can have a fourth input terminal (D port of the second D flip-flop D2), a fourth non-inverting output terminal (Q port of the second D flip-flop D2), and a fourth inverting output terminal (Q port of the second D flip-flop D2). The system has a first input terminal (the C port of the second D flip-flop D2), a sixth control terminal (the C port of the second D flip-flop D2), and a fourth input terminal connected to the third non-inverting output terminal. The fourth input terminal can be used to receive the first transmitted data DATA1. The sixth control terminal is connected to the fifth control terminal and can be used to receive the first clock signal CLK1. The fourth non-inverting output terminal serves as the second output terminal 4143 of the data processing unit and can be used to output the second transmitted data DATA2. For example, the second D flip-flop D2 can be used to delay the i-th bit of the first transmitted data DATA1 from the first trigger edge of the first clock signal to the second trigger edge of the first clock signal, and to delay the (i+n)-th bit of the first transmitted data from the second trigger edge of the first clock signal to the third trigger edge of the first clock signal, thus obtaining the second transmitted data DATA2.

[0201] It should be noted that, since a D flip-flop can output data from the D port to the output terminal Q when the input clock signal is at the trigger edge, for the first D flip-flop D1 in this embodiment, when the first clock signal CLK1 is at the first trigger edge, the i-th bit received at the D port can be transmitted to the output terminal Q, and when the first clock signal CLK1 is at the second trigger edge, the (i+n)-th bit received at the D port can be transmitted to the output terminal Q. That is, the first transmitted data DATA1 output from the output terminal Q of the first D flip-flop D1 is the i-th bit during the first time period between the occurrence of the first trigger edge and the occurrence of the second trigger edge of the first clock signal, and is the (i+n)-th bit during the second time period between the occurrence of the second and third trigger edges.

[0202] Furthermore, regarding the second D flip-flop D2, due to a certain transmission delay between the first D flip-flop D1 and the second D flip-flop D2, when the first clock signal CLK1 is at the second trigger edge, the data at the D port of the second D flip-flop D2 is still the i-th bit. At this time, the i-th bit can be transmitted to the output terminal Q of the second D flip-flop D2. Similarly, when the first clock signal CLK1 is at the third trigger edge, the data at the D port of the second D flip-flop D2 is still the (i+n)-th bit. At this time, the (i+n)-th bit can be transmitted to the output terminal Q of the second D flip-flop D2. In other words, the second transmitted data DATA2 output by the output terminal Q of the second D flip-flop D2 has the i-th bit during the second time period between the occurrence of the second and third trigger edges of the first clock signal, and the (i+n)-th bit during the third time period between the occurrence of the second and third trigger edges.

[0203] It should be noted that the embodiments of this application may also employ other circuit methods that enable the i-th bit and the (i+n)-th bit to be transmitted in parallel as two data items, and no specific limitation is made thereto.

[0204] In this embodiment, the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle can be adjusted from serial transmission to parallel transmission of two data streams within the time period between the second trigger edge and the third trigger edge of the first clock signal using a series-connected first D flip-flop D1 and second D flip-flop D2. Since the first D flip-flop D1 and second D flip-flop D2 are logic devices, the integration density of the semiconductor memory is ensured while the accuracy of data processing is guaranteed.

[0205] In an optional example, the sequential adjustment control signal may include a first control sub-signal CA3B and a second control sub-signal CA3, wherein the first control sub-signal CA3B and the second control sub-signal CA3 may be inverse signals of each other.

[0206] For example, Figure 17 This diagram illustrates the signal and data transmission timing involved in an exemplary sequence adjustment circuit provided in an embodiment of this application. Figure 17 As shown, when the data transmission order is reversed, for example, as indicated by the first control sub-signal CA3B and the second control sub-signal CA3 corresponding to the first read cycle, the first control sub-signal CA3B is at a low level and the second control sub-signal CA3 is at a high level. When the data transmission order is correct, for example, as indicated by the first control sub-signal CA3B and the second control sub-signal CA3 corresponding to the write cycle or the second read cycle, the first control sub-signal CA3B is at a high level and the second control sub-signal CA3 is at a low level.

[0207] The data selection subunit 5156 may include a first data selector M1 and a second data selector M2.

[0208] The first data selector M1 may include a first data input terminal (corresponding to port 0), a second data input terminal (corresponding to port 1), a first control terminal, and a first selection output terminal. The first data input terminal is connected to the third data input terminal (corresponding to port 0) of the second data selector M2, serving as the first input terminal 4157A of the data selection subunit, and can be used to receive the first transmitted data DATA1. The second data input terminal is connected to the fourth data input terminal (corresponding to port 1) of the second data selector M2, serving as the second input terminal 4157B of the data selection subunit, and can be used to receive the second transmitted data DATA2. The first control terminal can be used to receive a first control sub-signal CA3B. The first selection output terminal serves as a first output terminal, and can be used to output the first transmitted data DATA1 when the first control sub-signal is at a second level, and to output the second transmitted data DATA2 when the first control sub-signal is at a third level. For example, as... Figure 16 As shown, the first data input terminal corresponds to port 0. That is, if it is in a low-level state, the first data input terminal and the first selection output terminal are connected. At this time, the second level state is low and the third level state is high. Alternatively, if the first data input terminal corresponds to port 1, then if it is in a high-level state, the first data input terminal and the first selection output terminal are connected. At this time, the second level state is high and the third level state is low.

[0209] The second data selector M2 may include a third data input terminal (corresponding to port 0), a fourth data input terminal (corresponding to port 1), a second control terminal, and a second selection output terminal. The third data input terminal can be used to receive the first transmitted data DATA1. The fourth data input terminal can be used to receive the second transmitted data DATA2. The second control terminal can be used to receive the second control sub-signal CA3. The second selection output terminal, as a second output terminal, can be used to output the first transmitted data DATA1 when the second control sub-signal CA3 is in the second level state, and to output the second transmitted data DATA2 when the second control sub-signal CA3 is in the third level state. It should be noted that the specific details of the second data selector M2 can be found in the relevant description of the first data selector, and will not be repeated here.

[0210] In this embodiment, see continue to refer to Figure 17When the data transmission order is reversed, the second control sub-signal CA3 is in a high-level state (third-level state), the second data selector M2 outputs the second transmitted data DATA2, and the first control sub-signal CA3B is in a low-level state (second-level state), and the first data selector M1 outputs the first transmitted data DATA1. Conversely, when the data transmission order is correct, the second control sub-signal CA3 is in a low-level state (second-level state), the second data selector M2 outputs the first transmitted data DATA1, and the first control sub-signal CA3B is in a high-level state (third-level state), and the first data selector M1 outputs the second transmitted data DATA2.

[0211] It should be noted that other devices with data selection functions can also be used to implement the above functions in the embodiments of this application, which will not be elaborated here.

[0212] In this embodiment, under the control of two sequential adjustment control signals—the first control sub-signal and the second control sub-signal—the two data selectors respectively select the output of the first and second transmitted data. This allows for flexible selection of the first and second transmitted data to be output at corresponding output terminals based on whether the transmitted data is inverted, improving the flexibility of data adjustment. Furthermore, the small size and area of ​​the data selectors ensure the high integration density of the semiconductor memory.

[0213] In an optional example, see [link to example]. Figure 16 The first output subunit 4158 may include a first latch D3.

[0214] The first latch D3 may have a first input terminal (the D port of the first latch D3), a first non-inverting output terminal (the Q port of the first latch D3), and a first inverting output terminal (the Q port of the first latch D3). The system comprises three input terminals: a port (4158A) and a third control terminal (EN port of the first latch D3). The first input terminal serves as the input terminal 4158A of the first output sub-unit. The third control terminal serves as the control terminal 4158B of the first output sub-unit, and the first non-inverting output terminal serves as the output terminal 4158C of the first output sub-unit.

[0215] For example, the first latch D3 can be implemented as an edge-triggered D flip-flop. Alternatively, the first latch D3 can also be implemented as a level-triggered D flip-flop. It should be noted that the first latch D3 can also be implemented as other devices with latching functions, without specific limitations.

[0216] It should be noted that, since the third control terminal can be used to receive the second clock signal, and since the first input terminal receives the second transmitted data DATA2 when the data transmission order is correct, the i-th bit in the second transmitted data DATA2 can be latched using the second clock signal. Furthermore, since the data output from the first in-phase output terminal is used as the i-th bit, the latched i-th bit can still be used as the i-th bit. When the data transmission order is reversed, the first input terminal receives the first transmitted data DATA1, and the (i+n)-th bit in the first transmitted data DATA1 can be latched. This (i+n)-th bit is then used as the new i-th bit.

[0217] In an optional example, see [link to example]. Figure 16 The second output subunit 4159 may include a second latch D4.

[0218] The second latch D4 may have a second input terminal (the D port of the second latch D4), a second non-inverting output terminal (the Q port of the second latch D4), and a second inverting output terminal (the Q port of the second latch D4). The second input terminal serves as the input terminal 4159A of the second output sub-unit, the fourth control terminal serves as the control terminal 4159B of the second sub-unit, and the second in-phase output terminal serves as the output terminal 4159C of the second output sub-unit.

[0219] It should be noted that the second latch D4 is implemented in a similar manner to the first latch D3. For details, please refer to the above description of the first latch D3 in the embodiments of this application, which will not be repeated here.

[0220] It should be noted that, since the fourth control terminal can be used to receive the second clock signal, and since the second input terminal receives the first transmitted data DATA1 when the data transmission order is correct, the (i+n)th bit of the first transmitted data DATA1 can be latched using the second clock signal. Furthermore, since the data output from the second in-phase output terminal is considered the (i+n)th bit, the latched (i+n)th bit can still be used as the (i+n)th bit. When the data transmission order is reversed, the first input terminal receives the second transmitted data DATA2, and the ith bit of the second transmitted data DATA2 can be latched. This latched ith bit is then used as the new (i+n)th bit.

[0221] Through the two embodiments described above, by using the first latch D3 and the second latch D4, when the second clock signal is at the trigger level, the first transmission data and the second transmission data, which are adjusted to the normal order and transmitted in parallel after the second trigger edge of the first clock signal, are simultaneously latched and output, ensuring the accurate transmission of the data to be verified.

[0222] To facilitate understanding, the following will combine... Figure 17 right Figure 16 The sequence adjustment module shown is explained in its entirety. Specifically, the correct transmission order for the 16-bit data is pre-set to be bits 8 through 15 first.

[0223] like Figure 17 As shown, during the first and second read cycles, the read control command RD_EN is high (first level state) and the write control command WR_EN is low (fourth level state). Conversely, during the write cycle, the read control command RD_EN is low and the write control command WR_EN is high.

[0224] In the first read cycle of a data transmission sequence error, the data DATA0 received by the sequence adjustment module includes bits 0-7 transmitted in parallel first, and bits 8-15 transmitted in parallel later. At this time, under the control of the first clock signal CLK1, eight first D flip-flops D1 can modulate and output first transmission data DATA1 based on the input data DATA0. The first transmission data DATA1 includes bits 0-7 transmitted in parallel starting from the first trigger edge of the first clock signal, and bits 8-15 transmitted in parallel starting from the second trigger edge of the first clock signal. Under the control of the first clock signal CLK1, eight second D flip-flops D2 can modulate and output second transmission data DATA2 based on the first transmission data DATA1. The second transmission data DATA2 includes bits 0-7 transmitted in parallel starting from the second trigger edge of the first clock signal, and bits 8-15 transmitted in parallel starting from the third trigger edge of the first clock signal.

[0225] At this time, the eight first data selectors M1 and the eight second data selectors M2 can select the first transmission data DATA1 as the first selected data DATA_H and the second transmission data DATA2 as the second selected data DATA_L when the first control sub-signal CA3B is at a low level (second level state) and the second control sub-signal CA3 is at a high level (third level state).

[0226] By using eight first latches D3, the bits of the first selected data DATA_H can be output as the 15th to 8th bits when the second clock signal is high (trigger level). For example, for the first latch D3 in the i-th sequence adjustment submodule 41, the first selected data DATA_H it receives is the (i+n)th bit when the second clock signal is high; correspondingly, the first latch D3 in the i-th sequence adjustment submodule 41 outputs the (i+n)th bit.

[0227] Using eight second latches D4, the bits of the second selected data DATA_L, i.e., bits 0-7, can be output when the second clock signal is high (trigger level). For example, for the second latch D4 in the i-th sequence adjustment submodule 41, the second selected data DATA_L it receives is the i-th bit when the second clock signal is high; correspondingly, the second latch D4 in the i-th sequence adjustment submodule 41 outputs the i-th bit.

[0228] Correspondingly, the corrected data DATA3 can be obtained through the eight first latches D3 and the second latches D4. The corrected data DATA3 is then input into the CRC check module to obtain the check data CRC_CODE.

[0229] In the second read cycle where the data transmission sequence is correct, the data DATA0 received by the sequence adjustment module includes bits 8-15 transmitted in parallel first, and bits 0-7 transmitted in parallel later. At this time, under the control of the first clock signal CLK1, eight first D flip-flops D1 can modulate and output the first transmission data DATA1 based on the input data DATA0. The first transmission data DATA1 includes bits 8-15 transmitted in parallel starting from the first trigger edge of the first clock signal, and bits 0-7 transmitted in parallel starting from the second trigger edge of the first clock signal. Under the control of the first clock signal CLK1, eight second D flip-flops D2 can modulate and output the second transmission data DATA2 based on the first transmission data DATA1. The second transmission data DATA2 includes bits 8-15 transmitted in parallel starting from the second trigger edge of the first clock signal, and bits 0-7 transmitted in parallel starting from the third trigger edge of the first clock signal.

[0230] At this time, the eight first data selectors M1 and the eight second data selectors can use the second transmission data DATA2 as the first selected data DATA_H and the first transmission data DATA1 as the second selected data DATA_L when the first control sub-signal CA3B is at a low level (third level state) and the second control sub-signal CA3 is at a high level (second level state).

[0231] The first selected data DATA_H, i.e., bits 15-8, can be output via eight first latches D3 when the second clock signal is high (trigger level). Similarly, the second selected data DATA_L, i.e., bits 0-7, can be output via eight second latches D4 when the second clock signal is high (trigger level). It should be noted that the first latches D3 and second latches D4 are described in the relevant sections of the embodiments of this application, and will not be repeated here.

[0232] Correspondingly, the corrected data DATA3 can be obtained through the eight first latches D3 and the second latches D4. The corrected data DATA3 is then input into the CRC check module to obtain the check data CRC_CODE.

[0233] It should be noted that the processing principle of the write cycle is similar to that of the second read cycle, so it will not be elaborated further.

[0234] This application's embodiments are combined with Figures 10 to 17 The data processing circuit shown can be used to adjust the data transmission order of data before it is input to the data reading or writing order adjustment module. This adjustment allows the data to be input to the verification module in the correct transmission order, thus ensuring the correctness of the data input to the verification module. This, in turn, improves the correctness of the output verification data and further enhances the reliability of data reading and writing.

[0235] In some embodiments, the data processing circuit provided in this application may further include a signal splicing module 50. The signal splicing module 50 is connected to the data output module 30.

[0236] Figure 18 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown. Figure 18 As shown, the signal splicing module 50 can be used to acquire the read verification data and read data output by the data output module 30, splice the read verification data and read data to obtain the data to be read, and output the data to be read. Optionally, the data to be read can be transmitted to the controller of the semiconductor memory. For example, after receiving the data to be read, the controller of the semiconductor memory can split the data to be read into two parts: read data and read verification data, and use the read verification data to verify the correctness of the read data.

[0237] In this embodiment, the verification data and the read data are used as the data to be read. When data correctness verification is required in the subsequent process, the read data can be verified based on the read verification data in the data to be read, which improves the convenience and accuracy of the verification.

[0238] In some embodiments, the data processing circuit provided in this application may further include a verification module 60. The verification module 60 is connected to the data output module 30.

[0239] Figure 18 A schematic diagram of another data processing circuit provided in an embodiment of this application is shown. See also Figure 18The verification module 60 can be used to obtain the write verification data output by the data output module 30 and the baseline verification data of the write data, compare the write verification data with the baseline verification data, and obtain the verification result of the write data.

[0240] For example, the data to be written obtained from the controller of the semiconductor memory can be separated into two parts: write data and write verification data. Write verification data is generated by a data processing circuit, and the separated write verification data is used as benchmark verification data. If the generated write verification data matches the benchmark verification data, the verification passes, and the write data can be stored in the semiconductor memory cell. If the generated write verification data does not match the benchmark verification data, the verification fails, and a failure strategy can be implemented, such as requesting the write data again from the controller.

[0241] This embodiment allows for the verification of the correctness of the written data, thereby improving the accuracy of the written data.

[0242] Based on the same inventive concept, this application also provides a data processing method, as shown in the following embodiments. Since the principle of this method embodiment in solving the problem is similar to that of the above-described device embodiment, the implementation of this method embodiment can refer to the implementation of the above-described device embodiment, and repeated details will not be described again.

[0243] Figure 19 This document illustrates a flowchart of a data processing method according to an embodiment of this application, as shown below. Figure 19 As shown, the data processing method 1900 may include S1910 to S1930.

[0244] S1910, when the received write control command is in the first level state, the data selection module receives and outputs write data; and when the received read control command is in the first level state, it receives and outputs read data.

[0245] S1920, the verification module receives written data or read data, performs verification processing on the written data or read data, obtains written verification data or read verification data, and outputs written verification data or read verification data.

[0246] S1930, the data output module receives write verification data or read verification data, outputs write verification data when the write control command is in the first level state, and outputs read verification data when the read control command is in the first level state.

[0247] The data processing method provided in this application embodiment can, when the write control command is in the first level state, receive write data through the data selection module, send it to the verification module for verification processing, and output the write verification data obtained from the verification processing using the data output module. Similarly, when the read control command is in the first level state, receive read data through the data selection module, perform verification processing on it using the verification module, and output the read verification data obtained from the verification processing using the data output module. Since it is not necessary to use different data processing circuits to process write data and read data separately, only one data processing circuit can select write data or read data for verification processing according to the write control command and read control command. This data processing circuit generates write verification data for verifying the correctness of the write data or read verification data for verifying the correctness of the read data, thereby ensuring the reliability of data reading and writing while considering the size of the semiconductor memory.

[0248] In some embodiments, after S1910 and before S1920, the data processing method may further include step A1.

[0249] Step A1: The sequence adjustment module receives the write data or read data output by the data selection module, and performs a data transmission sequence adjustment operation on the write data or read data according to the sequence adjustment control signal, and outputs the write data or read data after adjusting it to the correct transmission sequence.

[0250] Accordingly, S1920 can specifically include:

[0251] The verification module receives write data or read data that has been adjusted to the correct transmission order; performs verification processing on the write data or read data that has been adjusted to the correct transmission order to obtain write verification data or read verification data; and outputs write verification data or read verification data.

[0252] In some embodiments, the data selection module transmits 2n bits of write data or read data to the sequence adjustment module through n data lines in one data transmission cycle. Bits (n+1) to 2n are transmitted in parallel, bits 1 to n are transmitted in parallel, and bits i and i+n are transmitted serially using the same data line. n is a positive integer greater than or equal to 1, and i is a positive integer greater than or equal to 1 and less than or equal to n.

[0253] The sequence adjustment module can include n parallel sequence adjustment sub-modules. Each sequence adjustment sub-module has a data input terminal, a first output terminal, and a second output terminal. The data input terminal of the i-th sequence adjustment sub-module is connected to the data selection module. The first and second output terminals of the i-th sequence adjustment sub-module are connected to the verification module.

[0254] Accordingly, step A1 may include:

[0255] The data input terminal of the i-th order adjustment submodule receives the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle, where i is a positive integer greater than or equal to 1 and less than or equal to n. The i-th order adjustment submodule adjusts the order of the i-th bit and the (i+n)-th bit in each data transmission cycle to the correct transmission order. Specifically, when the order adjustment control signal indicates that the data transmission order is reversed, the order of the i-th bit and the (i+n)-th bit received in each data transmission cycle is swapped. When the order adjustment control signal indicates that the data transmission order is correct, the order of the i-th bit and the (i+n)-th bit received in each data transmission cycle remains unchanged. The first and second output terminals of the i-th order adjustment submodule output the i-th bit and the (i+n)-th bit adjusted to the correct transmission order to the verification module, respectively.

[0256] In some embodiments, the i-th sequence adjustment submodule may include a data processing unit and a sequence adjustment unit. The data processing unit has an input terminal, a first output terminal, a second output terminal, and a first control terminal, with the input terminal serving as the data input terminal of the i-th sequence adjustment submodule. The sequence adjustment unit has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first control terminal, and a second control terminal; the first input terminal of the sequence adjustment unit is connected to the first output terminal of the data processing unit, and the second input terminal of the sequence adjustment unit is connected to the second output terminal of the data processing unit. The first output terminal of the sequence adjustment unit serves as the first output terminal of the i-th sequence adjustment submodule, and the second output terminal of the sequence adjustment unit serves as the second output terminal of the i-th sequence adjustment submodule.

[0257] Accordingly, step A1 may specifically include:

[0258] The first input terminal of the data processing unit receives the i-th bit and the (i+n)-th bit transmitted serially in each data transmission cycle; the control terminal of the data processing unit receives a first clock signal; in response to the control of the first clock signal, the data processing unit generates first transmission data and second transmission data to be transmitted in parallel based on the i-th bit and the (i+n)-th bit received serially; wherein, the first transmission data includes the (i+n)-th bit obtained by sampling at the second trigger edge of the first clock signal, and the second transmission data includes the i-th bit obtained by sampling at the second trigger edge of the first clock signal; the first output terminal and the second output terminal of the data processing unit are used to output the first transmission data and the second transmission data in parallel;

[0259] The first input terminal of the sequence adjustment unit receives the first transmitted data, and the second input terminal of the sequence adjustment unit receives the second transmitted data; the first control terminal of the sequence adjustment unit receives the sequence adjustment control signal; the second control terminal of the sequence adjustment unit receives the second clock signal; the sequence adjustment unit adjusts the sequence of the first transmitted data and the second transmitted data according to the sequence adjustment control signal and the second clock signal.

[0260] Specifically, when the sequence adjustment control signal indicates that the data transmission order is reversed, and the second clock signal is at the trigger level, the (i+n)th bit of the first transmitted data is output as the high-order bit data through the first output terminal of the sequence adjustment unit, and the ith bit of the second transmitted data is output as the low-order bit data through the second output terminal of the sequence adjustment unit. Conversely, when the sequence adjustment control signal indicates that the data transmission order is correct, and the second clock signal is at the trigger level, the ith bit of the second transmitted data is output as the high-order bit data through the first output terminal of the sequence adjustment unit, and the (i+n)th bit of the first transmitted data is output as the low-order bit data through the second bit output terminal of the sequence adjustment unit.

[0261] The trigger level of the second clock signal flips at a time that is aligned with the occurrence of the second trigger edge of the first clock signal. The trigger level of the second clock signal flips at the moment when the second clock signal flips from the non-trigger level to the trigger level.

[0262] In some embodiments, the sequence adjustment unit may include a data selection subunit, a first output subunit, and a second output subunit. The data selection subunit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the data selection subunit serves as the first input terminal of the sequence adjustment unit, and the second input terminal of the data selection subunit serves as the second input terminal of the sequence adjustment unit. The first output subunit includes an input terminal, a control terminal, and an output terminal. The input terminal of the first output subunit is connected to the first output terminal of the data selection subunit, and the output terminal of the first output subunit serves as the first output terminal of the sequence adjustment unit. The second output subunit includes an input terminal, a control terminal, and an output terminal. The input terminal of the second output subunit is connected to the second output terminal of the data selection subunit, and the control terminal of the second output subunit is used to receive a second clock signal. The control terminal of the first output subunit is connected, and the output terminal of the second output subunit serves as the second output terminal of the sequence adjustment unit.

[0263] Step A1 may include:

[0264] The first input terminal of the data selection subunit acquires the first transmission data; the second input terminal of the data selection subunit acquires the second transmission data; the data selection subunit selects and outputs the first transmission data and the second transmission data at their corresponding output terminals according to the sequence adjustment control signal. Specifically, when the sequence adjustment control signal indicates that the data transmission order is reversed, the first transmission data is output at the first output terminal and the second transmission data is output at the second output terminal. When the sequence adjustment control signal indicates that the data transmission order is correct, the second transmission data is output at the first output terminal and the first transmission data is output at the second output terminal.

[0265] When the second clock signal is at the trigger level, the first output subunit outputs the transmitted data received at the input terminal of the first output subunit through the output terminal of the first output subunit.

[0266] The second output subunit is used to output the transmitted data received at the input terminal of the second output subunit through the output terminal of the second output subunit when the second clock signal is at the trigger level.

[0267] The sequence adjustment control signal is determined based on the value of the preset bit in the burst sequence field. The preset bit is used to characterize whether the data transmission order is reversed. The burst sequence field is obtained by decoding the read and write commands.

[0268] In some embodiments, the sequential adjustment control signal may include a first control sub-signal and a second control sub-signal, wherein the first control sub-signal and the second control sub-signal are opposite signals to each other.

[0269] The data selection subunit may include:

[0270] The first data selector includes a first data input terminal, a second data input terminal, a first control terminal, and a first selection output terminal. The first data input terminal serves as the first input terminal of the data selection subunit and is used to receive first transmitted data. The second data input terminal serves as the second input terminal of the data selection subunit and is used to receive second transmitted data. The first control terminal is used to receive a first control sub-signal. The first selection output terminal serves as the first output terminal of the data selection subunit and is used to output the first transmitted data when the first control sub-signal is at a second level, and to output the second transmitted data when the first control sub-signal is at a third level.

[0271] The second data selector includes a third data input terminal, a fourth data input terminal, a second control terminal, and a second selection output terminal. The third data input terminal is connected to the first data input terminal and is used to receive first transmitted data. The fourth data input terminal is connected to the second data input terminal and is used to receive second transmitted data. The second control terminal is used to receive a second control sub-signal. The second selection output terminal serves as the second output terminal of the data selection sub-unit and is used to output the first transmitted data when the second control sub-signal is at a second level, and to output the second transmitted data when the second control sub-signal is at a third level.

[0272] In some embodiments, the first output subunit may include:

[0273] The first latch may have a first input terminal, a first non-inverting output terminal, a first inverting output terminal, and a third control terminal. The first input terminal serves as the input terminal of the first output sub-unit, the third control terminal serves as the control terminal of the first output sub-unit, and the first non-inverting output terminal serves as the output terminal of the first output sub-unit.

[0274] In some embodiments, the second output subunit may include:

[0275] The second latch may have a second input terminal, a second non-inverting output terminal, a second inverting output terminal, and a fourth control terminal. The second input terminal serves as the input terminal of the second output sub-unit, the fourth control terminal serves as the control terminal of the second output sub-unit, and the second non-inverting output terminal serves as the output terminal of the second output sub-unit.

[0276] In some embodiments, the output terminal of the data processing unit may include a third output sub-port and a fourth output sub-port, and the control terminal of the data processing unit may include a first control sub-port and a second control sub-port.

[0277] The data processing unit may include:

[0278] The first D flip-flop may have a third input terminal, a third non-inverting output terminal, a third inverting output terminal, and a fifth control terminal. The third input terminal serves as the input terminal of the data processing unit and is used to receive the i-th bit and the (i+n)-th bit transmitted serially in each data transmission cycle. The fifth control terminal is used to receive the first clock signal. The third non-inverting output terminal serves as the first output terminal of the data processing unit and is used to output the first transmitted data.

[0279] The second D flip-flop may have a fourth input terminal, a fourth non-inverting output terminal, a fourth inverting output terminal, and a sixth control terminal. The fourth input terminal is connected to the third non-inverting output terminal and is used to receive the first transmitted data. The sixth control terminal is connected to the fifth control terminal and is used to receive the first clock signal. The fourth non-inverting output terminal serves as the second output terminal of the data processing unit and is used to output the second transmitted data.

[0280] In some embodiments, data is written or read from the data selection module to the verification module through n data lines in one data transmission cycle. The (n+1)th to the 2nth bits of the 2n bits are transmitted in parallel, the 1st to the nth bits are transmitted in parallel, and the ith bit and the (i+n)th bit are transmitted serially using the same data line. n is a positive integer greater than or equal to 1, and i is a positive integer greater than or equal to 1 and less than or equal to n.

[0281] The data selection module can include n data selection sub-modules that are set in parallel.

[0282] S1910 may include: when the write control command is in the first level state, the i-th data selection submodule outputs the i-th bit and the (i+n)-th bit of the received write data in each data transmission cycle; or, when the read control command is in the first level state, it outputs the i-th bit and the (i+n)-th bit of the received read data in each data transmission cycle.

[0283] In some embodiments, the i-th data selection submodule may include: a write data selection unit, a read data selection unit, and a signal output unit.

[0284] The write data selection unit may include a write data control terminal, a write data input terminal, and a write data output terminal. The write data control terminal is used to receive write control commands; the write data input terminal is used to receive the i-th write sub-data, which is the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle; the write data selection unit is used to respond to the write control command and output the i-th write sub-data at the write data output terminal, wherein the i-th write sub-data is output when the write control command is in the first level state.

[0285] The read data selection unit may include a read data control terminal, a read data input terminal, and a read data output terminal. The read data control terminal is used to receive read control commands; the read data input terminal is used to receive the i-th read sub-data, which is the i-th bit and the (i+n)-th bit of the read data being transmitted continuously in each data transmission cycle; the read data selection unit is used to respond to the read control command and output the i-th read sub-data at the read data output terminal, wherein, when the read control command is in the first level state, the i-th read sub-data is output;

[0286] The signal output unit may include a first input terminal, a second input terminal, and an output terminal. The first input terminal of the signal output unit is connected to the write data output terminal, the second input terminal of the signal output unit is connected to the read data output terminal, and the output terminal of the signal output unit is used to output the i-th write sub-data or the i-th read sub-data.

[0287] In some embodiments, the write data selection unit includes a first AND gate, which includes a fifth input terminal, a sixth input terminal, and a third output terminal; the fifth input terminal serves as the write data input terminal; the sixth output terminal serves as the write data control terminal; and the third output terminal serves as the write data output terminal.

[0288] The read data selection unit includes a second AND gate, which includes a seventh input terminal, an eighth input terminal, and a fourth output terminal; the seventh input terminal serves as the read data input terminal; the eighth input terminal serves as the read data control terminal; and the fourth output terminal serves as the read data output terminal.

[0289] The signal output unit includes a NOR gate and a NOT gate. The NOR gate includes a ninth input terminal, a tenth input terminal, and a fifth output terminal. The ninth input terminal serves as the first input terminal of the signal output unit, and the tenth input terminal serves as the second input terminal of the signal output unit. The NOT gate includes an eleventh input terminal and a sixth output terminal. The eleventh input terminal is connected to the fifth output terminal, and the sixth output terminal serves as the output terminal of the signal output unit.

[0290] In some embodiments, the data output module may include a first output submodule and a second output submodule.

[0291] The first output submodule includes a write control terminal, a first verification data input terminal, and a write verification data output terminal. The second output submodule includes a read control terminal, a second verification data input terminal, and a read verification data output terminal.

[0292] S1930 may include:

[0293] The write control terminal receives the write control command, the first verification data input terminal receives the write verification data or read verification data output by the verification module, and the write verification data output terminal outputs the write verification data when the write control command is in the first level state.

[0294] The read control terminal receives the read control command, the second verification data input terminal receives the write verification data or read verification data output by the verification module, and the read verification data output terminal outputs the read verification data when the read control command is in the first level state.

[0295] In some embodiments, the first output submodule may include a third AND gate, which includes a twelfth input, a thirteenth input, and a seventh output. The twelfth input serves as the first verification data input, the thirteenth input serves as the write control input, and the seventh output serves as the write verification data output.

[0296] The second output submodule may include a fourth AND gate, which includes a fourteenth input, a fifteenth input, and an eighth output. The fourteenth input serves as the second verification data input, the fifteenth input serves as the read control input, and the eighth output serves as the read verification data output.

[0297] In some embodiments, the data processing circuit may further include step A2.

[0298] Step A2: The signal splicing module acquires the readout verification data and the readout data, splices the readout verification data and the readout data to obtain the data to be read, and outputs the data to be read.

[0299] In some embodiments, the data processing circuit may further include step A3.

[0300] Step A3: The verification module obtains the written verification data and the baseline verification data of the written data, compares the written verification data with the baseline verification data, and obtains the verification result of the written data.

[0301] The data processing method provided in this application embodiment can be used to implement the data processing circuits provided in the above-described device embodiments. The implementation principle and technical effect are similar, and will not be described in detail here for the sake of brevity.

[0302] Based on the same inventive concept, embodiments of this application also provide a semiconductor memory. The semiconductor memory may include data processing circuitry and a semiconductor memory cell array.

[0303] The data processing circuit can be found in the above-mentioned parts of the embodiments of this application. Figures 1-18 The relevant explanations will not be repeated here.

[0304] The semiconductor memory can be any of the following dynamic random access memories: DDR4 SDRAM, LPDDR4 SDRAM, DDR5 SDRAM, LPDDR4 SDRAM, etc., without any specific limitation.

[0305] It should be noted that semiconductor memory can also be other types of memory besides dynamic random access memory, without specific limitations.

[0306] In one example Figure 20 A schematic diagram of the structure of a semiconductor memory provided in an embodiment of this application is shown. Figure 20 As shown, the semiconductor memory 2000 may include a data processing circuit 2010 and a memory cell array 2020. The dashed lines indicate the data transmission path for writing data, and the solid lines indicate the data transmission path for reading data.

[0307] Specifically, written data can be stored in the corresponding storage unit array 2020 after passing the verification by the data processing circuit 2010. Read data can be processed by the data processing circuit 2011 to generate data to be read and output.

[0308] The semiconductor memory provided in this application embodiment can, when the write control command is in the first level state, receive write data through the data selection module, send it to the verification module for verification processing, and output the write verification data obtained from the verification processing using the data output module. Similarly, when the read control command is in the first level state, receive read data through the data selection module, perform verification processing on it using the verification module, and output the read verification data obtained from the verification processing using the data output module. Since it is not necessary to use different data processing circuits to process the write and read data separately, only one data processing circuit can select the write or read data for verification processing according to the write and read control commands. This data processing circuit generates write verification data for verifying the correctness of the write data or read verification data for verifying the correctness of the read data, thereby ensuring the reliability of data reading and writing while considering the size of the semiconductor memory.

[0309] Those skilled in the art will understand that various aspects of this application can be implemented as a system, method, or program product. Therefore, various aspects of this application can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, collectively referred to herein as a "circuit," "module," or "system."

[0310] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The method embodiments are described relatively simply, and relevant parts can be found in the description section of the circuit embodiments. This application is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application. Furthermore, for the sake of brevity, detailed descriptions of known methods and techniques are omitted here.

[0311] In the several embodiments provided in this application, it should be understood that the disclosed circuits, methods, and memories can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some ports, and may be electrical, mechanical, or other forms.

[0312] The units described as separate components may or may not be physically separate. Similarly, the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0313] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0314] Therefore, the scope of protection of this application should be determined by the scope of the claims. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary technical means in the art that are not disclosed in this application. The specification and embodiments are to be regarded as exemplary only, and the true scope and spirit of this application are indicated by the appended claims.

Claims

1. A data processing circuit, characterized in that, include: The data selection module is used to receive and output the write data when the received write control command is in the first level state. When the received read control command is in the first level state, the read data is received and the read data is output. The verification module is used to receive the written data or the read data; The written data or the read data is verified to obtain write verification data or read verification data; and the write verification data or the read verification data is output. The data output module is used to receive the written verification data or the read verification data; When the write control command is in the first level state, the write verification data is output; When the read control command is in the first level state, the read verification data is output; The data processing circuit further includes: The sequence adjustment module is connected to the verification module through the data selection module. The sequence adjustment module is used to receive the written data or the read data output by the data selection module, and perform a data transmission sequence adjustment operation on the written data or the read data according to the sequence adjustment control signal, and output the written data or the read data after adjusting it to the correct transmission sequence. Specifically, the verification module is used for: Receive write data or read data that has been adjusted to the correct transmission order; perform verification processing on the write data or read data that has been adjusted to the correct transmission order to obtain write verification data or read verification data; and output the write verification data or read verification data. The data selection module transmits 2n bits of the written data or the read data to the sequence adjustment module through n data lines in one data transmission cycle. Bits (n+1) to 2n are transmitted in parallel, bits 1 to n are transmitted in parallel, and bits 1 and (i+n) are transmitted serially using the same data line. n is a positive integer greater than or equal to 1, and i is a positive integer greater than or equal to 1 and less than or equal to n. The sequence adjustment module includes n parallel sequence adjustment sub-modules, each of which has a data input terminal, a first output terminal, and a second output terminal. The data input terminal of the i-th order adjustment submodule is connected to the data selection module and is used to receive the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle, where i is a positive integer greater than or equal to 1 and less than or equal to n. The i-th order adjustment submodule is used to adjust the order of the i-th bit and the (i+n)-th bit in each data transmission cycle to the correct transmission order. When the order adjustment control signal indicates that the data order is reversed, the order of the i-th bit and the (i+n)-th bit received in each data transmission cycle is swapped. When the order adjustment control signal indicates that the data transmission order is correct, the order of the i-th bit and the (i+n)-th bit received in each data transmission cycle remains unchanged. The first and second output terminals of the i-th order adjustment submodule are connected to the verification module and are respectively used to output the i-th bit and the (i+n)-th bit that have been adjusted to the correct transmission order to the verification module; The i-th order adjustment submodule includes: The data processing unit includes an input terminal, a first output terminal, a second output terminal, and a control terminal. The input terminal of the data processing unit serves as the data input terminal of the i-th sequence adjustment submodule, and is used to receive the i-th bit and the (i+n)-th bit transmitted serially in each data transmission cycle. The control terminal of the data processing unit receives a first clock signal. In response to the control of the first clock signal, the data processing unit generates first transmission data and second transmission data for parallel transmission based on the serially received i-th bit and the (i+n)-th bit. The first transmission data includes the (i+n)-th bit data sampled at the second trigger edge of the first clock signal, and the second transmission data includes the i-th bit data sampled at the second trigger edge of the first clock signal. The first output terminal and the second output terminal of the data processing unit are used to output the first transmission data and the second transmission data in parallel. A sequence adjustment unit is provided with a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first control terminal, and a second control terminal. The first input terminal of the sequence adjustment unit is connected to the first output terminal of the data processing unit and is used to receive the first transmitted data. The second input terminal of the sequence adjustment unit is connected to the second output terminal of the data processing unit and is used to receive the second transmitted data. The first output terminal of the sequence adjustment unit serves as the first output terminal of the i-th sequence adjustment submodule, and the second output terminal of the sequence adjustment unit serves as the second output terminal of the i-th sequence adjustment submodule. The first control terminal of the sequence adjustment unit is used to receive a sequence adjustment control signal, and the second control terminal of the sequence adjustment unit is used to receive a second clock signal. The sequence adjustment unit adjusts the data according to the sequence adjustment control signal and the... The second clock signal is used to adjust the order of the first and second transmitted data. When the order adjustment control signal indicates that the data transmission order is reversed, and the second clock signal is at the trigger level, the (i+n)th bit of the first transmitted data is output as the high-order bit data through the first output terminal of the order adjustment unit, and the ith bit of the second transmitted data is output as the low-order bit data through the second output terminal of the order adjustment unit. When the order adjustment control signal indicates that the data transmission order is correct, and the second clock signal is at the trigger level, the ith bit of the second transmitted data is output as the high-order bit data through the first output terminal of the order adjustment unit, and the (i+n)th bit of the first transmitted data is output as the low-order bit data through the second output terminal of the order adjustment unit. Wherein, the trigger level flipping time of the second clock signal is aligned with the occurrence time of the second trigger edge of the first clock signal, and the trigger level flipping time of the second clock signal is the moment when the second clock signal flips from the non-trigger level to the trigger level.

2. The circuit according to claim 1, characterized in that, The sequence adjustment unit includes: A data selection subunit is provided with a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the data selection subunit serves as the first input terminal of the sequence adjustment unit and is used to acquire the first transmitted data. The second input terminal of the data selection subunit serves as the second input terminal of the sequence adjustment unit and is used to acquire the second transmitted data. The data selection subunit selects and outputs the first transmitted data and the second transmitted data at corresponding output terminals according to the sequence adjustment control signal. Specifically, when the sequence adjustment control signal indicates that the data transmission order is reversed, the first transmitted data is output at the first output terminal and the second transmitted data is output at the second output terminal. When the sequence adjustment control signal indicates that the data transmission order is correct, the second transmitted data is output at the first output terminal and the first transmitted data is output at the second output terminal. The first output subunit includes an input terminal, a control terminal, and an output terminal. The input terminal of the first output subunit is connected to the first output terminal of the data selection subunit. The control terminal of the first output subunit is used to receive the second clock signal. The output terminal of the first output subunit serves as the first output terminal of the sequence adjustment unit. When the second clock signal is at a trigger level, the first output subunit outputs the transmitted data received at its input terminal through its output terminal. The second output subunit includes an input terminal, a control terminal, and an output terminal; the input terminal of the second output subunit is connected to the second output terminal of the data selection subunit; the control terminal of the second output subunit is connected to the control terminal of the first output subunit; the output terminal of the second output subunit serves as the second output terminal of the sequence adjustment unit; the second output subunit is used to output the transmitted data received at the input terminal of the second output subunit through the output terminal of the second output subunit when the second clock signal is at the trigger level. The sequence adjustment control signal is determined based on the value of a preset bit in the burst sequence field. The preset bit is used to characterize whether the data transmission order is reversed. The burst sequence field is obtained by decoding the read and write commands.

3. The circuit according to claim 2, characterized in that, The sequence adjustment control signal includes a first control sub-signal and a second control sub-signal, wherein the first control sub-signal and the second control sub-signal are inverse signals of each other; The data selection subunit includes: A first data selector includes a first data input terminal, a second data input terminal, a first control terminal, and a first selection output terminal. The first data input terminal serves as the first input terminal of the data selection subunit and is used to receive the first transmitted data. The second data input terminal serves as the second input terminal of the data selection subunit and is used to receive the second transmitted data. The first control terminal is used to receive the first control sub-signal. The first selection output terminal serves as the first output terminal of the data selection subunit and is used to output the first transmitted data when the first control sub-signal is at a second level, and to output the second transmitted data when the first control sub-signal is at a third level. The second data selector includes a third data input terminal, a fourth data input terminal, a second control terminal, and a second selection output terminal. The third data input terminal is connected to the first data input terminal and is used to receive the first transmitted data. The fourth data input terminal is connected to the second data input terminal and is used to receive the second transmitted data. The second control terminal is used to receive the second control sub-signal. The second selection output terminal serves as the second output terminal of the data selection sub-unit and is used to output the first transmitted data when the second control sub-signal is at the second level state, and to output the second transmitted data when the second control sub-signal is at the third level state.

4. The circuit according to claim 2, characterized in that, The first output subunit includes: The first latch has a first input terminal, a first non-inverting output terminal, and a third control terminal. The first input terminal serves as the input terminal of the first output sub-unit, the third control terminal serves as the control terminal of the first output sub-unit, and the first non-inverting output terminal serves as the output terminal of the first output sub-unit. And, the second output subunit includes: The second latch has a second input terminal, a second non-inverting output terminal, and a fourth control terminal. The second input terminal serves as the input terminal of the second output sub-unit, the fourth control terminal serves as the control terminal of the second output sub-unit, and the second non-inverting output terminal serves as the output terminal of the second output sub-unit.

5. The circuit according to claim 1, characterized in that, The data processing unit includes: The first D flip-flop has a third input terminal, a third non-inverting output terminal, and a fifth control terminal. The third input terminal serves as the input terminal of the data processing unit and is used to receive the i-th bit and the (i+n)-th bit serially transmitted in each data transmission cycle. The fifth control terminal is used to receive the first clock signal. The third non-inverting output terminal serves as the first output terminal of the data processing unit and is used to output the first transmitted data. The second D flip-flop has a fourth input terminal, a fourth non-inverting output terminal, and a sixth control terminal. The fourth input terminal is connected to the third non-inverting output terminal and is used to receive the first transmitted data. The sixth control terminal is connected to the fifth control terminal and is used to receive the first clock signal. The fourth non-inverting output terminal serves as the second output terminal of the data processing unit and is used to output the second transmitted data.

6. The circuit according to claim 1, characterized in that, The written data or the read data is transmitted from the data selection module to the verification module through n data lines in one data transmission cycle. The (n+1)th to the 2nth bits of the 2n bits are transmitted in parallel, the 1st to the nth bits are transmitted in parallel, and the ith bit and the (i+n)th bit are transmitted serially using the same data line. n is a positive integer greater than or equal to 1, and i is a positive integer greater than or equal to 1 and less than or equal to n. The data selection module includes n data selection sub-modules configured in parallel. The i-th data selection submodule is configured to output the i-th bit and the (i+n)-th bit of the received write data in each data transmission cycle when the write control command is in the first level state; or, when the read control command is in the first level state, to output the i-th bit and the (i+n)-th bit of the received read data in each data transmission cycle.

7. The circuit according to claim 6, characterized in that, The i-th data selection submodule includes: The write data selection unit includes a write data control terminal, a write data input terminal, and a write data output terminal. The write data control terminal is used to receive the write control command; the write data input terminal is used to receive the i-th write sub-data, which is the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle; the write data selection unit is used to respond to the write control command and output the i-th write sub-data at the write data output terminal, wherein the i-th write sub-data is output when the write control command is in the first level state; The read data selection unit includes a read data control terminal, a read data input terminal, and a read data output terminal. The read data control terminal is used to receive the read control command; the read data input terminal is used to receive the i-th read sub-data, wherein the i-th read sub-data is the i-th bit and the (i+n)-th bit continuously transmitted in each data transmission cycle; the read data selection unit is used to respond to the read control command and output the i-th read sub-data at the read data output terminal, wherein the i-th read sub-data is output when the read control command is in the first level state; The signal output unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the signal output unit is connected to the write data output terminal, the second input terminal of the signal output unit is connected to the read data output terminal, and the output terminal of the signal output unit is used to output the i-th write sub-data or the i-th read sub-data.

8. The circuit according to claim 7, characterized in that, The write data selection unit includes a first AND gate, which includes a fifth input terminal, a sixth input terminal, and a third output terminal; the fifth input terminal serves as the write data input terminal; the sixth input terminal serves as the write data control terminal; and the third output terminal serves as the write data output terminal. The readout data selection unit includes a second AND gate, which includes a seventh input terminal, an eighth input terminal, and a fourth output terminal; the seventh input terminal serves as the readout data input terminal; the eighth input terminal serves as the readout data control terminal; and the fourth output terminal serves as the readout data output terminal. The signal output unit includes a NOR gate and a NOT gate. The NOR gate includes a ninth input terminal, a tenth input terminal, and a fifth output terminal. The ninth input terminal serves as the first input terminal of the signal output unit, and the tenth input terminal serves as the second input terminal of the signal output unit. The NOT gate includes an eleventh input terminal and a sixth output terminal. The eleventh input terminal is connected to the fifth output terminal, and the sixth input terminal serves as the output terminal of the signal output unit.

9. The circuit according to claim 1, characterized in that, The data output module includes: The first output submodule includes a write control terminal, a first verification data input terminal, and a write verification data output terminal. The write control terminal is used to receive the write control command. The first verification data input terminal is used to receive the write verification data or the read verification data output by the verification module. The write verification data output terminal is used to output the write verification data when the write control command is in the first level state. The second output submodule includes a read control terminal, a second verification data input terminal, and a read verification data output terminal. The read control terminal is used to receive the read control command. The second verification data input terminal is connected to the first verification data input terminal and is used to receive the write verification data or the read verification data output by the verification module. The read verification data output terminal is used to output the read verification data when the read control command is in the first level state.

10. The circuit according to claim 9, characterized in that, The first output submodule includes a third AND gate, which includes a twelfth input, a thirteenth input, and a seventh output. The twelfth input serves as the first verification data input, the thirteenth input serves as the write control input, and the seventh output serves as the write verification data output. The second output submodule includes a fourth AND gate, which includes a fourteenth input, a fifteenth input, and an eighth output. The fourteenth input serves as the second verification data input, the fifteenth input serves as the read control input, and the eighth output serves as the read verification data output.

11. The circuit according to any one of claims 1-10, characterized in that, The circuit also includes: The signal splicing module is used to acquire the readout verification data output by the data output module and the readout data, splice the readout verification data and the readout data to obtain the data to be read, and output the data to be read. And / or, a verification module is used to obtain the write verification data output by the data output module and the baseline verification data of the write data, compare the write verification data with the baseline verification data, and obtain the verification result of the write data.

12. A data processing circuit, characterized in that, include: The data selection module is used to receive and output the write data when the received write control command is in the first level state. When the received read control command is in the first level state, the read data is received and the read data is output. The verification module is used to receive the written data or the read data; The written data or the read data is verified to obtain write verification data or read verification data; and the write verification data or the read verification data is output. The data output module is used to receive the written verification data or the read verification data; When the write control command is in the first level state, the write verification data is output; When the read control command is in the first level state, the read verification data is output; The written data or the read data is transmitted from the data selection module to the verification module through n data lines in one data transmission cycle. The (n+1)th to the 2nth bits of the 2n bits are transmitted in parallel, the 1st to the nth bits are transmitted in parallel, and the ith bit and the (i+n)th bit are transmitted serially using the same data line. n is a positive integer greater than or equal to 1, and i is a positive integer greater than or equal to 1 and less than or equal to n. The data selection module includes n data selection sub-modules configured in parallel. The i-th data selection submodule is configured to output the i-th bit and the (i+n)-th bit of the received write data in each data transmission cycle when the write control command is in the first level state; or, when the read control command is in the first level state, to output the i-th bit and the (i+n)-th bit of the received read data in each data transmission cycle. The i-th data selection submodule includes: The write data selection unit includes a write data control terminal, a write data input terminal, and a write data output terminal. The write data control terminal is used to receive the write control command; the write data input terminal is used to receive the i-th write sub-data, which is the i-th bit and the (i+n)-th bit transmitted in each data transmission cycle; the write data selection unit is used to respond to the write control command and output the i-th write sub-data at the write data output terminal, wherein the i-th write sub-data is output when the write control command is in the first level state; The read data selection unit includes a read data control terminal, a read data input terminal, and a read data output terminal. The read data control terminal is used to receive the read control command; the read data input terminal is used to receive the i-th read sub-data, wherein the i-th read sub-data is the i-th bit and the (i+n)-th bit continuously transmitted in each data transmission cycle; the read data selection unit is used to respond to the read control command and output the i-th read sub-data at the read data output terminal, wherein the i-th read sub-data is output when the read control command is in the first level state; The signal output unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the signal output unit is connected to the write data output terminal, the second input terminal of the signal output unit is connected to the read data output terminal, and the output terminal of the signal output unit is used to output the i-th write sub-data or the i-th read sub-data.

13. A data processing method, characterized in that, The data processing circuit as described in any one of claims 1-12 includes: When the received write control command is in the first level state, the data selection module receives and outputs the write data; and when the received read control command is in the first level state, it receives and outputs the read data. The verification module receives the written data or the read data, performs verification processing on the written data or the read data to obtain written verification data or read verification data, and outputs the written verification data or the read verification data. The data output module receives the write verification data or the read verification data, outputs the write verification data when the write control command is in the first level state, and outputs the read verification data when the read control command is in the first level state.

14. A semiconductor memory, characterized in that, include: The data processing circuit as described in any one of claims 1-12; Storage cell array.

Images