Simulation method, device, power line topology network, test circuit and storage medium

Abstract

The application provides a simulation method, device, power line topology network, test circuit and storage medium. The method comprises: generating a power line topology network according to a power line layout, the power line topology network comprising a plurality of first layer metal lines arranged horizontally, a plurality of second layer metal lines arranged longitudinally, power supply sub-nodes and parasitic elements, the parasitic elements being located between two power supply sub-nodes, determining minimum voltages of power input nodes of each circuit module in a circuit corresponding to the power line topology network, the power input node being one of the power supply sub-nodes in each circuit module, and performing timing simulation according to the minimum voltages of the power input nodes of each circuit module and an integrated circuit post-simulation circuit netlist. Thus, the influence of the power line voltage drop on the timing parameters of the integrated circuit can be evaluated through normal timing simulation, and the simulation accuracy and simulation speed are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a simulation method and device, a power line topology network, a test circuit and a storage medium. BACKGROUND

[0002] At present, in the design of integrated circuits, the design process of integrated circuits includes circuit design and pre-simulation, layout design and post-simulation processes. Among them, the circuit design is to complete the design of the circuit according to the circuit function, and the pre-simulation is to simulate the circuit function, including the simulation of parameters such as power consumption, current, voltage, temperature, input and output characteristics. The pre-simulation does not consider the influence of the parasitic capacitance and resistance generated by the metal line in the circuit, and after the layout design is completed, the parasitic capacitance and resistance is extracted and added to the circuit for post-simulation and circuit design verification and optimization. If the verification fails, the layout design is adjusted until the final layout is determined.

[0003] In the above simulation process, on the one hand, repeated verification is required, and on the other hand, due to the very large size of the netlist of the layout post-simulation including the parasitic capacitance and resistance, the simulation time is long, resulting in very slow simulation speed. SUMMARY

[0004] The present application provides a simulation method, device, power line topology network, test circuit and storage medium to improve the simulation speed and accuracy.

[0005] In a first aspect, the present application provides a simulation method, comprising:

[0006] generating a power line topology network according to a power line layout, the power line topology network comprising a plurality of first layer metal lines arranged horizontally, a plurality of second layer metal lines arranged vertically, power sub-nodes and parasitic elements, the parasitic elements being located between two power sub-nodes;

[0007] determining the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, the power input node being one of the power sub-nodes in the each circuit module;

[0008] performing timing simulation according to the minimum voltage of the power input node of the each circuit module and the integrated circuit post-simulation circuit netlist.

[0009] Optionally, the power line topology network is generated according to the power line layout, comprising:

[0010] determining the intersection of the first layer metal lines and the second layer metal lines as the power sub-nodes;

[0011] The parasitic elements are arranged between each two of the power supply sub-nodes, and the parasitic elements include a first parasitic resistor, a second parasitic resistor and a parasitic capacitor, wherein a first end of the first parasitic resistor is connected to a first power supply sub-node, a second end of the first parasitic resistor is connected to a first end of the second parasitic resistor and a first end of the parasitic capacitor; a second end of the second parasitic resistor is connected to a second power supply sub-node; and a second end of the parasitic capacitor is connected to a ground terminal.

[0012] The power supply line topology network is obtained according to the first layer of metal lines, the second layer of metal lines, the power supply sub-nodes and the parasitic elements.

[0013] Optionally, the first parasitic resistor and the second parasitic resistor have a resistance value of R / 2, and the parasitic capacitor has a capacitance value of C.

[0014] The R and the C are determined by the following formulas:

[0015] R = Rsh * L / W;

[0016] C = Cu * L * W;

[0017] wherein the L is a length of a metal line between the power supply sub-nodes, the W is a width of the metal line between the power supply sub-nodes, the Rsh is a square resistance of the metal, and the Cu is a capacitance value per unit area.

[0018] Optionally, the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power supply line topology network is determined by:

[0019] a first simulation is performed on the power supply line topology network with a preset power supply voltage to obtain a current of each circuit module in a circuit corresponding to the power supply line topology network;

[0020] a circuit simulation is performed according to the parasitic elements between the power supply sub-nodes and the current of each circuit module to obtain a voltage waveform of the power input node of each circuit module;

[0021] the minimum voltage of the power input node of each circuit module is determined according to the voltage waveform of the power input node of each circuit module.

[0022] Optionally, the circuit simulation is performed according to the parasitic elements between the power supply sub-nodes and the current of each circuit module to obtain a voltage waveform of the power input node of each circuit module, including:

[0023] a current source is set for each circuit module according to the current of each circuit module to obtain a test circuit;

[0024] Based on the parasitic elements between the power supply sub-nodes and the current of each circuit module, the test circuit is simulated to obtain the voltage waveform of the power input node of each circuit module.

[0025] Optionally, the timing simulation based on the minimum voltage of the power input node of each circuit module and the netlist of the integrated circuit post-simulation circuit includes:

[0026] The minimum voltage of the power input node of each circuit module is added to the power input node of each circuit module to obtain an embedded minimum voltage circuit.

[0027] Timing simulation of the circuit with embedded minimum voltage is performed based on the integrated circuit post-simulation circuit netlist.

[0028] Secondly, this application provides a simulation device, including: a memory and a processor;

[0029] The memory is used to store the executable instructions of the processor;

[0030] The processor is configured as follows:

[0031] A power line topology network is generated based on the power line layout. The power line topology network includes multiple first-layer metal lines arranged horizontally, multiple second-layer metal lines arranged vertically, power sub-nodes, and parasitic elements. The parasitic elements are located between two power sub-nodes.

[0032] Determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, wherein the power input node is one of the power sub-nodes in each circuit module;

[0033] Timing simulation is performed based on the minimum voltage of the power input node of each circuit module and the network list of the integrated circuit post-simulation circuit.

[0034] Thirdly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described in the first aspect and any of the possible embodiments of the first aspect.

[0035] Fourthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect and any of the possible embodiments of the first aspect.

[0036] Fifthly, this application provides a power line topology network, comprising:

[0037] The plurality of first layer metal wires are arranged transversely, the plurality of second layer metal wires are arranged longitudinally, the power supply sub-nodes and the parasitic element are located between two of the power supply sub-nodes.

[0038] The intersection of the first layer metal wires and the second layer metal wires is the power supply sub-node.

[0039] Optionally, the parasitic element includes a first parasitic resistor, a second parasitic resistor and a parasitic capacitor.

[0040] The first end of the first parasitic resistor is connected to a first power supply sub-node, the second end of the first parasitic resistor is connected to the first end of the second parasitic resistor and the first end of the parasitic capacitor.

[0041] The second end of the second parasitic resistor is connected to a second power supply sub-node.

[0042] The second end of the parasitic capacitor is connected to a ground terminal.

[0043] Optionally, the resistance values of the first parasitic resistor and the second parasitic resistor are both R / 2, and the capacitance value of the parasitic capacitor is C.

[0044] The R and the C are determined by the following formulas:

[0045] R = Rsh * L / W;

[0046] C = Cu * L * W;

[0047] Wherein, the L is the length of the metal wire between the power supply sub-nodes, the W is the width of the metal wire between the power supply sub-nodes, the Rsh is the square resistance of the metal, and the Cu is the capacitance value per unit area.

[0048] In a sixth aspect, the present application provides a test circuit, including at least one current source and the power line topology network as described in any one of the possible implementation manners of the fifth aspect and the fifth aspect.

[0049] Wherein, the input current of each of the current sources is the current of each circuit module in the circuit corresponding to the power line topology network.

[0050] The number of the current sources is the same as the number of the circuit modules included in the circuit corresponding to the power line topology network.

[0051] Optionally, the first end of each of the current sources is connected to a power input node of each of the circuit modules, the second end of each of the current sources is connected to a ground terminal, and the power input node is one of the power supply sub-nodes in each of the circuit modules.

[0052] Optionally, the current of each circuit module in the circuit corresponding to the power line topology network is obtained by a first simulation based on the power line topology network with a preset power supply voltage.

[0053] The simulation method, apparatus, power line topology network, test circuit, and storage medium provided in this application first generate a power line topology network based on the power line layout. Then, they determine the minimum voltage of the power input node for each circuit module in the circuit corresponding to the power line topology network. Finally, they perform timing simulation based on the minimum voltage of the power input node for each circuit module and the integrated circuit post-simulation circuit netlist. The integrated circuit post-simulation circuit netlist is a layout-based post-simulation netlist excluding parasitic capacitance and resistance, meaning the simulation time is approximately the same as the pre-simulation time excluding power supply parasitic effects. Therefore, post-simulation results can be obtained quickly, improving simulation speed. Furthermore, the timing simulation considers the minimum voltage of the power input node for each circuit module. The difference between the minimum voltage and the ideal power supply voltage is the power line voltage drop. Therefore, the impact of the power line voltage drop on the timing parameters of the integrated circuit can be evaluated through normal timing simulation, improving simulation accuracy. This achieves a trade-off between simulation accuracy and simulation speed. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 A flowchart illustrating a simulation method provided in an embodiment of this application;

[0056] Figure 2 This is a schematic diagram of a power line layout;

[0057] Figure 3 According to Figure 2 The diagram shown illustrates a power line topology network generated from the power line layout.

[0058] Figure 4 According to Figure 2 The diagram shown illustrates a power line topology network generated from the power line layout.

[0059] Figure 5 To and Figure 3 The circuit diagram shown is a schematic diagram of the circuit modules included in the power line topology network.

[0060] Figure 6 A flowchart illustrating a simulation method provided in an embodiment of this application;

[0061] Figure 7 for Figure 4 a corresponding test circuit structure schematic diagram;

[0062] Figure 8 a flowchart of an emulation method provided by the embodiment of the present application;

[0063] Figure 9 a circuit structure schematic diagram obtained by adding the minimum voltage of the power input node of each circuit module to the power input node of each circuit module;

[0064] Figure 10 a structure schematic diagram of an emulation device provided by the embodiment of the present application;

[0065] Figure 11 a structure schematic diagram of an emulation device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0067] In the existing integrated circuit design flow, in post-simulation, if the post-simulation netlist including the parasitic capacitance resistance of the power line layout is very large, which leads to very long simulation time, and cannot meet the actual project requirements. If the post-simulation netlist does not include the parasitic elements of the power line, the influence of the power layout parasitic on the timing characteristics of the circuit cannot be correctly evaluated, thereby reducing the simulation accuracy. To solve this problem, the simulation method, device, power line topology network, test circuit and storage medium provided by the present application, in the simulation method provided by the present application, first, the power line topology network is generated according to the power line layout, then the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network is determined, and finally, the timing simulation is performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist, wherein the integrated circuit post-simulation circuit netlist is a netlist of layout post-simulation not including parasitic capacitance resistance, that is, the simulation time is approximately the same as the pre-simulation time not including the power parasitic effect, so that the post-simulation result can be quickly obtained, the simulation speed is improved, and the timing simulation considers the minimum voltage of the power input node of each circuit module. The difference between the minimum voltage and the ideal power voltage is the power line voltage drop, so the influence of the power line voltage drop (industry term is IR-Drop) on the timing parameters of the integrated circuit can be evaluated through normal timing simulation, which can improve the simulation accuracy, wherein the timing parameters include timing parameters such as delay, thereby achieving a compromise between simulation accuracy and simulation speed.

[0068] The simulation method provided by the present application can be applied before layout design, during layout design, and the power line voltage drop in the power line layout will affect the timing parameters of the integrated circuit. The simulation method provided by the present application generates a power line topology network according to the power line layout, determines the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, that is, determines the power line voltage drop, and performs timing simulation according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist. The influence of the power line voltage drop on the timing parameters of the integrated circuit can be evaluated through the simulation result, which can provide guidance for integrated circuit design. When the layout design is completed, the parasitic resistance and parasitic capacitance of the entire circuit are extracted and post-simulation is performed. The timing result can be checked again according to the post-simulation result to provide the final guidance for the layout design. Therefore, the error of the layout design can be reduced, and the development cycle and development cost of the integrated circuit design can be reduced.

[0069] The specific process / concrete structure of the simulation method, device, power line topology network, test circuit and storage medium provided by the present application will be described in detail below through specific embodiments.

[0070] Figure 1This is a flowchart illustrating a simulation method provided in an embodiment of this application. The execution entity of the simulation method in this embodiment can be a simulation device or simulation equipment, and it can be applied before layout design, such as... Figure 1 As shown, the simulation method in this embodiment may include:

[0071] S101. Generate a power line topology network based on the power line layout. The power line topology network includes multiple first-layer metal lines arranged horizontally, multiple second-layer metal lines arranged vertically, power sub-nodes, and parasitic elements. The parasitic elements are located between two power sub-nodes.

[0072] Specifically, Figure 2 This is a schematic diagram of a power line layout, such as... Figure 2 As shown, the power line layout consists of four first-layer metal lines M1 and three second-layer metal lines M2. The first-layer metal lines M1 can be located above or below the second-layer metal lines M2, and each first-layer metal line M1 and each second-layer metal line has an intersection point.

[0073] Generate a power line topology network based on the power line layout, in order to Figure 2 Taking the power line layout shown as an example, Figure 3 According to Figure 2 The diagram shown illustrates a power line topology network generated from the power line layout, as follows: Figure 3 As shown, the power line topology network includes multiple first-layer metal lines M1 arranged horizontally, multiple second-layer metal lines M2 arranged vertically, power sub-nodes (VDD11-VDD31), and parasitic elements Q. The intersection of the first-layer metal lines and the second-layer metal lines in the power line layout is the power sub-node. The parasitic element is located between two power sub-nodes, and there is one parasitic element between every two power sub-nodes.

[0074] One feasible approach is to generate a power line topology network based on the power line layout. Specifically, this can be achieved by:

[0075] S1011. The intersection of the first layer of metal wire and the second layer of metal wire is determined as the power supply sub-node.

[0076] S1012. A parasitic element is provided between every two power sub-nodes. The parasitic element includes a first parasitic resistor, a second parasitic resistor, and a parasitic capacitor. The first end of the first parasitic resistor is connected to the first power sub-node, and the second end of the first parasitic resistor is connected to the first end of the second parasitic resistor and the first end of the parasitic capacitor. The second end of the second parasitic resistor is connected to the second power sub-node, and the second end of the parasitic capacitor is connected to the ground terminal.

[0077] S1013. Based on the first layer of metal wires, the second layer of metal wires, power sub-nodes, and parasitic elements, the power line topology network is obtained.

[0078] With reference to the power line layout shown in Figure 2 As shown in Figure 4 A schematic diagram of a power line topology network generated according to Figure 2 As shown in Figure 4 A parasitic element Q is arranged between each two power sub-nodes, the parasitic element Q includes a first parasitic resistor R1, a second parasitic resistor R2 and a parasitic capacitor C1. Taking the parasitic element between the power sub-node VDD31 and the power sub-node VDD32 as an example, a first end of the first parasitic resistor R1 is connected to the first power sub-node VDD31, a second end of the first parasitic resistor R1 is connected to a first end of the second parasitic resistor R2 and a first end of the parasitic capacitor C1, a second end of the second parasitic resistor R2 is connected to the second power sub-node VDD32, and a second end of the parasitic capacitor C1 is connected to a ground terminal.

[0079] In the formula, the resistance values of the first parasitic resistor R1 and the second parasitic resistor R2 are both R / 2, and the capacitance value of the parasitic capacitor is C, R and C are determined by the following formula:

[0080] R = Rsh * L / W;

[0081] C = Cu * L * W;

[0082] In the formula, L is the length of the metal line between the power sub-nodes, W is the width of the metal line between the power sub-nodes, Rsh is the square resistance of the metal, and Cu is the capacitance value per unit area.

[0083] It can be understood that the length and width of the metal line between different power sub-nodes are different. When generating the power line topology network for subsequent simulation, the initial length and the initial width of the metal line between the power sub-nodes can be set according to the empirical value to obtain an initial power line topology network. Then, the initial power line topology network is subjected to timing simulation through S102 and S103. According to the simulation result, the length and the width of the metal line between each two power sub-nodes in the initial power line topology network can be adjusted to obtain an adjusted power line topology network. The adjusted power line topology network is subjected to timing simulation through S102 and S103 again until a power line topology network in which the influence of the power line voltage drop on the timing parameters of the integrated circuit is small is determined through simulation. The specific adjustment rules of the length and the width of the metal line between each two power sub-nodes are not limited in the embodiments of the present application.

[0084] S102, determining the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, the power input node being one of the power sub-nodes in each circuit module.

[0085] Specifically, with reference to Figure 3 or Figure 4The shown power line topology network is taken as an example, Figure 5 For the power line topology network shown in Figure 3 The circuit corresponding to the shown power line topology network includes the circuit module schematic diagram shown in Figure 5 As shown in Figure 3 The circuit corresponding to the shown power line topology network includes 6 circuit modules (X1-X6), and the power input node of each circuit module is Figure 5 VDD shown in the figure, it can be seen that the power input node of each circuit module is one of the power sub-nodes in each circuit module.

[0086] Among them, the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network is determined, so that Figure 5 The circuit module shown in the figure is taken as an example, that is, the minimum voltage of the power input node VDD of each circuit module in the circuit modules X1-X6 is determined.

[0087] S103, timing simulation according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist.

[0088] Among them, the integrated circuit post-simulation circuit netlist is a netlist after layout simulation without parasitic capacitance and resistance, and the simulation result obtained by S103 is the timing analysis result considering the maximum voltage drop.

[0089] The simulation method provided by the embodiment, by first generating a power line topology network according to a power line layout, then determining the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, and finally performing timing simulation according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist, wherein the integrated circuit post-simulation circuit netlist is a netlist after layout simulation without parasitic capacitance and resistance, that is, the simulation time is approximately the same as the pre-simulation time without considering the power parasitic effect, so that the post-simulation result can be quickly obtained, the simulation speed is improved, and the timing simulation considers the minimum voltage of the power input node of each circuit module. The difference between the minimum voltage and the ideal power voltage is the power line voltage drop, so that the influence of the power line voltage drop on the timing parameters of the integrated circuit can be evaluated through normal timing simulation, the simulation accuracy can be improved, and the compromise between simulation accuracy and simulation speed is realized.

[0090] Figure 6 The flowchart of the simulation method provided by the embodiment of the application is shown in Figure 6 The simulation method of the embodiment is based on the method shown in Figure 5 The above S102 can be implemented by the following steps, which are optional based on the method shown in

[0091] S1021, first simulation is performed according to the power line topology network at a preset power supply voltage, and currents of each circuit module in the circuit corresponding to the power line topology network are obtained.

[0092] Specifically, taking the six circuit modules shown in FIG. 6 as an example, first simulation is performed according to the power line topology network shown in FIG. 6 at a preset power supply voltage, and currents of the six circuit modules are shown in Table 1 as follows: Figure 5 Figure 4 Specifically, taking the six circuit modules shown in FIG. 6 as an example, first simulation is performed according to the power line topology network shown in FIG. 6 at a preset power supply voltage, and currents of the six circuit modules are shown in Table 1 as follows:

[0093] Table 1: Currents of the six circuit modules

[0094] Circuit module Current X1 I1(t) X2 I2(t) X3 I3(t) X4 I4(t) X5 I5(t) X6 I6(t)

[0095] In the formula, the current In(t), n = 1, 2, …, 6 is a curve varying with time.

[0096] S1022, circuit simulation is performed according to the parasitic elements between the power supply sub-nodes and the currents of each circuit module, and voltage waveforms of the power supply input nodes of each circuit module are obtained.

[0097] As an implementable manner, S1022 can specifically include the following steps.

[0098] First, a current source is set for each circuit module according to the current of each circuit module, and a test circuit is obtained.

[0099] Specifically, a current source can be set for the power line topology network, one current source is set for each circuit module, the number of the current sources is the same as the number of the circuit modules included in the circuit corresponding to the power line topology network, and the input current of each set current source is the current In(t) of each circuit module, and the test circuit is obtained.

[0100] Taking the power line topology network shown in FIG. 6 as an example, Figure 4 Figure 7 a test circuit structure diagram corresponding to the power line topology network shown in FIG. 6 is shown in FIG. 7, and the test circuit of the embodiment is also called an IR drop test circuit, as shown in FIG. 7, the first end of each current source P is connected to the power supply input node of each circuit module, and the second end of each current source P is connected to the ground end. Figure 4 Figure 7 Taking the circuit module X1 as an example, the first end of the current source P is connected to the power supply input node VDD31 of the circuit module X1, and the second end of the current source P is connected to the ground end.

[0101] Then, circuit simulation is performed on the test circuit according to the parasitic elements between the power supply sub-nodes and the currents of each circuit module, and voltage waveforms of the power supply input nodes of each circuit module are obtained.

[0102] ​​​Specifically, after obtaining the test circuit, circuit simulation is performed on the test circuit to obtain the voltage waveform of the power input node of each circuit module. Figure 7 Taking the test circuit shown in FIG. 2 as an example, for each circuit module in the test circuit, for example, the circuit module X1, according to the current In(t) of the circuit module X1 and the parasitic element Q between the power sub-node VDD31 and the power sub-node VDD32 in the circuit module X1, circuit simulation is performed to obtain the voltage waveform VDD31(t) of the power input node VDD31 of the circuit module X1, which is taken as an example of one circuit module X1. It can be understood that simulation of the test circuit can obtain the voltage waveforms VDD31(t)-VDD24(t) of the power input nodes of the six circuit modules.

[0103] S1023, determining the minimum voltage of the power input node of each circuit module according to the voltage waveform of the power input node of each circuit module.

[0104] Specifically, the voltage waveform is a waveform diagram of the voltage value changing with time, and the minimum voltage value of each voltage waveform can be found according to the voltage waveform, that is, the minimum voltage of the power input node of each circuit module, which is the voltage at a certain time, denoted as VDDn min in Table 2 below. In Table 2, the minimum voltage of the power input node of each circuit module is denoted as VDDn min. Figure 7 The corresponding relationship between the current In(t) of each module in the test circuit shown in FIG. 2, the voltage waveform VDDn(t) of the power input node of each circuit module, and the minimum voltage VDDn min of the power input node of each circuit module.

[0105] Table 2

[0106]

[0107] The simulation method provided in this embodiment determines the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network by performing first simulation according to the power line topology network with a preset power voltage, performing circuit simulation according to the parasitic element between the power sub-nodes and the current of each circuit module, obtaining the voltage waveform of the power input node of each circuit module, and determining the minimum voltage of the power input node of each circuit module according to the voltage waveform of the power input node of each circuit module.

[0108] Figure 8 The flowchart of the simulation method provided in this embodiment is shown in FIG. 2. Figure 8As shown, the simulation method of the embodiment adds the minimum voltage of the power input node of each circuit module to the power input node of each circuit module to obtain a circuit embedded with the minimum voltage. Figure 6 Based on the method shown above, the S103 can be implemented by the following steps:

[0109] S1031, adding the minimum voltage of the power input node of each circuit module to the power input node of each circuit module to obtain a circuit embedded with the minimum voltage.

[0110] Specifically, Figure 9 The circuit structure diagram obtained by adding the minimum voltage of the power input node of each circuit module to the power input node of each circuit module.

[0111] S1032, performing timing simulation on the circuit embedded with the minimum voltage according to the post-simulation circuit netlist of the integrated circuit.

[0112] Specifically, the timing simulation is performed on the circuit embedded with the minimum voltage according to the post-simulation circuit netlist of the integrated circuit, and the simulation result obtained is the timing analysis result considering the maximum voltage drop effect. Through the simulation method of the embodiment, the influence of the power line voltage drop on the timing parameters of the integrated circuit is accurately evaluated without increasing the simulation time, all results are based on the post-simulation netlist of Spice and layout, ensuring the simulation accuracy, thereby realizing the compromise between simulation accuracy and simulation speed.

[0113] Figure 10 The structure diagram of a simulation device provided by the embodiment of the application is shown in the figure. Figure 10 As shown, the simulation device of the embodiment can include a generation module 11, a determination module 12, and a simulation module 13, wherein the generation module 11 is configured to generate a power line topology network according to a power line layout, the power line topology network includes a plurality of first layer metal lines arranged horizontally, a plurality of second layer metal lines arranged vertically, power sub-nodes, and parasitic elements, the parasitic elements are located between two power sub-nodes.

[0114] The determination module 12 is configured to determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network, the power input node being one of the power sub-nodes in each circuit module.

[0115] The simulation module 13 is configured to perform timing simulation according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit netlist of the integrated circuit.

[0116] Further, the generation module 11 is configured to determine the intersection of the first layer metal line and the second layer metal line as the power sub-node.

[0117] The parasitic elements are arranged between each two power supply sub-nodes, and the parasitic elements include a first parasitic resistor, a second parasitic resistor and a parasitic capacitor, wherein a first end of the first parasitic resistor is connected to the first power supply sub-node, a second end of the first parasitic resistor is connected to a first end of the second parasitic resistor and a first end of the parasitic capacitor; a second end of the second parasitic resistor is connected to the second power supply sub-node; and a second end of the parasitic capacitor is connected to a ground terminal.

[0118] The power supply line topology network is obtained according to the first layer metal line, the second layer metal line, the power supply sub-nodes and the parasitic elements.

[0119] Further, the resistance values of the first parasitic resistor and the second parasitic resistor are both R / 2, and the capacitance value of the parasitic capacitor is C.

[0120] R and C are determined by the following formulas:

[0121] R = Rsh * L / W;

[0122] C = Cu * L * W;

[0123] Wherein, L is the length of the metal line between the power supply sub-nodes, W is the width of the metal line between the power supply sub-nodes, Rsh is the square resistance of the metal, and Cu is the capacitance value per unit area.

[0124] Further, the determining module 12 is configured to:

[0125] The first simulation is performed on the power supply line topology network with a preset power supply voltage to obtain the current of each circuit module in the circuit corresponding to the power supply line topology network;

[0126] The circuit simulation is performed according to the parasitic elements between the power supply sub-nodes and the current of each circuit module to obtain the voltage waveform of the power supply input node of each circuit module.

[0127] The minimum voltage of the power supply input node of each circuit module is determined according to the voltage waveform of the power supply input node of each circuit module.

[0128] Further, the determining module 12 is configured to: set a current source for each circuit module according to the current of each circuit module to obtain a test circuit.

[0129] The circuit simulation is performed on the test circuit according to the parasitic elements between the power supply sub-nodes and the current of each circuit module to obtain the voltage waveform of the power supply input node of each circuit module.

[0130] Further, the simulation module 13 is configured to add the minimum voltage of the power supply input node of each circuit module to the power supply input node of each circuit module to obtain an embedded minimum voltage circuit.

[0131] The circuit with the minimum voltage is subjected to timing simulation according to the integrated circuit post-simulation circuit netlist.

[0132] The device provided by the embodiment of the present application can execute the above-mentioned method embodiments, and the specific implementation principles and technical effects can be referred to the above-mentioned method embodiments, which will not be described here again.

[0133] Figure 11 A structural schematic diagram of a simulation device provided by the embodiment of the present application is shown in the figure, Figure 11 The simulation device of the embodiment can include a memory 101 and a processor 102,

[0134] The memory 101 is configured to store executable instructions of the processor 102.

[0135] The processor 102 is configured to:

[0136] The power line topology network is generated according to the power line layout, and the power line topology network includes a plurality of first layer metal lines arranged horizontally, a plurality of second layer metal lines arranged longitudinally, power sub-nodes and parasitic elements, the parasitic elements are located between two power sub-nodes;

[0137] The minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network is determined, the power input node is one of the power sub-nodes in each circuit module;

[0138] Timing simulation is performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist.

[0139] Optionally, the memory 101 can be independent or integrated with the processor 102.

[0140] When the memory 101 is a device independent of the processor 102, the simulation device of the embodiment can further include:

[0141] A bus 103 is configured to connect the memory 101 and the processor 102.

[0142] Optionally, the embodiment further includes a communication interface 104, which can be connected with the processor 102 through the bus 103.

[0143] The device can be used to execute each step and / or process in the above-mentioned method embodiments.

[0144] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores computer execution instructions, when the computer execution instructions are run on a computer, the computer is caused to execute the method of the above-mentioned embodiment.

[0145] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the above embodiments.

[0146] This application also provides a power line topology network and a test circuit, which are described below in conjunction with... Figure 3 , Figure 4 and Figure 7 Please provide an explanation.

[0147] This application provides a power line topology network, including: multiple first-layer metal lines arranged horizontally, multiple second-layer metal lines arranged vertically, power sub-nodes, and parasitic elements. The parasitic elements are located between two power sub-nodes, wherein the intersection of the first-layer metal lines and the second-layer metal lines is a power sub-node.

[0148] by Figure 3 Taking the power line topology network shown as an example, as Figure 3 As shown, the power line topology network includes multiple first-layer metal lines M1 arranged horizontally, multiple second-layer metal lines M2 arranged vertically, power sub-nodes (VDD11-VDD31), and parasitic elements Q. The intersection of the first-layer metal line M1 and the second-layer metal line M2 is the power sub-node. The parasitic element is located between two power sub-nodes, and there is one parasitic element between every two power sub-nodes.

[0149] Optionally, the parasitic element includes a first parasitic resistor, a second parasitic resistor, and a parasitic capacitor, wherein the first end of the first parasitic resistor is connected to the first power supply sub-node, the second end of the first parasitic resistor is connected to the first end of the second parasitic resistor and the first end of the parasitic capacitor, the second end of the second parasitic resistor is connected to the second power supply sub-node, and the second end of the parasitic capacitor is connected to the ground terminal.

[0150] by Figure 4 Taking the power line topology network shown as an example, as Figure 4 As shown, the parasitic element Q includes a first parasitic resistor R1, a second parasitic resistor R2, and a parasitic capacitor C1. Taking the parasitic element Q between power sub-nodes VDD31 and VDD32 as an example, the first end of the first parasitic resistor R1 is connected to the first power sub-node VDD31, the second end of the first parasitic resistor R1 is connected to the first end of the second parasitic resistor R2 and the first end of the parasitic capacitor C1, the second end of the second parasitic resistor R2 is connected to the second power sub-node VDD32, and the second end of the parasitic capacitor C1 is connected to the ground terminal.

[0151] Optionally, the resistance values ​​of the first parasitic resistor and the second parasitic resistor are both R / 2, and the capacitance value of the parasitic capacitor is C;

[0152] R and C are determined by the following formula:

[0153] R = Rsh * L / W;

[0154] C = Cu * L * W;

[0155] Wherein, L is the length of the metal line between the power supply sub-nodes, W is the width of the metal line between the power supply sub-nodes, Rsh is the square resistance of the metal, and Cu is the capacitance value per unit area.

[0156] It should be noted that, Figure 3 and Figure 4 The power line topology network shown in the figure is only an example, and the number of the first layer metal line M1 and the second layer metal line M2 can be set arbitrarily in actual design.

[0157] The power line topology network provided in the embodiment can be used to implement the simulation method described above, for example, the simulation method shown in Figure 1 S102-S103 can be simulated directly on the power line topology network, and the post-simulation result can be quickly obtained, the simulation speed is improved, and the timing simulation considers the minimum voltage of each circuit module power input node. The difference between the minimum voltage and the ideal power voltage is the power line voltage drop, so the influence of the power line voltage drop on the timing parameters of the integrated circuit can be evaluated through normal timing simulation, the simulation accuracy can be improved, and the compromise between simulation accuracy and simulation speed is achieved.

[0158] The embodiment of the application also provides a test circuit comprising at least one current source and the power line topology network in the above embodiment, such as the power line topology network shown in Figure 3 or Figure 4 In the test circuit, the input current of each current source is the current of each circuit module in the circuit corresponding to the power line topology network, and the number of current sources is the same as the number of circuit modules included in the circuit corresponding to the power line topology network.

[0159] Further, the first end of each current source is connected to the power input node of each circuit module, and the second end of each current source is connected to the ground terminal. The power input node is one of the power sub-nodes in each circuit module.

[0160] Wherein, optionally, the current of each circuit module in the circuit corresponding to the power line topology network is obtained by first simulating the power line topology network with a preset power voltage.

[0161] Taking the test circuit shown in Figure 7 as an example, Figure 7In the shown test circuit, there are 6 current sources, the number of current sources is same as the number of circuit modules, the first end of each current source P is connected to the power input node of each circuit module, and the second end of each current source P is connected to the ground. For example, the first end of the current source P is connected to the power input node VDD31 of the circuit module X1, and the second end of the current source P is connected to the ground.

[0162] The test circuit provided by the embodiment can be used in the simulation method to determine the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power line topology network. The circuit simulation can be directly performed by the test circuit to obtain the voltage waveform of the power input node of each circuit module. The minimum voltage of the power input node of each circuit module can be determined according to the voltage waveform of the power input node of each circuit module. The timing simulation can be performed according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation netlist.

[0163] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A simulation method, characterized by, The method comprises the following steps: generating a power line topology network according to a power line layout, the power line topology network comprising a plurality of first layer metal lines arranged horizontally, a plurality of second layer metal lines arranged vertically, power sub-nodes, and parasitic elements between two power sub-nodes; determining the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power line topology network, the power input node being one of the power sub-nodes in the each circuit module; performing timing simulation according to the minimum voltage of the power input node of the each circuit module and a post-simulation circuit netlist of an integrated circuit; the post-simulation circuit netlist does not include parasitic capacitance and parasitic resistance; after the timing simulation is passed, performing post-simulation using the parasitic capacitance and the parasitic resistance.

2. The method of claim 1, wherein, The step of generating the power line topology network according to the power line layout comprises the following steps: determining the intersection of the first layer metal lines and the second layer metal lines as the power sub-nodes; arranging the parasitic elements between every two power sub-nodes, the parasitic elements comprising a first parasitic resistance, a second parasitic resistance, and a parasitic capacitance, wherein the first end of the first parasitic resistance is connected to a first power sub-node, the second end of the first parasitic resistance is connected to the first end of the second parasitic resistance and the first end of the parasitic capacitance; the second end of the second parasitic resistance is connected to a second power sub-node; and the second end of the parasitic capacitance is connected to a ground terminal; obtaining the power line topology network according to the first layer metal lines, the second layer metal lines, the power sub-nodes, and the parasitic elements.

3. The method of claim 2, wherein, The resistance values of the first parasitic resistance and the second parasitic resistance are both R / 2, and the capacitance value of the parasitic capacitance is C; the R and the C are determined by the following formulas: R = Rsh * L / W; C = Cu * L * W; wherein, the L is the length of the metal line between the power sub-nodes, the W is the width of the metal line between the power sub-nodes, the Rsh is the square resistance of the metal, and the Cu is the capacitance value per unit area.

4. The method of claim 1, wherein, The step of determining the minimum voltage of the power input node of each circuit module in a circuit corresponding to the power line topology network comprises the following steps: performing first simulation at a preset power voltage according to the power line topology network to obtain the current of each circuit module in a circuit corresponding to the power line topology network; performing circuit simulation according to the parasitic elements between the power sub-nodes and the current of the each circuit module to obtain the voltage waveform of the power input node of the each circuit module; determining the minimum voltage of the power input node of the each circuit module according to the voltage waveform of the power input node of the each circuit module.

5. The method of claim 4, wherein, The step of performing circuit simulation according to the parasitic elements between the power sub-nodes and the current of the each circuit module to obtain the voltage waveform of the power input node of the each circuit module comprises the following steps: setting a current source for the each circuit module according to the current of the each circuit module to obtain a test circuit; According to the parasitic elements between the power supply sub-nodes and the current of each circuit module, circuit simulation is performed on the test circuit to obtain the voltage waveform of the power supply input node of each circuit module.

6. The method according to any one of claims 1 to 5, characterized in that, The timing simulation according to the minimum voltage of the power supply input node of each circuit module and the post-simulation circuit netlist of the integrated circuit comprises: The minimum voltage of the power supply input node of each circuit module is added to the power supply input node of each circuit module to obtain a minimum voltage embedded circuit. Timing simulation is performed on the minimum voltage embedded circuit according to the post-simulation circuit netlist of the integrated circuit.

7. An emulation apparatus comprising: a memory and a processor; the memory is configured to store executable instructions of the processor; wherein the processor is configured to: generate a power line topology network according to a power line layout, the power line topology network comprising a plurality of first layer metal lines arranged horizontally, a plurality of second layer metal lines arranged vertically, power supply sub-nodes and parasitic elements, the parasitic elements being located between two power supply sub-nodes; determine the minimum voltage of the power supply input node of each circuit module in the circuit corresponding to the power line topology network, the power supply input node being one of the power supply sub-nodes in each circuit module; perform timing simulation according to the minimum voltage of the power supply input node of each circuit module and a post-simulation circuit netlist of the integrated circuit; the post-simulation circuit netlist does not include parasitic capacitance and parasitic resistance; after the timing simulation passes, perform post-simulation using the parasitic capacitance and the parasitic resistance.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the method of any one of claims 1 to 6.

9. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the method of any one of claims 1 to 6.

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