Shift register, gate driving circuit and display device

Abstract

The present disclosure discloses a shift register, which includes a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module, and an energy storage module; the first output module provides a first power signal at a first power signal terminal to a first output signal terminal under the control of the voltage at a second node, and the second output module provides a second power signal at a second power signal terminal to the first output signal terminal under the control of the voltage at a first node. The first control module, the second control module, the third control module, the fourth control module, the fifth control module, the sixth control module, and the energy storage module cooperate with each other to control the potentials of the first node, the second node, and the third node. The shift register of the present disclosure can output a pulse signal with a waveform meeting the requirements.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technologies, and particularly relates to a shift register, a gate driving circuit, and a display device. Background Art

[0002] The technology of Gate Driver on Array (GOA) integrates the thin film transistor (TFT) gate switching circuit on the array substrate of the display panel to form the driving of the display panel, thereby eliminating the wiring space in the bonding area and the fan-out area of the integrated circuit (IC), and thus achieving a narrow bezel.

[0003] Oxide thin film transistors have received increasing attention due to the transparency of the material, relatively simple manufacturing process, and low process temperature. For oxide thin film transistors, new GOA circuits need to be designed to adapt to the characteristics of lower carrier mobility of oxide thin film transistors. Summary of the Invention

[0004] In a first aspect, the present disclosure provides a shift register, including: a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module, and an energy storage module;

[0005] The first control module is connected to a first power signal terminal, a first input signal terminal, and a second node, and is configured to supply a first power signal of the first power signal terminal to the second node under the control of a first input signal of the first input signal terminal;

[0006] The first output module is connected to the second node, a first clock signal terminal, and a first output signal terminal, and is configured to supply a first clock signal of the first clock signal terminal to the first output signal terminal under the control of the voltage of the second node;

[0007] The second output module is connected to a first node, a second power signal terminal, and a first output signal terminal, and is configured to supply a second power signal of the second power signal terminal to the first output signal terminal under the control of the voltage of the first node;

[0008] The second control module is connected to the second power signal terminal, a second input signal terminal, the first clock signal terminal, and a third node, and is configured to supply the second power signal of the second power signal terminal to the third node under the control of a second input signal of the second input signal terminal, and supply the second power signal of the second power signal terminal to the third node under the control of the first clock signal of the first clock signal terminal;

[0009] A third control module, connected to a third node, a second clock signal terminal, and a first node, configured to provide a second clock signal at the second clock signal terminal to the first node under the voltage control of the third node;

[0010] A fourth control module, connected to the third node, a second power signal terminal, and a second node, configured to provide a second power signal at the second power signal terminal to the second node under the voltage control of the third node;

[0011] A fifth control module, connected to the first node, the second power signal terminal, and the second node, configured to provide the second power signal at the second power signal terminal to the second node under the voltage control of the first node;

[0012] A sixth control module, connected to the second node, the second power signal terminal, and the first node, configured to provide the second power signal at the second power signal terminal to the first node under the voltage control of the second node;

[0013] An energy storage module, including a first capacitor, with two ends of the first capacitor respectively connected to the third node and the second clock signal terminal.

[0014] In a second aspect, the present disclosure provides a gate driving circuit, including N cascaded shift registers SR(i); a first output signal terminal of the kth shift register SR(k) is connected to a first input signal terminal of the (k + 1)th shift register SR(k + 1); 1 ≤ k ≤ N - 1, N > 1; at least one of the N shift registers SR(i) adopts the above-mentioned shift register; 1 ≤ i ≤ N.

[0015] In a third aspect, the present disclosure provides a display device, including the above-mentioned gate driving circuit.

[0016] Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display device. The shift register includes a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module, and an energy storage module; the first output module provides a first clock signal at the first clock signal terminal to the first output signal terminal under the voltage control of the second node, the second output module provides a second power signal at the second power signal terminal to the first output signal terminal under the voltage control of the first node, the third control module and the sixth control module control the voltage of the first node, the first control module, the fourth control module, and the fifth control module control the voltage of the second node, the second control module controls the voltage of the third node, and through the cooperation of the six control modules and the energy storage module, the node potential can jump in time, so as to output a pulse signal with a waveform meeting the requirements. Description of the Drawings

[0017] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure and form a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation to the technical solutions of the present disclosure.

[0018] Figure 1 A structural schematic diagram of a shift register provided for an embodiment of the present disclosure;

[0019] Figure 2 An equivalent circuit schematic diagram of a shift register provided for an embodiment of the present disclosure;

[0020] Figure 3 An equivalent circuit schematic diagram of another shift register provided for an embodiment of the present disclosure (including a second capacitor and a third capacitor);

[0021] Figure 4 An equivalent circuit schematic diagram of another shift register provided for an embodiment of the present disclosure (including a tenth transistor);

[0022] Figure 5 An equivalent circuit schematic diagram of another shift register provided for an embodiment of the present disclosure (including a second output signal terminal);

[0023] Figure 6 A signal timing diagram of a shift register provided for an embodiment of the present disclosure;

[0024] Figure 7 A signal timing diagram of another shift register provided for an embodiment of the present disclosure;

[0025] Figure 8 A cascaded structure schematic diagram of a gate driving circuit provided for an embodiment of the present disclosure;

[0026] Figure 9 A cascaded structure schematic diagram of a gate driving circuit provided for an embodiment of the present disclosure (the first input signal and the second input signal are the same);

[0027] Figure 10 A cascaded structure schematic diagram of a gate driving circuit provided for an embodiment of the present disclosure (the first input signal and the second input signal are different). Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the present disclosure more clearly understood, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be arbitrarily combined with each other.

[0029] In the drawings, for the sake of clarity, the sizes of the respective components, the thicknesses of the layers, or the regions are sometimes exaggerated. Therefore, one embodiment of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0030] The ordinal numbers such as "first", "second", and "third" in this specification are set to avoid confusion of the components, rather than to limit the quantity.

[0031] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0032] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The source and drain of a transistor are symmetric. In the case of using transistors with opposite polarities or when the current direction changes during the operation of a circuit, etc., the functions of the "source" and "drain" sometimes swap with each other. In the embodiments of the present disclosure, one of the source and the drain is referred to as the first pole, the other of the source and the drain is referred to as the second pole, and the gate is referred to as the control pole.

[0033] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0034] In the following examples, the driving transistor is described as an N-type thin film transistor. Other transistors may have the same or different types as the driving transistor according to the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as a P-type thin film transistor. Those skilled in the art can understand that by correspondingly changing the types of other transistors and inverting the respective driving signals and level signals (and / or making other additional adaptive modifications), the technical solutions of the present disclosure can also be achieved.

[0035] An embodiment of the present disclosure provides a shift register, as Figure 1 shown, the shift register provided by the embodiment of the present disclosure includes: a first control module 10, a first output module 20, a second output module 30, a second control module 40, a third control module 50, a fourth control module 60, a fifth control module 70, a sixth control module 80, and an energy storage module 90;

[0036] The first control module is connected to a first power supply signal terminal VGH, a first input signal terminal IN1, and a second node N2, and is configured to supply a first power supply signal of the first power supply signal terminal to the second node under the control of a first input signal of the first input signal terminal;

[0037] The first output module is connected to the second node N2, a first clock signal terminal CK1, and a first output signal terminal OUT1, and is configured to supply a first clock signal of the first clock signal terminal to the first output signal terminal under the control of the voltage of the second node;

[0038] The second output module is connected to a first node N1, a second power supply signal terminal VGL, and the first output signal terminal OUT1, and is configured to supply a second power supply signal of the second power supply signal terminal to the first output signal terminal under the control of the voltage of the first node;

[0039] The second control module is connected to the second power supply signal terminal VGL, a second input signal terminal IN2, the first clock signal terminal CK1, and a third node N3, and is configured to supply a second power supply signal of the second power supply signal terminal to the third node under the control of a second input signal of the second input signal terminal, and supply a second power supply signal of the second power supply signal terminal to the third node under the control of a first clock signal of the first clock signal terminal;

[0040] The third control module is connected to the third node N3, a second clock signal terminal CK2, and the first node N1, and is configured to supply a second clock signal of the second clock signal terminal to the first node under the control of the voltage of the third node;

[0041] The fourth control module is connected to the third node N3, the second power supply signal terminal VGL, and the second node N2, and is configured to supply the second power supply signal of the second power supply signal terminal to the second node under the voltage control of the third node;

[0042] The fifth control module is connected to the first node N1, the second power supply signal terminal VGL, and the second node N2, and is configured to supply the second power supply signal of the second power supply signal terminal to the second node under the voltage control of the first node;

[0043] The sixth control module is connected to the second node N2, the second power supply signal terminal VGL, and the first node N1, and is configured to supply the second power supply signal of the second power supply signal terminal to the first node under the voltage control of the second node;

[0044] The energy storage module includes a first capacitor C1, and two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal CK2.

[0045] The shift register provided in the above embodiment includes a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module, and an energy storage module; the first output module supplies the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node, the second output module supplies the second power supply signal of the second power supply signal terminal to the first output signal terminal under the voltage control of the first node, the third control module and the sixth control module control the voltage of the first node, the first control module, the fourth control module, and the fifth control module control the voltage of the second node, and the second control module controls the voltage of the third node. Through the cooperation of the six control modules and the energy storage module, the node potential can jump in time, shortening the rise time and fall time of the output pulse signal, so that the output waveform meets the requirements.

[0046] Figure 2 An equivalent circuit diagram of a shift register is provided.

[0047] As Figure 2 shown, in some exemplary embodiments, the first control module includes a first transistor T1, a control electrode of the first transistor is connected to the first input signal terminal, a first pole of the first transistor is connected to the first power supply signal terminal, and a second pole of the first transistor is connected to the second node.

[0048] As Figure 2 shown, in some exemplary embodiments, the first output module includes a second transistor T2, a control electrode of the second transistor is connected to the second node, a first pole of the second transistor is connected to the first clock signal terminal, and a second pole of the second transistor is connected to the first output signal terminal.

[0049] As Figure 2 shown, in some exemplary embodiments, the second output module includes a third transistor T3, a control electrode of the third transistor is connected to a first node, a first pole of the third transistor is connected to a second power signal terminal, and a second pole of the third transistor is connected to a first output signal terminal.

[0050] As Figure 2 shown, in some exemplary embodiments, the second control module includes a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is connected to a first clock signal terminal, a first pole of the fourth transistor is connected to a second power signal terminal, a second pole of the fourth transistor is connected to a third node, a control electrode of the fifth transistor is connected to a second input signal terminal, a first pole of the fifth transistor is connected to a second power signal terminal, and a second pole of the fifth transistor is connected to the third node.

[0051] As Figure 2 shown, in some exemplary embodiments, the third control module includes a sixth transistor T6, a control electrode of the sixth transistor is connected to the third node, a first pole of the sixth transistor is connected to a second clock signal terminal, and a second pole of the sixth transistor is connected to the first node.

[0052] As Figure 2 shown, in some exemplary embodiments, the fourth control module includes a seventh transistor T7, a control electrode of the seventh transistor is connected to the third node, a first pole of the seventh transistor is connected to a second power signal terminal, and a second pole of the seventh transistor is connected to a second node.

[0053] As Figure 2 shown, in some exemplary embodiments, the fifth control module includes an eighth transistor T8, a control electrode of the eighth transistor is connected to the first node, a first pole of the eighth transistor is connected to a second power signal terminal, and a second pole of the eighth transistor is connected to the second node.

[0054] As Figure 2 shown, in some exemplary embodiments, the sixth control module includes a ninth transistor T9, a control electrode of the ninth transistor is connected to the second node, a first pole of the ninth transistor is connected to a second power signal terminal, and a second pole of the ninth transistor is connected to the first node.

[0055] Figure 3 Another equivalent circuit diagram of a shift register is provided.

[0056] As Figure 3As shown, in some exemplary embodiments, the first output module further includes a second capacitor C2. One end of the second capacitor is connected to the control electrode of the second transistor, and the other end of the second capacitor is connected to the second electrode of the second transistor. The second capacitor is connected across the control electrode and the second electrode of the second transistor, and can stabilize the potential of the control electrode of the second transistor.

[0057] As Figure 3 As shown, in some exemplary embodiments, the second output module further includes a third capacitor C3. One end of the third capacitor is connected to the control electrode of the third transistor, and the other end of the third capacitor is connected to the first electrode of the third transistor. The third capacitor is connected across the control electrode and the first electrode of the third transistor, and can stabilize the potential of the control electrode of the third transistor.

[0058] Figure 4 Another equivalent circuit diagram of a shift register is provided.

[0059] As Figure 4 As shown, in some exemplary embodiments, the first output module further includes a tenth transistor T10. The control electrode of the tenth transistor is connected to the first power signal terminal, the first electrode of the tenth transistor is connected to the second node, and the second electrode of the tenth transistor is connected to the control electrode of the second transistor. Providing the tenth transistor between the second node and the control electrode of the second transistor can stabilize the potential of the control electrode of the second transistor.

[0060] Figure 5 Another equivalent circuit diagram of a shift register is provided.

[0061] As Figure 5 As shown, in some exemplary embodiments, the second node N2 is further connected to the second output signal terminal OUT2. The second output signal terminal outputs a second output signal.

[0062] In some exemplary embodiments, all the transistors in the shift register are N-type transistors.

[0063] In some exemplary embodiments, when all the transistors in the shift register are N-type transistors, one working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and multiple alternately occurring fifth time periods and sixth time periods;

[0064] The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high-level signal, the second power supply signal is a low-level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first period and low-level signals in other periods; the first clock signal is a low-level signal in the first period, the third period, and the fifth period, and a high-level signal in the second period, the fourth period, and the sixth period; the second clock signal is a high-level signal in the first period, the third period, and the fifth period, and a low-level signal in the second period, the fourth period, and the sixth period.

[0065] In some exemplary embodiments, when all the transistors in the shift register are N-type transistors, one operating cycle of the shift register includes the following multiple periods: a first period, a second period, a third period, a fourth period, and multiple alternating fifth periods and sixth periods;

[0066] The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high-level signal, the second power supply signal is a low-level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal is a high-level signal in the first period and a low-level signal in other periods; the second input signal is a high-level signal in the first period and the second period and a low-level signal in other periods; the first clock signal is a low-level signal in the first period, the third period, and the fifth period, and a high-level signal in the second period, the fourth period, and the sixth period; the second clock signal is a high-level signal in the first period, the third period, and the fifth period, and a low-level signal in the second period, the fourth period, and the sixth period.

[0067] In some exemplary embodiments, all the transistors in the shift register are oxide thin film transistors. The carrier mobility of the oxide thin film transistors is relatively low. Through the cooperation of six control modules and an energy storage module, the node potential can jump in time, shortening the rise time and fall time of the output pulse signal, so that the output waveform meets the requirements.

[0068] The working process of the shift register will be described below with reference to the signal timing diagram.

[0069] Figure 6 A signal timing diagram of the shift register is provided. The shift register adopts Figures 2 to 5Any of the structures, all transistors are N-type transistors. The first power signal terminal provides a first power signal, the second power signal terminal provides a second power signal, the first clock signal terminal provides a first clock signal, the second clock signal terminal provides a second clock signal, the first input signal terminal provides a first input signal, the second input signal terminal provides a second input signal, the first output signal terminal outputs a first output signal, and the second output signal terminal outputs a second output signal (for Figure 5 ). The first power signal and the second power signal are DC signals, the first input signal and the second input signal are pulse signals, the first input signal and the second input signal are the same, the first clock signal and the second clock signal are periodic pulse signals, and the first clock signal and the second clock signal are in opposite phases.

[0070] For an N-type transistor, when the voltage of the transistor gate (control electrode) is higher than the turn-on voltage, the transistor conducts; when the voltage of the transistor gate is lower than the turn-on voltage, the transistor is in the cut-off state. A high-level signal is a signal higher than the turn-on voltage of the transistor, and a low-level signal is a signal lower than the turn-on voltage of the transistor. The first power signal is a high-level signal, and the second power signal is a low-level signal.

[0071] One working cycle of the shift register may include multiple time periods: a first time period (t1), a second time period (t2), a third time period (t3), a fourth time period (t4), and multiple alternating fifth time periods (t5) and sixth time periods (t6).

[0072] (1) The first time period (t1 time period)

[0073] The first input signal and the second input signal are high-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

[0074] The first clock signal is a low-level signal, the fourth transistor is cut off, the second input signal is a high-level signal, the fifth transistor conducts, and the second power signal is supplied to the third node. The second power signal is a low-level signal, so the potential of the third node is a low level.

[0075] The potential of the third node is a low level, and the sixth transistor and the seventh transistor are cut off. The second clock signal is a high-level signal, and the second clock signal charges the first capacitor.

[0076] The first input signal is a high-level signal, the first transistor conducts, and the first power signal is supplied to the second node. The first power signal is a high-level signal, so the potential of the second node is a high level.

[0077] The potential of the second node is a high level, the ninth transistor conducts, and the second power signal is supplied to the first node. The second power signal is a low-level signal, so the potential of the first node is a low level.

[0078] The potential of the first node is at a low level, and the third transistor and the eighth transistor are cut off. The potential of the second node is at a high level, the second transistor is turned on, and the first clock signal is provided to the first output signal terminal. The first clock signal is a low-level signal, so the first output signal output from the first output signal terminal is a low-level signal. When the second capacitor is connected across the control electrode and the second electrode of the second transistor, the second node charges the second capacitor.

[0079] When the second node is also connected to the second output signal terminal, the second output signal output from the second output signal terminal is a high-level signal.

[0080] (II) Second time period (t2 time period)

[0081] The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

[0082] The second input signal is a low-level signal, the fifth transistor is cut off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low-level signal, so the potential of the third node is at a low level.

[0083] The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are cut off.

[0084] The first input signal is a low-level signal, the first transistor is cut off, the second node maintains the potential of the previous time period (t1), and the potential of the previous time period is at a high level.

[0085] The potential of the second node is at a high level, the ninth transistor is turned on, and the second power supply signal is provided to the first node. The second power supply signal is a low-level signal, so the potential of the first node is at a low level.

[0086] The potential of the first node is at a low level, and the third transistor and the eighth transistor are cut off. The potential of the second node is at a high level, the second transistor is turned on, and the first clock signal is provided to the first output signal terminal. The first clock signal is a high-level signal, so the first output signal output from the first output signal terminal jumps from a low-level signal to a high-level signal. Since the second transistor is always turned on during the second time period, it can quickly follow the jump of the first clock signal, shortening the rising edge time of the first output signal.

[0087] When the second node is also connected to the second output signal terminal, the second output signal output from the second output signal terminal is a high-level signal.

[0088] (III) Third time period (t3 time period)

[0089] The first input signal and the second input signal are high-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

[0090] The first clock signal is a low-level signal, the fourth transistor is turned off, the second input signal is a low-level signal, and the fifth transistor is turned off.

[0091] The second clock signal jumps from a low-level signal to a high-level signal, and the third node also jumps from a low-level signal to a high-level signal under the action of the third capacitor. After the third node jumps to a high level, the sixth transistor and the seventh transistor are turned on, the second clock signal is supplied to the first node, and the second power supply signal is supplied to the second node. The second clock signal is a high-level signal, and the potential of the first node jumps from a low level to a high level. The first input signal is a low-level signal, and the first transistor is turned off. The second power supply signal is a low-level signal, and the potential of the second node changes from a high level to a low level.

[0092] The potential of the second node is a low level, and the ninth transistor and the second transistor are turned off.

[0093] The potential of the first node is a high level, and the eighth transistor and the third transistor are turned on. The second power supply signal is supplied to the second node. The second power supply signal is a low-level signal, and the potential of the second node is a low level. The second power supply signal is supplied to the first output signal terminal. The second power supply signal is a low-level signal, and the first output signal output from the first output signal terminal jumps from a high-level signal to a low-level signal. When the third capacitor is connected across the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

[0094] After the potential of the third node jumps, it simultaneously controls the potentials of the second node and the first node to jump, so that the second transistor is turned off and the third transistor is turned on simultaneously, and the first output signal jumps from a high level to a low level, shortening the falling edge time of the first output signal.

[0095] When the second node is also connected to the second output signal terminal, the second output signal output from the second output signal terminal is a low-level signal.

[0096] (IV) The fourth time period (time period t4)

[0097] The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

[0098] The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is supplied to the third node. The second power supply signal is a low-level signal, so the potential of the third node changes from a high level to a low level.

[0099] The potential of the third node is at a low level, and the sixth and seventh transistors are turned off.

[0100] The first input signal is a low-level signal, the first transistor is turned off, the second node maintains the potential of the previous period (t3), and the potential of the previous period is at a low level.

[0101] The potential of the second node is at a low level, and the ninth and second transistors are turned off.

[0102] The sixth and ninth transistors are turned off, and the first node maintains the potential of the previous period (t3), and the potential of the previous period is at a high level.

[0103] The potential of the first node is at a high level, and the eighth and third transistors continue to be turned on. The potential of the second node continues to be at a low level, and the first output signal continues to be a low-level signal. The third capacitor maintains the high level of the control electrode of the third transistor.

[0104] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low-level signal.

[0105] After the fourth period, the fifth and sixth periods alternate multiple times until the end of this working cycle.

[0106] (V) The fifth period (t5 period)

[0107] The first input signal and the second input signal are low-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

[0108] The first clock signal is a low-level signal, the fourth transistor is turned off, the second input signal is a low-level signal, and the fifth transistor is turned off.

[0109] The second clock signal jumps from a low-level signal to a high-level signal, and the third node also jumps from a low level to a high level under the action of the third capacitor. After the third node jumps to a high level, the sixth and seventh transistors are turned on, the second clock signal is supplied to the first node, and the second power supply signal is supplied to the second node. The second clock signal is a high-level signal, and the potential of the first node continues to be at a high level. The first input signal is a low-level signal, and the first transistor is turned off. The second power supply signal is a low-level signal, and the potential of the second node continues to be at a low level.

[0110] The potential of the second node is at a low level, and the ninth and second transistors are turned off.

[0111] The potential of the first node is at a high level, and the eighth transistor and the third transistor continue to conduct. The potential of the second node continues to be at a low level, and the first output signal continues to be at a low-level signal. When the third capacitor is connected across the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

[0112] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low-level signal.

[0113] (Six) The sixth time period (t6 time period)

[0114] The first input signal and the second input signal are at low-level signals, the first clock signal is at a high level, and the second clock signal is at a low level.

[0115] The second input signal is at a low level, the fifth transistor is cut off, the first clock signal is at a high level, the fourth transistor conducts, and the second power supply signal is supplied to the third node. The second power supply signal is at a low level, so the potential of the third node changes from a high level to a low level.

[0116] The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are cut off.

[0117] The first input signal is at a low level, the first transistor is cut off, the second node maintains the potential of the previous time period (t5), and the potential of the previous time period is at a low level.

[0118] The potential of the second node is at a low level, and the ninth transistor and the second transistor are cut off.

[0119] The sixth transistor and the ninth transistor are cut off, and the first node maintains the potential of the previous time period (t5), and the potential of the previous time period is at a high level.

[0120] The potential of the first node is at a high level, and the eighth transistor and the third transistor continue to conduct. The potential of the second node continues to be at a low level, and the first output signal continues to be at a low-level signal. The third capacitor maintains the high level of the control electrode of the third transistor.

[0121] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low-level signal.

[0122] Figure 7 Another signal timing diagram of the shift register is provided. The shift register adopts Figures 2 to 5Any one of the structures, all transistors are N-type transistors, the first power signal terminal provides a first power signal, the second power signal terminal provides a second power signal, the first clock signal terminal provides a first clock signal, the second clock signal terminal provides a second clock signal, the first input signal terminal provides a first input signal, the second input signal terminal provides a second input signal, the first output signal terminal outputs a first output signal, and the second output signal terminal outputs a second output signal (for Figure 5 ). The first power signal and the second power signal are DC signals, the first input signal and the second input signal are pulse signals, the first input signal and the second input signal are different, the first clock signal and the second clock signal are periodic pulse signals, and the first clock signal and the second clock signal are in opposite phases.

[0123] One working cycle of the shift register may include multiple time periods: a first time period (t1), a second time period (t2), a third time period (t3), a fourth time period (t4), and multiple alternating fifth time periods (t5) and sixth time periods (t6).

[0124] Figure 6 The first input signal of Figure 7 has the same waveform as the first input signal of Figure 6 The second input signal of Figure 7 has a different waveform from the second input signal of Figure 6 The difference is that: Figure 7 The second input signal of

[0125] is at a low level in the second time period. Figure 7 It can be known that the fifth transistor is turned on according to Figure 6 It can be known that the fifth transistor is turned off according to

[0126] However, whether the fifth transistor is turned on or off, since the first clock signal is at a high level, the fourth transistor is turned on, so the second power signal is always supplied to the third node, making the potential of the third node become low. Figure 7 and Figure 6 Although the second input signals in

[0127] are different, the potential changes of all nodes (the first node, the second node, and the third node) of the shift register are the same within one working cycle, and the waveforms of the first output signal and the second output signal are also exactly the same. Figure 8As shown in the figure, an embodiment of the present disclosure further provides a gate driving circuit, which includes N cascaded shift registers SR(i); the first output signal terminal of the k-th shift register SR(k) is connected to the first input signal terminal of the (k + 1)-th shift register SR(k + 1); 1 ≤ k ≤ N - 1, N > 1; at least one of the N shift registers SR(i) adopts the shift register in the above embodiment; 1 ≤ i ≤ N.

[0128] As Figure 9 shown in the figure, in some exemplary embodiments, the first output signal terminal of the k-th shift register SR(k) is further connected to the second input signal terminal of the (k + 1)-th shift register SR(k + 1). In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are the same.

[0129] As Figure 10 shown in the figure, in some exemplary embodiments, the gate driving circuit further includes N cascaded other shift registers R(i), and the second input signal terminal of the (k + 1)-th shift register SR(k + 1) is connected to the output signal terminal GOUT of the k-th other shift register R(k); 1 ≤ k ≤ N - 1, N > 1; 1 ≤ i ≤ N; the output signal output by the output signal terminal of the k-th other shift register R(k) meets the requirements of the second input signal of the (k + 1)-th shift register SR(k + 1). In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are different.

[0130] The above gate driving circuit can be connected to the pixel driving circuit of the display panel to provide various control signals to the pixel driving circuit, such as: row scanning signals, reset signals, etc.

[0131] The display panel includes: an organic light-emitting diode (Organic Light-Emitting Diode, abbreviated as: OLED) display panel.

[0132] An embodiment of the present disclosure further provides a display device, which includes the above gate driving circuit.

[0133] The display device can be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present invention.

[0134] Although the embodiments disclosed in this application are as above, the content described is only the embodiments adopted for the convenience of understanding this application and is not intended to limit the present invention. Any person skilled in the art within the field of the present invention may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A shift register, comprising: a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module, and an energy storage module; The first control module is connected to a first power signal terminal, a first input signal terminal, and a second node, and is configured to supply a first power signal of the first power signal terminal to the second node under the control of a first input signal of the first input signal terminal; The first output module is connected to the second node, a first clock signal terminal, and a first output signal terminal, and is configured to supply a first clock signal of the first clock signal terminal to the first output signal terminal under the control of the voltage of the second node; The second output module is connected to the first node, a second power signal terminal, and a first output signal terminal, and is configured to supply a second power signal of the second power signal terminal to the first output signal terminal under the control of the voltage of the first node; The second control module is connected to the second power signal terminal, a second input signal terminal, the first clock signal terminal, and a third node, and is configured to supply a second power signal of the second power signal terminal to the third node under the control of a second input signal of the second input signal terminal, and supply a second power signal of the second power signal terminal to the third node under the control of a first clock signal of the first clock signal terminal; The third control module is connected to the third node, a second clock signal terminal, and the first node, and is configured to supply a second clock signal of the second clock signal terminal to the first node under the control of the voltage of the third node; The fourth control module is connected to the third node, the second power signal terminal, and the second node, and is configured to supply a second power signal of the second power signal terminal to the second node under the control of the voltage of the third node; The fifth control module is connected to the first node, the second power signal terminal, and the second node, and is configured to supply a second power signal of the second power signal terminal to the second node under the control of the voltage of the first node; The sixth control module is connected to the second node, the second power signal terminal, and the first node, and is configured to supply a second power signal of the second power signal terminal to the first node under the control of the voltage of the second node; The energy storage module includes a first capacitor, and two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal.

2. The shift register according to claim 1, wherein: The first output module includes a second transistor, a control pole of the second transistor is connected to the second node, a first pole of the second transistor is connected to the first clock signal terminal, and a second pole of the second transistor is connected to the first output signal terminal; The second output module includes a third transistor, a control pole of the third transistor is connected to the first node, a first pole of the third transistor is connected to the second power signal terminal, and a second pole of the third transistor is connected to the first output signal terminal.

3. The shift register according to claim 1, wherein: The first control module includes a first transistor, a control pole of the first transistor is connected to the first input signal terminal, a first pole of the first transistor is connected to the first power signal terminal, and a second pole of the first transistor is connected to the second node; The fourth control module includes a seventh transistor. The control electrode of the seventh transistor is connected to the third node. The first electrode of the seventh transistor is connected to the second power signal terminal. The second electrode of the seventh transistor is connected to the second node; The fifth control module includes an eighth transistor. The control electrode of the eighth transistor is connected to the first node. The first electrode of the eighth transistor is connected to the second power signal terminal. The second electrode of the eighth transistor is connected to the second node.

4. The shift register according to claim 1, wherein: The third control module includes a sixth transistor. The control electrode of the sixth transistor is connected to the third node. The first electrode of the sixth transistor is connected to the second clock signal terminal. The second electrode of the sixth transistor is connected to the first node; The sixth control module includes a ninth transistor. The control electrode of the ninth transistor is connected to the second node. The first electrode of the ninth transistor is connected to the second power signal terminal. The second electrode of the ninth transistor is connected to the first node.

5. The shift register according to claim 1, wherein: The second control module includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is connected to the first clock signal terminal. The first electrode of the fourth transistor is connected to the second power signal terminal. The second electrode of the fourth transistor is connected to the third node. The control electrode of the fifth transistor is connected to the second input signal terminal. The first electrode of the fifth transistor is connected to the second power signal terminal. The second electrode of the fifth transistor is connected to the third node.

6. The shift register according to claim 2, wherein: The first output module further includes a second capacitor. One end of the second capacitor is connected to the control electrode of the second transistor. The other end of the second capacitor is connected to the second electrode of the second transistor; The second output module further includes a third capacitor. One end of the third capacitor is connected to the control electrode of the third transistor. The other end of the third capacitor is connected to the first electrode of the third transistor.

7. The shift register according to claim 2, wherein: The first output module further includes a tenth transistor. The control electrode of the tenth transistor is connected to the first power signal terminal. The first electrode of the tenth transistor is connected to the second node. The second electrode of the tenth transistor is connected to the control electrode of the second transistor.

8. The shift register according to claim 1, wherein: The second node is further connected to a second output signal terminal, and the second output signal terminal outputs a second output signal.

9. The shift register according to any one of claims 2-8, wherein: All the transistors included in the shift register are oxide thin film transistors.

10. The shift register according to any one of claims 2-8, wherein: When all the transistors in the shift register are N-type transistors, one working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and multiple alternating fifth time periods and sixth time periods; The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high-level signal, the second power supply signal is a low-level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first time period and low-level signals in other time periods; the first clock signal is a low-level signal in the first time period, the third time period, and the fifth time period, and a high-level signal in the second time period, the fourth time period, and the sixth time period; the second clock signal is a high-level signal in the first time period, the third time period, and the fifth time period, and a low-level signal in the second time period, the fourth time period, and the sixth time period.

11. A gate driving circuit comprising: comprising N cascaded shift registers SR(i); the first output signal terminal of the k-th shift register SR(k) is connected to the first input signal terminal of the (k + 1)-th shift register SR(k + 1); 1 ≤ k ≤ N - 1, N > 1; at least one of the N shift registers SR(i) adopts the shift register described in any one of claims 1-10 above; 1 ≤ i ≤ N.

12. The gate driving circuit according to claim 11, characterized in that: the first output signal terminal of the k-th shift register SR(k) is further connected to the second input signal terminal of the (k + 1)-th shift register SR(k + 1).

13. A display device comprising: the gate driving circuit according to claim 11 or 12.

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