A shift register, a display panel and a display device

Abstract

The embodiment of the present application provides a shift register, a display panel and a display device. In the shift register, the input end of the first output unit is electrically connected to the first signal line, and the input end of the second output unit is electrically connected to the second signal line; the output end of the first control unit is electrically connected to the control end of the first output unit, and is used to control the first output unit to provide the signal on the first signal line to the output end of the shift register; the output end of the second control end is electrically connected to the control end of the second output unit, and is used to control the second output unit to provide the signal on the second signal line to the output end of the shift register; one end of the voltage stabilizing unit is connected to the first output unit, and is used to control the first signal line to maintain electrical insulation from the output end of the shift register when the second output unit provides the signal on the second signal line to the output end of the shift register. The present application can solve the problem of screen flickering in display panels and display devices.

Description

[Technical field]

[0001] The present application relates to the field of display technology, and in particular to a shift register, a display panel and a display device. [Background technology]

[0002] The display panel mainly realizes display through a pixel matrix. Generally speaking, each row of pixels is coupled to a corresponding scanning gate line. During the operation of the display panel, the shift register converts the input clock signal, trigger signal and other signals into a scanning signal that controls the circuit on / off in the pixel, and the gate drive circuit composed of a plurality of cascaded shift registers can sequentially apply the scanning signal to the scanning line corresponding to each row of pixels of the display panel to sequentially select the circuit in each row of pixels.

[0003] However, in the prior art, the gate driving circuit may output multiple pulse signals, that is, multiple shift registers may output enable signals at the same time, which may cause an abnormal phenomenon of high-brightness flickering on the display device, thereby affecting the display effect.

[0004]

Application Contents

[0005] In view of this, embodiments of the present application provide a shift register, a display panel, and a display device.

[0006] In a first aspect, the present application provides a shift register, comprising a first output unit, a second output unit, a first control unit, a second control unit and a voltage stabilizing unit;

[0007] The input end of the first output unit is electrically connected to the first signal line, and the input end of the second output unit is electrically connected to the second signal line;

[0008] The output terminal of the first control unit is electrically connected to the control terminal of the first output unit, and the first output unit provides the signal on the first signal line to the output terminal of the shift register in response to the signal at its control terminal;

[0009] The output end of the second control end is electrically connected to the control end of the second output unit; the second output unit provides the signal on the second signal line to the output end of the shift register in response to the control end signal;

[0010] One end of the voltage stabilizing unit is connected to the first output unit; the voltage stabilizing unit is used to control the first signal line to maintain electrical insulation from the output end of the shift register when the second output unit provides the signal on the second signal line to the output end of the shift register.

[0011] In an implementation of the first aspect, the voltage stabilizing unit includes a first transistor, a first electrode of the first transistor is connected to the second signal line, and a second electrode of the first transistor is connected to the control end of the first output unit;

[0012] The second signal line receives a first fixed potential signal, where the first fixed potential signal is a signal for controlling the first output unit to be turned off.

[0013] In an implementation of the first aspect, the first output unit includes a second transistor, a gate of the second transistor is electrically connected to the control end of the first output unit, a first electrode of the second transistor is electrically connected to the input end of the first output unit, and a second electrode of the second transistor is electrically connected to the output end of the first output unit;

[0014] The voltage stabilizing unit is used for transmitting the first fixed potential signal on the second signal line to the gate of the second transistor when the second output unit provides the signal on the second signal line to the output end of the shift register.

[0015] In an implementation manner of the first aspect, the first signal line receives a pulse signal.

[0016] In an implementation of the first aspect, the voltage stabilizing unit includes a third transistor, and the first output unit includes a second transistor; a first electrode of the second transistor is connected to the first signal line, a second electrode of the second transistor is connected to a first electrode of the third transistor, and a second electrode of the third transistor is connected to an output end of the gate drive circuit;

[0017] The second transistor and the third transistor have different channel types.

[0018] In an implementation manner of the first aspect, the third transistor is an N-channel transistor.

[0019] In an implementation of the first aspect, the shift register further includes a first capacitor, a first plate of the first capacitor is electrically connected to an output end of the shift register, and a second plate of the first capacitor is electrically connected to a control end of the first output unit.

[0020] In a second aspect, the present application provides a display panel, comprising a gate driving circuit, wherein the gate driving circuit comprises a shift register as provided in the first aspect.

[0021] In an implementation of the second aspect, the display panel further includes a pixel circuit and a light-emitting device, the pixel circuit provides a light-emitting driving current for the light-emitting device; the pixel circuit includes a data writing transistor;

[0022] Among them, in the electrically connected shift register and pixel circuit, the output end of the shift register is electrically connected to the gate of the data writing transistor.

[0023] In an implementation of the second aspect, the voltage stabilizing unit includes a first transistor, a first electrode of the first transistor is connected to the second signal line, and a second electrode is electrically connected to a control end of the first output unit;

[0024] The second signal line receives a first fixed potential signal, where the first fixed potential signal is a signal for controlling the first output unit to be turned off.

[0025] In an implementation of the second aspect, the pixel circuit further includes a light emission control transistor; the first transistor and the light emission control transistor have the same channel type;

[0026] Among them, in the electrically connected shift register and the pixel circuit, the gate of the first transistor is electrically connected to the gate of the light emitting control transistor.

[0027] In an implementation of the second aspect, the voltage stabilizing unit includes a third transistor, and the first output unit includes a second transistor; a first electrode of the second transistor is connected to the first signal line, a second electrode of the second transistor is connected to a first electrode of the third transistor, and a second electrode of the third transistor is connected to an output end of the gate drive circuit;

[0028] The second transistor and the third transistor have different channel types.

[0029] In an implementation of the second aspect, the pixel circuit further includes a threshold grabbing transistor; the third transistor has the same channel type as the threshold grabbing transistor;

[0030] Among them, in the electrically connected shift register and the pixel circuit, the gate of the third transistor is electrically connected to the gate of the threshold grabbing transistor.

[0031] In an implementation manner of the second aspect, the third transistor and the threshold grabbing transistor both include a metal oxide semiconductor layer.

[0032] In a third aspect, the present application provides a display device including the display panel provided in the second aspect.

[0033] The present application sets a voltage stabilizing unit electrically connected to the first output unit, and the voltage stabilizing unit can prevent the signal transmitted on the first signal line from being transmitted to the output end of the shift register through the first output unit when the second output unit outputs a signal to the output end of the shift register. This effectively prevents the first output end unit from starting to transmit an enable signal to the scan line when the scan line receives a non-enable signal, and effectively solves the problem of screen flickering of the display panel and the display device.

Brief Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a shift register provided by an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of a shift register provided by an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of a shift register provided by an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of a shift register provided by an embodiment of the present invention;

[0039] Figure 5 is a schematic diagram of a shift register provided by an embodiment of the present invention;

[0040] Figure 6 is a schematic diagram of a shift register provided by an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of a shift register provided by an embodiment of the present invention;

[0042] Figure 8 A schematic diagram of a shift register provided by an embodiment of the present invention;

[0043] Fig. 9 An equivalent circuit diagram of a shift register provided in an embodiment of the present application;

[0044] Fig.10 for Fig. 9 A corresponding working timing diagram;

[0045] Fig.11 for Fig. 9 Another corresponding working timing diagram;

[0046] Fig.12 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0047] Fig.13 A schematic diagram of the connection between the shift register and the pixel circuit provided in the embodiment of the present application;

[0048] Fig.14 for Fig.13 A corresponding driving timing diagram;

[0049] Fig.15 A schematic diagram of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0050] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0052] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0053] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0054] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0055] It should be understood that, although the terms first, second, third, etc. may be used to describe directions, etc. in the embodiments of the present application, these directions, etc. should not be limited to these terms. These terms are only used to distinguish directions, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first direction may also be referred to as the second direction, and similarly, the second direction may also be referred to as the first direction. The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0056] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0057] Figure 1 A schematic diagram of a shift register provided by an embodiment of the present invention, Figure 2 A schematic diagram of a shift register provided by an embodiment of the present invention.

[0058] The present application embodiment provides a shift register, such as Figure 1 and Figure 2 As shown, the shift register provided by the embodiment of the present invention includes: a first output unit 01 , a second output unit 02 , a first control unit 03 , a second control unit 04 and a voltage stabilizing unit 05 .

[0059] The input end of the first output unit 01 is electrically connected to the first signal line L1, and the first output unit 01 is used to receive the signal transmitted by the first signal line L1. The output end of the first control unit 03 is electrically connected to the control end of the first output unit 01, and the first output unit 01 provides the signal on the first signal line L1 to the output end OUT of the shift register in response to the control signal output by the first control unit 03. That is, the first control unit 03 is used to control the first output unit 01 to transmit the received signal to the output end OUT of the shift register.

[0060] The input end of the second output unit 02 is electrically connected to the second signal line L2, and the second output unit 02 is used to receive the signal transmitted by the second signal line L2. The output end of the second control unit 04 is electrically connected to the control end of the second output unit 02, and the second output unit 02 provides the signal on the second signal line L2 to the output end OUT of the shift register in response to the control signal output by the second control unit 04. In other words, the second control unit 04 is used to control the second output unit 02 to transmit the received signal to the output end OUT of the shift register.

[0061] like Figure 1 and Figure 2As shown, in the embodiment of the present application, one end of the voltage stabilizing unit 05 is connected to the first output unit 01; the voltage stabilizing unit 05 is used to control the first signal line L1 to maintain electrical insulation from the output end of the shift register when the second output unit 02 provides the signal on the second signal line L2 to the output end OUT of the shift register.

[0062] Due to the existence of the voltage stabilizing unit 05, when the output terminal OUT of the shift register outputs the signal transmitted on the second signal line L2, the signal at the output terminal OUT of the shift register will not be interfered by the signal transmitted on the first signal line L1. Specifically, the voltage stabilizing unit 05 can prevent the signal transmitted on the first signal line L1 from being transmitted to the output terminal OUT of the shift register through the first output unit 01 when the second output unit 02 outputs the signal to the output terminal OUT of the shift register.

[0063] In the embodiment of the present application, when the signal on the first signal line L1 is provided to the output end of the shift register, the output end OUT of the shift register outputs an enable signal, that is, a signal that controls the transistor in the pixel circuit electrically connected to the scan line to turn on to the scan line; and when the signal on the second signal line L2 is provided to the output end of the shift register, the output end OUT of the shift register outputs a disable signal, that is, a signal that controls the transistor in the pixel circuit electrically connected to the scan line to turn off to the scan line. Then, in the shift register provided in the embodiment of the present application, the second output unit 02 transmits the disable signal when it is turned on, and the voltage stabilizing unit 05 controls the first signal line L1 to maintain electrical insulation from the output end of the shift register; thereby effectively avoiding the first output unit 01 from turning on to transmit the enable signal to the scan line when the scan line receives the disable signal, and thus effectively solving the problem of screen flickering of the display panel.

[0064] Figure 3 A schematic diagram of a shift register provided by an embodiment of the present invention.

[0065] In one embodiment of the present application, Figure 3 As shown, the voltage stabilizing unit 05 includes a first transistor T1. The second electrode of the first transistor T1 and the control end of the first output unit 01 are both electrically connected to the first node N1. That is, the first transistor T1 included in the voltage stabilizing unit 05 is connected to the control end of the first output unit 01, which can control the first output unit 01 to be stably turned off, so as to achieve electrical insulation between the first signal line L1 and the output end OUT of the shift register when the second output unit 02 outputs a signal to the output end OUT of the shift register.

[0066] A technical solution of this embodiment is that the first electrode of the first transistor T1 is connected to the second signal line L2, and the second signal line L2 receives a first fixed potential signal VGH, wherein the first fixed potential signal VGH is a signal for controlling the first output unit 01 to be turned off. In other words, the first electrode of the first transistor T1 included in the voltage stabilizing unit 05 receives a fixed signal transmitted on the second signal line L2, and when the first transistor T1 is turned on, the fixed signal on the second signal line L2 can be transmitted to the control end of the first output unit 01 to control the first output unit 01 to maintain a stable off state. It can be understood that the first transistor T1 is turned on in at least part of the stage when the second output unit 02 outputs a signal to the output end OUT of the shift register. It should be noted that the first transistor T1 can be as follows Figure 3 A P-type transistor is shown, but an N-type transistor may also be used.

[0067] Figure 4 A schematic diagram of a shift register provided by an embodiment of the present invention.

[0068] In one implementation of this embodiment, Figure 4 As shown, the first output unit 01 includes a second transistor T2. The gate of the second transistor T2 is electrically connected to the output end of the voltage stabilizing unit 05, the first electrode of the second transistor T2 is electrically connected to the input end of the first output unit 01, and the second electrode of the second transistor T2 is electrically connected to the output end of the first output unit 01. That is, the first electrode of the second transistor T2 is electrically connected to the first signal line L1, and the gate is electrically connected to the output end of the voltage stabilizing unit 05. Then, when the second output unit 02 is turned on and the second output unit 02 provides the signal on the second signal line L2 to the output end OUT of the shift register, the output end OUT of the shift register outputs a non-enable signal, and the voltage stabilizing unit 05 transmits the first fixed potential signal VGH on the second signal line L2 to the gate of the second transistor, thereby maintaining the gate potential of the second transistor T2, so that the second transistor T2 remains in the off state, and the first output unit 01 remains in the off state. Thereby effectively avoiding that the first output end unit 01 starts to transmit an enable signal to the scanning line when receiving a non-enable signal, and effectively solving the problem of screen flickering of the display panel.

[0069] Alternatively, if Figure 4 As shown, the second electrode of the second transistor T2 is connected to the output terminal OUT of the first output unit 01.

[0070] A technical solution of this embodiment is that the first signal line L1 receives a pulse signal.

[0071] The inventors have analyzed the shift register and its working process and found that when the first pulse signal XCK is received on the first signal line L1, the potential of the first node N1 will be pulled down in the process of the first pulse signal XCK jumping from a high level signal to a low level signal, and the jump of the first pulse signal XCK will turn on the second transistor T2. For example, when the second transistor T2 is a P-type transistor, the potential of the first node N1 is pulled down in the process of the first pulse signal XCK jumping from a high level signal to a low level signal, thereby turning on the second transistor T2. When the output terminal OUT of the shift register should output a non-enable signal, the second transistor T2 is turned on by the first pulse signal XCK received by the first signal line L1, so that the first output unit 01 outputs an enable signal, that is, the output terminal OUT of the shift register will output an enable signal, and then output to the scan line a signal to control the conduction of the transistor electrically connected to the scan line in the pixel circuit, resulting in a flickering screen problem.

[0072] Based on the above problems and the analysis of the causes of the above problems, in the present technical solution, the second signal line L2 receives the first fixed potential signal VGH. When the voltage stabilizing unit 05 is turned on, the gate of the second transistor T2 can continuously receive the fixed potential signal and the potential signal can control the second transistor T2 to remain in the off state, thereby preventing the gate potential of the second transistor T2 from being affected by the first pulse signal XCK transmitted by the first signal line L1.

[0073] Figure 5 It is a schematic diagram of a shift register provided by an embodiment of the present invention.

[0074] In one embodiment of the present application, Figure 5 As shown, the first output unit 01 includes a second transistor T2, and the voltage stabilizing unit 05 includes a third transistor T3. The second transistor T2 is connected in series with the third transistor T3, wherein the first electrode of the second transistor T2 is connected to the first signal line L1, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, and the second electrode of the third transistor T3 is connected to the output terminal OUT of the first control unit 03. In this implementation, only when the second transistor T2 and the third transistor T3 are turned on at the same time, can the signal on the first signal line L1 be provided to the output terminal of the shift register, so that the output terminal OUT outputs an enable signal, which greatly reduces the probability of highlight flickering on the display panel.

[0075] In one implementation of this embodiment, the channel types of the second transistor T2 and the third transistor T3 are different. For example, the second transistor T2 in the first output unit 01 is a P-type transistor and the third transistor T3 in the voltage stabilizing unit 05 is an N-type transistor. When interfered by surrounding signals, the switching states of the second transistor T2 and the third transistor T3 are different, that is, one transistor tends to be turned on and the off state of the other transistor is more stable, so that when the second output unit 02 provides the signal on the second signal line L2 to the output terminal OUT of the shift register, the first signal line L1 and the output terminal OUT of the shift register will remain electrically insulated.

[0076] It can be understood that, due to the existence of the third transistor T3, when the output terminal OUT of the shift register outputs the signal transmitted on the second signal line L2, the first signal line L1 can remain electrically insulated from the output terminal OUT of the shift register.

[0077] Preferably, if Figure 5 As shown, the third transistor T3 is an N-channel transistor. When interfered by surrounding signals, the third transistor T3 is an N-channel transistor, which can make the voltage stabilizing unit 05 more stable; and because the leakage current generated by the N-channel is not obvious, the potential of the shift register output terminal OUT can be effectively maintained.

[0078] Figure 6 It is a schematic diagram of a shift register provided by an embodiment of the present invention.

[0079] In one embodiment of the present application, Figure 6 As shown, the voltage stabilizing unit 05 includes a first voltage stabilizing unit 051 and a second voltage stabilizing unit 052 .

[0080] like Figure 6 As shown, in the embodiment of the present application, the input end of the first voltage stabilizing unit 051 is connected to the second signal line L2, the output end of the first voltage stabilizing unit 051 is electrically connected to the control end of the first output unit 01 and intersects at the first node N1; the input end of the second voltage stabilizing unit 052 is electrically connected to the output end of the first output unit 01, and the output end of the second voltage stabilizing unit 052 is connected to the output end OUT of the shift register.

[0081] The first voltage stabilizing unit 051 and the second voltage stabilizing unit 052 are both used to control the first signal line L1 to maintain electrical insulation from the output end OUT of the shift register when the second output unit 02 provides the signal on the second signal line L2 to the output end OUT of the shift register.

[0082] Figure 7 A schematic diagram of a shift register provided by an embodiment of the present invention.

[0083] In one embodiment of the present application, Figure 7 As shown, the first output unit 01 includes a second transistor T2, the first voltage stabilizing unit 051 includes a first transistor T1, and the second voltage stabilizing unit 052 includes a third transistor T3.

[0084] Among them, the first electrode of the first transistor T1 in the first voltage stabilizing unit 051 is electrically connected to the second signal line L2, and the second electrode of the first transistor T1 is connected to the gate of the second transistor T2 in the first output unit 01 and intersects at the first node N1. When the first transistor T1 is turned on, the first transistor T1 can transmit the first fixed potential signal VGH on the second signal line L2 to the gate of the second transistor T2, which is used to control the second transistor T2 to be in a stable off state, so that the pulse signal on the first signal line L1 cannot be transmitted to the output end OUT of the shift register, which effectively solves the problem of screen flickering of the display panel.

[0085] like Figure 7 As shown, the third transistor T3 in the second voltage stabilizing unit 052 can be set as an N-type transistor. The second transistor T2 in the first output unit 01 is connected in series with the third transistor T3 in the second voltage stabilizing unit 052, wherein the first electrode of the second transistor T2 is connected to the first signal line L1, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, and the second electrode of the third transistor T3 is electrically connected to the output terminal OUT of the shift register; in this implementation, only when the second transistor T2 and the third transistor T3 are turned on at the same time, can the signal on the first signal line L1 be provided to the output terminal OUT of the shift register, so that the output terminal OUT outputs an enable signal, which greatly reduces the probability of highlight flickering on the display panel.

[0086] Figure 8 A schematic diagram of a shift register provided by an embodiment of the present invention.

[0087] In one embodiment of the present application, Figure 8 As shown, the shift register also includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected to the output terminal OUT of the shift register, a second plate of the first capacitor C1 is electrically connected to the control terminal of the first output unit 01 and intersects at the first node N1, and the first capacitor C1 can maintain the potential of the first node N1.

[0088] Fig. 9 An equivalent circuit diagram of a shift register provided in an embodiment of the present application is shown in FIG. Fig.10 for Fig. 9 A corresponding working timing diagram.

[0089] like Fig. 9As shown, the present application implements a shift register, which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1 and a second capacitor C2.

[0090] In the following, the shift register provided in the embodiment of the present application is described by taking the case where the third transistor T3 is an N-type transistor and the other transistors are all P-type transistors as an example.

[0091] The first output unit 01 includes a second transistor T2, the first voltage stabilizing unit 051 includes a first transistor T1, the second voltage stabilizing unit 052 includes a third transistor T3, and the second output unit 02 includes a fourth transistor T4.

[0092] Among them, the gate of the first transistor T1 receives the first control signal EMITn, the first electrode of the first transistor T1 is connected to the second signal line L2 to receive the first fixed signal VGH, the second electrode of the first transistor T1 and the gate of the second transistor T2 are both connected to the first node N1, and when the first transistor T1 is turned on, the first fixed potential signal VGH is output to the gate of the second transistor T2, thereby controlling the second transistor T2 to be in a stable off state.

[0093] A first electrode of the second transistor T2 is connected to the first signal line L1 to receive the first pulse signal XCK, and a second electrode of the second transistor T2 is connected to a first electrode of the third transistor T3 .

[0094] The gate of the third transistor T3 receives the second control signal SNn, the first electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the second electrode of the third transistor T3 is connected to the output terminal OUT of the shift register.

[0095] The second output unit 02 includes a fourth transistor T4, a gate of which is connected to the second node N2, and the potential of the second node N2 controls the switching state of the fourth transistor T4; a first electrode of the fourth transistor T4 is connected to the second signal line L2, and a second electrode of the fourth transistor T4 is connected to the shift register output terminal OUT.

[0096] The first control unit 03 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0097] The gate of the fifth transistor T5 receives the second fixed potential signal VGL, so that the fifth transistor T5 is always in the on state. The first electrode of the fifth transistor T5 is connected to the second electrode of the sixth transistor T6, and the second electrode of the fifth transistor T5 is connected to the first node N1.

[0098] The gate of the sixth transistor T6 receives the second pulse signal CK, the first electrode of the sixth transistor T6 receives the trigger signal IN, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7 and the first electrode of the fifth transistor T5.

[0099] A gate of the seventh transistor T7 receives the first pulse signal XCK, and a second electrode of the seventh transistor is connected to a second electrode of the eighth transistor T8.

[0100] The gate of the eighth transistor T8 is connected to the second node N2, the potential of the N2 node controls the switching state of the eighth transistor T8, and the first electrode of the eighth transistor T8 receives the first fixed potential signal VGH.

[0101] It can be understood that the first control unit 03 can receive the first fixed potential signal VGH and the trigger signal IN, and output a signal to the first node N1, so as to control the switching state of the second transistor T2 in the first output unit 01.

[0102] The second control unit 04 includes a ninth transistor T9 and a tenth transistor T10.

[0103] like Fig. 9 As shown, the gate of the ninth transistor T9 receives the second pulse signal CK, the first electrode of the ninth transistor T9 is connected to the second fixed potential signal VGL, and the second electrode of the ninth transistor T9 is connected to the second node N2.

[0104] A gate of the tenth transistor T10 is connected to the second electrode of the sixth transistor T6 , a first electrode of the tenth transistor T10 receives the second pulse signal CK, and a second electrode of the tenth transistor T10 is connected to the second node N2 .

[0105] It can be understood that the second control unit 04 can receive the second fixed potential signal VGL and the signal at the output end of the sixth transistor T6 , and output a signal to the second node N2 , thereby controlling the switch state of the second output unit 02 .

[0106] like Fig. 9 As shown, the first plate of the first capacitor C1 is electrically connected to the output terminal OUT of the shift register, and the second plate of the first capacitor C1 is electrically connected to the first node. The first plate of the second capacitor C2 receives the first fixed potential signal VGH, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The first capacitor C1 and the second capacitor C2 are used to maintain the potential of the first node N1 and the second node N2, respectively.

[0107] Combine the following Fig.10 For example Fig. 9 The working process of the shift register shown is described in detail:

[0108] Phase t1: The trigger signal IN is a low-level signal, the second pulse signal CK is a low-level signal, the first pulse signal XCK is a high-level signal, the first control signal EMITn is a high-level signal, and the second control signal SNn is a low-level signal. Because the second pulse signal CK is a low-level signal, the sixth transistor T6 and the ninth transistor T9 are turned on, the second fixed potential signal VGL is transmitted to the second node N2 through the turned-on ninth transistor T9, the fourth transistor T4 and the eighth transistor T8 are turned on, and the second output unit 02 outputs a high-level signal to the output terminal OUT of the shift register. The trigger signal IN is a low-level signal at this time and is transmitted to the first electrode of the fifth transistor T5 through the first electrode of the turned-on sixth transistor T6. Because the gate of the fifth transistor T5 is connected to the fixed second fixed potential signal VGL, the fifth transistor T5 is always in the turned-on state, then the trigger signal IN is transmitted to the first node N1 through the turned-on fifth transistor, the second transistor T2 is turned on, and the first pulse signal XCK is a high-level signal at this time and is output to the first electrode of the third transistor T3 through the second transistor. Since the second control signal SNn is a low level signal, the third transistor T3 is turned off, so the output signal of the first output unit O1 cannot be transmitted to the output terminal OUT of the shift register.

[0109] Phase t2: The trigger signal IN is a high-level signal, the second pulse signal CK is a high-level signal, the first pulse signal XCK is a low-level signal, the first control signal EMITn is a high-level signal, and the second control signal SNn is a high-level signal. At this time, due to the action of the first transistor T1, the first node N1 maintains a low potential and the tenth transistor T10, the second pulse signal CK is transmitted to the second node N2 so that the fourth transistor T4 and the eighth transistor T8 are turned off. And the second transistor T2 and the third transistor T3 are turned on, and the low-level potential of the first pulse signal XCK is transmitted to the output terminal OUT of the shift register.

[0110] Phase t3: The trigger signal IN is a high-level signal, the second pulse signal CK is a low-level signal, the first pulse signal XCK is a high-level signal, and the second control signal SNn is a low-level signal. Since the second pulse signal CK is a low-level signal, the sixth transistor T6 and the ninth transistor T9 are turned on, and the high-level potential of the trigger signal IN is transmitted to the gate of the tenth transistor T10 through the sixth transistor T6, and the tenth transistor T10 is turned off; the second fixed potential signal VGL is output to the second node N2 through the ninth transistor T9, the fourth transistor T4 and the eighth transistor T8 are turned on, and the output terminal OUT of the shift register outputs a high level. And the high-level potential of the trigger signal IN is transmitted to the first node N1 through the sixth transistor T6 and the fifth transistor T5, so that the second transistor T2 is turned off; and the second control signal SNn controls the third transistor T3 to also be turned off. Thereafter, the output terminal OUT of the shift register can maintain the output high level until the first stage T1 and the second stage T2 are re-entered.

[0111] like Fig.10 As shown, after entering the stage T3, the first control signal EMITn maintains a low potential until entering the first stage T1 and the second stage T2 again, and the first transistor T1 remains turned on to transmit the first fixed potential signal VGH to the first node N1, so that the second transistor T2 remains turned off.

[0112] Fig.11 for Fig. 9 Another corresponding working timing diagram.

[0113] like Fig.11 As shown, the working sequence of the shift register also includes a stage t4, in which the first control signal EMITn starts to be low and remains low until the first stage T1 and the second stage T2 are entered again, and the first transistor T1 remains turned on to transmit the first fixed potential signal VGH to the first node N1, so that the second transistor T2 remains turned off. In other words, the first transistor T1 can be turned on after the output terminal OUT of the shift register outputs a high level for a period of time.

[0114] Fig.12 is a schematic diagram of a display panel provided by an embodiment of the present invention.

[0115] An embodiment of the present application further provides a display panel, including a gate driving circuit, wherein the gate driving circuit includes a shift register as provided in any one of the above embodiments.

[0116] like Fig.12 As shown, the display panel 10 provided by the embodiment of the present invention includes a display area AA and a non-display area NA surrounding the display area AA.

[0117] The display area AA includes a plurality of sub-pixels, each of which includes a pixel circuit 11 and a light-emitting device 12. The pixel circuit 11 provides a light-emitting driving current for the light-emitting device 12. The light-emitting device 12 may be an organic light-emitting device, or a Micro-LED or Mini-LED. The plurality of sub-pixels included in the display area AA may be arranged in an array, such as in multiple rows and columns.

[0118] The non-display area NA includes a gate drive circuit 13, and the gate drive circuit includes a shift register 130 as provided in any of the above embodiments. The output end of the shift register 130 can be electrically connected to the gate of at least one transistor in the pixel circuit 11 and control the switching state of the at least one transistor. For example, the shift register 13 can be electrically connected to transistors with the same function in all pixel circuits 11 in a pixel circuit row.

[0119] Fig.13 A schematic diagram of the connection between the shift register and the pixel circuit provided in the embodiment of the present application is shown in FIG. Fig.14 for Fig.13 A corresponding driving timing diagram.

[0120] in, Fig.13 The pixel circuit 11 shown in FIG. 1 includes a driving transistor M0, reset transistors M1 and M2, a data writing transistor M3, a threshold grabbing transistor M4, a power supply voltage writing transistor M5, a light emitting control transistor M6 and a storage capacitor C0. The output end of the pixel circuit 11 is electrically connected to the light emitting device 12.

[0121] Among them, the first electrodes of the reset transistors M1 and M2 can both receive the reset voltage Vref, the second electrode of the reset transistor M1 is electrically connected to the gate of the driving transistor M0, and is used to reset the gate of the driving transistor M0; the second electrode of the reset transistor M2 is electrically connected to the output end of the pixel circuit 11, and is used to reset the light-emitting device 12. The first electrode of the data writing transistor M3 is electrically connected to the data line DL, and the second electrode is electrically connected to the first electrode of the driving transistor M0; the first electrode of the threshold grabbing transistor M4 is electrically connected to the second electrode of the driving transistor M0, and the second electrode is electrically connected to the gate of the driving transistor M0, and the data writing transistor M3 cooperates with the threshold grabbing transistor M4 to write the data voltage on the data line DL into the gate of the driving transistor M0. The first electrode of the power supply voltage writing transistor M5 receives the power supply voltage PVDD, and the second electrode is electrically connected to the first electrode of the driving transistor M0; the first electrode of the light-emitting control transistor M6 is electrically connected to the second electrode of the driving transistor M0, and the second electrode is electrically connected to the light-emitting device 12. One plate of the storage capacitor receives the power supply voltage, and the other plate is electrically connected to the gate of the driving transistor M0.

[0122] Combination Fig.13 and Fig.14 In the embodiment of the present application, the output terminal OUT of the shift register can provide a control signal for the data writing transistor M3 in the pixel circuit 11. That is, in the electrically connected shift register and the pixel circuit 11, the output terminal OUT of the shift register is electrically connected to the gate of the data writing transistor M3. Then the shift register can control the data writing transistor M in the pixel circuit 11 to turn on so that the pixel circuit 11 enters the data writing stage.

[0123] In the working phase t2 of the shift register, the output terminal OUT of the shift register provides an enable signal to the gate of the data writing transistor M3 in the electrically connected pixel circuit 11 to control the data writing transistor M3 to turn on. That is, the working phase t2 of the shift register corresponds to the data writing phase t2' of the pixel circuit.

[0124] Combination Fig.13 and Fig.14 In one embodiment of the present application, the voltage stabilizing unit 05 includes a first transistor T1. The second electrode of the first transistor T1 is electrically connected to the control end of the first output unit 01, and the first electrode of the first transistor T1 is connected to the second signal line L2. The second signal line L2 receives a first fixed potential signal VGH, wherein the first fixed potential signal VGH is a signal for controlling the first output unit 01 to be turned off. In other words, the first electrode of the first transistor T1 included in the voltage stabilizing unit 05 receives a fixed signal transmitted on the second signal line L2. When the first transistor T1 is turned on, the fixed signal on the second signal line L2 can be transmitted to the control end of the first output unit 01 to control the first output unit 01 to maintain a stable off state. It can be understood that the first transistor T1 is turned on at least part of the stage when the second output unit 02 outputs a signal to the output end OUT of the shift register.

[0125] Among them, the channel type of the first transistor T1 in the shift register is the same as the channel type of the light-emitting control transistor M6 in the pixel circuit 11. And in the electrically connected shift register and pixel circuit 11, the gate of the first transistor T1 is electrically connected to the gate of the light-emitting control transistor M6, then in the light-emitting stage t3' of the pixel circuit 11, the first transistor T1 in the voltage stabilizing unit 05 can be turned on. That is, the light-emitting stage t3' in the pixel circuit 11 corresponds to the stage t3 of the shift register and the subsequent stages.

[0126] In one embodiment of the present application, the first output unit 01 includes a second transistor T2, and the voltage stabilizing unit 05 includes a third transistor T3. The second transistor T2 is connected in series with the third transistor T3, wherein the first electrode of the second transistor T2 is connected to the first signal line L1, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, and the second electrode of the third transistor T3 is connected to the output terminal OUT of the first control unit 03. In this implementation, only when the second transistor T2 and the third transistor T3 are turned on at the same time, the signal on the first signal line L1 can be provided to the output terminal of the shift register, so that the output terminal OUT outputs an enable signal, which greatly reduces the probability of highlight flickering on the display panel.

[0127] In an implementation of this embodiment, the second transistor T2 and the third transistor T3 have different channel types.

[0128] In a technical solution of this embodiment, the third transistor T3 has the same channel type as the threshold capture transistor M4, such as Fig.14 As shown, the third transistor T3 and the threshold grabbing transistor M4 can both be N-type transistors. In the electrically connected shift register and pixel circuit 11, the gate of the third transistor T3 is electrically connected to the gate of the threshold grabbing transistor M4.

[0129] Combination Fig.13 and Fig.14 In the present technical solution, in the electrically connected shift register and pixel circuit, the third transistor T3 of the shift register and the threshold grabbing transistor M4 can be electrically connected to the same scan line. Then, in the working stage t2 of the shift register, the output terminal OUT of the shift register provides an enable signal to the gate of the data writing transistor M3 in the electrically connected pixel circuit 11, and the third transistor T3 and the threshold grabbing transistor M4 are turned on at the same time. That is, the working stage t2 of the shift register corresponds to the data writing stage t2' of the pixel circuit.

[0130] Specifically, the third transistor T3 and the threshold capture transistor M4 may both include a metal oxide semiconductor layer, that is, the third transistor T3 and the threshold capture transistor M4 may both be metal oxide transistors, reducing the influence of leakage current on the output terminal OUT potential of the shift register and the gate voltage of the driving transistor M0.

[0131] Fig.15 A schematic diagram of a display device provided by an embodiment of the present invention.

[0132] like Fig.15As shown, the embodiment of the present application further provides a display device, including a display panel 001 provided in any of the above embodiments. Exemplarily, the display device may be an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention.

[0133] In the display device provided in the present application, the second output unit 02 in the shift register transmits a non-enable signal when turned on, and the voltage stabilizing unit 05 controls the first signal line L1 to maintain electrical insulation from the output end of the shift register; thereby effectively avoiding the situation where the first output unit 01 turns on to transmit an enable signal to the scanning line when the scanning line receives a non-enable signal, thereby effectively solving the problem of screen flickering in the display device.

[0134] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: A gate driving circuit is included, wherein the gate driving circuit includes a shift register, and the shift register includes a first output unit, a second output unit, a first control unit, a second control unit and a voltage stabilizing unit; The input end of the first output unit is electrically connected to the first signal line, and the input end of the second output unit is electrically connected to the second signal line; The output terminal of the first control unit is electrically connected to the control terminal of the first output unit, and the first output unit provides the signal on the first signal line to the output terminal of the shift register in response to the signal at its control terminal; The output terminal of the second control unit is electrically connected to the control terminal of the second output unit; the second output unit provides the signal on the second signal line to the output terminal of the shift register in response to the control terminal signal thereof; One end of the voltage stabilizing unit is connected to the first output unit; the voltage stabilizing unit is used to control the first signal line to maintain electrical insulation from the output end of the shift register when the second output unit provides the signal on the second signal line to the output end of the shift register; The display panel further comprises a pixel circuit and a light emitting device, wherein the pixel circuit provides a light emitting driving current for the light emitting device; the pixel circuit comprises a data writing transistor; Wherein, in the electrically connected shift register and the pixel circuit, the output end of the shift register is electrically connected to the gate of the data writing transistor; The voltage stabilizing unit includes a third transistor, and the first output unit includes a second transistor; a first electrode of the second transistor is connected to the first signal line, a second electrode of the second transistor is connected to a first electrode of the third transistor, and a second electrode of the third transistor is connected to an output end of the gate driving circuit; Wherein, the channel types of the second transistor and the third transistor are different; The pixel circuit further includes a threshold grabbing transistor; the third transistor has the same channel type as the threshold grabbing transistor; Among them, in the electrically connected shift register and the pixel circuit, the gate of the third transistor is electrically connected to the gate of the threshold grabbing transistor.

2. The display panel according to claim 1, characterized in that: The voltage stabilizing unit further includes a first transistor, a first electrode of the first transistor is connected to the second signal line, and a second electrode of the first transistor is connected to the control end of the first output unit; The second signal line receives a first fixed potential signal, where the first fixed potential signal is a signal for controlling the first output unit to be turned off.

3. The display panel according to claim 2, characterized in that: The gate of the second transistor is electrically connected to the control terminal of the first output unit, the first electrode of the second transistor is electrically connected to the input terminal of the first output unit, and the second electrode of the second transistor is electrically connected to the output terminal of the first output unit; The voltage stabilizing unit is used for transmitting the first fixed potential signal on the second signal line to the gate of the second transistor when the second output unit provides the signal on the second signal line to the output end of the shift register.

4. The display panel according to claim 3, characterized in that: The first signal line receives a pulse signal.

5. The display panel according to claim 1, characterized in that: The third transistor is an N-channel transistor.

6. The display panel according to claim 1, characterized in that: The shift register further includes a first capacitor, a first plate of the first capacitor is electrically connected to the output end of the shift register, and a second plate of the first capacitor is electrically connected to the control end of the first output unit.

7. The display panel according to claim 2, characterized in that: The pixel circuit further includes a light emission control transistor; the first transistor and the light emission control transistor have the same channel type; Among them, in the electrically connected shift register and the pixel circuit, the gate of the first transistor is electrically connected to the gate of the light emitting control transistor.

8. The display panel according to claim 1, characterized in that: The third transistor and the threshold grabbing transistor both include a metal oxide semiconductor layer.

9. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-8.

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