Display substrate and display device

Abstract

At least one embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a first display area and a second display area, and the pixel density of the first display area is higher than that of the second display area. The first pixel circuit of the first sub-pixel of the first display area includes a pixel circuit unit, and the second pixel circuit of the second sub-pixel of the second display area includes two pixel circuit units; the first pixel circuit is configured to be connected to the first power supply voltage terminal to receive the first power supply voltage as the pixel power supply voltage, and the second pixel circuit is configured to be connected to the second power supply voltage terminal to receive the second power supply voltage as the pixel power supply voltage, and the first power supply voltage and the second power supply voltage are different. The display substrate can effectively improve display uniformity.

Description

[0001] This application is a divisional application of the invention patent application with application date of June 29, 2020, application number 202010606709.1, and invention name “Display substrate and display device”. Technical Field

[0002] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0003] In the display field, organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple manufacturing, etc., and have broad development prospects. In order to enrich the functions of display panels, components with other functions are usually integrated, such as imaging elements with photosensitivity, etc., to realize functions such as camera and fingerprint recognition. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, which has a first side for display and a second side opposite to the first side. The display substrate includes a display area, the display area includes a plurality of pixel circuit units located on a base substrate, the plurality of pixel circuit units are arranged in a plurality of rows and columns along a first direction and a second direction, the first direction and the second direction are different; each of the plurality of pixel circuit units includes a driving subcircuit and a first connecting electrode for connecting to a light-emitting element, the first end of the driving subcircuit is configured to receive a pixel power supply voltage, the second end is configured to be electrically connected to the light-emitting element through the first connecting electrode, and the driving subcircuit of the pixel circuit unit is configured to form a driving current flowing through the light-emitting element in response to the pixel power supply voltage; the display area includes a first display area and a second display area, the first display area includes a plurality of first sub-pixels, each of the first sub-pixels includes a first pixel circuit, and the first pixel circuit includes one of the pixel circuit units; the second display area includes a plurality of second sub-pixels, each of the second sub-pixels includes a second pixel circuit, and the second pixel circuit includes two adjacent The pixel circuit unit and the first connecting electrodes of the two pixel circuit units of the second pixel circuit are electrically connected to each other to be connected to the same light-emitting element; the pixel density of the multiple first sub-pixels in the first display area is higher than the pixel density of the multiple second sub-pixels in the second display area; the display substrate also includes a first power supply voltage terminal and a second power supply voltage terminal, the first power supply voltage terminal and the second power supply voltage terminal are insulated from each other, the first power supply voltage terminal is configured to output a first power supply voltage, the second power supply voltage terminal is configured to output a second power supply voltage, and the first power supply voltage is different from the second power supply voltage; the first pixel circuit is configured to be connected to the first power supply voltage terminal to receive the first power supply voltage as the pixel power supply voltage of the pixel circuit unit of the first pixel circuit, and the second pixel circuit is configured to be connected to the second power supply voltage terminal to receive the second power supply voltage as the pixel power supply voltage of the two pixel circuit units of the second pixel circuit.

[0005] In some examples, the system further includes a plurality of first power lines and a plurality of second power lines extending along the second direction, the plurality of first power lines and the plurality of second power lines being arranged along the first direction respectively; the plurality of first power lines and the plurality of second power lines being insulated in the same layer; the plurality of first power lines being electrically connected to the first power supply voltage terminal and connected to the driving subcircuit of the plurality of first sub-pixels to provide the first power supply voltage; the plurality of second power lines being electrically connected to the second power supply voltage terminal and connected to the driving subcircuit of the plurality of second sub-pixels to provide the second power supply voltage.

[0006] In some examples, the plurality of second power lines correspond one-to-one to the plurality of first power lines, and each second power line is arranged in parallel with the corresponding first power line in the second direction and is spaced apart from each other.

[0007] In some examples, the display substrate further includes a non-display area and a power supply line located in the non-display area, wherein the power supply line is disposed around the display area and electrically connects the second power supply voltage terminal to a plurality of second power supply lines.

[0008] In some examples, the display substrate also includes a plurality of third power lines and a plurality of fourth power lines extending along the first direction, and the plurality of third power lines and the plurality of fourth power lines are arranged along the second direction; the plurality of third power lines and the plurality of fourth power lines are insulated on the same layer and are located on a side of the plurality of first power lines and the plurality of second power lines close to the base substrate; the plurality of third power lines correspond one-to-one to the plurality of fourth power lines, and each third power line and the corresponding fourth power line are arranged side by side in the first direction and spaced from each other.

[0009] In some examples, each third power line is electrically connected to at least one of the plurality of first power lines through at least one first via; and each fourth power line is electrically connected to at least one of the plurality of second power lines through at least one second via.

[0010] In some examples, the pixel circuit unit also includes a data writing subcircuit, a compensation subcircuit and a storage subcircuit; the data writing subcircuit includes a control end, a first end and a second end, and the second end of the data writing subcircuit is electrically connected to the driving subcircuit; the compensation subcircuit includes a control end, a first end and a second end, and the control end of the compensation subcircuit is configured to receive a scanning signal, the first end and the second end of the compensation subcircuit are respectively electrically connected to the second end and the control end of the driving subcircuit, and the compensation subcircuit is configured to perform threshold compensation on the driving subcircuit in response to the scanning signal; the storage subcircuit is electrically connected to the control end and the first voltage end of the driving subcircuit; the storage subcircuit includes a storage capacitor, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is configured to receive the pixel power supply voltage, and the second capacitor electrode is connected to the control end of the driving subcircuit.

[0011] In some examples, the multiple third power lines are respectively arranged in one-to-one correspondence with multiple rows of first pixel circuits, and the multiple fourth power lines are respectively arranged in one-to-one correspondence with multiple rows of second pixel circuits; each third power line is integrally formed with the first capacitor electrode of the pixel circuit unit of the corresponding row of first sub-pixels, and each fourth power line is integrally formed with the first capacitor electrode of the pixel circuit unit of the corresponding row of second sub-pixels.

[0012] In some examples, first ends of the data writing subcircuits of the two pixel circuit units of the second pixel circuit are electrically connected to each other.

[0013] In some examples, the second pixel circuit further includes a second connecting electrode that electrically connects the first end of the sub-circuit for writing data of two pixel circuit units in the second pixel circuit.

[0014] In some examples, the second connecting electrode is insulated from the first capacitor electrodes of two pixel circuit units of the second pixel circuit in the same layer.

[0015] In some examples, the display substrate further includes a plurality of main data lines and a plurality of auxiliary data lines extending along a second direction, the plurality of main data lines being arranged along the first direction, and the plurality of auxiliary data lines being arranged along the first direction; the plurality of main data lines being electrically connected one-to-one with first ends of data subcircuits of multiple columns of pixel circuit units in the first display area to provide first data signals; the plurality of auxiliary data lines being electrically connected to first ends of data subcircuits of multiple pixel circuit units in the second display area; the plurality of auxiliary data lines being corresponding one-to-one with the plurality of main data lines to provide second data signals, and each of the plurality of data lines being arranged in parallel with the corresponding main data in the second direction.

[0016] In some examples, the plurality of main data lines and the plurality of auxiliary data lines are disposed in the same layer and are disposed on a side of the first capacitor electrode away from the base substrate.

[0017] In some examples, the plurality of auxiliary data lines are divided into a plurality of data line groups, each data line group includes two of the plurality of auxiliary data lines; and the plurality of data line groups are electrically connected to a plurality of columns of second pixel circuits in a one-to-one correspondence.

[0018] In some examples, two second pixel circuits located in the nth row and the (n+1th)th row and in the same column among the multiple rows of second pixel circuits constitute a pixel circuit group and share an auxiliary data line; n is an odd or even number greater than 0.

[0019] In some examples, for each column of second pixel circuits in the second direction, a plurality of pixel circuit groups thereof are alternately electrically connected to two auxiliary data lines in the corresponding data line group.

[0020] In some examples, two adjacent data line groups include four auxiliary data lines, namely a first data line, a second data line, a third data line and a fourth data line arranged in sequence in the first direction; the first data line is directly electrically connected to its corresponding main data line.

[0021] In some examples, the second data line, the third data line, and the fourth data line are respectively arranged in the same layer and spaced apart from their corresponding main data lines.

[0022] In some examples, the fourth data line is electrically connected to the main data line corresponding to the second data line through a third connecting electrode.

[0023] In some examples, the third connection electrode and the first connection electrode are insulated and arranged in the same layer, and are located at a boundary between the first display area and the second display area.

[0024] In some examples, the third data line and the fourth data line are configured to receive the second data signal from a side of the second display area away from the first display area in the second direction.

[0025] In some examples, the first display area further includes a plurality of first light-emitting elements, and the plurality of first light-emitting elements are electrically connected to the first connection electrodes of the pixel circuit units of the plurality of first pixel circuits in a one-to-one correspondence.

[0026] In some examples, the number of second pixel circuits in the second display area is X, and the second display area further includes Y second light-emitting elements, and the Y second light-emitting elements are electrically connected to Y second pixel circuits of the X second pixel circuits in a one-to-one correspondence, X and Y are both positive integers, and Y is less than X; each of the Y second light-emitting elements is electrically connected to the first connection electrodes of two pixel circuit units in the corresponding second pixel circuit.

[0027] In some examples, the light emitting region of at least one of the Y second light emitting elements has a larger area than the light emitting region of the first light emitting element that emits light of the same color as the first light emitting element.

[0028] In some examples, the display area also includes a third display area at least partially surrounded by the second display area, the third display area is configured to allow light from the first side to be transmitted to the second side for sensing; the third display area includes Z third light-emitting elements, and the Z third light-emitting elements are electrically connected to Z second pixel circuits in the multiple second sub-pixels one by one, Z is a positive integer and Z is less than or equal to XY; each third light-emitting element is electrically connected to the first connection electrodes of two pixel circuit units in the corresponding second sub-pixel.

[0029] In some examples, each third light-emitting element includes a first electrode, a second electrode and a light-emitting layer, and the first electrode of each third light-emitting element is closer to the base substrate than the second electrode of each third light-emitting element; the display substrate also includes a plurality of fourth connecting electrodes, and the plurality of fourth connecting electrodes are arranged one by one corresponding to the plurality of third light-emitting elements, and each fourth connecting electrode electrically connects the first electrode of the corresponding third light-emitting element with the first connecting electrodes of two pixel circuit units corresponding to the third light-emitting element.

[0030] In some examples, the plurality of fourth connecting electrodes are located in the second display area and are located on a side of the first electrodes of the plurality of third light emitting elements close to the base substrate.

[0031] In some examples, the display substrate also includes a plurality of connecting lines extending from the second display area to the third display area, and the plurality of connecting lines are respectively arranged in one-to-one correspondence with the plurality of fourth connecting electrodes and the plurality of third light-emitting elements, and each of the plurality of connecting lines connects the corresponding fourth connecting electrode to the first electrode of the corresponding third light-emitting element.

[0032] In some examples, the plurality of connection lines are disposed in the same layer as the plurality of fourth connection electrodes, and each of the plurality of connection lines is an integral structure with the corresponding fourth connection electrode.

[0033] At least one embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display substrates.

[0034] In some examples, the display device further includes a sensor disposed on the second side of the display substrate and configured to receive light from the first side of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments or related technical descriptions will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and are not limitations of the present disclosure.

[0036] Figure 1 The basic architecture of a pixel circuit of a display substrate provided by at least one embodiment of the present disclosure is shown;

[0037] Figure 2A One of the schematic diagrams of a display substrate provided by at least one embodiment of the present disclosure;

[0038] Figure 2B A second schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0039] Figure 2CA third schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0040] Figure 3A A schematic diagram of a pixel circuit unit provided by at least one embodiment of the present disclosure;

[0041] Figure 3B for Figure 3A A circuit diagram of a specific implementation example of the pixel circuit unit shown;

[0042] Figure 3C A schematic diagram of a second pixel circuit provided by at least one embodiment of the present disclosure;

[0043] Figure 3D A timing signal diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0044] Figure 4A A fourth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0045] Figure 4B for Figure 4A A cross-sectional view along section line II′;

[0046] Figure 5 A fifth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0047] Fig. 6A A sixth schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0048] Figure 6B A seventh schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0049] Fig. 7A An eighth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0050] Figure 7B A ninth schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0051] Figure 7C A tenth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0052] Fig. 8A An eleventh schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0053] Figure 8B A twelfth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0054] Fig.9A A thirteenth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0055] Fig. 9B A fourteenth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0056] Fig. 10A A schematic diagram of a display device provided for at least one embodiment of the present disclosure; and

[0057] Fig. 10B for Fig. 10A Cross-sectional view along section line CC′. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. With reference to the non-limiting exemplary embodiments shown in the accompanying drawings and described in detail in the following description, the exemplary embodiments of the present disclosure and their various features and advantageous details are more fully described. It should be noted that the features shown in the figures are not necessarily drawn to scale. The present disclosure omits the description of known materials, components and process technologies so as not to obscure the exemplary embodiments of the present disclosure. The examples given are only intended to facilitate the understanding of the implementation of the exemplary embodiments of the present disclosure, and to further enable those skilled in the art to implement the exemplary embodiments. Therefore, these examples should not be construed as limiting the scope of the embodiments of the present disclosure.

[0059] Unless otherwise specifically defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. In addition, in various embodiments of the present disclosure, the same or similar reference numerals represent the same or similar components.

[0060] In a display device integrated with an imaging element, the imaging element is arranged in the display area of ​​the display device, which helps to increase the proportion of the display screen, for example, to achieve a full-screen display. Since a display device is made in the display area, the light transmittance of the imaging element will be affected. For example, the light-emitting element in the sub-pixel, the opaque wiring, etc. may block the light captured by the imaging element, thereby affecting the imaging quality. For example, the transmittance of the area where the imaging element is arranged can be increased by reducing the density of the sub-pixels in the area, but this will reduce the display brightness of the area with a lower sub-pixel density, resulting in uneven display.

[0061] At least some embodiments of the present disclosure provide a display substrate having a first side for display and a second side opposite to the first side, the display substrate comprising a display area, the display area comprising a plurality of pixel circuit units, the plurality of pixel circuit units being arranged in a plurality of rows and columns along a first direction and a second direction; the first direction and the second direction are different; each of the plurality of pixel circuit units comprises a driving subcircuit and a first connecting electrode for connecting to a light-emitting element, the first end of the driving subcircuit being configured to receive a pixel power supply voltage, the second end being configured to be electrically connected to the light-emitting element through the first connecting electrode, the driving subcircuit of the pixel circuit unit being configured to form a driving current flowing through the light-emitting element in response to the pixel power supply voltage; the display area comprises a first display area and a second display area, the first display area comprising a plurality of first sub-pixels, each of the first sub-pixels comprising a first pixel circuit, the first pixel circuit comprising one of the pixel circuit units; the second display area comprising a plurality of second sub-pixels, each of the second sub-pixels comprising a second pixel The circuit comprises two adjacent pixel circuit units, and the first connection electrodes of the two pixel circuit units of the second pixel circuit are electrically connected to each other so as to be connected to the same light-emitting element; the pixel density of the multiple first sub-pixels in the first display area is higher than the pixel density of the multiple second sub-pixels in the second display area; the display substrate further comprises a first power supply voltage terminal and a second power supply voltage terminal, the first power supply voltage terminal and the second power supply voltage terminal are insulated from each other, the first power supply voltage terminal is configured to output a first power supply voltage, the second power supply voltage terminal is configured to output a second power supply voltage, and the first power supply voltage is different from the second power supply voltage; the first pixel circuit is configured to be connected to the first power supply voltage terminal to receive the first power supply voltage as the pixel power supply voltage of the pixel circuit unit of the first pixel circuit, and the second pixel circuit is configured to be connected to the second power supply voltage terminal to receive the second power supply voltage as the pixel power supply voltage of the two pixel circuit units of the second pixel circuit.

[0062] The display substrate provided by the embodiment of the present disclosure can improve the brightness of the light-emitting elements in the second display area with lower pixel density by setting two pixel circuit units as pixel circuits to drive the light-emitting elements to emit light in the second display area, and at the same time provide pixel power supply voltages to the first display area and the second display area respectively, which helps to further improve the brightness of the second display area while also improving the stability of the pixel circuit and reducing circuit power consumption.

[0063] like Figure 1The basic pixel architecture shown includes a driving transistor T, a storage capacitor C and a light-emitting element D. The degree of opening of the channel of the driving transistor T controls the current Id flowing through the light-emitting element. The voltage difference between the power supply voltage VDD and the gate node of the driving transistor can control the degree of opening of the driving transistor T. For example, in the case where the light-emitting element is an organic light-emitting diode (OLED), when the driving transistor T operates in the saturation region, the current flowing through the OLED is Id=k / 2(Vdata-VDD)2, where k is the conductivity of the driving transistor T, Vdata is the written data voltage, and VDD is the power supply voltage.

[0064] For example, circuit simulation results show that, under the drive of the same data voltage Vdata voltage and power supply voltage VDD, compared with using one pixel unit to drive the OLED to emit light, two pixel units jointly driving the OLED can increase the light-emitting current to about 1.8 times.

[0065] At the same time, the inventors found that although the use of two pixel circuit units to drive the light-emitting element can increase the light-emitting current, it will also increase the voltage difference VEL across the light-emitting element, thereby reducing the source-drain voltage difference Vds of the driving transistor T, causing the working state of the driving transistor T to change, such as entering the linear region from the saturation region, which will reduce the stability of the light-emitting current, thereby reducing the light-emitting stability of the light-emitting element, and then reducing the stability of the display. The embodiment of the present disclosure can effectively solve this problem by providing the pixel power supply voltage VDD to the first display area and the second display area respectively to control the pixel power supply voltage VDD of the second display area separately. According to the voltage formula VDD-VSS=Vds+VEL, it can be known that the source-drain voltage difference Vds of the driving transistor T can be adjusted by increasing the voltage difference between VDD and VSS. For example, the pixel power supply voltage VDD of the second display area can be increased as needed, so that the working area of ​​the driving transistor is kept in the saturation region while increasing the light-emitting current, thereby not affecting the light-emitting stability of the light-emitting element. In addition, providing the power supply voltage VDD to the first display area and the second display area respectively can also reduce the impact on the power consumption of the display device.

[0066] It should be noted that the pixel density in the present disclosure refers to the number of sub-pixels per unit area, for example, it may be the number of light-emitting elements or the number of pixel circuits per unit area, and each pixel circuit is configured to be electrically connected to a light-emitting element.

[0067] Figure 2A This is one of the planar schematic diagrams of a display substrate provided in an embodiment of the present disclosure, Figure 2A The layout of the display area of ​​the display substrate is shown in FIG. Figure 2AAs shown, the display substrate 20 includes a display area 101, and the display area 101 includes a first display area 21 and a second display area 22. The second display area 22 can be located inside the first display area 21 and surrounded by the first display area 21; the second display area 22 can also be located outside the first display area 21, for example, half surrounded by the first display area 21. Figure 2A As shown, the display area 101 may further include a third display area 23 located in the second display area 22, and the third display area 23 is completely surrounded by the second display area 22, that is, sub-pixels in the second display area are arranged on each side of the third display area 23. In other examples, the second display area may also at least partially surround the third display area. Figure 2A The non-display area of ​​the display substrate is not shown.

[0068] Figure 2B The second schematic plan view of the display substrate provided in the embodiment of the present disclosure is as follows. Figure 2B FIG. 2 shows a pixel layout diagram of the display substrate. Figure 2B As shown, the display substrate 20 includes a plurality of pixel circuit units 100 located in a display area 101, and the plurality of pixel circuit units 100 are arranged in a plurality of rows and columns along a first direction D1 and a second direction D2; the first direction D1 and the second direction D2 are different, for example, the two directions are orthogonal. For example, the pixel rows and pixel columns do not necessarily extend strictly along a straight line, but may also extend along a curve (for example, a broken line), and the curve generally extends along the first direction D1 or the second direction D2, respectively. For example, the density of the pixel circuit units in the first display area 21 and the second display area 22 is the same, thereby improving the uniformity of the process.

[0069] like Figure 2B As shown, the display substrate includes a plurality of gate lines 11 and a plurality of data lines 12. For example, the gate lines 11 extend along a first direction D1, and the data lines 12 extend along a second direction D2. Figure 2B The figure only schematically shows the approximate positional relationship among the gate line 11 , the data line 12 and the pixel circuit unit 100 in the display substrate, and the specific positional relationship can be designed according to actual needs. Figure 2B Although it is shown that each gate line 11 and each data line 12 runs through the first display area 21 and the second display area 22, this is only for the convenience of drawing and is not intended to limit the present disclosure.

[0070] For example, each pixel circuit unit 100 includes a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, or nTmC (n, m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit unit 100 may further include a compensation subcircuit, the compensation subcircuit includes an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light emitting control subcircuit, a detection circuit, etc. For example, Figure 2B As shown, the display substrate 20 includes a non-display area 102 outside the display area 101. The display substrate may also include a gate driving circuit 13 and a data driving circuit 14 located in the non-display area. The gate driving circuit 13 is connected to the pixel circuit unit 100 through the gate line 11 to provide various scanning signals, and the data driving circuit 14 is connected to the pixel circuit unit 100 through the data line 12 to provide data signals.

[0071] Each pixel circuit unit 100 includes a driving subcircuit and a first connecting electrode for connecting to a light-emitting element. The first end of the driving subcircuit is configured to receive a pixel power supply voltage, and the second end is configured to be electrically connected to the light-emitting element through the first connecting electrode. The driving subcircuit of the pixel circuit unit is configured to form a driving current flowing through the light-emitting element in response to the pixel power supply voltage. The driving subcircuit will be described in detail in conjunction with the pixel circuit below.

[0072] like Figure 2B As shown, the first display area 21 includes a plurality of first sub-pixels, each of which includes a first pixel circuit 110, and the first pixel circuit 110 includes a pixel circuit unit 100, that is, it is composed of a pixel unit 100. The second display area 22 includes a plurality of second sub-pixels, each of which includes a second pixel circuit 120, and the second pixel circuit 120 includes two adjacent pixel circuit units 100, for example, the two pixel circuit units 100 are adjacent in the first direction D1. The first connection electrodes of the two pixel circuit units 100 of the second pixel circuit are electrically connected to each other to connect to the same light-emitting element, that is, the two pixel circuit units 100 are connected to the same pixel electrode, and jointly drive the same light-emitting element to emit light. Since the same light-emitting element is jointly driven by two pixel circuit units 100 in the second display area 22, the pixel density in the second display area is low, the distribution density of the light-emitting element is also low, and the light transmittance of the second display area is therefore higher than that of the first display area.

[0073] Figure 2B The third display area 23 is also schematically shown in FIG. Figure 2BAs shown, the pixel circuit unit 100 is not provided in the third display area 23, thereby improving the light transmittance of the third display area 23. When a photosensitive element is provided on the side of the display substrate opposite to the display side, the light to be detected mainly reaches the photosensitive element via the third display area 23, which will be described in detail later.

[0074] Figure 2C The third schematic plan view of the display substrate provided in the embodiment of the present disclosure is as follows: Figure 2C Schematic diagram of the layout of the power supply line of the display substrate. For the sake of clarity, Figure 2C The third display area 23 is omitted. The display substrate 20 also includes a first power supply voltage terminal 103 and a second power supply voltage terminal 104 located in the non-display area 102, the first power supply voltage terminal 103 and the second power supply voltage terminal 104 are insulated from each other, the first power supply voltage terminal 104 is configured to output a first power supply voltage VDD1, and the second power supply voltage terminal 104 is configured to output a second power supply voltage VDD2, and the first power supply voltage VDD1 is different from the second power supply voltage VDD2. The first pixel circuit 110 is configured to be connected to the first power supply voltage terminal 103 to receive the first power supply voltage VDD1 as the pixel power supply voltage of the pixel circuit unit 100 of the first pixel circuit 110. The second pixel circuit 120 is configured to be connected to the second power supply voltage terminal 104 to receive the second power supply voltage VDD2 as the pixel power supply voltage of the two pixel circuit units 100 of the second pixel circuit 120. The driving sub-circuits in the two pixel circuit units 100 in the second pixel circuit 120 are both configured to receive the second power supply voltage VDD2 to drive the light-emitting element to emit light.

[0075] The display substrate 20 further includes a first power line 210 and a second power line 220 . The first power line 210 is configured to provide a first power voltage VDD1 to the first sub-pixel 110 in the first display area 21 , and the second power line 220 is configured to provide a second power voltage VDD2 to the second sub-pixel in the second display area 22 .

[0076] like Figure 2C As shown, the plurality of first power lines 210 and the plurality of second power lines 220 extend along the second direction D2, respectively, and the plurality of first power lines 210 and the plurality of second power lines 220 are arranged along the first direction D1, respectively. Figure 2CAs shown, a plurality of first power lines 210 are located in the first display area 21, and a plurality of second power lines 220 are located in the second display area 22. For example, the first power lines 210 and the second power lines 220 are arranged in the same layer and insulated from each other. For example, a plurality of second power lines 220 correspond to a plurality of first power lines 210 one by one, and each second power line 220 is arranged in parallel with the corresponding first power line 210 in the second direction D2 and is spaced from each other; that is, at least one end of the second power line 220 (i.e., the end close to the first display area) is floating. Figure 2C The dotted line in the figure shows the boundary between the first display area 21 and the second display area 22. Each second power line 220 and the corresponding first power line 210 are located on a virtual line, and the virtual line is disconnected at the boundary.

[0077] For example, multiple first power lines 210 are electrically connected to the first power supply voltage terminal 103 and connected to the driving sub-circuit of multiple first pixel circuits to provide the first power supply voltage VDD1, and multiple second power lines 220 are electrically connected to the second power supply voltage terminal 104 and connected to the driving sub-circuit of multiple second sub-pixels to provide the second power supply voltage VDD2.

[0078] For example, Figure 2C As shown, the display substrate 20 further includes a first power supply line 105 and a second power supply line 106 located in the non-display area 102. The first power supply line 105 electrically connects the first power supply voltage terminal 103 with a plurality of first power supply lines 210, and the second power supply line 106 electrically connects the second power supply voltage terminal 104 with a plurality of second power supply lines 220. For example, Figure 2C As shown, the first power line 105 and the second power line 106 are both arranged around the display area 101, and the first power line 105 is closer to the display area 101 than the second power line 106. For example, the second power line 106 is led out from the second power supply voltage terminal 104 located at the lower side of the first display area 21, extends around the left and right sides of the first display area 21, and connects to the second display area 22 from the upper side of the display area (the side opposite to the first power supply voltage terminal and the second power supply voltage terminal).

[0079] For example, Figure 2C As shown, the display substrate 20 further includes a third power line 230 and a fourth power line 240. The third power line 230 is configured to provide a first power voltage VDD1 for the first sub-pixel in the first display area 21, and the fourth power line 240 is configured to provide a second power voltage VDD2 for the second sub-pixel in the second display area 22.

[0080] like Figure 2C As shown, the plurality of third power lines 230 and the plurality of fourth power lines 240 extend along the first direction D1, respectively, and the plurality of third power lines 230 and the plurality of fourth power lines 240 are arranged along the second direction D2, respectively. Figure 2C As shown, a plurality of third power lines 230 are located in the first display area 21, and a plurality of fourth power lines 240 are located in the second display area 22. For example, the third power lines 230 and the fourth power lines 240 are arranged in the same layer and insulated from each other, for example, located on the side of the first power line 210 and the second power line 220 close to the substrate. Figure 2C As shown, a plurality of third power lines 230 correspond to a plurality of fourth power lines 240 one by one, and each third power line 230 and the corresponding fourth power line 240 are arranged side by side in the first direction D1 and are spaced from each other; that is, both ends of the fourth power line 220 are floating. Each third power line 230 and the corresponding fourth power line 240 are on a virtual line, and the virtual line is disconnected at the boundary area.

[0081] It should be noted that the "floating" of one end of the power line of the present disclosure means that the one end of the power line is not connected to other wires or structures, but does not mean that the power line is in a floating state. For example, the first power line and the second power line are arranged on the same layer and are formed by the same conductive layer through an etching process, so that the floating end of the second power line has an etched surface. Similarly, the floating end of the fourth power line has an etched surface.

[0082] For example, each third power line 230 is electrically connected to at least one of the plurality of first power lines 210 through at least one via hole (not shown), so that the third power lines 230 and the first power lines 210 are interwoven into a mesh structure; each fourth power line 240 is electrically connected to at least one of the plurality of second power lines 220 through at least one via hole (not shown), so that the fourth power lines 240 and the second power lines 220 are interwoven into a mesh structure. This structure helps to reduce the resistance of the power line, thereby reducing the voltage drop on the power line, and helps to evenly deliver the power voltage to each sub-pixel, thereby improving the uniformity of the display substrate.

[0083] For example, the display substrate 20 may further include a control circuit (not shown). For example, the control circuit is configured to control the data drive circuit 14 to apply the data signal, and control the gate drive subcircuit to apply the scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit may be in various forms, such as including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0084] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0085] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium.

[0086] The pixel circuit may include a driving subcircuit, a data writing subcircuit, a compensation subcircuit and a storage subcircuit, and may also include a light emitting control subcircuit, a reset circuit, etc. as required.

[0087] Figure 3A FIG. 1 is a circuit diagram of a pixel circuit unit 100 provided in at least one embodiment of the present disclosure.

[0088] like Figure 3A As shown, the pixel circuit unit 100 includes a driving subcircuit 122, a compensation subcircuit 128, a data writing subcircuit 126, a storage subcircuit 127, a first light-emitting control subcircuit 123, a second light-emitting control subcircuit 124, a first reset subcircuit 125 and a second reset subcircuit 129.

[0089] For example, the driving subcircuit 122 includes a control terminal 122a, a first terminal 122b, and a second terminal 122c, and is configured to be connected to the light emitting element 121 and control the driving current flowing through the light emitting element 121. The control terminal 122a of the driving subcircuit 122 is connected to the first node N1, the first terminal 122b of the driving subcircuit 122 is connected to the second node N2 and is configured to receive the pixel power supply voltage VDD, and the second terminal 122c of the driving subcircuit 122 is connected to the third node N3.

[0090] For example, the data writing subcircuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c, wherein the control terminal 126a is configured to receive a first scanning signal Ga1, the first terminal 126b is configured to receive a data signal Vd, and the second terminal 126c is connected to a first terminal 122b (i.e., a second node N2) of the driving subcircuit 122. The data writing subcircuit 126 is configured to write the data signal Vd into the first terminal 122b of the driving subcircuit 122 in response to the first scanning signal Ga1. For example, the first terminal 126b of the data writing subcircuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11 as a scanning line to receive the first scanning signal Ga1. For example, in the data writing and compensation stage, the data writing sub-circuit 126 can be turned on in response to the first scanning signal Ga1, so that the data signal can be written to the first end 122b (the second node N2) of the driving sub-circuit 122, and the data signal can be stored in the storage sub-circuit 127, so that a driving current can be generated according to the data signal to drive the light-emitting element 121 to emit light, for example, in the light-emitting stage.

[0091] For example, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b and a second terminal 128c. The control terminal 128a of the compensation sub-circuit 128 is configured to receive a second scanning signal Ga2. The first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the driving sub-circuit 122, respectively. The compensation sub-circuit 128 is configured to perform threshold compensation on the driving sub-circuit 122 in response to the second scanning signal Ga2.

[0092] For example, the first scan signal Ga1 may be the same as the second scan signal Ga2. For example, the first scan signal Ga1 may be connected to the same signal output terminal as the second scan signal Ga2. For example, the first scan signal Ga1 may be transmitted through the same scan line as the second scan signal Ga2.

[0093] In some other examples, the first scanning signal Ga1 may be different from the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to different signal output terminals. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted through different scanning lines.

[0094] For example, the storage subcircuit 127 includes a first terminal 127a and a second terminal 127b, wherein the first terminal 127a of the storage subcircuit is configured to receive the pixel power supply voltage VDD, and the second terminal 127b of the storage subcircuit is electrically connected to the control terminal 122a of the driving subcircuit. For example, in the data writing and compensation stage, the compensation subcircuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 can be stored in the storage subcircuit 127; at the same time, the compensation subcircuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving subcircuit 122, so that the relevant information of the threshold voltage of the driving subcircuit 122 can also be stored in the storage subcircuit accordingly, so that, for example, in the light emitting stage, the stored data signal and the threshold voltage can be used to control the driving subcircuit 122, so that the output of the driving subcircuit 122 is compensated.

[0095] For example, the storage subcircuit 127 is electrically connected to the control terminal 122a of the driving subcircuit 122 and the pixel power supply voltage terminal VDD, and is configured to store the data signal written by the data writing subcircuit 126. For the pixel circuit unit of the first pixel circuit 110 located in the first display area 21, the pixel power supply voltage terminal VDD is the first power supply voltage terminal 103; for the pixel circuit unit of the second pixel circuit 120 located in the second display area 22, the pixel power supply voltage terminal VDD is the second power supply voltage terminal 104. For example, in the data writing and compensation stage, the compensation subcircuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 can be stored in the storage subcircuit 127. For example, during the data writing and compensation stages, the compensation sub-circuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving sub-circuit 122, so that the relevant information of the threshold voltage of the driving sub-circuit 122 can also be correspondingly stored in the storage sub-circuit, so that, for example, the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 during the light-emitting stage, so that the output of the driving sub-circuit 122 is compensated.

[0096] For example, the first light emitting control subcircuit 123 is connected to the first terminal 122b (the second node N2) and the first voltage terminal VDD of the driving subcircuit 122, and is configured to apply the first power supply voltage of the first voltage terminal VDD to the first terminal 122b of the driving subcircuit 122 in response to the first light emitting control signal EM1. Figure 3A As shown, the first light emitting control sub-circuit 123 is connected to the first light emitting control terminal EM1, the first voltage terminal VDD and the second node N2.

[0097] For example, the second light emitting control subcircuit 124 is connected to the second light emitting control terminal EM2, the first terminal 134 of the light emitting element 121 and the second terminal 122c of the driving subcircuit 122, and is configured to respond to the second light emitting control signal so that the driving current can be applied to the light emitting element 122.

[0098] For example, in the light-emitting stage, the second light-emitting control subcircuit 123 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving subcircuit 122 can be electrically connected to the light-emitting element 121 through the second light-emitting control subcircuit 123, thereby driving the light-emitting element 121 to emit light under the control of the driving current; while in the non-light-emitting stage, the second light-emitting control subcircuit 123 is turned off in response to the second light-emitting control signal EM2, thereby preventing current from flowing through the light-emitting element 121 to cause it to emit light, thereby improving the contrast of the corresponding display device.

[0099] For another example, in the initialization phase, the second light emitting control sub-circuit 124 may also be turned on in response to the second light emitting control signal EM2 , so that the reset circuit may be combined to perform a reset operation on the driving sub-circuit 122 and the light emitting element 121 .

[0100] For example, the second light emitting control signal EM2 may be the same as the first light emitting control signal EM1, for example, the second light emitting control signal EM2 may be connected to the same signal output terminal as the first light emitting control signal EM, for example, the second light emitting control signal EM2 may be transmitted through the same light emitting control line as the first light emitting control signal EM1.

[0101] In some other examples, the second light emitting control signal EM2 may be different from the first light emitting control signal EM1. For example, the second light emitting control signal EM2 and the first light emitting control signal EM1 may be connected to different signal output terminals, respectively. For example, the second light emitting control signal EM2 and the first light emitting control signal EM1 may be transmitted through different light emitting control lines, respectively.

[0102] For example, the first reset subcircuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the driving subcircuit 122, and is configured to apply the first reset voltage Vinit1 to the control terminal 122a of the driving subcircuit 122 in response to the first reset control signal Rst1.

[0103] For example, the second reset subcircuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 122b (fourth node N4) of the light emitting element 122, and is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light emitting element 121 in response to the second reset control signal Rst2.

[0104] For example, the first reset sub-circuit 125 and the second reset sub-circuit 129 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 can be applied to the first node N1 and the first reset voltage Vinit1 can be applied to the first end 134 of the light-emitting element 121, respectively, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting element 121 can be reset to eliminate the influence of the previous light-emitting stage.

[0105] For example, the second reset control signal Rst2 of each row of sub-pixels can be the same signal as the first scanning signal Ga1 of the sub-pixels in the row, and the two can be transmitted through the same gate line 11. For example, the first reset control signal Rst1 of each row of sub-pixels can be the same signal as the first scanning signal Ga1 of the sub-pixels in the previous row, and the two can be transmitted through the same gate line 11.

[0106] For example, the light emitting element 121 includes a first terminal 134 and a second terminal 135, the first terminal 134 of the light emitting element 121 is configured to be connected to the second terminal 122c of the driving sub-circuit 122, and the second terminal 135 of the light emitting element 121 is configured to be connected to the second voltage terminal VSS. Figure 3A As shown, the first terminal 134 of the light emitting element 121 may be connected to the fourth node N4 through the second light emitting control sub-circuit 124. The embodiments of the present disclosure include but are not limited to this case.

[0107] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but represent the junction points of related circuit connections in the circuit diagram.

[0108] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scanning signal and the second scanning signal, and can also represent the first scanning signal terminal and the second scanning signal terminal. Rst can represent both the reset control terminal and the reset control signal. The symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal, and can also represent the first reset voltage and the second reset voltage. The symbol VDD can represent both the pixel power supply voltage and the pixel power supply voltage terminal. The symbol VSS can represent both the common power supply voltage terminal and the common power supply voltage. The following embodiments are the same as this and will not be repeated.

[0109] Figure 3B for Figure 3A A circuit diagram of a specific implementation example of a pixel circuit is shown. Figure 3AAs shown, the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and a storage capacitor Cst. For example, the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

[0110] For example, Figure 3B As shown, the driving subcircuit 122 can be implemented as a first transistor T1. The gate of the first transistor T1 serves as a control terminal 122a of the driving subcircuit 122 and is connected to the first node N1; the first electrode of the first transistor T1 serves as a first terminal 122b of the driving subcircuit 122 and is connected to the second node N2; the second electrode of the first transistor T1 serves as a second terminal 122c of the driving subcircuit 122 and is connected to the third node N3.

[0111] For example, Figure 3B As shown, the data writing subcircuit 126 can be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second electrode of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.

[0112] For example, Figure 3B As shown, the compensation subcircuit 128 can be implemented as a third transistor T3. The gate, the first electrode, and the second electrode of the third transistor T3 serve as the control electrode 128a, the first electrode 128b, and the second electrode 128c of the compensation subcircuit, respectively. The gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first electrode T3s of the third transistor T3 is connected to the second electrode T1d (the third node N3) of the first transistor T1, and the second electrode T3d of the third transistor T3 is electrically connected to the gate T1g (the first node N1) of the first transistor T1. For example, Figure 3B As shown, the storage subcircuit 127 can be implemented as a storage capacitor Cst, which includes a first capacitor electrode Ca and a second capacitor electrode Cb. The first capacitor electrode Ca is electrically connected to the pixel power supply voltage terminal VDD, and the second capacitor electrode Cb is electrically connected to the gate T1g (first node N1) of the first transistor T1.

[0113] For example, Figure 3BAs shown, the first light-emitting control subcircuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, the first electrode of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, and the second electrode of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.

[0114] For example, the light emitting element 121 is specifically implemented as a light emitting diode (LED), for example, an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED) or an inorganic light emitting diode, for example, a micro light emitting diode (Micro LED) or a micro OLED. For example, the light emitting element 121 can be a top emission structure, a bottom emission structure or a double-sided emission junction. The light emitting element 121 can emit red light, green light, blue light or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light emitting element.

[0115] For example, the first electrode 134 (e.g., an anode) of the light emitting element 121 and the fourth node N4 are connected and configured to be connected to the second terminal 122c of the driving subcircuit 122 through the second light emitting control subcircuit 124, and the second electrode 135 (e.g., a cathode) of the light emitting element 121 is configured to be connected to the common power supply voltage terminal VSS to receive the common power supply voltage VSS, and the circuit that flows from the second terminal 122c of the driving subcircuit 122 into the light emitting element 121 determines the brightness of the light emitting element. For example, the common power supply voltage terminal VSS can be grounded, that is, VSS can be 0V. For example, the common power supply voltage VSS can be a negative voltage.

[0116] For example, the second light emitting control subcircuit 124 can be implemented as a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second light emitting control line (the second light emitting control terminal EM2) to receive the second light emitting control signal, the first electrode of the fifth transistor T5 is connected to the second terminal 122c (the third node N3) of the driving subcircuit 122, and the second electrode of the fifth transistor T5 is connected to the first terminal 134 (the fourth node N4) of the light emitting element 121.

[0117] For example, the first reset subcircuit 125 can be implemented as a sixth transistor T6, and the second reset subcircuit can be implemented as a seventh transistor T7. The gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and the second electrode of the sixth transistor T6 is configured to be connected to the first node N1. The gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and the second electrode of the seventh transistor T7 is configured to be connected to the fourth node N4.

[0118] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as examples. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0119] In addition, transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages). For example, Figure 3B As shown, the first to seventh transistors T1-T7 are all P-type transistors, such as low temperature polysilicon thin film transistors. However, the disclosed embodiment does not limit the type of transistors, and when the type of transistors changes, the connection relationship in the circuit can be adjusted accordingly.

[0120] It can be understood that the circuit diagram of the pixel circuit unit 100 is the circuit diagram of the first pixel circuit of the first sub-pixel 110 .

[0121] Figure 3C FIG. 1 shows a circuit diagram of a second pixel circuit 120 of a second sub-pixel. Figure 3C As shown, the second pixel circuit is composed of two pixel circuit units 100 , and the fourth nodes of the two pixel circuit units 100 are electrically connected to each other and connected to the same light emitting element 121 .

[0122] The following combination Figure 3D The signal timing diagram shown is Figure 3B The working principle of the pixel circuit shown in FIG. Figure 3D As shown, the display process of each frame of image includes three stages, namely initialization stage 1, data writing and compensation stage 2, and light emitting stage 3.

[0123] like Figure 3D As shown, in this embodiment, the first scanning signal Ga1 and the second scanning signal Ga2 use the same signal, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 use the same signal; and the second reset control signal Rst2 and the first scanning signal Ga1 / the second scanning signal Ga2 have the same waveform, that is, the second reset control signal Rst2 and the first scanning signal Ga1 / the second scanning signal Ga2 can use the same signal; the first reset signal Rst1 of the sub-pixel in this row has the same waveform as the first scanning signal Ga1 / the second scanning signal Ga2 of the sub-pixel in the previous row, that is, the same signal is used. However, this is not a limitation to the present disclosure, and in other embodiments, different signals can be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first light-emitting control signal EM1 and the second light-emitting control signal EM2.

[0124] In the initialization phase 1, the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.

[0125] In the data writing and compensation stage 2, the first scanning signal Ga1, the second scanning signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, the data signal Vd is written into the second node N2 by the second transistor T2, and the first node N1 is charged through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd+Vth, and the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. The potential of the first node N1 is stored in the storage capacitor Cst and maintained, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.

[0126] In the data writing phase 2, the second reset control signal Rst2 may be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 may be applied to the fourth node N4, thereby resetting the fourth node N4. For example, the fourth node N4 may also be reset in the initialization phase 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. The embodiments of the present disclosure are not limited to this.

[0127] In the light emitting stage 3, the first light emitting control signal EM1 and the second light emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5 and the first transistor T1, and the fifth transistor T5 applies the driving current to the OLED to make it emit light. The value of the driving current Id flowing through the OLED can be obtained according to the following formula:

[0128] Id=K(VGS-Vth) 2 =K[(Vdata+Vth-VDD)-Vth] 2 =K(Vdata-VDD) 2 , where K is the conductivity coefficient of the first transistor.

[0129] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and the source (here, the first electrode) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. It can be seen from the above calculation formula of Id that the driving current Id flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1, thereby achieving compensation for the pixel circuit, solving the problem of threshold voltage drift caused by the process and long-term operation of the driving transistor (the first transistor T1 in the embodiment of the present disclosure), eliminating its influence on the driving current Id, and thus improving the display effect of the display device using it.

[0130] The following Figure 3B-3C As an example, the pixel circuit shown in FIG. Figure 4A-4B , Figure 5 , Figure 6A-6B , Figures 7A-7C The structure of a display substrate provided in at least one embodiment of the present disclosure is exemplarily described.

[0131] Figure 4A A schematic diagram of a display substrate 20 provided in at least one embodiment of the present disclosure, Figure 4A The corresponding Figure 2C FIG. 2 is an enlarged schematic diagram of a region A at the boundary between the first display region 21 and the second display region 22, wherein a dotted line BB' is used to indicate the boundary between the first display region 21 and the second display region 22; Figure 4ASchematically shows four rows and four columns of pixel circuit units in the second display area 22 and the pixel circuit units adjacent thereto in the first display area 21 . Figure 4B for Figure 4A A cross-sectional view along section line II′. It should be noted that for the sake of clarity, Figure 4B Some structures that do not have direct electrical connections at the cross-section lines are omitted. Figure 5 , Figure 6A-6B , Figure 7A-7B as well as Figure 8B The corresponding position of FIG. 1 is also shown as the section line II′.

[0132] Combination Figure 4A-4B It can be seen that the display substrate 20 includes a semiconductor layer 107, a first insulating layer 301, a first conductive layer 201, a second insulating layer 302, a second conductive layer 202, a third insulating layer 303, a third conductive layer 203, a fourth insulating layer 304 and a fourth conductive layer 204 which are sequentially arranged on the base substrate 20.

[0133] The pattern of the semiconductor layer and the pattern of the first conductive layer in each pixel circuit unit are the same. Figure 5 Schematically shows the semiconductor layer 107 and the first conductive layer (gate layer) 201 of the transistors T1 to T7 in four adjacent pixel circuit units in the first direction D1; Fig. 6A correspond Figure 4A A second conductive layer 202 is shown, Figure 6B correspond Figure 4A The semiconductor layer 107, the first conductive layer 201 and the second conductive layer 202 are shown; Fig. 7A A third conductive layer 203 is shown, Figure 7B exist Figure 6B The third conductive layer 203 is shown on the basis of Figure 7C shows a schematic diagram of data line connection; Fig. 8A A fourth conductive layer 204 is shown, Figure 8B exist Figure 7B The fourth conductive layer 204 is shown on the basis.

[0134] For the convenience of explanation, in the following description, Tng, Tns, and Tnd are used to represent the gate, the first electrode, and the second electrode of the nth transistor Tn, respectively, where n is 1-7.

[0135] It should be noted that the "same-layer arrangement" referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process, and their materials may be the same or different. The "integrated structure" in the present disclosure refers to a structure in which two (or more) structures are connected to each other by patterning the same film layer through the same composition process, and their materials may be the same or different.

[0136] For example, Figure 5 As shown, the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines. Figure 5 The area where each pixel circuit unit is located is shown by a large dotted line frame, and the gates T1g-T7g of the first to seventh transistors T1-T7 in a pixel circuit unit 100 are shown by a small dotted line frame.

[0137] The semiconductor layer 107 includes active layers T1a-T7a of the first to seventh transistors T1-T7. Figure 5 As shown, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integrated structure. For example, the semiconductor layers 107 in each column of sub-pixels are connected to each other as an integrated structure, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.

[0138] For example, Figure 5 As shown, the first conductive layer 201 includes gate electrodes T1g-T7g of the first to seventh transistors T1-T7. For example, the display substrate 20 adopts a self-alignment process, and uses the first conductive layer 201 as a mask to perform a conductorization process (e.g., a doping process) on the semiconductor layer 107, so that the portion of the semiconductor layer 107 not covered by the first conductive layer 201 is conductorized, so that the portion of the active layer of each transistor located on both sides of the channel region is conductorized to form the first electrode and the second electrode of the transistor respectively.

[0139] For example, the first conductive layer 201 further includes a plurality of gate lines 11 insulated from each other, and the gate lines 11 include, for example, a plurality of scan lines 310, a plurality of reset control lines 320, and a plurality of light-emitting control lines 330. Here, the gate line 11 refers to a signal line directly connected to the gate of the transistor to provide a scan signal or a control signal. For example, each row of sub-pixels is respectively connected to a scan line 310, two reset control lines 320, and a light-emitting control line 330.

[0140] The scan line 310 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide a first scan signal Ga1, a reset control line 320 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a first reset control signal Rst1, and the light-emitting control line 330 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a first light-emitting control signal EM1.

[0141] For example, Figure 5 As shown, the gate of the seventh transistor T7 of the pixel circuit in this row is electrically connected to the reset control line 220 corresponding to the pixel circuit in the next row (i.e., the pixel circuit row where the scan lines that are sequentially turned on after the scan lines in this row are located according to the scan order of the scan lines) to receive the second reset control signal Rst2.

[0142] For example, Figure 5 As shown, the scan line 310 is also electrically connected to the gate of the third transistor T3 to provide a second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 can be the same signal; the light-emitting control line 330 is also electrically connected to the gate of the fifth transistor T5 to provide a second light-emitting control signal EM2, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same signal.

[0143] For example, the first gate T3g1 extends along the first direction D1 and is a part of the scan line 310. The second gate T3g2 extends along the second direction D2 and is an extension of the scan line 210 extending along the second direction D2.

[0144] For example, Figure 6A-6B As shown, the second conductive layer 202 includes a first capacitor electrode Ca. The first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 200 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 acts as a second capacitor electrode Cb of the storage capacitor Cst. For example, the first capacitor electrode Ca includes an opening 221, and the opening 221 exposes at least a portion of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures. The first capacitor electrode Ca located in the first display area is electrically connected to the first power line 210 through a via hole to receive the first power supply voltage VDD1, and the first capacitor electrode Ca located in the second display area is electrically connected to the second power line 220 through a via hole to receive the second power supply voltage VDD2, which will be described in detail later.

[0145] like Fig. 6AAs shown, for example, in the first display area 21, the first capacitor electrodes Ca of the pixel circuit units 100 located in the same pixel row and adjacent to each other are connected to each other as an integrated structure; in the second display area 22, the first capacitor electrodes Ca of the pixel circuit units 100 located in the same row and adjacent to each other are connected to each other as an integrated structure.

[0146] For example, Fig. 6A As shown, the first capacitor electrode Ca of the first sub-pixel and the first capacitor electrode Ca of the second sub-pixel adjacent to each other in the first direction D1 are arranged in the same layer and spaced apart from each other. This is because the first capacitor electrodes located in the two display areas need to receive different pixel power supply voltages VDD respectively, so the two need to be insulated. Fig. 6A and 6B The dotted line BB′ shows the boundary between the first display area and the second display area, and the following embodiments are the same and will not be described in detail.

[0147] In some examples, multiple third power lines 230 are respectively arranged in one-to-one correspondence with multiple rows of first pixel circuits (i.e., multiple rows of pixel circuit units located in the first display area), and multiple fourth power lines 240 are respectively arranged in one-to-one correspondence with multiple rows of second pixel circuits (i.e., multiple rows of pixel circuit units located in the second display area); each third power line is integrally formed with the first capacitor electrode Ca of the pixel circuit unit of the corresponding row of first sub-pixels, and each fourth power line 240 is integrally formed with the first capacitor electrode Ca of the pixel circuit unit of the corresponding row of second sub-pixels; that is, a portion of the third power line 230 serves as the first capacitor electrode Ca of the first pixel circuit, and a portion of the fourth power line 240 serves as the first capacitor electrode Ca of the second pixel circuit.

[0148] For example, Figure 6A-6B As shown, the second conductive layer 202 may further include a plurality of reset voltage lines 340 extending along the first direction D1, the plurality of reset voltage lines 340 being connected one-to-one with a plurality of rows of sub-pixels. The reset voltage line 340 is electrically connected to the first electrode of the sixth transistor T6 in a corresponding row of sub-pixels to provide a first reset voltage Vinit1.

[0149] For example, Figure 6B As shown, the first electrode of the seventh transistor T7 in the sub-pixel of this row is electrically connected to the reset voltage line 340 corresponding to the sub-pixel of the next row to receive the second reset voltage Vinit2. Figure 7B This is described in detail.

[0150] For example, Figure 6A-6BAs shown, each second sub-pixel located in the second display area 22 further includes a connecting electrode 222 (an example of the second connecting electrode disclosed in the present disclosure) located in the second conductive layer 202, and the connecting electrode 222 writes the data of the two pixel circuit units of the second pixel circuit into the first end of the sub-circuit (reference Figure 5 , that is, the first electrode T2s of the second transistor T2 is electrically connected to each other, so that the data writing sub-circuit of the two pixel circuit units writes the same data voltage in the data writing and compensation stages, so that the light-emitting element can emit light according to the corresponding display grayscale data in the light-emitting stage.

[0151] For example, Figure 6A-6B As shown, the second conductive layer 202 further includes a connecting electrode 223 (an example of the third connecting electrode of the present disclosure), and the connecting electrode 223 is located at the boundary between the first display area 21 and the second display area 22. The connecting electrode 223 is used to write the data of the first sub-pixel in the first display area 21 into the first end of the sub-circuit and electrically connect the data line in the second display area 22 to provide a data signal for the second sub-pixel. Figure 7B-7C This is described in detail.

[0152] For example, Figure 6A-6B As shown, the second conductive layer 202 may further include a shielding electrode 224. For example, the shielding electrode 224 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the substrate 200, thereby protecting the signal in the first electrode T2s of the second transistor T2 from interference by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive a data signal Vd, and the data signal Vd determines the display grayscale of the sub-pixel, the shielding electrode 224 improves the stability of the data signal, thereby improving the display performance.

[0153] For example, combined with reference Figure 6B and Figure 5 The shielding electrode 224 also at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the substrate 200 to improve the stability of the signal in the second electrode T6d, thereby improving the stability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0154] For example, combined with reference Figure 6B and Figure 5 The shielding electrode 224 also extends to the adjacent pixel circuit unit and at least partially overlaps with the active layer of the third transistor T3 in the adjacent pixel circuit unit in a direction perpendicular to the substrate 200, so as to improve the stability of the third transistor T3 and further stabilize the gate voltage of the first transistor T1.

[0155] For example, the shielding electrode 224 is configured to load a fixed voltage; for example, the shielding electrode 224 is electrically connected to a power line in the third conductive layer to load a pixel power voltage VDD, which will be described later in conjunction with Figure 7B This is described in detail.

[0156] For example, Figure 7A-7B As shown, the third conductive layer 203 includes a plurality of first power lines 210 and a plurality of second power lines 220. For example, the plurality of first power lines 210 are electrically connected to a plurality of columns of pixel circuit units located in the first display area 21 in a one-to-one correspondence to provide a first power supply voltage VDD1. The plurality of second power lines 220 are electrically connected to a plurality of columns of pixel circuit units located in the second display area 22 in a one-to-one correspondence to provide a second power supply voltage VDD2. The first power lines 210 and the second power lines 220 corresponding to the same column of pixel circuit units are arranged at intervals to be insulated from each other; that is, the first power line 210 corresponding to the first sub-pixel and the second power line 220 corresponding to the pixel circuit unit of the second sub-pixel adjacent to the first sub-pixel in the second direction D2 are arranged at intervals to each other. For example, the first power line 210 corresponding to the first sub-pixel adjacent to the second sub-pixel in the first direction D1 is continuously arranged in the second direction D2, running through the entire first display area 21.

[0157] Combined with reference Figure 7B , the first power line 210 is electrically connected to the first capacitor electrode Ca in the corresponding column of pixel circuit units 100 through a via 341 (an example of the first via of the present disclosure), and the second power line 220 is electrically connected to the first capacitor electrode Ca in the corresponding column of pixel circuit units 100 through a via 342 (an example of the second via of the present disclosure). The first power line 210 and the second power line are also electrically connected to the first pole T4s of the fourth transistor T4 through a via 343, respectively. The first power line 210 and the second power line 220 are also electrically connected to the shielding electrode 224 through a via 344, respectively, so that the shielding electrode 224 has a fixed potential, thereby improving the shielding ability of the shielding electrode. For example, the vias 341, 342 and the via 344 all penetrate the third insulating layer 303, and the via 343 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0158] For example, the third conductive layer 203 further includes a plurality of main data lines 250 and a plurality of auxiliary data lines 260 extending along the second direction, the plurality of main data lines 250 are arranged along the first direction D1, and the plurality of auxiliary data lines 260 are arranged along the first direction D1; the plurality of main data lines 250 are electrically connected to the first ends of the data subcircuits of the plurality of columns of pixel circuit units in the first display area 21 in a one-to-one correspondence to provide data signals; the plurality of auxiliary data lines 260 are electrically connected to the first ends of the data subcircuits of the plurality of pixel circuit units in the second display area 22 in a one-to-one correspondence to provide data signals. The main data lines 250 and the auxiliary data lines 260 corresponding to the same column of pixel circuit units in the second direction D2 correspond to each other in a one-to-one correspondence, and each auxiliary data line 260 is arranged in parallel with the corresponding main data line 250 in the second direction D2.

[0159] like Figure 7A-7B As shown, the auxiliary data lines 260 are directly electrically connected to the corresponding main data lines 250 or are spaced apart and insulated from each other, which is related to the pixel arrangement of the display substrate 20 .

[0160] Figure 7C A schematic diagram of data lines of a display substrate provided by at least one embodiment of the present disclosure is shown. Figure 7C Schematically shows four rows and eight columns of pixel circuit units 100 (ie, four rows and four columns of second pixel circuits 120) located in the second display area and a corresponding row and eight columns of pixel circuit units 100 (ie, one row and eight columns of first pixel circuits 110) located in the first display area.

[0161] like Figure 7C As shown, the plurality of auxiliary data lines 260 are divided into a plurality of data line groups 140 , each data line group 140 includes two auxiliary data lines 260 , and the plurality of data line groups 140 are electrically connected to a plurality of columns of second pixel circuits 120 in a one-to-one correspondence to provide data signals. Figure 7C Four data line groups 140 corresponding to four columns of second pixel circuits are shown.

[0162] Combined with reference Figure 4A-4B and Figure 7B-7C The first ends of the first data sub-circuits of the two pixel circuit units in each second pixel circuit 120 are electrically connected through the connecting electrode 222, and each second pixel circuit 120 is electrically connected to the corresponding auxiliary data line 260 through the connecting electrode 222 to receive data signals for use by its two data sub-circuits.

[0163] For example, combined with reference Figure 7B and Figure 7C, two second pixel circuits located in the nth row and the n+1th row and in the same column in the plurality of rows of second pixel circuits 120 constitute a pixel circuit group 130, sharing one auxiliary data line 260, that is, the connection electrodes 222 of the two second pixel circuits in the pixel circuit group 130 are both electrically connected to the auxiliary data line 260; n is an odd or even number greater than 0. In the second direction D2, the pixel circuit group 130 located in the same column is alternately electrically connected to the two auxiliary data lines 260 in the data line group 140 corresponding to the second pixel circuits 120 in the column.

[0164] Combined with reference Figure 7B and Figure 7C , the four auxiliary data lines 260 in two adjacent data line groups 140 are a first data line 261, a second data line 262, a third data line 263 and a fourth data line 264 arranged in sequence in the first direction. The first data line 261 is directly electrically connected to the corresponding main data line 250, and the second data line 262, the third data line 263 and the fourth data line 264 are respectively arranged in the same layer and spaced apart from the corresponding main data line 250. The fourth data line 264 is electrically connected to the main data line 260 corresponding to the second data line 262 through the connecting electrode 223. This arrangement is related to the pixel arrangement of the display substrate.

[0165] For example, Figure 7C As shown, two adjacent pixel circuit groups 130 correspond to four second pixel circuits 120 and constitute a minimum repeating unit P. For example, the four second pixel circuits are respectively configured to drive a red light-emitting element, two green light-emitting elements and one blue light-emitting element to emit light, thereby achieving full-color display. In this embodiment, a minimum repeating unit P includes four second pixel circuits, which is related to the pixel arrangement of the display substrate provided in the embodiment of the present disclosure. However, the number of pixel circuits included in the minimum repeating unit of the embodiment of the present disclosure is not limited. For example, in other examples, the minimum repeating unit may include three pixel circuits, which are respectively configured to drive a red light-emitting element, a green light-emitting element and a blue light-emitting element to emit light.

[0166] For example, in order to improve the display uniformity of the display substrate, it is necessary to set a light-emitting element in the third display area for display, and in order to improve the transmittance of the third display area, the third display area does not have a pixel circuit, so the pixel circuit corresponding to the light-emitting element in the third display area needs to be set in other areas, such as the second display area. Therefore, in the second display area, a part of the light-emitting elements corresponding to the second pixel circuit are set in the second display area, and a part of the light-emitting elements corresponding to the second pixel circuit are not set in the second display area, and this part of the second pixel circuit is set in units of the minimum repeating unit P, so as not to affect the display function of the display substrate. For example, the second display area includes N minimum repeating units P, and the light-emitting elements corresponding to the second pixel circuit 120 of M minimum repeating units P (referred to as the first minimum repeating unit P1) among the N minimum repeating units P are set in the second display area, and the light-emitting elements corresponding to the remaining NM minimum repeating units P (referred to as the second minimum repeating unit P2) are not set in the second display area 22. For example, the light emitting elements corresponding to the second pixel circuits of L minimum repeating units P among the N minimum repeating units P are arranged in the third display area 23, for example, L is less than or equal to NM; M is less than N, and N, M, and L are all positive integers.

[0167] For example, Figure 7C The four minimum repeating units P arranged in an array are shown, and the four minimum repeating units P are arranged in two rows and two columns. The four minimum repeating units P are divided into two pairs, Figure 7C The two pairs of minimum repeating units are distinguished by different fillings, and each pair of minimum repeating units P includes two minimum repeating units P in different rows and columns. Among the two pairs of minimum repeating units P, only one pair of minimum repeating units P is configured to emit light in the second display area, that is, only the light-emitting elements corresponding to one pair of minimum repeating units P are located in the second display area, and the other pair of minimum repeating units P does not have a corresponding light-emitting element in the second display area. In other words, among the two minimum repeating units P adjacent to each other in the row direction or the column direction, only one corresponding light-emitting element is located in the second display area, and the other minimum repeating unit does not have a corresponding light-emitting element in the second display area, that is, the two minimum repeating units P include a first minimum repeating unit P1 and a second minimum repeating unit P2. This staggered arrangement avoids a large display blank area in the second display area, thereby improving the uniformity of the second display area.

[0168] For example, the light-emitting element corresponding to the second minimum repeating unit P2 is located in the third display area 23 or no light-emitting element is set. When the minimum repeating unit P is set in the second display area as described above, when the number of light-emitting elements corresponding to the second minimum repeating unit exceeds the number of light-emitting elements required to be set in the third display area, a part of the second minimum repeating unit P2 will not be set with a corresponding light-emitting element to form a virtual pixel; in this case, L is less than NM. This setting can improve the display uniformity of the second display area 22.

[0169] For example, refer to Figure 7C , the auxiliary data lines 260 connected to the second pixel circuit in the first minimum repeating unit P1 all receive data signals from the main data lines 250 in the first display area below (i.e., the display area adjacent to the second display area in the second direction D2), and the auxiliary data lines 260 connected to the second pixel circuit in the second minimum repeating unit P2 receive data signals from the data signal routing line (not shown) arranged above the second display area (on the side away from the first display area in the second direction D2). This arrangement is conducive to simplifying wiring.

[0170] For example, Figure 2C As shown, the second display area 22 is located at the edge of the display area, and the display substrate also includes a data signal line (not shown) located in the non-display area, and the data line signal line is arranged around the display area, and is connected to the second display area from the upper side of the display area (the side opposite to the first power supply voltage terminal and the second power supply voltage terminal). For example, the display substrate also includes a data signal terminal (not shown) located in the non-display area, and the data signal terminal is, for example, located at the lower side of the display area, one end of the data signal line is electrically connected to the data signal line to receive the data signal, and the other end is connected to the second display area to provide the data signal. For example, the setting method of the data signal line is similar to the setting method of the second power supply line 106.

[0171] For example, Figure 7C The first data line 261 and the fourth data line 264 are respectively connected to the second pixel circuits 120 belonging to the first minimum repeating unit P1 in two adjacent columns of second pixel circuits 120 in the second display area to provide data signals. Therefore, the first data line 261 and the fourth data line 264 are respectively connected to the corresponding two adjacent main data lines 250 in the first display area to receive corresponding data signals.

[0172] For example, Figure 7CAs shown, the second data line 262 and the third data line 263 are respectively connected to the second pixel circuits 120 belonging to the second minimum repeating unit P2 in two adjacent columns of second pixel circuits 120 in the second display area to provide data signals, so the second data line 262 and the third data line 263 receive data signals from a data signal line (not shown) arranged on a side of the second display area away from the first display area in the second direction D2.

[0173] like Figure 4A-4B , 7A-7B, the third conductive layer 203 further includes a connecting electrode 231, one end of the connecting electrode 231 is electrically connected to the gate T1g of the first transistor T1, that is, the second capacitor electrode Cb, through the opening 221 in the first capacitor electrode Ca and the via 346 in the insulating layer, and the other end is electrically connected to the second electrode T3d of the third transistor T3 through the via 347, thereby electrically connecting the second capacitor electrode Cb to the second electrode T3d of the third transistor T3. For example, the via 346 penetrates the second insulating layer 302 and the third insulating layer 303. For example, the via 347 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0174] For example, combined with Figure 4A-4B , Figure 7A-7B As shown, the third conductive layer 203 further includes a connecting electrode 232 (an example of a first connecting electrode of the present disclosure) located in each pixel circuit unit 100, and the second connecting electrode 232 is electrically connected to the second electrode T5d of the fifth transistor T5 through a via hole 348, and is used to electrically connect the second electrode T5d of the fifth transistor T5 to the first electrode 134 of the light-emitting element. For example, the via hole 348 passes through the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0175] For example, the first sub-pixel includes a light-emitting element 121 (an example of the first light-emitting element of the present disclosure), and the light-emitting element 121 is electrically connected to the connection electrode 134 of the pixel circuit unit of the first sub-pixel in a one-to-one correspondence.

[0176] For example, the second sub-pixel includes a light-emitting element 121 (an example of the second light-emitting element of the present disclosure), and the light-emitting element 121 is electrically connected to the connection electrodes 134 of the two pixel circuit units of the second sub-pixel.

[0177] For example, Figure 7A-7BAs shown, the third conductive layer 203 further includes a connecting electrode 233, one end of the third connecting electrode 233 is electrically connected to the reset voltage line 340 through a via 351, and the other end is electrically connected to the first electrode T6s of the sixth transistor T6 through a via 352, so that the first electrode T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 340. For example, the via 351 penetrates the third insulating layer 303. For example, the via 352 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0178] For example, Figure 7B As shown, the first electrode of the seventh transistor T7 in the previous row of sub-pixels is electrically connected to the reset voltage line 340 corresponding to the sub-pixels in this row to receive the second reset voltage Vinit2, and the first electrode of the seventh transistor T7 in the current row of sub-pixels is electrically connected to the reset voltage line 340 corresponding to the sub-pixels in the next row to receive the second reset voltage Vinit2.

[0179] For example, Figure 4A-4B , Figure 7A-7B As shown, the third conductive layer 203 also includes a connecting electrode 234 located in each pixel circuit unit, and the connecting electrode 234 is used to electrically connect the first electrode T2s of the second transistor T2 with the connecting electrode 222, that is, the connecting electrode 222 is not directly electrically connected to the first electrode T2s of the second transistor T2 through a via hole penetrating the second insulating layer 302, thereby saving a composition process for the second insulating layer 302.

[0180] like Figure 4A-4B As shown, for a second pixel circuit, the two connecting electrodes 234 in its two pixel units are respectively arranged close to the two auxiliary data lines 260 corresponding to the two pixel circuit units, one of the two auxiliary data lines 260 is electrically connected to the second pixel circuit, and is directly connected to the connecting electrode 234 close to it to form an integrated structure; the other is spaced apart from the connecting electrode 234 close to it to be insulated from the second pixel circuit.

[0181] like Figure 4A-4B and Figure 7A-7B As shown, the connection electrode 234 is electrically connected to the connection electrode 222 through the via hole 353, and is electrically connected to the first electrode T2s of the second transistor T2 through the via hole 354. For example, the via hole 353 penetrates the third insulating layer 303, and the via hole 354 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0182] For example, Figure 7BAs shown, the connection electrode 223 is electrically connected to the connection electrode 234 located in the first display area 21 and the fourth data line 264 located in the second display area 22 through the via hole 355 and the via hole 356 respectively.

[0183] Fig. 8A correspond Figure 7C The circuit structure of FIG. 1 shows the fourth conductive layer 204 , wherein the dashed line BB′ shows the boundary between the first display area 21 and the second display area 22 , and the dashed frame shows the area where the first minimum repeating unit P1 and the area where the second minimum repeating unit P2 are located.

[0184] like Fig. 8A As shown, the fourth conductive layer 204 has no pattern in the first display area 21. In other examples, the fourth conductive layer 204 may include a switching electrode located in the first display area, and the switching electrode is used to electrically connect the light emitting element to the pixel circuit below. The embodiments of the present disclosure are not limited to this.

[0185] like Fig. 8A As shown, the fourth conductive layer 204 includes a connecting electrode 241 (an example of the fourth connecting electrode of the present disclosure) located in the second display area 22. The connecting electrode 241 is arranged corresponding to each second pixel circuit 120 in the second minimum repeating unit P2. The connecting electrode 241 is used to electrically connect the connecting electrodes 232 of the two pixel circuit units 100 in the second pixel circuit 120. Figure 8B The connection electrode is electrically connected to the connection electrodes 232 of the two pixel circuit units 100 through the via holes 357 , respectively. The via holes 357 , for example, penetrate the fourth insulating layer 304 .

[0186] For example, Fig. 8A As shown, the fourth conductive layer 204 includes a plurality of connection lines 242, which are arranged one-to-one with the connection electrodes 241 and are electrically connected, for example, as an integrated structure. The connection lines 242 extend from the second display area 22 to the third display area 23, and are used to electrically connect the connection electrodes 241 to the light-emitting elements located in the third display area 23. For example, the plurality of connection lines 242 extend along the first direction D1.

[0187] In other examples, the connection electrode 241 is not electrically connected to the light emitting element, and the connection line 242 is not provided correspondingly, that is, the second pixel circuit in the second minimum repeating unit corresponding to the connection electrode forms a virtual pixel.

[0188] For example, Fig. 8A Combined with Figure 4A-4BAs shown, the fourth conductive layer 204 does not have the connecting electrode 241 in the region corresponding to the first minimum repeating unit P1. This is because the connecting electrode 232 of the pixel circuit unit in the first minimum repeating unit P1 is directly electrically connected to the first electrode of the corresponding light emitting element (refer to Figure 4B ), without setting the connecting electrode 241 and the connecting line 242 in the fourth conductive layer 204. In other examples, the fourth conductive layer 204 may be provided with a switching electrode in the area corresponding to the first minimum repeating unit P1, and the switching electrode is used to electrically connect the light-emitting element to the pixel circuit below. The embodiments of the present disclosure are not limited to this.

[0189] For example, Fig. 8A As shown, the connection line 242 corresponding to the second minimum repeating unit P2 can conduct the third display area 23 through the area corresponding to the first minimum repeating unit P1, that is, the connection line 242 can overlap with the pixel circuit unit in the first minimum repeating unit P1 in a direction perpendicular to the substrate.

[0190] For example, the material of the fourth conductive layer 204 is a transparent conductive metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc. Since the connecting line 242 extends to the third display area 23, setting the fourth conductive layer 204 as a transparent conductive material can improve the light transmittance of the third display area.

[0191] For example, the display substrate 20 may further include a fifth insulating layer and a fifth conductive layer sequentially located on the fourth conductive layer. Fig.9A and 9B A schematic diagram of the fifth conductive layer 205 is shown, wherein Fig.9A The fifth conductive layer 205 corresponds to Figure 2C The pattern in area A, Fig. 9B The pattern of the fifth conductive layer 205 in the third display area 23 is shown. The fifth conductive layer 205 includes the first electrode 134 of each light emitting element 121.

[0192] Fig.9A The dashed line BB′ shows the boundary between the first display area 21 and the second display area 22, and the dashed lines respectively show the first electrode of the light-emitting element corresponding to the first minimum repeating unit P1 in the second display area 22 and the first electrode of the light-emitting element corresponding to the minimum repeating unit P in the first display area 21. For example, each minimum repeating unit corresponds to four light-emitting elements 121.

[0193] like Fig.9AAs shown, in the second display area 22, the first electrode 134 is not set in the area of ​​the fifth conductive layer 205 corresponding to the second minimum repeating unit P2. This is because the light-emitting element corresponding to the second minimum repeating unit P2 is set in the third display area or no light-emitting element is set accordingly (corresponding to the case of a virtual pixel).

[0194] Combined with reference Figure 4A-4B The first electrode 134 is electrically connected to the connection electrodes 232 of the two pixel circuit units 100 in the corresponding second pixel circuit 120 through the via 358 , so that the two pixel circuit units 100 are connected to the same light emitting element 121 . Fig.9A The figure shows two contact hole regions 610 of the first electrode 134 corresponding to the two via holes 358, that is, the region where the first electrode 134 contacts the connection electrode 232 to form an electrical connection. Fig.9A As shown, when the main body of the first electrode 134 does not cover the two via holes 358, the first electrode 134 includes an extension portion 620 to cover the via holes 358. The via holes 358 penetrate the fourth insulating layer 304 and the fifth insulating layer 305, for example.

[0195] For ease of explanation, Fig. 9B The connecting line 242 in the fourth conductive layer 204 is also shown. Fig. 8A , a plurality of connection lines 242 extend from the second display area 22 to the third display area 23, and are electrically connected to a plurality of first electrodes 134 in the third display area 23 one by one, and each first electrode 134 is connected to a corresponding connection electrode 241 through a corresponding connection line 242, thereby being electrically connected to a corresponding second pixel circuit 120. Fig. 9B As shown, each first electrode 134 includes a connecting portion 150, and the connecting portion 150 is used to be electrically connected to the corresponding connecting line 242 through a via hole 359. The via hole 359 penetrates the fifth insulating layer 305, for example.

[0196] like Fig. 9B As shown, for example, every four first electrodes 134 constitute a pixel electrode group T, and the four first electrodes 134 are electrically connected to four second pixel circuits 120 in a second minimum repeating unit P2 in a one-to-one correspondence. For each row, the pixel electrode group T exists only on odd columns or even columns; for each column, the pixel electrode group T exists only on odd rows or even rows; that is, for each pixel electrode group T, there is no pixel electrode group directly adjacent to it in the first direction D1 (row direction) and the second direction D2 (column direction). This arrangement rule is similar to the arrangement rule of the fifth conductive layer 205 in the third display area 23, which is to improve the uniformity of display.

[0197] For example, refer to Figure 4A-4B, the display substrate 20 may further include a pixel defining layer 306 located on the side of the first electrode of the light-emitting element away from the base substrate 200. An opening is formed in the pixel defining layer 306 to expose at least part of the first electrode 134, thereby defining an opening area (i.e., a light-emitting area) 600 of each sub-pixel of the display substrate. The light-emitting layer 136 of the light-emitting element 121 is at least formed in the opening (the light-emitting layer 136 may also cover part of the surface of the pixel defining layer away from the first electrode of the light-emitting element), and the second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 121. For example, the second electrode 135 is a common electrode, which is arranged in the display substrate 20 on its entire surface. For example, the first electrode 134 is the anode of the light-emitting element, and the second electrode 135 is the cathode of the light-emitting element.

[0198] Fig.9A and Fig. 9B The position of the opening area 600 is shown on the first electrode of the light emitting element 121, and the position of the contact hole area 610 or the via hole 359 of the first electrode relative to each first electrode 134 is shown. Fig.9A and 9B As shown, the orthographic projections of the contact hole region 610 or the via hole 358 and the opening region 600 on the base substrate 200 do not overlap, that is, the orthographic projections of the contact hole region 610 or the via hole 358 on the base substrate 200 are located outside the opening region 600. This arrangement prevents the via hole from affecting the flatness of the light-emitting layer in the opening region and thus affecting the light-emitting quality.

[0199] For example, the second display area 22 includes X second pixel circuits 120 and Y light-emitting elements 121 (an example of the second light-emitting element disclosed in the present invention), and the Y light-emitting elements are electrically connected to Y second pixel circuits among N second pixel circuits in a one-to-one correspondence, and X and Y are both positive integers, and Y is less than X.

[0200] For example, the third display area 23 includes Z light-emitting elements 121 (an example of the third light-emitting element disclosed in the present invention), and the first electrodes of the Z light-emitting elements are electrically connected one-to-one with the connecting electrodes 241 of the Z second pixel circuits 120 in the X second sub-pixel circuits through connecting lines 242, where Z is a positive integer and is less than or equal to XY.

[0201] like Fig.9A As shown, for the four light-emitting elements driven by each minimum repeating unit P, the opening area 600 of the green light-emitting element (G) is the smallest, and the opening area of ​​the blue light-emitting element (B) is the largest. This is because the human eye is more sensitive to green, and the life of the blue light-emitting material is the shortest, so a larger light-emitting area is required to improve the stability of the light emission of the display substrate.

[0202] For example, Fig.9AAs shown, the area of ​​the opening area 600 of at least one light-emitting element in the second display area 23 is larger than the area of ​​the opening area of ​​the light-emitting element emitting light of the same color in the first display area 22. This is because the pixel density in the second display area is low, and the density of the light-emitting elements (the number of light-emitting elements per unit area) can be further improved by increasing the light-emitting area of ​​a single light-emitting element, that is, the opening area, so as to further improve the uniformity of the entire display substrate.

[0203] For example, the base substrate 200 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

[0204] For example, the material of the semiconductor layer 107 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0205] For example, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or transparent conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0206] For example, the light emitting element 121 is a top emission structure, the first electrode 134 is reflective and the second electrode 135 is transmissive or semi-transmissive. For example, the first electrode 134 is a material with a high work function to act as an anode, such as an ITO / Ag / ITO stacked structure; the second electrode 135 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0207] For example, the first insulating layer 301, the second insulating layer 302, the third insulating layer 303, the fourth insulating layer 304 and the fifth insulating layer 305 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride and other silicon oxides, silicon nitrides or silicon nitride oxides, or aluminum oxide, titanium nitride and other metal nitride oxide insulating materials. For example, the fourth insulating layer 304 and the fifth insulating layer 305 can also be organic insulating materials like the pixel defining layer 306, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials. For example, the fourth insulating layer 304 and the fifth insulating layer are planarization layers. The embodiments of the present disclosure are not limited to this.

[0208] At least one embodiment of the present disclosure further provides a display device, which includes any one of the above-mentioned display substrates 20 and a sensor. Fig. 10A shows a schematic structural diagram of a display device 40 provided in some embodiments of the present disclosure, Fig. 10B for Fig. 10A The shown device is a cross-sectional view taken along CC'.

[0209] like Fig. 10A As shown, the sensor 401 is disposed correspondingly to the third display area 23 of the display substrate 20 and is disposed on a side of the display substrate opposite to the display side, for example, on a side of the base substrate 200 away from the light-emitting element. The sensor 401 is, for example, a photoelectric sensor, configured to receive light from the first side of the display substrate and convert the light into an electrical signal for forming an image. For example, the light reaches the sensor from the display side through the third display area 23, for example, the light is visible light or infrared light.

[0210] For example, the display device 40 also includes an encapsulation layer 207 and a cover plate 208 disposed on the display substrate 20, and the encapsulation 207 is configured to seal the light-emitting element in the display substrate 20 to prevent external moisture and oxygen from penetrating into the light-emitting element and the driving circuit and causing damage to the device. For example, the encapsulation layer 207 includes an organic film or a structure including an organic film and an inorganic film alternately stacked. For example, a water-absorbing layer (not shown) can also be disposed between the encapsulation layer 207 and the display substrate 20, configured to absorb residual water vapor or sol of the light-emitting element in the early production process. The cover plate 208 is, for example, a glass cover plate. For example, the cover plate 208 and the encapsulation layer 207 can be an integrated structure.

[0211] For example, the sensor 401 may be attached to the back side (the side opposite to the display surface) of the display substrate 20. Fig. 10B As shown, the imaging element 401 is attached to a side of the substrate 200 away from the second electrode 136 of the light emitting element. The sensor 401 can be implemented as a camera, for example.

[0212] The display device can be, for example, a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a display, a laptop computer, a navigator, or any other product or component with a display function.

[0213] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate having a first side for display and a second side opposite to the first side, in, The display substrate comprises a base substrate and a first display area and a second display area, wherein the pixel density in the first display area is higher than the pixel density in the second display area; The second display area includes a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels are arranged in a plurality of rows and columns along a first direction and a second direction, and the first direction intersects the second direction; The display substrate further comprises a data line extending along the second direction, wherein the data line is connected to one column of sub-pixels in the plurality of columns of sub-pixels to provide a data signal; Each sub-pixel in the row of sub-pixels comprises a storage capacitor, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is configured to receive a power supply voltage; The second display area further includes a plurality of second power lines extending along the second direction and a plurality of fourth power lines extending along the first direction; each fourth power line is electrically connected to at least one of the plurality of second power lines through at least one via hole; the fourth power lines are spaced apart from the third power lines located in the first display area; The plurality of sub-pixels include a plurality of pixel circuit units, and the plurality of pixel circuit units are arranged in a plurality of rows and columns along the first direction and the second direction; the plurality of pixel circuit units include two pixel circuit units adjacent to each other in the first direction; Each pixel circuit unit includes a driving subcircuit and a data writing subcircuit, wherein a first end of the driving subcircuit is configured to receive the power supply voltage, a second end of the driving subcircuit is configured to be electrically connected to the light emitting element through a first connecting electrode, and the driving subcircuit is configured to form a driving current flowing through the light emitting element in response to the power supply voltage; The first connection electrodes of two adjacent pixel circuit units are electrically connected to each other so as to be connected to the same light emitting element, and jointly drive the same light emitting element to emit light; The data writing subcircuit comprises a control end, a first end and a second end, and the second end of the data writing subcircuit is connected to the first end of the driving subcircuit; The first ends of the data writing subcircuits of the two pixel circuit units are electrically connected to each other through a second connecting electrode extending along the first direction, so as to share the data line; the second connecting electrode is arranged corresponding to one of the sub-pixels in the column, the second connecting electrode is connected to the data line, and is configured to access the data signal; in a direction perpendicular to the substrate, the second power line overlaps with the second connecting electrode, and the fourth power line has an overlapping area with the data line; The orthographic projection of the overlapping area on the base substrate does not overlap with the orthographic projection of the second capacitor electrode of the storage capacitor of any sub-pixel in the row of sub-pixels on the base substrate.

2. The display substrate according to claim 1, wherein: The second power line located in the second display area is configured to be connected to the power supply voltage, and at least one end of the second power line is floating.

3. The display substrate according to claim 1, wherein: The first capacitor electrode is a part of the fourth power line.

4. A display device, comprising the display substrate according to any one of claims 1 to 3.

5. The display device according to claim 4, further comprising a sensor, wherein: The sensor is disposed on the second side of the display substrate and is configured to receive light from the first side of the display substrate.

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