A control circuit and control method for liquid crystal pixels

Abstract

The present invention discloses a control circuit and a control method for liquid crystal pixels. The control circuit for liquid crystal pixels includes a preset charging module, a second-order programming module, and a first-order programming module connected in sequence. The present invention first charges the preset charging module; then, the preset charging module is programmed through the second-order programming module to make its voltage reach the sustain voltage required for the liquid crystal screen to display an image; finally, when the liquid crystal screen displays the current image at the sustain voltage, the first-order programming module stores electric energy for the display of the next frame of image; that is, while the current image is being displayed, preparations are made in advance for the electric energy required for the display of the next frame of image. By this way of carrying out display and advance storage simultaneously, time is saved, and the color chaos and picture tearing phenomena caused by the time delay from the first row to the last row in the gate scan driving mode of the liquid crystal display are effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of liquid crystal display screens, and particularly relates to a control circuit and a control method for liquid crystal pixels. Background Art

[0002] The display principle of an ordinary liquid crystal display screen is as follows: after each row of thin film transistors in the display device of the liquid crystal display screen is turned on by the gate circuit, the source circuit is responsible for charging. During this period, the backlight source on the back of the liquid crystal display screen is responsible for providing light illumination. Each pixel of the liquid crystal is responsible for whether light passes through and the amount of light passing through, so that a color image is formed with the cooperation of a color filter; its characteristic is that there is a color filter and the backlight source is always on.

[0003] With the progress of technology, the principle of sequential field display liquid crystal has been proposed. Its basic logic is to use a liquid crystal display screen with only grayscale control in monochrome, cooperate with backlight sources of different colors, and achieve color display by mixing colors in time. Generally speaking, three light sources of RGB are turned on in a non-interval sequential manner, and the image is decomposed into three sub-images of red, green, and blue. When outputting a red image, the red light is turned on, and the liquid crystal pixels control the grayscale to allow a certain proportion of red light to pass through. When green is needed, the green light is turned on, and the liquid crystal pixels control the grayscale to allow a certain proportion of green light to pass through. The same control is applied to blue. When the actions of the liquid crystal pixels and the backlight source can both achieve a relatively high switching speed, such as the liquid crystal pixels achieving a refresh rate of 180 Hz, and the three backlight sources of red, green, and blue also achieving a refresh rate of 180 Hz for cooperation, it is possible to control one color for each frame of the picture, complete the cooperation of all red, green, and blue lights for every three frames of the picture, and every three frames of the picture form a frame of color image. For a refresh rate of 180 Hz, the refresh of the light source and the liquid crystal pixels with this timing cooperation can achieve a color picture of 60 Hz.

[0004] However, in reality, since there is a certain action time for the opening and closing of the liquid crystal, the display driving of the liquid crystal scans and turns on the charging circuit of the liquid crystal pixels row by row, and then another circuit conducts the charging. After the charging is completed, the liquid crystal twists to achieve specific executions such as light passing through. Since the resolution of the displayed image is getting higher and higher, the time taken for scanning from the first row to the last row is getting longer and longer, and the requirements for the driving circuit are getting higher and higher; taking 1080P as an example, 1080 rows of scanning need to be completed within each sub-frame time, so the time for each row is very short. After all the scanning is completed, the backlight source is turned on. It can be found from this that the time left for driving and turning on the backlight source is very little within each sub-frame range.

[0005] For example, at 180 Hz, each frame takes 5.6 milliseconds. If it takes 5.4 milliseconds from the completion of charging the first row to the completion of charging the last row, it means that the human eye has been viewing the image of the first row for 5.4 milliseconds before the last row of this frame is displayed. This will result in image tearing and misalignment.

[0006] If the refresh rate is higher, this problem becomes more serious. For products that require field-sequential display, the backlight display colors of each sub-field are different. If the first row is displayed in a certain color, such as red, then it takes 5.4 milliseconds to charge and refresh to the last row, which is row 1080. Then, 0.2 milliseconds later, the first row has already started to display the color of the next field, such as blue, while the last row is still red. For the backlight, it is necessary to distinguish and display in a time-division and area-division manner, and this problem will lead to huge design difficulties and cost increases. Summary of the Invention

[0007] To solve the above problems, the present invention provides a control circuit for liquid crystal pixels, which can achieve the synchronous operation of liquid crystal pixels on the premise that the existing liquid crystal pixels scan and input image display content through the cooperation of the gate and the source, thereby effectively improving the color chaos and image tearing phenomenon caused by the time delay from the first row to the last row.

[0008] Another object of the present invention is to provide a control method for liquid crystal pixels, which is a method implemented based on the control circuit for liquid crystal pixels.

[0009] The technical solution adopted by the present invention is as follows:

[0010] A control circuit for liquid crystal pixels, which includes a preset charging module, a second-order programming module, and a first-order programming module connected in sequence;

[0011] The preset charging module is used to charge the liquid crystal pixel capacitor through a high level to preset the liquid crystal pixel to a high level state;

[0012] The second-order programming module discharges the preset charging module according to the programming data of the first-order programming module to make its charge reach the holding voltage required for the liquid crystal pixel to display an image;

[0013] The first-order programming module receives and stores the charge delivered from an external control unit for the display of the next frame of image.

[0014] Preferably, the preset charging module includes a liquid crystal pixel capacitor Cls, and the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen.

[0015] Preferably, the preset charging module further includes a second transistor T2, the gate of the second transistor T2 is coupled to an external level Vpre, the drain of the second transistor T2 is coupled to an external level VH, and the source of the second transistor T2 is connected through an internal node Vpx and a liquid crystal pixel capacitor Cls.

[0016] Preferably, when the preset charging module is operating, the internal node Vpx is pulled high to a high level by the external level VH; after secondary programming by the second-order programming module, the internal node Vpx is the holding voltage required for the liquid crystal pixel to display an image.

[0017] Preferably, the second-order programming module includes a storage capacitor Cs and a third transistor T3, the drain of the third transistor T3 is coupled to the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2, the source of the third transistor T3 is coupled to a second synchronization signal Vst2, the gate of the third transistor T3 is connected through an internal node to one end of the storage capacitor Cs, and the other end of the storage capacitor Cs is connected to a first synchronization signal Vst1.

[0018] Preferably, the second-order programming module includes a double-gate transistor T4, the drain of the double-gate transistor T4 is connected in parallel with the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2 through an internal node Vpx, the source of the double-gate transistor T4 is coupled to the second synchronization signal Vst2, one gate of the double-gate transistor T4 is connected to the first synchronization signal Vst1, and the other gate is coupled to the first-order programming module through an internal node Q.

[0019] Preferably, the first-order programming module includes a first transistor T1, the gate of the first transistor T1 is connected to a gate driver for driving the entire liquid crystal screen, the source of the first transistor T1 is connected to a source driver for driving the entire liquid crystal screen, and the drain of the first transistor T1 is coupled to the storage capacitor Cs and the third transistor T3 through an internal node Q.

[0020] A control method for liquid crystal pixels, which applies the above-mentioned control circuit for liquid crystal pixels, and is specifically implemented according to the following steps:

[0021] S1, charge the liquid crystal pixel capacitor with a high level to preset the liquid crystal pixel to a high level state;

[0022] S2, perform programming through the second-order programming module to discharge the preset charging module so that its charge reaches the holding voltage required for the liquid crystal pixel to display an image;

[0023] S3. Maintain the charge voltage of the liquid crystal pixels, and at the same time receive and save the charges delivered from the external control unit through the first-order programming module for the display of the next frame of image.

[0024] Preferably, in the S1, all the liquid crystal pixels constituting the liquid crystal screen are preset to a high level at one time and synchronously through a high level.

[0025] Preferably, in the S2, the charges are programmed through second-order programming to discharge the preset charging module so that its charge reaches the holding voltage required for the liquid crystal pixels to display an image. Specifically:

[0026] Through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2, the third transistor T3 is turned on to discharge the liquid crystal pixel capacitor Cls. The conduction ability and conduction duration of the third transistor T3 are jointly determined by the charges stored in the storage capacitor Cs, the first synchronization signal Vst1, and the second synchronization signal Vst2 in the S3. The electric quantity of the liquid crystal pixel capacitor Cls is released from the high level state to the required electric quantity, and then the voltage of the liquid crystal pixel capacitor Cls is programmed to the holding voltage required for the liquid crystal pixels to display an image.

[0027] Preferably, in the S2, the second-order programming of all the pixels constituting the liquid crystal screen is completed synchronously at one time.

[0028] Preferably, in the S3, the charge voltage of the liquid crystal pixels is maintained, and at the same time, the charges delivered from the external control unit are received and saved through the first-order programming module for the display of the next frame of image. Specifically:

[0029] S31. Buffer stage: In the buffer stage, the charging time of the first-order programming module starting from the first row of the liquid crystal screen is postponed, and thus the holding time of the storage capacitor Cs in the first-order programming module is adjusted;

[0030] S32. First-order programming stage: The entire liquid crystal screen is charged row by row from the first row to the last row. The gate driver and the source driver of the liquid crystal screen cooperate with each other to perform first-order programming charging on each liquid crystal pixel from the first row to the last row;

[0031] Among them, the charging data is related to the displayed image and is controlled by the source driver.

[0032] Preferably, the time of the buffer stage depends on the manufacturing process of the liquid crystal screen, and its maximum time is not greater than the time used for one frame of picture.

[0033] Preferably, the first-order programming time of all liquid crystal pixels is also completed in this frame, or can be extended to the S1 stage of the next frame, but cannot be extended to the S2 stage.

[0034] Preferably, the method further includes: the backlight of the liquid crystal screen is turned on and off in sequence, and the first-order programming process carried out in the S3 stage in sequence forms a pipeline-type driving logic.

[0035] Preferably, when the first synchronization signal Vst1 and the second synchronization signal Vst2 are square waves, the sustain voltage V 维持 has a range of 0 ≤ V 维持 ≤ V 全亮 , where V 全亮 is the voltage when the liquid crystal pixel is preset to the highest level.

[0036] Preferably, when the first synchronization signal Vst1 and the second synchronization signal Vst2 are ramp waves, the sustain voltage is a high level or zero level.

[0037] Preferably, when the sustain voltage is at a high level, the duration of maintaining the high level depends on the charge in the S3 and the parameters of the ramp wave.

[0038] Compared with the prior art, when the present invention is used, first, the liquid crystal pixel capacitor is charged through a high level to preset the liquid crystal pixel to a high level state; then, the charge is programmed through a second-order programming module to discharge the preset charging module so that its charge reaches the sustain voltage required for the liquid crystal pixel to display an image; finally, the charge voltage of the liquid crystal pixel is maintained, and at the same time, the first-order programming module receives and stores the charge delivered from the external control unit for the display of the next frame of image; by presetting the liquid crystal pixel unit to a high level first and then discharging it to the level required for displaying the image, it is faster than charging from a low level to a high level; secondly, by presetting to a high level in each frame of the picture, the ghosting phenomenon that occurs in the liquid crystal capacitor under a specific picture is eliminated; at the same time, while the current image is being displayed, the power required for the display of the next frame of image is programmed and charged. Since this programming and charging needs to be carried out row by row in sequence and takes a long time, by this way of simultaneously storing the power data of the current picture display and the next frame of picture, the driving capabilities requirements for the external gate driver and source driver are greatly reduced, and the backlight illumination time of the picture display is also greatly extended, effectively improving the problem that in the gate scan driving mode of the liquid crystal display, the time from the first row to the last row is very long, resulting in insufficient brightness due to the compressed backlight illumination time, or color confusion and picture tearing phenomena due to too long backlight time. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1It is the circuit diagram of a control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0040] Figure 2 It is the circuit diagram when charging the liquid crystal pixel capacitor through an external timing control circuit in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0041] Figure 3 It is the circuit diagram when the preset charging module is in the charging stage in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0042] Figure 4 It is the circuit diagram when the second-order programming module is in the programming stage in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0043] Figure 5 It is the circuit diagram when the second-order programming module has a double-gate structure in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0044] Figure 6 It is the design schematic diagram inside the liquid crystal pixel when the second-order programming module adopts a double-gate design logic in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0045] Figure 7 It is the double-threshold voltage mode diagram of the double-gate transistor in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0046] Figure 8 It is the circuit diagram when the first-order programming module is in the programming stage in the control circuit for liquid crystal pixels provided in Embodiment 1 of the present invention;

[0047] Figure 9 It is the flowchart of a control method for liquid crystal pixels provided in Embodiment 2 of the present invention;

[0048] Figure 10 It is the schematic diagram of the pipelined field-sequential emission and programming mode of the control method for liquid crystal pixels provided in Embodiment 2 of the present invention;

[0049] Figure 11 It is the schematic diagram of the preferred pipelined field-sequential emission and programming mode of the control method for liquid crystal pixels provided in Embodiment 2 of the present invention;

[0050] Figure 12 It is the liquid crystal timing display diagram of the control method for liquid crystal pixels provided in Embodiment 2 of the present invention.

[0051] Among them: 1. Preset charging module, 2. Second-order programming module, 3. First-order programming module. Detailed Implementation Manner

[0052] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] In the description of the present invention, it should be clear that the terms "vertical", "lateral", "longitudinal", "front", "rear", "left", "right", "upper", "lower", "horizontal", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and does not mean that the indicated device or element must have a specific orientation or position. Therefore, it should not be construed as a limitation of the present invention.

[0054] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] In the description of the present invention, it should also be noted that the bottom gate control and the top gate control in the text are relative, and the source and the drain are also relative; those skilled in the art can adjust according to conventional means.

[0056] Embodiment 1

[0057] Embodiment 1 of the present invention provides a circuit for a liquid crystal pixel, as Figure 1 shown, which includes a preset charging module 1, a second-order programming module 2, and a first-order programming module 3 connected in sequence;

[0058] The preset charging module 1 is used to charge the liquid crystal pixel capacitor through a high level and preset the liquid crystal pixel to a high level state;

[0059] The second-order programming module 2 discharges the preset charging module 1 according to the programming data of the first-order programming module 3 so that its charge reaches the holding voltage required for the liquid crystal pixel to display an image;

[0060] The first-order programming module 3 receives and stores the charge delivered from an external control unit for the display of the next frame of image;

[0061] In this way, with the above structure, first, the liquid crystal pixel capacitor of the preset charging module 1 is charged through a high level, and the liquid crystal pixel is preset to a high level state; then, the charge is programmed by the second-order programming module 2 to discharge the preset charging module so that its charge reaches the sustain voltage required for the liquid crystal pixel to display an image; finally, during the process of the liquid crystal pixel displaying an image, the first-order programming module 3 receives and stores the charge delivered from the external control unit for the display of the next frame of image; that is, while the current image is being displayed, the power required for the display of the next frame of image is prepared in advance. By this way of performing display and advance storage simultaneously, time is saved, and the color chaos and picture tearing phenomena caused by the time delay from the first row to the last row in the gate scan driving mode of the liquid crystal display are effectively improved.

[0062] In the specific embodiment:

[0063] As Figure 2 shown, the preset charging module 1 includes a liquid crystal pixel capacitor Cls, and the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen;

[0064] In this way, the liquid crystal pixel capacitor Cls can be directly charged through the external timing control circuit VH.

[0065] As Figure 1 shown, the preset charging module 1 further includes a second transistor T2. The gate of the second transistor T2 is coupled to the external level Vpre, the drain of the second transistor T2 is coupled to the external level VH, and the source of the second transistor T2 is connected to the liquid crystal pixel capacitor Cls through the internal node Vpx;

[0066] In this way, the external level Vpre is set to a high-level voltage, the first synchronization signal Vst1 is set to a low-level voltage, the second synchronization signal Vst2 is a high-level voltage, and the gate data signal Vg[n] of the first transistor T1 is a low-level voltage; thus, the second transistor T2 is turned on, and the first transistor T1 and the third transistor T3 are both in the off state. As Figure 3 shown, the liquid crystal pixel capacitors Cls in all the pixel arrays are synchronously pulled up to the high-level voltage VH, realizing the charging of the preset charging module 1.

[0067] Moreover, when the preset charging module 1 is working, the internal node Vpx is at a high level; after being secondarily programmed by the second-order programming module 2, the internal node Vpx is the sustain voltage required for the liquid crystal pixel to display an image.

[0068] In a specific embodiment, the second-order programming module 2 has two structures:

[0069] For the first type, the second-order programming module 2 includes a storage capacitor Cs and a third transistor T3. The drain of the third transistor T3 is coupled to the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2. The source of the third transistor T3 is coupled to the second synchronization signal Vst2. The gate of the third transistor T3 is connected to one end of the storage capacitor Cs through an internal node. The other end of the storage capacitor Cs is connected to the first synchronization signal Vst1;

[0070] In this way, set the first synchronization signal Vst1 to a high-level voltage, the second synchronization signal Vst2 to a low-level voltage, Vpre to a low-level voltage, and the gate data signal Vg[n] to a low-level voltage. Then the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on. As Figure 4 shown, the conducting third transistor T3 discharges the liquid crystal pixel capacitor Cls.

[0071] For the second type, the second-order programming module 2 includes a double-gate transistor T4. As Figure 5 shown, the drain of the double-gate transistor T4 is connected in parallel to the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2 through an internal node Vpx. The source of the double-gate transistor T4 is coupled to the second synchronization signal Vst2. One gate of the double-gate transistor T4 is connected to the first synchronization signal Vst1, and the other gate is coupled to the first-order programming module 3 through an internal node Q;

[0072] The second-order programming module 2 with this structure adopts double-gate logic and reduces the method of one capacitor Cs, which has an optimized design of saving circuit area and increasing the aperture ratio, and is the preferred design of the present invention;

[0073] Moreover, after setting the double-gate transistor, the light-shielding area is significantly reduced by one capacitor. This is a significant change for the inside of the liquid crystal pixel.

[0074] Adopting the design logic of the double-gate transistor T4, the schematic diagram of the internal design of the liquid crystal pixel is as Figure 6 shown. For convenience, an IGZO liquid crystal screen is used as an example in this embodiment;

[0075] Among them, Figure 6 the meanings of the parameters in are:

[0076] ESL is the SiOx dielectric protection layer; TG is the top gate, the transistor top gate signal line; BG is the bottom gate, the transistor bottom gate signal line; IGZO is the IGZO layer of the liquid crystal screen; GLASS is the liquid crystal screen glass substrate layer; S is the transistor source; D is the transistor drain;

[0077] Taking the common structure in IGZO TFT pixel design, the back-channel protection type (ESL type) as an example, under this structure, the IGZO active layer is controlled by the bottom gate insulating layer to form the first gate control, that is, bottom gate control. And because the IGZO active layer is protected by the SiOx dielectric layer on the back (i.e., the ESL layer), a top gate control structure can be designed to form a second gate control structure with the IGZO active layer, that is, top gate control. Among them, for ESL type devices, the top gate control structure can be composed of source-drain metal layer, ESL layer, and IGZO layer.

[0078] When the voltage of the top gate control is different, a dual-threshold voltage mode can be formed, and a liquid crystal LCD display pixel circuit under a two-step programming charging logic can be formed.

[0079] Furthermore, the top gate control structure can also be composed of a top ITO metal layer, ESL layer, and IGZO layer;

[0080] During the first-order programming charging and second-order programming charging processes, the conversion from the first-order programming state completed in the previous timing to the second-order programming state in this timing depends on the change in the top gate control voltage in the dual-gate transistor T4, that is, the voltage level conversion of the connected first synchronization signal Vst1.

[0081] In the first-order programming charging state, the first synchronization signal Vst1 is in a low voltage level state. Therefore, the threshold voltage of the dual-gate transistor T4 is relatively large, and the third transistor T3 is not conducting, maintaining the display data of the previous frame.

[0082] When entering the second-order programming charging state, the first synchronization signal Vst1 is high, so the threshold voltage of the dual-gate transistor T4 is relatively small, and the third transistor T3 enters the conducting state to perform the second-order programming mode, and the upper-end voltage Vpx of the liquid crystal pixel capacitor Cls is updated to the final required voltage state.

[0083] Furthermore, due to the device conduction performance of the dual-gate transistor T4 being affected by the top gate control, it can be switched between multiple working modes. When the top gate control voltage is low, it operates in a high threshold voltage mode; when the top gate control voltage is high, it operates in a low threshold voltage mode, as Figure 7 shown;

[0084] Among them, Figure 7 the meanings of the parameters in

[0085] V TG is the voltage of the top gate; V GH is the externally set high voltage; V GL is the externally set low voltage; High V TH is the threshold voltage under high voltage; Low V TH is the threshold voltage under low voltage; Log IDS is the logarithm of the drain and source currents; V BG is the voltage of the bottom gate-source;

[0086] In addition, when one of the gates is a top gate control / bottom gate control, the other gate is a bottom gate control / top gate control.

[0087] Under the specific working logic, during the conduction stage of the double-gate transistor T4, from the Vpx terminal to the Vst2 terminal, it is an equivalent circuit of a linear resistor. Therefore, the conduction ability and conduction time of the entire circuit are jointly determined by the charge quantity stored in the double-gate transistor T4T4, as well as Vst1 and Vst2. Thus, the charge of the pixel capacitor Cls can be discharged to an appropriate voltage to achieve the goal of the final display.

[0088] In a specific embodiment:

[0089] The first-order programming module 3 includes a first transistor T1. The gate of the first transistor T1 is connected to the gate driver gate driver for driving the entire liquid crystal screen. The source of the first transistor T1 is connected to the source driver source driver for driving the entire liquid crystal screen. The drain of the first transistor T1 is coupled to the storage capacitor Cs and the third transistor T3 through an internal node Q;

[0090] In this way, set the first synchronization signal Vst1 to a low-level voltage, the second synchronization signal Vst2 to a high-level voltage, and Vpre to a low-level voltage. Then, both the second transistor T2 and the third transistor T3 are in the off state, as Figure 8 shown;

[0091] Furthermore, the source data signal Vdata is in a high-level voltage state, and the gate data signal Vg[n] is in a high-level voltage state. At this time, it enters the first-order programming state; that is, according to the basic principle of liquid crystals, several rows of the first transistors T1 are sequentially scanned and opened by the gate circuit Vg[n]. The storage capacitor Cs is in a state of receiving external charges, and the source data circuit of the liquid crystal conducts charging work, that is, programming work. At this time, the storage capacitor Cs will obtain an appropriate amount of charge from Vdata for the display in the next cycle.

[0092] In addition, it should be noted that the first synchronization signal Vst1, the second synchronization signal Vst2, Vpre, and VH in this embodiment all act on all pixels of the entire liquid crystal screen. That is, for any pixel, the size and nature of any one of these four levels received are the same for all pixels.

[0093] The beneficial effects of this embodiment are as follows:

[0094] All liquid crystal pixels of the liquid crystal screen can be displayed normally synchronously; secondly, through the design of dual-gate transistors, the internal design of the liquid crystal pixels is significantly changed, the opaque area occupied by the capacitor is saved, the aperture ratio is improved, and it is beneficial to improve the brightness; and, in the normal display stage, the present embodiment cooperates with the gate circuit and the source circuit to program the data used for display, so as to retain the advantages of the traditional liquid crystal screen gate scanning drive mode, because the scanning drive mode takes a long time from the first line to the last line, and the driving capability requirement is relatively low; in addition, by setting a certain time of black field in each frame, the alternation with the light field of the backlight is improved, and the image quality is improved; through the specific buffer design logic, for liquid crystal screens with different manufacturing processes, due to different TFT processes, their leakage current capabilities are different, and the buffer design logic can better reduce the leakage current that causes the storage capacitor voltage to drop, resulting in inaccurate programming data and inaccurate display.

[0095] Example 2

[0096] Embodiment 2 of the present invention provides a control method for a liquid crystal pixel, which uses the control circuit for a liquid crystal pixel described in embodiment 1, such as Figure 9 and Figure 12 As shown, the specific steps are as follows:

[0097] S1, charging the liquid crystal pixel capacitor through a high level, presetting the liquid crystal pixel to a high level state; specifically:

[0098] All liquid crystal pixels constituting the liquid crystal screen are preset to a high level at one time and synchronously through a high level;

[0099] S2, programming through the second-order programming module to discharge the preset charging module so that its charge reaches the maintenance voltage required for the liquid crystal pixel to display the image; specifically:

[0100] Through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2, the third transistor T3 is turned on to discharge the liquid crystal pixel capacitor Cls. The turn-on capability and the turn-on duration of the third transistor T3 are jointly determined by the charge stored in the storage capacitor Cs in S3, the first synchronization signal Vst1 and the second synchronization signal Vst2. The charge of the liquid crystal pixel capacitor Cls is released from a high level state to a required charge, and then the voltage of the liquid crystal pixel capacitor Cls is programmed to the maintenance voltage required for the liquid crystal pixel to display an image;

[0101] It should be noted that the second-order programming of all pixels that make up the LCD screen is done synchronously and at once;

[0102] S3, maintain the charge voltage of the liquid crystal pixels, and at the same time receive and save the charge delivered from the external control unit through the first-order programming module for the display of the next frame of image; specifically:

[0103] S31, buffering stage: In the buffering stage, by delaying the time when the first-order programming module starts to work and charge from the first row of the liquid crystal screen, the holding time of the storage capacitor Cs in the first-order programming module is adjusted.

[0104] S32, first-order programming stage: For the entire liquid crystal screen from the first row to the last row, charge operations are performed in sequence. The gate driver and the source driver of the liquid crystal screen cooperate with each other to perform first-order programming charging on each liquid crystal pixel from the first row to the last row.

[0105] Among them, the charging data is related to the displayed image and is controlled by the source driver.

[0106] More specifically:

[0107] In the said S1, the external level Vpre is set to a high-level voltage, the first synchronization signal Vst1 is set to a low-level voltage, the second synchronization signal Vst2 is a high-level voltage, and the gate data signal Vg[n] of the first transistor T1 is a low-level voltage.

[0108] According to the above settings, as Figure 3 shown, then the second transistor T2 is turned on, and the first transistor T1 and the third transistor T3 are both in the off state. All the liquid crystal pixel capacitors Cls in the pixel array are synchronously pulled up to the high-level voltage VH to charge the preset charging module.

[0109] And in this step, VH and Vpre of the liquid crystal pixels are outside the liquid crystal screen and are each controlled by the same set of circuits. For all the liquid crystal pixels, their preset charging voltage VH is synchronously pulled up, and their liquid crystal pixel capacitors Cls are also synchronously charged.

[0110] More specifically:

[0111] In the said S2, the first synchronization signal Vst1 is set to a high-level voltage, the second synchronization signal Vst2 is set to a low-level voltage, Vpre is a low-level voltage, and the gate data signal Vg[n] is a low-level voltage.

[0112] According to the above settings, then the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on. The conducting third transistor T3 discharges the liquid crystal pixel capacitor Cls.

[0113] The main function of this step is to release a part of the charge in the liquid crystal pixel capacitor Cls pre-charged in the S1 stage to achieve the voltage for finally displaying the correct image. By turning on the third transistor T3, the capacitance data of the storage capacitor Cs, as well as the high and low level states of Vst1 and Vst2, affect the conduction ability and conduction time of T3, so as to realize appropriate charge release for the liquid crystal pixel capacitor Cls, realize second-order programming, and thus adjust the voltage of the liquid crystal pixel capacitor Cls to the voltage charge state required for final display. When the backlight drive is lit and enters the optical field timing link, the correct image can be displayed.

[0114] Among them, to what voltage the liquid crystal pixel capacitor Cls is discharged depends on the conduction ability of the third transistor T3, and the conduction ability of the third transistor T3 depends on the amount of charge stored on the storage capacitor Cs coupled to the gate of the third transistor T3 in the previous cycle. Specifically:

[0115] The more charge stored on the storage capacitor Cs coupled to the gate of the third transistor T3, the stronger the conduction ability of the third transistor T3, and the lower the voltage to which the liquid crystal pixel capacitor Cls is pulled down; conversely, the higher the voltage on the liquid crystal pixel capacitor Cls.

[0116] In the S2, the voltage of the liquid crystal pixel capacitor Cls is programmed to the sustain voltage required for the liquid crystal screen to display an image. Among them, to what voltage the liquid crystal pixel capacitor Cls is discharged also depends on the duration of the S2. Specifically:

[0117] When the duration of the S2 is longer, the voltage to which the liquid crystal pixel capacitor Cls is pulled down is lower; conversely, the voltage on the liquid crystal pixel capacitor Cls is higher.

[0118] More specifically:

[0119] In the S31: The time of the buffer stage depends on the manufacturing process of the liquid crystal screen, and its maximum time is not greater than the time used for one frame of the picture.

[0120] In the S3, the display control system drives the gate data line of each row to control the first transistor T1 to turn on by setting Vg[n] to a high level through the gate driver GATE DRIVER; the source driver SOURCE DRIVER transports the voltage signal Vdata used for displaying the image to the storage capacitor Cs through the first transistor T1.

[0121] In S3, the first-order programming module receives and stores the charge delivered from the external control unit for the display of the next frame of image. Since there are many rows of liquid crystal pixel units in the liquid crystal display screen, programming starts from the first row until the end, which takes a relatively long time. In this embodiment, the first-order programming process can continue to the preset charging link of the next frame of image, i.e., the S1 process.

[0122] More specifically:

[0123] In the buffering stage of S31, the backlight has been turned on. At this stage, the liquid crystal pixel capacitor Cls maintains the holding voltage obtained after discharging during the previous discharging stage. After the backlight is driven, the liquid crystal display can display the correct image.

[0124] The buffering stage is used for the buffering period and preparation period during the driving process. Considering the actual situation when the liquid crystal gate circuit starts, a certain preparation period needs to be set, which ranges from 10 microseconds to 1 millisecond and is adjusted and fixed according to the liquid crystal performance and the performance of the gate driver GATE DRIVER of the liquid crystal display screen. Different applications have different settings.

[0125] More specifically:

[0126] In S3, the first synchronization signal Vst1 is set to a low-level voltage, the second synchronization signal Vst2 is set to a high-level voltage, and Vpre is set to a low-level voltage.

[0127] According to the above settings, the second transistor T2 and the third transistor T3 are both in the off state.

[0128] Furthermore, the source data signal Vdata is in a high-level voltage state, and the gate data signal Vg[n] is in a high-level voltage state. At this time, it enters the first-order programming state; that is, according to the basic principle of liquid crystal, several rows of liquid crystal are sequentially scanned and opened by the gate circuit Vg[n] to store the capacitor Cs, and the source data circuit of the liquid crystal conducts the charging work, i.e., the programming work. At this time, the storage capacitor Cs will obtain a suitable charge state for the display of the next cycle.

[0129] In S1 and S2, the backlight of the liquid crystal display screen is turned off; in S3 and the buffering stage, the backlight of the liquid crystal display screen is turned on.

[0130] In one embodiment:

[0131] The backlight of the liquid crystal display screen in S1 and S2 is turned off, which is called the black field; the backlight of the liquid crystal display screen in S3 and the buffering stage is turned on, which is called the light field.

[0132] The backlight turning off and turning on alternate with each other to form a pipeline-type field-sequential driving timing. For the purpose of illustration, in the case of no CF film color filter layer in this embodiment, the field-sequential driving mode of RGB three sub-field display is taken as an example:

[0133] As Figure 10 shown, it is a pipeline-type field-sequential light-emitting and programming mode. Among them, Disp is to turn on the backlight to display an image once; Prog is the time for all pixels of the liquid crystal screen to sequentially scan and execute a first-order programming action once; 1Frame Time is the time of a normal frame including RGB three sub-fields; K is the black field, that is, the backlight off state.

[0134] During the 3-sub-field timing display process, there are 3 sub-fields; for the logic of field-sequential display, these three sub-fields can be the R red sub-field, the G green sub-field, and the B blue sub-field, that is, the color of the backlight, which coincides with the data of the sub-field, and is also R red, G green, and B blue;

[0135] Furthermore, during the display process of the R red sub-field, the first-order programming charging data is completed. This programming data is used for the display of the next sub-field. And so on.

[0136] Further preferably, the backlight timing of the pipeline-type field-sequential display liquid crystal drive can be optimized to the logic shown in the following figure. As Figure 11 shown: In this preferred mode, the first-order programming process continues until the S1 stage of the next sub-field, that is, the preset charging stage, but does not extend to the S2 stage, that is, the second-order programming stage; the duration of the K field, that is, the black field, is greater than or equal to the sum of the preset charging time and the second-order programming charging time.

[0137] Furthermore, the first-order programming time of all liquid crystal pixels can extend to the S1 stage of the next frame and cannot extend to the S2 stage. The specific reason is: If the driving ability of the source data driver SOURCE driver or the gate data driver GATE DRIVER of the liquid crystal is insufficient, or due to the large number of liquid crystal scanning rows, resulting in a longer time spent from the start of the first row scan to the completion of the first-order programming charging behavior until the last row is completed, then the preferred pipeline-type backlight drive and programming mode shown in Figure 11 can be adopted. Under this logic, the programming can continue during the K field, that is, the black field.

[0138] And, it is also possible to move the first-order programming charging link of the next sub-frame backward by adjusting the time of the buffer stage, and the first-order programming charging time continues until the K field, that is, the black field picture; this can reduce the problem of uneven partial display caused by charge leakage due to the too long interval between the first-order programming charging time and the actual light-emitting sub-frame.

[0139] In addition, in this embodiment, when the first synchronization signal Vst1 and the second synchronization signal Vst2 are square waves, the sustain voltage V 维持 has a range of 0 ≤ V 维持 ≤ V 全亮 , where V 全亮 is the voltage when the liquid crystal pixel is preset to the highest level;

[0140] When the first synchronization signal Vst1 and the second synchronization signal Vst2 are ramp waves, the sustain voltage is a high level or zero level;

[0141] When the sustain voltage is at a high level, the duration of maintaining the high level depends on the charge in S3 and the parameters of the ramp wave;

[0142] Furthermore, the first synchronization signal Vst1 is a ramp signal, and the gate voltage of the transistor is Vst2 + VQ(n); as time changes, since the voltage of the first synchronization signal Vst1 is a ramp signal, its voltage value keeps changing. Therefore, the threshold voltage of the transistor will change. Until a certain moment when the transistor is fully turned on, the charge of Vpx is released completely.

[0143] The beneficial effects of this embodiment are as follows:

[0144] (1) In a conventional display situation, since the liquid crystal capacitor programming is carried out sequentially, and the data programming is completed from the first row to the last row, the required normal time is very long. Therefore, the content displayed in the first row is actually out of sync with the content displayed in the last row; especially in a high-resolution liquid crystal display environment, the out-of-sync situation is more serious;

[0145] When using the field-sequential method for display and using an RGB light source to achieve color display, when using the above programming method for image display, the light source must be turned on for display only after the programming of the last row is completed. Therefore, the time available for actual display is squeezed to a very small value. In this case, on the one hand, the requirements for the backlight become extremely high, which is likely to cause problems such as the lifespan of the display light source; on the other hand, the requirements for the data driving ability of the display are also very high, and all data programming needs to be completed in the shortest possible time. Therefore, the cost and driving ability requirements of the driving chip are very high.

[0146] In this embodiment, however, the data programming and the light emission are in a parallel pipelined operation. For example, in the link of displaying the red R sub-frame, the data programming operation required for the next sub-frame G is also being carried out synchronously. Thus, the data writing operation does not occupy the effective display time, which significantly increases the effective time, improves the time of field-sequential display, and reduces the driving ability requirements for the programming device;

[0147] Of course, the technical solution provided in this embodiment can be applied not only to the liquid crystal display screen using the field sequential method for display, but also to the traditional liquid crystal display screen, that is, the ordinary liquid crystal display screen in the background art.

[0148] (2) When using the storage capacitor Cs, the main drawback is that the number of components is relatively large. A relatively large area in the liquid crystal pixel is occupied by transistors and capacitors, reducing the actual space available for display. As a result, the aperture ratio of the display pixel is low and the light transmission efficiency is low. Especially in the pixel circuit, the capacitor occupies a large area, further reducing the aperture ratio.

[0149] The dual-gate transistor of this embodiment has a simpler pixel structure. It omits the capacitor element that consumes the most area in the original circuit, and only 3 TFTs are required for each unit pixel. Therefore, its pixel has a higher aperture ratio and a higher efficiency of converting backlight to actual display light.

[0150] (3) The programming process of the original circuit depends on the charge distribution relationship of the capacitor. Since the IGZO TFT itself has a certain parasitic capacitance, especially for the ESL type device, its parasitic capacitance is relatively large. Then the actual programming voltage value is strongly affected by the parasitic capacitance. Due to the inevitable deviation of the parasitic capacitance and others between process batches, this leads to the possible deviation of the actual programming voltage value of the original pixel circuit with different process batches.

[0151] The voltage programming process of this embodiment, especially the conversion from the previous frame programming state to the current frame programming state, mainly depends on the auxiliary gate of the dual-gate device, that is, the high / low voltage of Vst1 connected thereto. In the programming state of the previous frame, Vst1 is low, so the threshold voltage of the dual-gate transistor T4 is relatively large, and the third transistor T3 is not conducting, and vpx maintains the display data of the previous frame. When entering the programming state of the current frame, Vst1 is high, so that the threshold voltage of the dual-gate transistor T4 is relatively small, and the third transistor T3 enters the conducting state, and Vpx is updated to the display data of the current frame.

[0152] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A control circuit for a liquid crystal pixel, characterized in that, it includes a preset charging module (1), a second-order programming module (2) and a first-order programming module (3) connected in sequence; the preset charging module (1) is used to charge the liquid crystal pixel capacitor through a high level, and preset the liquid crystal pixel to a high level state; the second-order programming module (2) discharges the preset charging module (1) according to the programming data of the first-order programming module (3) to make its charge reach the holding voltage required for the liquid crystal pixel to display an image; the first-order programming module (3) receives and stores the charge delivered from an external control unit for the display of the next frame of image; the preset charging module (1) includes a liquid crystal pixel capacitor Cls and a second transistor T2, the second-order programming module (2) includes a storage capacitor Cs and a third transistor T3, the drain of the third transistor T3 is coupled to the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2, the source of the third transistor T3 is coupled to the second synchronization signal Vst2, the gate of the third transistor T3 is coupled to one end of the storage capacitor Cs through an internal node, and the other end of the storage capacitor Cs is connected to the first synchronization signal Vst1.

2. The control circuit for a liquid crystal pixel according to claim 1, characterized in that, the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen.

3. The control circuit for a liquid crystal pixel according to claim 2, characterized in that, the gate of the second transistor T2 is coupled to an external level Vpre, the drain of the second transistor T2 is coupled to an external level VH, and the source of the second transistor T2 is connected to the liquid crystal pixel capacitor Cls through an internal node Vpx.

4. The control circuit for a liquid crystal pixel according to claim 3, characterized in that, when the preset charging module (1) works, the internal node Vpx is pulled high to a high level by the external level VH; after secondary programming by the second-order programming module (2), the internal node Vpx is the holding voltage required for the liquid crystal pixel to display an image.

5. The control circuit for a liquid crystal pixel according to claim 1, characterized in that, the second-order programming module (2) can also be composed of a double-gate transistor T4, the drain of the double-gate transistor T4 is connected in parallel to the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2 through an internal node Vpx, the source of the double-gate transistor T4 is coupled to the second synchronization signal Vst2, one gate of the double-gate transistor T4 is connected to the first synchronization signal Vst1, and the other gate is coupled to the first-order programming module (3) through an internal node Q.

6. The control circuit for a liquid crystal pixel according to claim 4 or 5, characterized in that, The first-order programming module (3) comprises a first transistor T1, wherein the gate of the first transistor T1 is connected to a gate driver for driving the entire liquid crystal screen, the source of the first transistor T1 is connected to a source driver for driving the entire liquid crystal screen, and the drain of the first transistor T1 is coupled to a storage capacitor Cs and a third transistor T3 via an internal node Q.

7. A control method for a liquid crystal pixel, It is characterized in that The control circuit for liquid crystal pixels according to any one of claims 1 to 6 is implemented in the following steps: S1, charging the liquid crystal pixel capacitor through a high level to preset the liquid crystal pixel to a high level state; S2, programming through the second-order programming module to discharge the preset charging module so that its charge reaches the maintenance voltage required for the liquid crystal pixel to display an image; S3, maintaining the charge voltage of the liquid crystal pixel, and at the same time receiving and storing the charge transmitted from the external control unit through the first-order programming module for displaying the next frame of image.

8. A control method for liquid crystal pixels according to claim 7, It is characterized in that In the S1, all liquid crystal pixels constituting the liquid crystal screen are preset to a high level at once and synchronously through a high level.

9. A control method for liquid crystal pixels according to claim 8, It is characterized in that In S2, the charge is programmed by a second-order programming module to discharge the preset charging module so that the charge reaches the maintenance voltage required for the liquid crystal pixel to display an image, specifically: Through the coordination of the first synchronization signal Vst1 and the second synchronization signal Vst2, the third transistor T3 is turned on to discharge the liquid crystal pixel capacitor Cls. The conduction capability and conduction duration of the third transistor T3 are jointly determined by the charge stored in the storage capacitor Cs in S3, the first synchronization signal Vst1 and the second synchronization signal Vst2. The charge of the liquid crystal pixel capacitor Cls is released from a high level state to a required charge, and then the voltage of the liquid crystal pixel capacitor Cls is programmed to the maintenance voltage required for the liquid crystal pixel to display an image.

10. A control method for liquid crystal pixels according to claim 9, It is characterized in that In the S2, the second-level programming of all pixels constituting the liquid crystal screen is completed synchronously at one time.

11. A control method for liquid crystal pixels according to any one of claims 7 to 10, It is characterized in that In S3, the charge voltage of the liquid crystal pixel is maintained, and at the same time, the charge transmitted from the external control unit is received and stored through the first-order programming module for displaying the next frame of the image, specifically: S31, buffer stage: the buffer stage adjusts the retention time of the storage capacitor Cs in the first-order programming module by delaying the time for the first-order programming module to start charging from the first row of the liquid crystal screen; S32, First-order programming stage: The entire liquid crystal display screen is charged row by row from the first row to the last row. The gate driver and source driver of the liquid crystal display screen cooperate with each other to perform first-order programming charging on each liquid crystal pixel from the first row to the last row; Among them, the charging data is related to the displayed image and is controlled by the source driver.

12. A control method for liquid crystal pixels according to claim 11, characterized in that, the time of the buffering stage in S31 depends on the manufacturing process of the liquid crystal display screen, and its maximum time is not greater than the time used for one frame of the picture.

13. A control method for liquid crystal pixels according to claim 12, characterized in that, The first-order programming time of all liquid crystal pixels can be completed in this frame of the picture, or extended to the S1 stage of the next frame, but cannot be extended to the S2 stage.

14. A control method for liquid crystal pixels according to claim 13, characterized in that, This method further includes: The backlight of the liquid crystal display screen is turned on and off in sequence, and the first-order programming process performed in the S3 stage in sequence forms a pipeline-type driving logic.

15. A control method for liquid crystal pixels according to claim 9, characterized in that, When the first synchronization signal Vst1 and the second synchronization signal Vst2 are square waves, the range of the sustain voltage V_sustain is 0 ≤ V_sustain ≤ V_full_bright, where V_full_bright is the voltage when the liquid crystal pixel is preset to the highest level.

16. A control method for liquid crystal pixels according to claim 9 or 15, characterized in that, When the first synchronization signal Vst1 and the second synchronization signal Vst2 are ramp waves, the sustain voltage is a high level or zero level.

17. A control method for liquid crystal pixels according to claim 16, characterized in that, When the sustain voltage is a high level, the duration of the high level depends on the charge in S3 and the parameters of the ramp wave.

Images