Memory macro including through-silicon via

Abstract

The present disclosure relates to memory macros including through-silicon vias. A memory macro structure includes a first memory array; a second memory array; a cell activation circuit coupled to and located between the first memory array and the second memory array; a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit; and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory macros including through-silicon vias. BACKGROUND

[0002] The trend toward integration of integrated circuits (ICs) has resulted in devices that are smaller and consume less power, but provide more functionality at higher speeds than earlier technologies. This miniaturization has been achieved through design and manufacturing innovations associated with increasingly stringent specifications.

[0003] IC packaging is often used for applications that distribute power among one or more IC dies. In some cases, the dies are stacked in a three-dimensional (3D) arrangement, where power distribution relies on through-silicon vias (TSVs) in one or more of the stacked IC dies. SUMMARY

[0004] According to one aspect of the present disclosure, a memory macro structure is provided, comprising: a first memory array; a second memory array; a cell activation circuit coupled to the first memory array and the second memory array and positioned between the first memory array and the second memory array; a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit; and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

[0005] According to another aspect of the present disclosure, an integrated circuit (IC) package is provided, comprising: a logic die; a substrate; and a memory die positioned between the logic die and the substrate, wherein the memory die comprises: a plurality of memory macros; and a plurality of through-silicon vias (TSVs) spanning a front side and a back side of the memory die and electrically coupled to the logic die and the substrate, wherein a TSV of the plurality of TSVs extends through a memory macro of the plurality of memory macros and is electrically isolated from the memory macro.

[0006] According to yet another aspect of the present disclosure, a method of fabricating a memory macro structure is provided, the method comprising: constructing a memory macro in a semiconductor wafer, the memory macro comprising a cell activation circuit and a control circuit; and fabricating a through-silicon via (TSV) spanning a front side and a back side of the semiconductor wafer and extending through one of the cell activation circuit or the control circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure can best be understood from the following detailed description when read with the accompanying drawings, in which: FIG. 1 is a diagram of a memory macro structure, according to some embodiments.

[0008] Figure 1A and Figure 1B is a diagram of a memory macro structure, according to some embodiments.

[0009] Figure 2 is a diagram of a memory macro structure, according to some embodiments.

[0010] Figures 3A-3C is a diagram of a portion of a memory macro structure, according to some embodiments.

[0011] Figure 4 is a diagram of an IC package, according to some embodiments.

[0012] Figure 5 is a flow diagram of a method of operating an IC package, according to some embodiments.

[0013] Figure 6 is a flow diagram of a method of manufacturing a memory macro structure, according to some embodiments.

[0014] Figure 7 is a flow diagram of a method of generating an IC layout, according to some embodiments.

[0015] Figures 8A-8C is an IC layout, according to some embodiments.

[0016] Figure 9 is a block diagram of an IC layout generation system, according to some embodiments.

[0017] Figure 10 is a block diagram of an IC manufacturing system and IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For instance, in the following description, forming a first feature on or over a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0019] Moreover, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0020] In various embodiments, a memory macro structure includes TSVs that extend through the memory macros and across the front and back surfaces of a memory die that includes the memory macros. A power distribution structure of an IC package that includes a memory die between a logic die and a substrate can thereby include TSVs that extend between the memory macros and through the memory macros. Compared to approaches that do not include TSVs that extend through the memory macros, the TSV density is increased, such that for a given memory macro size, the resistance and power loss in the power distribution structure is reduced.

[0021] Figure 1A And Figure 1B is an illustration of a memory macro structure 100 in accordance with some embodiments. Figure 1A depicts a plan view that includes X and Y directions, and Figure 1B depicts a cross-sectional view along plane A-A' that includes X and Z directions.

[0022] The memory macro structure 100 includes a plurality of instances of memory macros 100M and TSVs 100T; each instance of the TSVs 100T across a front surface FS and a back surface BS of an IC die 100D (also referred to as a memory die 100D in some embodiments). In Figure 1A and Figure 1BIn the illustrated embodiment, each instance of the memory macro 100M includes two instances of TSV 100T extending through and electrically isolated from the memory macro 100M, as discussed below. The memory macro structure 100M and the IC die 100D can be used as an IC package (e.g., as discussed below regarding...). Figure 4 The components of the IC package 400 discussed.

[0023] Figure 1A and Figure 1B The number, location, and relative size of the memory macros 100M and TSVs 100T shown are for illustrative purposes and are non-limiting examples. In various embodiments, the memory macrostructure 100 includes structures with different... Figure 1A and Figure 1B The quantities, locations, and / or relative sizes of memory macros 100M and TSVs 100T are shown.

[0024] A memory macro (e.g., memory macro 100M) is a memory circuit comprising: at least one array of memory cells configured to store data, and one or more circuits configured to control data input, output, and storage operations. Figure 1A and Figure 1B (Details not shown). In some embodiments, the memory cells of the memory macro 100M include static random access memory (SRAM) cells. In various embodiments, the SRAM cells include five-transistor (5T) SRAM cells, six-transistor (6T) SRAM cells, eight-transistor (8T) SRAM cells, nine-transistor (9T) SRAM cells, or SRAM cells having other numbers of transistors. In various embodiments, the memory cells of the memory macro 100M include dynamic random access memory (DRAM) cells, read-only memory (ROM) cells, non-volatile memory (NVM) cells, or other memory cell types capable of storing data.

[0025] A TSV (e.g., TSV 100T) is a conductive structure spanning the front and back sides of an IC die (e.g., the front FS and back BS of IC die 100D) and is thereby configured to provide a low-resistance path through the IC die. The TSV comprises one or more conductive materials, such as copper, aluminum, tungsten, titanium, and / or one or more other materials suitable for providing a low-resistance path between the front and back sides of the IC die. By being configured to provide a low-resistance path through the IC die, the TSV can be included in the power distribution structure of the IC package, for example, as described below. Figure 4 The power distribution structure of IC package 400, 400PDS, is discussed.

[0026] An instance of the memory macro 100M, including one or more instances of the TSV 100T extending through the instance of the memory macro 100M, is also referred to as a memory macro structure 100M. In some embodiments, one or more instances of the memory macro structure 100M include one or more instances of the TSV 100T extending through the instance of the memory macro 100M, as described below with respect to Figures 2-3C The memory macro structure 200 under discussion.

[0027] In the embodiment shown in Figure 1A and Figure 1B each instance of the memory macro 100M includes two instances of the TSV 100T extending through and electrically isolated from the instance of the memory macro 100M. In various embodiments, a given instance of the memory macro 100M includes zero, one, or more than two instances of the TSV 100T extending through and electrically isolated from the instance of the memory macro 100M.

[0028] In the embodiment shown in Figure 1A and Figure 1B The memory macro structure 100, also referred to as a memory die structure 100 in some embodiments, includes each of the memory macro 100M and the TSV 100T arranged in a row along the X direction. The row of the TSV 100T is both within the memory macro 100M in the row of the memory macro 100M and between adjacent rows of the memory macro 100M. The TSV 100T is centered in the Y direction among the memory macro 100M such that the TSV 100T has a pitch PI in the Y direction. Thus, the pitch P2 in the Y direction of the memory macro 100M is twice the pitch PI.

[0029] For a given size of the memory macro 100M, by including the TSV 100T having the pitch PI (half of the pitch P2), the memory macro structure 100 includes the TSV 100T at a density greater than in methods that do not include a TSV extending through the memory macro. In some embodiments, the memory macro structure 100 includes the TSV 100T otherwise arranged to include at least one TSV 100T extending through and electrically isolated from at least one memory macro 100M such that the TSV 100T is at a density greater than in methods that do not include a TSV extending through the memory macro.

[0030] In various embodiments, the memory macro structure 100 includes TSVs 100T that are not centered in the Y direction in the memory macro 100M and / or are located between adjacent columns of the memory macro 100M instead of and / or in addition to being located between adjacent rows of the memory macro 100M. In various embodiments, the memory macro structure 100 includes a subset of the memory macros 100M, e.g., alternating rows and / or columns, where a first subset includes one or more TSVs 100V and a second subset does not include one or more TSVs 100T.

[0031] By including at least one TSV 100T that extends through at least one memory macro 100M and is electrically isolated therefrom such that the density of TSVs 100T is greater than in the method of including TSVs that extend through memory macros, an IC die 100D including the at least one memory macro 100M can be included in an IC package, e.g., the IC package 400 discussed below with respect to Figure 4 where, for a given memory macro size, the resistance and power loss in the power distribution structure is reduced.

[0032] Figure 2 is an illustration of a memory macro structure 200 in accordance with some embodiments. The memory macro structure 200 can be used as one or more instances of the memory macro 100M discussed above with respect to Figure 1A and Figure 1B . Figure 2 depicts a plan view of the memory macro structure 200, including the X and Y directions discussed above with respect to Figure 1A and Figure 1B . Each of the figures in Figures 3A-3C discussed below is an illustration of a portion of the memory macro structure 200 in accordance with some embodiments.

[0033] The memory macro structure 200 includes global control circuitry 200GCT, global input / output (I / O) circuitry 200GIO, local control circuitry 200LCT, local I / O circuitry 200LIO, cell activation circuitry 200WLD, a memory array 200A, and TSVs 100T discussed above with respect to Figure 1A and Figure 1B .

[0034] Global control circuitry 200GCT is located between and electrically coupled to global I / O circuitry 200GIO, and is electrically coupled to each instance of local control circuitry 200LCT. Each instance of local control circuitry 200LCT is located between and electrically coupled to two instances of local I / O circuitry 200LIO, and is located between and electrically coupled to two instances of cell activation circuitry 200WLD (also referred to as word line drivers 200WLD in some embodiments). Each instance of local I / O circuitry 200LIO and each instance of activation circuitry 200WLD is located between and electrically coupled to two instances of memory array 200A. In various embodiments, memory macro 200 includes a combination of one or more of address lines, bit lines, data lines, cell activation lines (also referred to as word lines in some embodiments), and / or signal lines (not shown in Figure 2 FIG. 1) by which global control circuitry 200GCT, global I / O circuitry 200GIO, local control circuitry 200LCT, local I / O circuitry 200LIO, cell activation circuitry 200WLD, and memory array 200A are electrically coupled to one another as discussed.

[0035] Memory array 200A is an array of memory cells configured to store data, as discussed above with respect to Figure 1A and Figure 1B Each of global control circuitry 200GCT, global I / O circuitry 200GIO, local control circuitry 200LCT, local I / O circuitry 200LIO, and activation circuitry 200WLD is an IC configured to perform a subset of operations by which data is input into, output from, and stored in a respective instance of memory array 200A in response to various combinations of address, clock, control, and / or data signals (not shown in Figure 2

[0036] ​The global control circuit 200GCT is configured to generate and receive one or more of address, clock, control, and / or data signals configured to control top-level operations of the memory macro 200; each instance of the global IO circuit 200GIO is configured to perform top-level I / O operations in response to one or more of the address, clock, control, and / or data signals; each instance of the local control circuit 200LCT is configured to control operations of the local IO circuit 200LIO and the adjacent instance of the cell activation circuit 200WLD in response to one or more of the address, clock, control, and / or data signals, thereby controlling diagonally adjacent instances of the memory array 200A; and each instance of the local IO circuit 200LIO and the cell activation circuit 200WLD is configured to partially control operations of the adjacent instance of the memory array 200A in response to one or more of the address, clock, control, and / or data signals.

[0037] In Figure 2 In the illustrated embodiment, the memory macro 200 includes a total of two instances of the local control circuit 200LCT, each corresponding to four diagonally adjacent instances of the memory array 200A. In various embodiments, the memory macro 200 includes a total of one or more than two instances of the local control circuit 200LCT, each corresponding to four diagonally adjacent instances of the memory array 200A. In some embodiments, the memory macro 200 includes at least one instance of the local control circuit 200LCT corresponding to fewer or more than four instances of the memory array 200A.

[0038] In Figure 2 In the illustrated embodiment, a single instance of the TSV 100T extends through and is electrically isolated from each of the global control circuit 200GCT, each instance of the local control circuit 200LCT, and each instance of the cell activation circuit 200WLD. In some embodiments, more than one instance of the TSV 100T extends through and is electrically isolated from one or more of the global control circuit 200GCT, each instance of the local control circuit 200LCT, and each instance of the cell activation circuit 200WLD. In some embodiments, one or more of the global control circuit 200GCT, each instance of the local control circuit 200LCT, and each instance of the cell activation circuit 200WLD do not include a TSV 100T.

[0039] In some embodiments, one or more instances of TSVs 100T extend through each of the instances of global control circuitry 200GCT and local control circuitry 200LCT and are electrically isolated therefrom; and each instance of cell activation circuitry 200WLD does not include TSVs 100T. In some embodiments, one or more instances of TSVs 100T extend through each instance of cell activation circuitry 200WLD and are electrically isolated therefrom; and each of the instances of global control circuitry 200GCT and local control circuitry 200LCT does not include TSVs 100T.

[0040] In various embodiments, one or more instances of TSVs 100T (not shown) extend through each of the instances of global I / O circuitry 200GIO, local I / O circuitry 200LIO, and / or memory array 200A and are electrically isolated therefrom.

[0041] In Figures 3A-3C In each of the embodiments shown, an instance of cell activation circuitry 200WLD is adjacent to and electrically coupled with each of the two instances of memory array 200A, and an instance of local control circuitry 200LCT is adjacent to the instance of cell activation circuitry 200WLD, e.g., in the positive X direction or the negative X direction. Cell activation circuitry 200WLD includes a portion 200WLDA electrically coupled to the first instance of memory array 200A and a portion 200WLDB electrically coupled to the second instance of memory array 200A.

[0042] In Figure 3A and Figure 3B In each of the embodiments shown, cell activation circuitry 200WLD includes an instance of dummy region 200D, and an instance of TSVs 100T extends through the instance of dummy region 200D and is thereby electrically isolated from cell activation circuitry 200WLD. In some embodiments, control circuitry 200LCT includes an instance of dummy region 200D, and an additional instance of TSVs 100T extends through control circuitry 200LCT and is electrically isolated therefrom. In Figure 3C In the embodiment shown, control circuitry 200LCT includes an instance of dummy region 200D, and an instance of TSVs 100T extends through the instance of dummy region 200D and is thereby electrically isolated from control circuitry 200LCT, and cell activation circuitry 200WLD does not include TSVs 100T.

[0043] In Figure 3A and Figure 3BIn each of the illustrated embodiments, the local control circuit 200LCT is coupled to the portion 200WLDA by a signal bus CTLBA, and is separately coupled to the portion 200WLDB by a signal bus CTLBB. Thus, the local control circuit 200LCT is configured to separately communicate a first set of signals CTLA to the portion 200WLDA by the signal bus CTLBA, and a second set of signals CTLB to the portion 200WLDB by the signal bus CTLBB.

[0044] In some embodiments, each of the portions 200WLDA and 200WLDB includes an address decoder, and each of the first set of signals CTLA and the second set of signals CTLB includes one or more sets of predecode signals.

[0045] In Figure 3C In the illustrated embodiment, the local control circuit 200LCT is coupled to both the portion 200WLDA and the portion 200WLDB by a single signal bus CTLB, and the local control circuit 200LCT is thereby configured to communicate a set of signals CTL to both the portion 200WLDA and the portion 200WLDB by the signal bus CTLB. In some embodiments, each of the portions 200WLDA and 200WLDB includes an address decoder, and the set of signals CTL includes one or more sets of predecode signals.

[0046] In Figure 3A In the illustrated embodiment, an instance of the dummy region 200D extends across the entire cell activation circuit 200WLD, such that the portion 200WLDA and the portion 200WLDB are separated by the instance of the dummy region 200D. In some embodiments, the cell activation circuit 200WLD includes one or more additional instances of the dummy region 200D (not shown), such that the portion 200WLDA and the portion 200WLDB are separated by one or more instances of the dummy region 200D. Figure 3B In the illustrated embodiment, an instance of the dummy region 200D extends across a portion of the cell activation circuit 200WLD, such that the portion 200WLDA and the portion 200WLDB share a first boundary and a second boundary (not labeled) that are separated by the instance of the dummy region 200D.

[0047] In some embodiments, an instance of the dummy region 200D extends across a portion of the cell activation circuit 200WLD, such that the portion 200WLDA and the portion 200WLDB share a single boundary (not labeled) that is adjacent to the instance of the dummy region 200D. In some embodiments, the cell activation circuit 200WLD includes one or more additional instances of the dummy region 200D (not shown), such that the portion 200WLDA and the portion 200WLDB share one or more boundaries that are adjacent to each instance of the dummy region 200D.

[0048] In Figure 3A and Figure 3BIn the illustrated embodiment, a single instance of the TSV 100T extends through an instance of the dummy region 200D in the cell activation circuit 200WLD. In various embodiments, two or more instances of the TSV 100T extend through an instance of the dummy region 200D in the cell activation circuit 200WLD, or an instance of the dummy region 200D in the cell activation circuit 200WLD does not include a TSV 100T.

[0049] With the above-discussed configurations, the memory macro structure 200 can include at least one TSV 100T that extends through the memory macro structure 200 and is electrically isolated from the memory macro structure 200, enabling an IC die that includes the memory macro structure 200 to realize the benefits discussed above with respect to the memory macro structure 100.

[0050] Figure 4 is an illustration of an IC package 400 in accordance with some embodiments. Figure 4 A cross-sectional view of the IC package 400 is depicted, including the X and Z directions discussed above with respect to Figure 1A and Figure 1B The IC package 400 is a non-limiting example of an IC package that includes at least one instance of an IC die 100D in which one or more instances of the TSV 100T extend through one or more instances of the memory macro 100M, as discussed above with respect to Figures 1A-3C .

[0051] The IC package 400 includes a logic die 400L, a substrate 400S, memory dies 100D0-100D3 between the logic die 400L and the substrate 400S, and a power distribution structure 400PDS. Each of the memory dies 100D0-100D3 is an instance of the IC die 100D that includes one or more instances of the TSV 100T (labeled representative instances) that extend through one or more instances of the memory macro 100M, each of which is discussed above with respect to Figures 1A-3C The power distribution structure 400PDS includes bump structures 400B and instances of the TSV 100T, and is thereby configured to electrically couple the logic die 400L to the substrate 400S.

[0052] Memory die 100D0 is adjacent to logic die 400L; memory dies 100D1A-100D1C are aligned along the X direction, and each of memory dies 100D1A-100D1C is adjacent to memory die 100D0; memory die 100D2 is adjacent to each of memory dies 100D1A-100D1C; and memory die 100D3 is adjacent to each of memory die 100D2 and substrate 400S. An instance of TSV 100T is between memory dies 100D0, 100D1A, 100D1B, and 100D2, and an instance of TSV 100T is between memory dies 100D0, 100D1B, 100D1C, and 100D2.

[0053] Logic die 400L, memory dies 100D0, 100D1A, 100D2, and 100D3, and substrate 400S are aligned along the Z direction; logic die 400L, memory dies 100D0, 100D1B, 100D2, and 100D3, and substrate 400S are aligned along the Z direction; and logic die 400L, memory dies 100D0, 100D1C, 100D2, and 100D3, and substrate 400S are aligned along the Z direction.

[0054] Logic die 400L is an IC chip including one or more IC devices, such as one or a combination of a logic circuit, a signal circuit, or an application processor, a system on IC (SoIC), a transmitter and / or receiver, an application specific IC (ASIC), a large scale integration (LSI) or very large scale integration (VLSI) circuit, a voltage or current regulator, and / or the like.

[0055] Substrate 400S is an IC chip or a printed circuit board including electrically conductive sections supported and electrically separated by a plurality of insulating layers, and is configured to receive one or more supply voltages and a reference (e.g., ground) voltage, and to distribute the one or more supply voltages and the reference voltage to one or more of bump structures 400B.

[0056] The electrically conductive sections include electrically conductive lines, vias, contact pads, and / or under-bump metallization (UBM) structures including one or more electrically conductive materials, such as a metal, such as copper, aluminum, tungsten, or titanium, polysilicon, or another material capable of providing a low resistance path. The insulating layers include one or more dielectric materials, such as silicon dioxide, silicon nitride, or one or more high-k dielectric materials, a molding compound, or other materials capable of electrically insulating adjacent electrically conductive sections from one another.

[0057] The power distribution structure 400PDS (also referred to as a power distribution network 400PDS in some embodiments) includes a plurality of electrically conductive segments supported by and electrically separated by a plurality of insulating layers and arranged in accordance with power delivery requirements of, for example, the logic die 400L. In various embodiments, the power distribution structure 400PDS includes one or a combination of TSVs (e.g., TSVs 100T), dielectric vias (TDVs), power rails, super power rails, buried power rails, contact pads, electrically conductive segments arranged in a grid or mesh structure, or another arrangement suitable for distributing power to one or more IC devices.

[0058] The plurality of electrically conductive segments are arranged to contact the logic die 400L and some or all instances of the TSVs 100T included in some or all of the memory dies 100D0-100D3 such that the power distribution structure 400PDS is configured to electrically couple the logic die 400L to the substrate 400S through some or all instances of the TSVs 100T and the bump structure 400B.

[0059] The bump structure 400B is an electrically conductive structure overlying and contacting portions of the substrate 400S, thereby configured to provide an electrical connection between the substrate 400S and some or all instances of the TSVs 100T included in the memory die 100D3. In some embodiments, the bump structure 400B includes lead. In some embodiments, the bump structure 400B includes a lead-free material, such as tin, nickel, gold, silver, copper, or other material suitable for providing an electrical connection to an external electrically conductive element.

[0060] In some embodiments, the bump structure 400B has a substantially spherical shape. In some embodiments, the bump structure 400B is a controlled collapse chip connection (C4) bump, a ball grid array bump, a micro bump, or the like.

[0061] In Figure 4 In the illustrated non-limiting example, the IC package 400 includes six instances of the memory die 100D: the memory dies 100D0-100D3 arranged in four rows between the logic die 400L and the substrate 400S so as to electrically couple the logic die 400L to the substrate 400S. In various embodiments, the IC package includes more or fewer than six instances of the memory die 100D and / or includes instances of the memory die 100D arranged otherwise so as to electrically couple the logic die 400L to the substrate 400S. In some embodiments, the IC package 400 includes a single instance of the memory die 100D between the logic die 400L and the substrate 400S so as to electrically couple the logic die 400L to the substrate 400S.

[0062] In Figure 4In the illustrated non-limiting example, the IC package 400 includes memory dies 100D0-100D3 that are oriented with the front side FS farther along the Z direction than the back side BS (a representative example of the memory die 100D3 is labeled). In various embodiments, one or more of the memory dies 100D0-100D3 have an opposite orientation, with the back side BS farther along the Z direction than the front side FS.

[0063] In Figure 4 In the illustrated non-limiting example, the IC package 400 includes a single instance of each of the logic dies 400L and the substrate 400S. In various embodiments, the IC package 400 includes two or more instances of one or both of the logic dies 400L or the substrate 400S, and the instances of the memory dies 100D are arranged such that each instance of the logic dies 400L is electrically coupled to each instance of the substrate 400S.

[0064] In Figure 4 In the illustrated non-limiting example, the memory dies 100D0-100D3 include a number of instances of the memory macro 100M ranging from 1 to 5. In various embodiments, one or more of the memory dies 100D0-100D3 do not include an instance of the memory macro 100M, or include a number of instances of the memory macro 100M greater than 5.

[0065] In Figure 4 In the illustrated non-limiting example, the instances of the memory macro 100M include a number of instances of the TSV 100T ranging from 1 to 3. In various embodiments, one or more of the instances of the memory macro 100M include a number of instances of the TSV 100T greater than 3.

[0066] With the above-discussed configurations, the IC package 400 includes at least one instance of the IC die 100D in which one or more instances of the TSV 100T extend through one or more instances of the memory macro 100M, enabling the IC package 400 to realize the benefits described above with respect to the memory macro 100.

[0067] Figure 5 is a flowchart of a method 500 of operating an IC package in accordance with one or more embodiments. The method 500 can be used with an IC package, such as the IC package 400 discussed above with respect to Figure 4 .

[0068] Figure 5 The order of the operations of the method 500 described in Figure 5 may be performed in an order different than described in Figure 5 In some embodiments, operations other than those depicted in Figure 5The operations described herein are performed before, between, during, and / or after. In some embodiments, the operation of method 500 is part of operating a circuit, such as a circuit including an IC package.

[0069] In operation 510, in some embodiments, a power supply voltage is received at a first terminal of the TSV of the memory die. Receiving a power supply voltage at the first terminal of the TSV of the memory die includes the memory die being positioned within an IC package, and receiving a power supply voltage at the first terminal of the TSV of the memory die includes receiving a power supply voltage from a power distribution structure of the IC package. In some embodiments, receiving a power supply voltage at the first terminal of the TSV of the memory die includes receiving a power supply voltage from the above-mentioned... Figure 4 The power distribution structure discussed is 400PDS, which receives a power supply voltage. In some embodiments, receiving a power supply voltage from the power distribution structure includes receiving a voltage from a bump structure (e.g., as mentioned above). Figure 4 The bump structure 400B under discussion receives the power supply voltage.

[0070] In some embodiments, the memory die is located between a logic die and a substrate configured to receive a power supply voltage, and receiving the power supply voltage at a first end of the memory die's TSV includes receiving the power supply voltage at the substrate. In some embodiments, receiving the power supply voltage at the substrate includes, as described above, receiving the power supply voltage at the substrate. Figure 4 The IC package 400 discussed receives the power supply voltage at the substrate 400S.

[0071] In some embodiments, receiving the power supply voltage at the first terminal of the TSV of the memory die includes the above-mentioned... Figures 1A-4 The power supply voltage is received at one end of the TSV 100T of the memory die 100D under discussion.

[0072] In some embodiments, a TSV is one of a plurality of TSVs, and receiving a power supply voltage at a first terminal of the TSV includes receiving a power supply voltage at each of the plurality of TSVs, for example, as mentioned above. Figures 1A-4 Several instances of the TSV 100T are discussed.

[0073] In some embodiments, the memory die is one of a plurality of memory dies, and receiving a power supply voltage at a first terminal of the memory die's TSV includes receiving a power supply voltage converted by one or more additional memory dies among the plurality of memory dies.

[0074] In some embodiments, receiving a power supply voltage at the first terminal of the TSV of the memory die includes receiving a reference voltage, such as a ground voltage.

[0075] At operation 520, the power supply voltage is converted through the memory macro to the second end of the TSV. Converting the power supply voltage through the memory macro includes converting the power supply voltage that is electrically isolated from the memory macro. In some embodiments, converting the power supply voltage through the memory macro includes converting the power supply voltage through the memory macro 100 discussed above with respect to Figures 1A-4 At operation 520, the power supply voltage is converted through the memory macro to the second end of the TSV. Converting the power supply voltage through the memory macro includes converting the power supply voltage that is electrically isolated from the memory macro. In some embodiments, converting the power supply voltage through the memory macro includes converting the power supply voltage through the memory macro 100 discussed above with respect to

[0076] In some embodiments, converting the power supply voltage through the memory macro includes activating a circuit (e.g., the global control circuit 200GCT, the local control circuit 200LCT, or the wordline driver circuit 200WLD discussed above with respect to Figures 2-3C In some embodiments, converting the power supply voltage through the memory macro includes activating a circuit (e.g., the global control circuit 200GCT, the local control circuit 200LCT, or the wordline driver circuit 200WLD discussed above with respect to

[0077] In some embodiments, the TSV is one of a plurality of TSVs included in the memory macro, and converting the power supply voltage through the memory macro includes converting the power supply voltage to the second end of each of the plurality of TSVs, e.g., the plurality of instances of the TSV 100T discussed above with respect to Figures 1A-4 In some embodiments, the TSV is one of a plurality of TSVs included in the memory macro, and converting the power supply voltage through the memory macro includes converting the power supply voltage to the second end of each of the plurality of TSVs, e.g., the plurality of instances of the TSV 100T discussed above with respect to

[0078] In some embodiments, the memory macro is one of a plurality of memory macros, and converting the power supply voltage through the memory macro includes converting the power supply voltage through each of the plurality of memory macros, e.g., the plurality of instances of the memory macro 100M discussed above with respect to Figures 1A-4 In some embodiments, the memory macro is one of a plurality of memory macros, and converting the power supply voltage through the memory macro includes converting the power supply voltage through each of the plurality of memory macros, e.g., the plurality of instances of the memory macro 100M discussed above with respect to

[0079] In some embodiments, converting the power supply voltage through the memory macro includes converting a reference voltage through the memory macro.

[0080] At operation 530, the power supply voltage is received at the logic die from the second end of the TSV. Receiving the power supply voltage at the logic die includes receiving the power supply voltage from a power distribution structure of the IC package, e.g., the power distribution structure 400PDS of the IC package 400 discussed above with respect to Figure 4 At operation 530, the power supply voltage is received at the logic die from the second end of the TSV. Receiving the power supply voltage at the logic die includes receiving the power supply voltage from a power distribution structure of the IC package, e.g., the power distribution structure 400PDS of the IC package 400 discussed above with respect to

[0081] In some embodiments, the memory die is one of a plurality of memory dies, and receiving the power supply voltage from the second end of the TSV includes receiving the power supply voltage converted through one or more additional memory dies of the plurality of memory dies.

[0082] In some embodiments, the TSV is one of a plurality of TSVs, and receiving the power supply voltage from the second end of the TSV includes receiving the power supply voltage from the second end of each of the plurality of TSVs, e.g., the plurality of instances of the TSV 100T discussed above with respect to Figures 1A-4 In some embodiments, the TSV is one of a plurality of TSVs, and receiving the power supply voltage from the second end of the TSV includes receiving the power supply voltage from the second end of each of the plurality of TSVs, e.g., the plurality of instances of the TSV 100T discussed above with respect to

[0083] In some embodiments, receiving the supply voltage from the second end of the TSV includes receiving a reference voltage from the second end of the TSV.

[0084] By performing some or all of the operations of method 500, the IC package operations include converting a supply voltage by the memory macro including the TSV, thereby obtaining the benefits discussed above with respect to memory macro structure 100.

[0085] Figure 6 is a flowchart of a method 600 of fabricating a memory macro structure in accordance with some embodiments. Method 600 is operable to form memory macro structure 100 discussed above with respect to Figure 1A and Figure 1B IC package 400 discussed above with respect to Figure 4 In some embodiments, the operations of method 600 are a subset of the operations of a method of forming an IC package (e.g., a 2.5D IC package, a 3D IC package, or an InFO package).

[0086] In some embodiments, the operations of method 600 are performed in the order shown in Figure 6 In some embodiments, the operations of method 600 are performed in a different order than depicted in Figure 6 In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 600. In some embodiments, performing some or all of the operations of method 600 includes performing one or more operations discussed below with respect to IC fabrication system 1000 and Figure 10

[0087] At operation 610, in some embodiments, a memory macro is constructed in a semiconductor wafer. In some embodiments, constructing the memory macro includes constructing memory macro 100M discussed above with respect to Figures 1A-4

[0088] Constructing the memory macro includes constructing a plurality of IC devices, e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices, configured to operate as discussed above with respect to memory macro 100M.

[0089] Constructing the memory macro includes performing one or more of a variety of fabrication operations, e.g., photolithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing a plurality of IC devices in a semiconductor wafer.

[0090] In some embodiments, constructing the memory macro includes constructing a dummy region (e.g., discussed above with respect to Figures 3A-3C ​​Memory macro of dummy region 200D) discussed. Building a memory macro that includes a dummy region includes forming one or more dielectric layers that configure the dummy region to be electrically isolated from the memory macro, e.g., as discussed above with respect to Figures 2-3C Global control circuit 200GCT, local control circuit 200LCT, or cell activation circuit 200WLD discussed.

[0091] Forming one or more dielectric layers includes depositing one or more dielectric materials, e.g., silicon dioxide, silicon nitride, or one or more high-k dielectric materials, or other materials that are capable of electrically insulating adjacent conductive segments from one another. In various embodiments, depositing a dielectric material includes performing a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process, a laser chemical vapor deposition (LCVD) process, an evaporation process, an electron beam evaporation (electron gun) process, or another suitable deposition process.

[0092] In some embodiments, operation 620 is performed prior to performing operation 610, and building a memory macro includes forming a dummy region adjacent to one or more TSVs that extend through a structure of the memory macro.

[0093] In some embodiments, building a memory macro in a semiconductor wafer includes building a plurality of memory macros in the semiconductor wafer, e.g., a plurality of instances of a memory macro discussed above with respect to Figures 1A-4

[0094] In some embodiments, operation 610 is repeated such that building a memory macro in a semiconductor wafer includes building a plurality of memory macros in a corresponding plurality of semiconductor wafers, e.g., corresponding to a plurality of memory dies 100D0-100D3 discussed above with respect to Figure 4

[0095] In operation 620, in some embodiments, a TSV is constructed that spans a front side and a back side of the semiconductor wafer and extends through the memory macro. Constructing the TSV includes performing a plurality of fabrication operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, whereby one or more conductive materials are configured to form a continuous, low-resistance structure that spans the front side and the back side of the semiconductor wafer.

[0096] In some embodiments, constructing a TSV that spans a front side and a back side of the semiconductor wafer and extends through the memory macro includes constructing a TSV 100T that spans a front side FS and a back side BS of the IC die 100D and extends through the memory macro 100M, as discussed above with respect to Figures 1A-4

[0097] ​​​In some embodiments, constructing the TSVs extending through the memory macro includes constructing TSVs extending through dummy regions of the memory macro (e.g., dummy regions 200D discussed above with respect to Figures 3A-3C FIG. 2).

[0098] In some embodiments, operation 610 is performed prior to performing operation 620, and constructing the TSVs extending through the memory macro includes constructing TSVs extending through one or more dielectric layers of the semiconductor wafer, the one or more dielectric layers corresponding to the memory macro. In some embodiments, portions of each operation are iteratively performed, whereby the TSVs are constructed spanning the front and back sides of the semiconductor wafer and extending through the memory macro.

[0099] In some embodiments, constructing the TSVs spanning the front and back sides of the semiconductor wafer and extending through the memory macro includes constructing a plurality of TSVs, e.g., a plurality of instances of TSV 100T discussed above with respect to Figures 1A-4 FIG. 2).

[0100] In some embodiments, operation 610 is repeated, whereby constructing the TSVs spanning the front and back sides of the semiconductor wafer and extending through the memory macro includes constructing a plurality of TSVs spanning the front and back sides of a corresponding plurality of semiconductor wafers and extending through a corresponding plurality of memory macros, e.g., a plurality of instances of TSV 100T corresponding to memory dies 100D0-100D3 discussed above with respect to Figure 4 FIG. 2).

[0101] In operation 630, in some embodiments, the TSVs are connected to a power distribution structure of the IC package, thereby electrically connecting the logic dies to the substrate. Connecting the TSVs to the power distribution structure of the IC package includes performing one or more IC package fabrication operations, whereby a portion or all of the semiconductor wafer including the TSVs extending through the memory macro are connected to the power distribution structure of the IC package.

[0102] In various embodiments, the one or more IC package fabrication operations include one or more of: a die separation process, a molding injection or deposition, a bonding process, a metal deposition process, a soldering process, an annealing process, or another process suitable for fabricating an IC package.

[0103] In some embodiments, connecting the TSVs to the power distribution structure of the IC package includes connecting instances of TSV 100T to power distribution structure 400PDS, as discussed above with respect to Figure 4 FIG. 2).

[0104] In some embodiments, the TSV is one of a plurality of TSVs, and connecting the TSV to the power distribution structure of the IC package includes connecting each of the plurality of TSVs to the power distribution structure of the IC package, e.g., connecting a plurality of instances of the TSV 100T to the power distribution structure 400PDS, as discussed above with respect to Figure 4 .

[0105] In some embodiments, the operation 630 is repeated such that TSVs of a plurality of semiconductor wafers are connected to a power distribution structure, e.g., TSVs of one or more IC dies 100D0-100D3 are connected to the power distribution structure 400PDS, as discussed above with respect to Figure 4 .

[0106] The operations of the method 600 can be performed as a whole or individual subsets of operations. For example, by performing some or all of the operations 610 and 620, a memory macro structure is formed that includes a TSV extending through and electrically isolated from the memory macro, thereby obtaining the benefits discussed above with respect to the memory macro structure 100. By performing some or all of the operation 630 based on the memory macro structure formed according to the operations 610 and 620, an IC package is formed in which the memory macro structure includes a TSV extending through and electrically isolated from the memory macro, thereby obtaining the benefits discussed above with respect to the memory macro structure 100 and with respect to the IC package 400.

[0107] Figure 7 is a flowchart of a method 700 of generating an IC layout according to some embodiments. In some embodiments, generating an IC layout includes generating an IC layout (e.g., the IC layout 800A-800C discussed below with respect to Figures 1A-4 regarding the memory macro structure 100 discussed above with respect to Figures 8A-8C .

[0108] In some embodiments, some or all of the method 700 is performed by a processor of a computer. In some embodiments, some or all of the method 700 is performed by the processor 902 of the IC layout generation system 900 discussed below with respect to Figure 9 .

[0109] Some or all of the operations of the method 700 can be performed as part of a design program executed in a design room (e.g., the design room 1020 discussed below with respect to Figure 10 .

[0110] In some embodiments, the operations of the method 700 are performed in accordance with Figure 7The order shown is performed. In some embodiments, the operations of the method 700 are performed concurrently, and / or in a different order than Figure 7 depicted in FIG. 7. In some embodiments, one or more operations of the method 700 are performed before, between, during, and / or after one or more operations of the method 700.

[0111] Figures 8A-8C depicted in FIG. 8. In some embodiments, each of the IC layout diagrams 800A-800C includes features other than those depicted in FIG. 8, such as one or more transistor elements, vias, contacts, isolation structures, wells, conductive elements, and the like. In addition to the respective IC layout diagrams 800A-800C, Figures 8A-8C depicted in FIG. 8, such as one or more transistor elements, vias, contacts, isolation structures, wells, conductive elements, and the like. In addition to the respective IC layout diagrams 800A-800C, Figures 8A-8C depicted in FIG. 8, such as one or more transistor elements, vias, contacts, isolation structures, wells, conductive elements, and the like. In addition to the respective IC layout diagrams 800A-800C, Figures 1A-4 depicted in FIG. 8, such as one or more transistor elements, vias, contacts, isolation structures, wells, conductive elements, and the like. In addition to the respective IC layout diagrams 800A-800C,

[0112] At operation 710, in some embodiments, the layout diagram of the memory macro is modified to include a dummy region. Modifying the layout diagram of the memory macro to include the dummy region includes that the dummy region is usable in a fabrication process as a portion of defining the dummy region in a memory macro fabricated based on the layout diagram of the memory macro. In some embodiments, modifying the layout diagram of the memory macro to include the dummy region includes modifying the memory macro 100M discussed above with respect to FIG. 1. Figures 1A-4

[0113] In some embodiments, modifying the layout diagram of the memory macro to include the dummy region includes positioning the dummy region in a control circuit region or a cell activation circuit region of the memory macro. In some embodiments, modifying the layout diagram of the memory macro to include the dummy region includes that the dummy region is usable as a portion of defining an instance of the dummy region 200D discussed above with respect to FIG. 2. Figures 2-3C

[0114] In some embodiments, modifying the layout diagram of the memory macro to include the dummy region includes modifying the layout diagram of the memory macro to include a plurality of dummy regions. In some embodiments, modifying the layout diagram of the memory macro to include the dummy region includes modifying the IC layout diagram 800A to include dummy regions 800DR, as shown in FIG. 8. The IC layout diagram 800A corresponds to the memory macro 100M, and each of the dummy regions 800DR corresponds to an instance of the dummy region 200D discussed above with respect to FIG. 2. Figures 8A-8C Figures 1A-4

[0115] ​​​​In some embodiments, modifying the layout of the memory macro includes receiving the memory macro from a storage device (e.g., the non-transitory computer-readable storage medium 904 discussed below with respect to Figure 9 In some embodiments, modifying the layout of the memory macro includes receiving the memory macro through a network interface (e.g., the network interface 912 discussed below with respect to Figure 9 In some embodiments, modifying the layout of the memory macro includes receiving the memory macro in the form of one or more electronic files, e.g., transmitted over a network.

[0116] In some embodiments, modifying the layout of the memory macro includes the memory macro being included in an intellectual property (IP) block. In some embodiments, modifying the layout of the memory macro includes receiving the IP block, e.g., in the form of one or more electronic files, e.g., transmitted over a network.

[0117] In some embodiments, modifying the layout of the memory macro includes storing the memory macro in a storage device, and / or transmitting the memory macro through a network interface.

[0118] At operation 720, a layout of a memory macro including a dummy region is received. In some embodiments, receiving the layout of the memory macro includes receiving the layout at an IC layout generation system (e.g., the IC layout generation system 900 discussed below with respect to Figure 9 In some embodiments, receiving the layout of the memory macro includes receiving the IC layout 800A.

[0119] In some embodiments, receiving the layout of the memory macro includes receiving a plurality of layouts of the memory macro. In various embodiments, receiving the plurality of layouts of the memory macro includes the layouts being the same or different layouts.

[0120] In some embodiments, receiving the layout of the memory macro includes receiving a plurality of layouts of the memory macro. In various embodiments, receiving the plurality of layouts of the memory macro includes the layouts being the same or different layouts.

[0121] At operation 730, the layout of the memory macro is placed in a layout of an IC die. In some embodiments, placing the layout of the memory macro in the layout of the IC die includes a layout of the IC die corresponding to the IC die 100D discussed above with respect to Figures 1A-4 In some embodiments, the layout is one of a plurality of layouts of the memory macro, and placing the layout of the memory macro in the layout of the IC die includes placing the plurality of layouts of the memory macro in the layout of the IC die. In some embodiments, placing the plurality of layouts of the memory macro in the layout of the IC die includes arranging the plurality of layouts of the memory macro in rows and / or columns.

[0122] In some embodiments, placing the layout of the memory macro in the layout of the IC die includes placing the IC layout 800A in the IC layout 800B shown, or

[0123] In some embodiments, placing the layout of the memory macro in the layout of the IC die includes placing the IC layout 800A in the IC layout 800B shown, or Figure 8B Figure 8C ​The IC layout diagram shown is one of the 800C.

[0124] In operation 740, multiple TSV regions are arranged in the layout diagram of the IC die by placing a first TSV region among the multiple TSV regions in a dummy region. In some embodiments, placing the first TSV region among the multiple TSV regions in the dummy region includes placing the first TSV region in the dummy region as described above. Figures 1A-4 The first TSV region corresponding to the TSV 100T instance under discussion.

[0125] In some embodiments, the dummy region is a first dummy region among a plurality of dummy regions of a memory macro, and arranging a plurality of TSV regions in the layout diagram of the IC die includes: placing a second TSV region among the plurality of TSV regions into a second dummy region among the plurality of dummy regions.

[0126] In some embodiments, the layout diagram of a memory macro is one of a plurality of layout diagrams of a memory macro, and arranging a plurality of TSV regions in the layout diagram of an IC die includes: placing the TSV regions of the plurality of TSV regions in each dummy region of the corresponding memory macro in the plurality of layout diagrams of the memory macro.

[0127] In some embodiments, the layout diagram of the memory macro is one of a plurality of layout diagrams of the memory macro arranged in rows, and arranging a plurality of TSV regions in the layout diagram of the IC die includes placing a subset of the plurality of TSV regions between adjacent rows of the plurality of layout diagrams of the memory macro.

[0128] In some embodiments, arranging multiple TSV regions in the layout diagram of the IC die includes: Figure 8B The IC layout diagram 800B shown is as follows: Figure 8C The IC layout diagram 800C shown depicts a TSV region 800TSV arranged in one of its components. Each TSV region 800TSV is a TSV that can be used in the manufacturing process to define the TSV (e.g., as mentioned above). Figures 1A-4 The area discussed is part of the IC layout diagram of the TSV 100T.

[0129] exist Figure 8B In the non-limiting example shown, arranging the TSV region 800TSV includes placing instances of the TSV region 800TSV in each instance of the dummy region 800DR of each instance of the IC layout diagram 800A. Figure 8CIn the illustrated non-limiting example, arranging the TSV regions 800TSV includes placing an instance of the TSV regions 800TSV in a single instance of the dummy region 800DR of each instance of the IC layout 800A. In various embodiments, arranging the TSV regions 800TSV includes otherwise placing an instance of the TSV regions 800TSV in an instance of the dummy region 800DR of an instance of the IC layout 800A, e.g., placing a different number of instances of the TSV regions in an instance of the dummy region 800DR for a given instance of the IC layout 800A.

[0130] In some embodiments, arranging the plurality of TSV regions in the layout of the IC die is based on one or more design criteria of a logic die, e.g., the logic die 400L discussed above with respect to Figure 4 In some embodiments, the one or more design criteria includes a power supply voltage drop based on resistance values of a plurality of TSVs corresponding to the plurality of TSV regions.

[0131] At operation 750, in some embodiments, the IC layout is generated and stored in a storage device. Generating the IC layout is performed by a processor, e.g., the processor 902 of the IC layout generation system 900 discussed below with respect to Figure 9

[0132] In some embodiments, generating the IC layout includes positioning one or more features (not shown), e.g., contacts, vias, or conductive regions, that correspond to one or more IC structures fabricated based on the one or more features and are configured to be electrically connected through to one or more memory macros corresponding to the memory macros including the dummy regions.

[0133] In various embodiments, storing the IC layout in the storage device includes storing the IC layout in a non-volatile computer-readable memory, e.g., a database, and / or includes storing the IC layout over a network. In various embodiments, storing the IC layout in the storage device includes storing the IC layout in the non-volatile computer-readable memory 904, and / or over the network 914 of the IC layout generation system 900 discussed below with respect to Figure 9

[0134] In various embodiments, generating and storing the IC layout includes generating and storing one or more of the IC layouts 800A-800C.

[0135] At operation 760, in some embodiments, at least one of the one or more semiconductor masks, or at least one component of the semiconductor IC layer, is fabricated based on the IC layout. The IC fabrication system 1000 and Figure 10 ​​The fabrication of one or more semiconductor masks, or at least one component in a semiconductor IC layer, is discussed.

[0136] In various embodiments, the fabrication of one or more semiconductor masks, or at least one component in a semiconductor IC layer, is based on one or more of IC layout diagrams 800A-800C.

[0137] In operation 770, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithographic exposures based on the IC layout diagram. The following is about... Figure 10 The execution of one or more manufacturing operations (e.g., one or more photolithography exposures) based on IC layout diagrams is discussed.

[0138] In various embodiments, one or more manufacturing operations are performed based on one or more of the IC layout diagrams 800A-800C.

[0139] By performing some or all of the operations of method 700, an IC layout diagram corresponding to the memory macrostructure in which TSVs extend through the memory macrostructure is generated, such as IC layout diagrams 800A-800C, thereby achieving the benefits mentioned above regarding memory macrostructure 100. Furthermore, by placing the layout diagram of the memory macrostructure and arranging multiple TSV regions separately, design flexibility is improved compared to methods where multiple TSV regions are arranged and the layout diagram of the memory macrostructure is not separated.

[0140] Figure 9 This is a block diagram of an IC layout generation system 900 according to some embodiments. According to some embodiments, the method for designing an IC layout according to one or more embodiments described herein can be implemented, for example, using the IC layout generation system 900.

[0141] In some embodiments, the IC layout generation system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. Among other things, the storage medium 904 is encoded with (i.e., stores) computer program code 906, which is an executable instruction set. The hardware processor 902 executes the instructions 906, which represent (at least partially) an EDA tool that implements part or all of a method (e.g., the method 700 for generating the IC layout described above) (hereinafter referred to as the process and / or method).

[0142] The processor 902 is electrically coupled via the bus 908 to the computer readable storage medium 904. The processor 902 is also electrically coupled through the bus 908 to the I / O interface 910. The network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to the network 914, enabling the processor 902 and the computer readable storage medium 904 to connect to external elements via the network 914. The processor 902 is configured to execute the computer program code 906 encoded in the computer readable storage medium 904, in order to cause the IC layout generation system 900 to be operable to perform portions or all of the processes and / or methods. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0143] In one or more embodiments, the computer readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In one or more embodiments using optical discs, the computer readable storage medium 904 includes a compact disc - read only memory (CD-ROM), a compact disc - read / write (CD-R / W), and / or a digital video disc (DVD).

[0144] In one or more embodiments, the storage medium 904 stores computer program code 906 configured to cause the IC layout generation system 900 (where such execution represents (at least partially) an EDA tool) to be operable to perform portions or all of the processes and / or methods. In one or more embodiments, the storage medium 904 also stores information that facilitates performance of portions or all of the processes and / or methods. In one or more embodiments, the storage medium 904 stores an IC die library 907 of IC dies, including the IC layout 800A and / or 800B discussed above with respect to Figures 8A-8C

[0145] The IC layout generation system 900 includes the I / O interface 910. The I / O interface 910 is coupled to external circuits. In one or more embodiments, the I / O interface 910 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or a cursor direction key for communicating information and commands to the processor 902.

[0146] ​The IC layout generation system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914 to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet, USB, or IEEE- 1364. In one or more embodiments, part or all of the processes and / or methods are implemented in two or more IC layout generation systems 900.

[0147] The IC layout generation system 900 is configured to receive information through the I / O interface 910. The information received through the I / O interface 910 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 902. The information is transmitted to the processor 902 via the bus 908. The IC layout generation system 900 is configured to receive information related to a UI through the I / O interface 910. This information is stored in the computer readable medium 904 as a user interface (UI) 942.

[0148] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the IC layout generation system 900. In some embodiments, a tool such as Encounter® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool is used to generate the layout including the standard cells.

[0149] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage devices or memory units, such as an optical disc (e.g., a DVD), a magnetic disc (e.g., a hard disk), a semiconductor memory (e.g., a ROM, a RAM), a memory card, and the like.

[0150] Figure 10 ​is a block diagram of an IC fabrication system 1000 and IC fabrication flow associated therewith, in accordance with some embodiments. In some embodiments, the fabrication system 1000 is used to fabricate at least one of (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit, based on an IC layout.

[0151] In Figure 10 the IC fabrication system 1000 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to fabricating IC devices 1060, e.g., a design house 1020, a mask house 1030, and an IC fabricator / manufacturer (“fab”) 1050. The entities in the system 1000 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, e.g., an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1020, the mask house 1030, and the IC fabricator / manufacturer 1050 are owned by a single larger company. In some embodiments, two or more of the design house 1020, the mask house 1030, and the IC fabricator / manufacturer 1050 coexist in a common facility and use common resources.

[0152] The design house (or design team) 1020 generates an IC design layout 1022. The IC design layout 1022 includes various geometric patterns, e.g., the IC layout described above. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC devices 1060 to be fabricated. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1022 includes various IC features (e.g., active regions, gate electrodes, source and drain, interconnects of metal lines or vias, and openings for pads) formed in a semiconductor substrate (e.g., a silicon wafer), as well as various material layers disposed on the semiconductor substrate. The design house 1020 implements appropriate design processes to form the IC design layout 1022. The design processes include one or more of logic design, physical design, or placement and routing. The IC design layout 1022 is represented in one or more data files with geometric pattern information. For example, the IC design layout 1022 can be expressed in a GDSII file format or a DFII file format.

[0153] The mask room 1030 includes data preparation 1032 and mask manufacturing 1044. The mask room 1030 uses the IC design layout 1022 to manufacture one or more masks 1045 that are used to manufacture the various layers of the IC device 1060 according to the IC design layout 1022. The mask room 1030 performs mask data preparation 1032 in which the IC design layout 1022 is converted into a representative data file ("RDF"). The mask data preparation 1032 provides the RDF to the mask manufacturing 1044. The mask manufacturing 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, e.g., a mask (reticle) 1045 or a semiconductor wafer 1053. The mask data preparation 1032 processes the IC design layout 1022 to conform to the particular characteristics of the mask writer and / or the requirements of the IC manufacturer / fabric 1050. In Figure 10 In some embodiments, the mask data preparation 1032 and the mask manufacturing 1044 can be collectively referred to as mask data preparation.

[0154] In some embodiments, the mask data preparation 1032 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, e.g., that can be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 1022. In some embodiments, the mask data preparation 1032 includes further resolution enhancement techniques (RET), e.g., off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used that treat the OPC as an inverse imaging problem.

[0155] In some embodiments, the mask data preparation 1032 includes a mask rule checker (MRC) that checks the IC design layout 1022 that has already been processed in the OPC against a set of mask creation rules that include certain geometric and / or connectivity restrictions to ensure sufficient margins to address variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for limitations during the mask manufacturing 1044, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0156] In some embodiments, mask data preparation 1032 includes lithography process check (LPC), which simulates the process to be implemented by IC manufacturer / fabric 1050 to manufacture IC device 1060. LPC simulates the process based on IC design layout 1022 to create a simulated manufactured device, e.g., IC device 1060. Process parameters in the LPC simulation can include parameters associated with individual processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, e.g., aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after a simulated manufactured device is created by the LPC, if the simulated device is not close enough in shape to satisfy design rules, then OPC and / or MRC are repeated to further refine IC design layout 1022.

[0157] It should be appreciated that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOP), to modify IC design layout 1022 according to manufacturing rules. Moreover, the processing applied to IC design layout 1022 during data preparation 1032 can be performed in a variety of different orders.

[0158] After mask data preparation 1032 and during mask manufacturing 1044, a mask 1045 or a set of masks 1045 is manufactured based on the modified IC design layout 1022. In some embodiments, mask manufacturing 1022 includes performing one or more photolithography exposures based on the IC design layout 1022. In some embodiments, based on the modified IC design layout 1022, a mechanism of electron beam (e-beam) or multiple e-beams is used to form a pattern on a mask (photomask or reticle) 1045. The mask 1045 can be formed in various techniques. In some embodiments, the mask 1045 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation (e.g., an ultraviolet (UV) beam or an EUV beam) used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1045 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1045 is formed using phase shift techniques. In a phase shift mask (PSM) version of the mask 1045, individual features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 1044 are used in various processes. For example, such mask(s) are used in ion implantation processes to form various doped regions in a semiconductor wafer 1053, in etching processes to form various etched regions in the semiconductor wafer 1053, and / or for other suitable processes.

[0159] An IC manufacturer / fabrication facility 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC manufacturer / fabrication facility 1050 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnecting and packaging the IC products, and a third manufacturing facility can provide other services for the foundry enterprise.

[0160] IC manufacturer / manufacturer 1050 includes wafer fabrication tool 1052, which is configured to perform various manufacturing operations on a semiconductor wafer 1053 such that an IC device 1060 is fabricated according to one or more masks (e.g., mask 1045). In various embodiments, fabrication tool 1052 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0161] IC manufacturer / manufacturer 1050 uses one or more masks 1045 manufactured by mask chamber 1030 to manufacture IC device 1060. Therefore, IC manufacturer / manufacturer 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC manufacturer / manufacturer 1050 using one or more masks 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0162] Regarding IC manufacturing systems (e.g., Figure 10 Detailed information on the System 1000 and its associated IC manufacturing process can be found in, for example, U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are hereby incorporated herein by reference.

[0163] In some embodiments, a memory macro structure includes: a first memory array; a second memory array; a cell activation circuit coupled to and located between the first memory array and the second memory array; a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit; and a TSV extending through one of the cell activation circuit or the control circuit. In some embodiments, the cell activation circuit includes a first portion coupled to the first memory array and a second portion coupled to the second memory array, the TSV extends through the cell activation circuit between the first portion and the second portion, and the control circuit is configured to communicate a first set of predecode signals to the first portion and a second set of predecode signals to the second portion. In some embodiments, the first portion and the second portion are separated by a dummy region, and the TSV extends through the dummy region. In some embodiments, the TSV extends through the control circuit, and the control circuit is configured to communicate a single set of predecode signals to the cell activation circuit. In some embodiments, the TSV is a first TSV, the control circuit is a local control circuit, the memory macro structure includes a global control circuit coupled to the local control circuit, and a second TSV extends through the global control circuit. In some embodiments, the cell activation circuit is a first cell activation circuit, the TSV is a first TSV extending through the first cell activation circuit, and the memory macro structure includes a second cell activation circuit and a second TSV extending through the second cell activation circuit. In some embodiments, the control circuit is a first local control circuit, the TSV is a first TSV extending through the first local control circuit, and the memory macro structure includes a second local control circuit and a second TSV extending through the second local control circuit. In some embodiments, the memory macro structure is one of a plurality of memory macro structures, each of the plurality of memory macro structures includes a corresponding cell activation circuit and a corresponding control circuit, the TSV is one of a plurality of TSVs, and each of the plurality of TSVs extends through a corresponding one of the cell activation circuit or the control circuit of a corresponding memory macro structure of the plurality of memory macro structures.

[0164] In some embodiments, an IC package includes a logic die, a substrate, and a memory die between the logic die and the substrate. The memory die includes a plurality of memory macros and a plurality of TSVs across a front side and a back side of the memory die and electrically coupled to the logic die and the substrate, a TSV of the plurality of TSVs extending through a memory macro of the plurality of memory macros and electrically isolated from the memory macro. In some embodiments, the TSV extends through one of a cell activation circuit or a control circuit of the memory macro. In some embodiments, the TSV is one of a first subset of the plurality of TSVs, each TSV of the first subset of the plurality of TSVs extending through a corresponding memory macro of the plurality of memory macros, and a second subset of the plurality of TSVs, each TSV of the second subset of the plurality of TSVs extending through the memory die outside each memory macro of the plurality of memory macros. In some embodiments, a pitch of the plurality of memory macros is twice a pitch of the plurality of TSVs. In some embodiments, the memory die is one of a plurality of memory dies between the logic die and the substrate, and each memory die of the plurality of memory dies includes a corresponding plurality of memory macros and a corresponding plurality of TSVs across a front side and a back side of the corresponding memory die and electrically coupled to the logic die and the substrate, a corresponding TSV of the plurality of TSVs extending through a corresponding memory macro of the plurality of memory macros. In some embodiments, the logic die, the plurality of memory dies, and the substrate are aligned along a single direction. In some embodiments, each memory macro of the plurality of memory macros includes an array of SRAM cells.

[0165] In some embodiments, a method of fabricating a memory macro structure includes constructing a memory macro in a semiconductor wafer, the memory macro including a cell activation circuit and a control circuit, and fabricating a TSV that spans a front side and a back side of the semiconductor wafer and extends through one of the cell activation circuit or the control circuit. In some embodiments, constructing the memory macro includes forming a dummy region including one or more dielectric layers in the one of the cell activation circuit or the control circuit, and constructing the TSV includes constructing the TSV to extend through the dummy region. In some embodiments, the memory macro is a first memory macro, the TSV is a first TSV, constructing the memory macro includes constructing a second memory macro adjacent to the first memory macro, and fabricating the TSV includes fabricating a second TSV that extends between the first memory macro and the second memory macro. In some embodiments, the TSV is a first TSV, and fabricating the TSV includes fabricating a second TSV that extends through the other of the cell activation circuit or the control circuit. In some embodiments, the method further includes connecting the TSV to a power distribution structure of an IC package.

[0166] The foregoing summary of some embodiments has been presented for the purposes of illustration and description. It is, of course, not intended to be an exhaustive list of aspects of the disclosure. It will be appreciated that those skilled in the art can readily apply the broad principles

[0167] Example 1. A memory macro structure, comprising: a first memory array; a second memory array; a cell activation circuit coupled to the first memory array and the second memory array and positioned between the first memory array and the second memory array; a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit; and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

[0168] Example 2. The memory macro structure of Example 1, wherein the cell activation circuit includes a first portion coupled to the first memory array and a second portion coupled to the second memory array, the TSV extends through the cell activation circuit between the first portion and the second portion, and the control circuit is configured to communicate a first set of predecode signals to the first portion and a second set of predecode signals to the second portion.

[0169] Example 3. The memory macro structure of Example 2, wherein the first portion and the second portion are separated by a dummy region, and the TSV extends through the dummy region.

[0170] Example 4. The memory macro structure of Example 1, wherein the TSV extends through the control circuitry, and the control circuitry is configured to deliver a single set of predecode signals to the cell activation circuitry.

[0171] Example 5. The memory macro structure of Example 4, wherein the TSV is a first TSV, the control circuitry is local control circuitry, the memory macro structure includes global control circuitry coupled to the local control circuitry, and a second TSV extends through the global control circuitry.

[0172] Example 6. The memory macro structure of Example 1, wherein the cell activation circuitry is a first cell activation circuitry, the TSV is a first TSV that extends through the first cell activation circuitry, and the memory macro structure includes a second cell activation circuitry and a second TSV that extends through the second cell activation circuitry.

[0173] Example 7. The memory macro structure of Example 1, wherein the control circuitry is a first local control circuitry, the TSV is a first TSV that extends through the first local control circuitry, and the memory macro structure includes a second local control circuitry and a second TSV that extends through the second local control circuitry.

[0174] Example 8. The memory macro structure of Example 1, wherein the memory macro structure is one of a plurality of memory macro structures, each of the plurality of memory macro structures includes a corresponding cell activation circuitry and a corresponding control circuitry, the TSV is one of a plurality of TSVs, and each of the plurality of TSVs extends through a corresponding one of a cell activation circuitry or a control circuitry of a corresponding memory macro structure of the plurality of memory macro structures.

[0175] Example 9. An integrated circuit (IC) package, comprising: a logic die; a substrate; and a memory die between the logic die and the substrate, wherein the memory die includes: a plurality of memory macros; and a plurality of through-silicon vias (TSVs) spanning a front side and a back side of the memory die and electrically coupled to the logic die and the substrate, wherein a TSV of the plurality of TSVs extends through a memory macro of the plurality of memory macros and is electrically isolated from the memory macro.

[0176] Example 10. The IC package of example 9, wherein the TSV extends through one of a cell activation circuit or a control circuit of the memory macro.

[0177] Example 11. The IC package of example 9, wherein the TSV is one of a first subset of the plurality of TSVs, each TSV of the first subset of the plurality of TSVs extending through a corresponding memory macro of the plurality of memory macros, and each TSV of a second subset of the plurality of TSVs extending through the memory die outside of each memory macro of the plurality of memory macros.

[0178] Example 12. The IC package of example 9, wherein a pitch of the plurality of memory macros is twice a pitch of the plurality of TSVs.

[0179] Example 13. The IC package of example 9, wherein the memory die is one of a plurality of memory dies located between the logic die and the substrate, and each memory die of the plurality of memory dies includes: a corresponding plurality of memory macros; and a corresponding plurality of TSVs spanning a front side and a back side of the corresponding memory die and electrically coupled to the logic die and the substrate, wherein a corresponding TSV of the plurality of TSVs extends through a corresponding memory macro of the plurality of memory macros.

[0180] Example 14. The IC package of example 13, wherein the logic die, the plurality of memory dies, and the substrate are aligned along a single direction.

[0181] Example 15. The IC package of example 9, wherein each memory macro of the plurality of memory macros includes an array of static random access memory (SRAM) cells.

[0182] Example 16. A method of fabricating a memory macro structure, the method comprising: building a memory macro in a semiconductor wafer, the memory macro including a cell activation circuit and a control circuit; and constructing a through-silicon via (TSV) spanning a front side and a back side of the semiconductor wafer and extending through one of the cell activation circuit or the control circuit.

[0183] Example 17. The method of example 16, wherein building a memory macro includes forming a dummy region including one or more dielectric layers in the one of the cell activation circuit or the control circuit, and building the TSV includes building a TSV extending through the dummy region.

[0184] Example 18. The method according to Example 16, wherein the memory macro is a first memory macro, the TSV is a first TSV, constructing the memory macro includes constructing a second memory macro adjacent to the first memory macro, and constructing the TSV includes constructing a second TSV extending between the first memory macro and the second memory macro.

[0185] Example 19. The method according to Example 16, wherein the TSV is a first TSV, and constructing the TSV includes constructing a second TSV extending through the other of the cell activation circuit or the control circuit.

[0186] Example 20. The method according to Example 16 further includes: connecting the TSV to a power distribution structure of an integrated circuit IC package.

Claims

1. A memory macrostructure located in an integrated circuit die, the memory macrostructure comprising: First memory array; Second memory array; A cell activation circuit is coupled to the first memory array and the second memory array, and is located between the first memory array and the second memory array; A control circuit is coupled to the unit activation circuit and is positioned adjacent to the unit activation circuit; as well as A through-silicon via (TSV) that spans the front and back sides of the integrated circuit die and extends through either the cell activation circuit or the control circuit.

2. The memory macrostructure according to claim 1, wherein, The cell activation circuit includes a first portion coupled to the first memory array and a second portion coupled to the second memory array. The TSV extends through the unit activation circuit between the first portion and the second portion, and The control circuit is configured to transmit a first set of pre-decoding signals to the first part and a second set of pre-decoding signals to the second part.

3. The memory macrostructure according to claim 2, wherein, The first part and the second part are separated by a dummy region, and The TSV extends through the dummy region.

4. The memory macrostructure according to claim 1, wherein, The TSV extends through the control circuit, and The control circuit is configured to transmit a single set of pre-decoding signals to the unit activation circuit.

5. The memory macrostructure according to claim 4, wherein, The TSV is the first TSV. The control circuit is a local control circuit. The memory macrostructure includes a global control circuit coupled to the local control circuit, and The second TSV extends through the global control circuit.

6. The memory macrostructure according to claim 1, wherein, The unit activation circuit is the first unit activation circuit. The TSV is a first TSV that extends through the first unit activation circuit, and The memory macrostructure includes a second cell activation circuit and a second TSV extending through the second cell activation circuit.

7. The memory macrostructure according to claim 1, wherein, The control circuit is a first local control circuit. The TSV is a first TSV that extends through the first local control circuit, and The memory macrostructure includes a second local control circuit and a second TSV extending through the second local control circuit.

8. The memory macrostructure according to claim 1, wherein, The memory macrostructure is one of multiple memory macrostructures. Each of the plurality of memory macrostructures includes a corresponding cell activation circuit and a corresponding control circuit. The TSV is one of a plurality of TSVs, and Each of the plurality of TSVs extends through one of the corresponding cell activation circuits or control circuits of the corresponding memory macrostructure in the plurality of memory macrostructures.

9. An integrated circuit (IC) package, comprising: Logic chip; Substrate; as well as A memory die, located between the logic die and the substrate, wherein the memory die comprises: Multiple memory macros; and Multiple through-silicon vias (TSVs) span the front and back sides of the memory die and are electrically coupled to the logic die and the substrate. Among them, the TSV of the plurality of TSVs extends through the memory macro of the plurality of memory macros and is electrically isolated from the memory macro.

10. The IC package according to claim 9, wherein, The TSV extends through either the cell activation circuit or the control circuit of the memory macro.

11. The IC package according to claim 9, wherein, The TSV is one TSV in the first subset of the plurality of TSVs. Each TSV in the first subset of the plurality of TSVs extends through the corresponding memory macro in the plurality of memory macros, and Each TSV in the second subset of the plurality of TSVs extends outside each memory macro in the plurality of memory macros through the memory die.

12. The IC package according to claim 9, wherein, The spacing between the plurality of memory macros is twice the spacing between the plurality of TSVs.

13. The IC package according to claim 9, wherein, The memory die is one of a plurality of memory dies located between the logic die and the substrate, and Each of the plurality of memory dies includes: The corresponding multiple memory macros; and The corresponding multiple TSVs span the front and back sides of the corresponding memory die and are electrically coupled to the logic die and the substrate. Among them, the TSV corresponding to one of the plurality of TSVs extends through the memory macro corresponding to one of the plurality of memory macros.

14. The IC package according to claim 13, wherein, The logic die, the plurality of memory dies, and the substrate are aligned in a single direction.

15. The IC package according to claim 9, wherein, Each of the plurality of memory macros includes an array of static random access memory (SRAM) cells.

16. A method for manufacturing a memory macrostructure, the method comprising: A memory macro is constructed in a semiconductor wafer, the memory macro including a cell activation circuit and a control circuit; as well as Construct a through-silicon via (TSV) that spans the front and back sides of the semiconductor wafer and extends through either the cell activation circuit or the control circuit.

17. The method according to claim 16, wherein, Constructing the memory macro includes forming a dummy region comprising one or more dielectric layers in one of the cell activation circuits or the control circuit, and Constructing the TSV includes constructing a TSV that extends through the dummy region.

18. The method of claim 16, wherein The memory macro is the first memory macro. The TSV is the first TSV. Constructing the memory macro includes constructing a second memory macro adjacent to the first memory macro, and Constructing the TSV includes constructing a second TSV that extends between the first memory macro and the second memory macro.

19. The method of claim 16, wherein, The TSV is the first TSV, and Constructing the TSV includes constructing a second TSV that extends through either the cell activation circuit or the control circuit.

20. The method of claim 16, further comprising: The TSV is connected to the power distribution structure of the integrated circuit IC package.

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