Semiconductor structure and method of forming the same

Abstract

Embodiments of the invention relate to a semiconductor structure and a method for forming a semiconductor structure. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implant is performed on a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interface layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interface layer in the gate trench.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor structures and methods for forming the same. Background Technology

[0002] Electronic devices involving semiconductor devices are essential for many modern applications. Technological advancements in materials and design have resulted in generations of semiconductor devices, each containing smaller and more complex circuitry than the previous generation. This scaling down process also increases the complexity of handling and manufacturing ICs, and similar development of IC handling and manufacturing techniques is needed to realize these advancements. For example, three-dimensional transistors, such as FinFETs, have been introduced to replace planar transistors. While existing FinFET devices and methods for manufacturing them are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. For instance, replacing polysilicon gate electrodes with metal gate electrodes presents challenges for FinFET process development. Improvements in this area are expected. Summary of the Invention

[0003] Embodiments of the present invention relate to a method comprising: receiving a substrate, the substrate including a sacrificial gate structure disposed thereon, wherein the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer; removing the sacrificial gate layer to form a gate trench exposing the sacrificial dielectric layer; performing ion implantation on a portion of the substrate covered by the sacrificial dielectric layer in the gate trench; removing the sacrificial dielectric layer to expose the substrate from the gate trench; forming an interface layer over the substrate in the gate trench; and forming a metal gate structure over the interface layer in the gate trench.

[0004] Embodiments of the present invention relate to a method comprising: receiving a semiconductor structure including a sacrificial gate structure extending across a fin structure and disposed between a pair of spacers, wherein the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer; removing the sacrificial gate layer to expose the sacrificial dielectric layer between the pair of spacers; introducing a plurality of dopants to form doped regions in the fin structure and a pair of doped spacers; removing the sacrificial dielectric layer and a first portion of the fin structure from a second portion of the fin structure; forming an interface layer over the second portion of the fin structure between the pair of doped spacers; and forming a metal gate structure over the interface layer between the pair of doped spacers.

[0005] Embodiments of the present invention relate to a semiconductor structure comprising: a semiconductor substrate having a fin-like structure; an interface layer having a concave profile located above the semiconductor substrate; and a metal gate structure located above the interface layer, the metal gate structure comprising a gate dielectric layer, a work function metal layer, and a gap-filling metal layer, wherein the thickness of the gap-filling metal layer, measured along a first direction substantially parallel to the upper surface of the semiconductor substrate, varies along a second direction substantially perpendicular to the upper surface of the semiconductor substrate. Attached Figure Description

[0006] The following [Detailed Description], read in conjunction with the accompanying drawings, provides the best understanding of aspects of embodiments of the invention. It should be noted that, in accordance with industry standard practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to an aspect of the present invention.

[0008] Figure 2 This is a schematic diagram illustrating the semiconductor structure constructed during the manufacturing stage according to aspects of the present invention.

[0009] Figures 3 to 6 This is a cross-sectional view illustrating the semiconductor structure constructed in different manufacturing stages according to aspects of the present invention.

[0010] Figure 7 This is a schematic diagram illustrating the semiconductor structure constructed during the manufacturing stage according to aspects of the present invention.

[0011] Figure 8A Is along a similar Figure 7 The cross-sectional views of reference sections AA and BB are shown in the figure. Figure 8B Is along a similar Figure 7 The cross-sectional view of the reference section CC is shown in the figure.

[0012] Figure 9 This is a schematic diagram illustrating the semiconductor structure constructed during the manufacturing stage according to aspects of the present invention.

[0013] Figure 10A Is along a similar Figure 9 The cross-sectional views of reference sections AA and BB are shown in the figure. Figure 10B Is along a similar Figure 9 The cross-sectional view of the reference section CC is shown in the figure.

[0014] Figure 11 This is a top view illustrating the semiconductor structure constructed during the manufacturing stage according to aspects of the present invention.

[0015] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B This invention describes semiconductor structures constructed in various manufacturing stages according to aspects thereof.

[0016] Figure 16A and Figure 16B This describes a semiconductor structure constructed during the manufacturing stage according to aspects of the present invention. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, having a first member formed above or on a second member may include embodiments in which the first and second members form direct contact, and may also include embodiments in which additional members may be formed between the first and second members such that the first and second members do not form direct contact. Furthermore, element symbols and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially related terms (such as "below," "under," "down," "above," "over," "on," "on," and similar) may be used herein to describe the relationship between one element or component and another element or component(s), as illustrated in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and this also interprets the spatially relative descriptive terms used herein.

[0019] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, regions, layers, and / or sections, which should not be limited to these terms. These terms may be used only to distinguish elements, components, regions, layers, or sections from one another. Unless the context clearly indicates otherwise, the terms such as “first,” “second,” and “third” used herein do not imply a sequence or order.

[0020] As used herein, the terms “approximately,” “substantially,” “substantial,” and “about” are used to describe and take into account minor variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurs precisely and examples in which the event or situation occurs very closely approximately.

[0021] Fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes that include dual or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to allow the production of patterns with pitches (e.g., smaller than those that would otherwise be obtained using a single direct photolithography process). For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the fins.

[0022] As technology nodes continue to shrink in scale, researchers in some integrated circuit (IC) designs are looking to replace polysilicon gates with metal gates to improve device performance by reducing feature size. The method for forming metal gates is called the "gate-last" method, sometimes referred to as the replacement polysilicon gate (RPG) method. In the RPG method, the metal gate is fabricated last, allowing for a reduction in the number of subsequent operations. However, the RPG method is complex and presents several challenges.

[0023] For example, in high-k metal gate (HKMG) operation, it is necessary to remove the polysilicon gate (also called a dummy gate or sacrificial gate) to replace the polysilicon gate with the desired metal gate. During the removal of the polysilicon gate, in some embodiments, not only is the polysilicon gate removed, but the spacers adjacent to the polysilicon gate are also consumed, thus increasing the size of the gate trench. Subsequently, an oxide cleaning operation is performed after the removal of the polysilicon gate. During the oxide cleaning operation, a pad dielectric layer is consumed. In some embodiments, not only the pad dielectric layer is consumed, but the spacers adjacent to the pad dielectric layer are also etched during the oxide cleaning operation, thus increasing the size of the gate trench. The gate trench may have non-uniform sidewalls due to the etching of the spacers. The gate trench may be filled with a material for forming the metal gate. The metal gate may have protrusions extending into the etched spacers. The protrusions of the metal gate (called the "feet" of the metal gate) can cause gate length non-uniformity problems. Therefore, it can degrade the device performance of the semiconductor structure.

[0024] Therefore, embodiments of methods for forming semiconductor structures are provided. According to embodiments, the semiconductor structure is formed during an RPG or post-gate process. According to some embodiments, the semiconductor structure can be formed during a planar device process. In alternative embodiments, the semiconductor structure can be formed in a non-planar device. In some embodiments, the method for forming a semiconductor structure includes introducing a surface treatment onto a substrate beneath a pad dielectric layer. The surface treatment facilitates the formation of a curved upper surface of the substrate. The curved upper surface of the substrate can create a shrinkage space for the material used to form the metal gate. Therefore, the metal gate formed thereon can have a smaller base or can have substantially no base. Furthermore, the metal gate formed thereon can have a shorter gate length. In short, the method for forming a semiconductor structure alleviates the problem of gate length non-uniformity and thus improves the device performance of the semiconductor structure.

[0025] Figure 1 This is a flowchart illustrating a method 10 for forming a semiconductor structure 20 according to one or more embodiments of the present invention. Method 10 for forming the semiconductor structure 20 includes operation 102, wherein a substrate is received. In some embodiments, the substrate includes a sacrificial gate structure disposed thereon. In some embodiments, the substrate includes a fin structure, and the sacrificial gate structure is disposed across the fin structure. In some embodiments, the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer. Method 10 further includes operation 104, wherein the sacrificial gate layer is removed to form a gate trench exposing the sacrificial dielectric layer. Method 10 further includes operation 106, wherein ion implantation is performed on a portion of the substrate covered by the sacrificial dielectric layer in the gate trench. Method 10 further includes operation 108, wherein the sacrificial dielectric layer is removed to expose the substrate from the gate trench. Method 10 further includes operation 110, wherein an interface layer is formed over the substrate in the gate trench. Method 10 further includes operation 112, wherein a metal gate structure is formed over the interface layer in the gate trench.

[0026] Figure 2 This is a schematic diagram illustrating a semiconductor structure 20 constructed according to aspects of the present invention during a manufacturing stage in one or more embodiments. For example... Figure 2As shown, substrate 202 is received according to operation 102. Substrate 202 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, substrate 202 may comprise elemental semiconductor materials, compound semiconductor materials, or alloy semiconductor materials. Examples of elemental semiconductor materials may be (e.g., but not limited to) single-crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge), and / or diamond. Examples of compound semiconductor materials may be (e.g., but not limited to) silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb). Examples of alloy semiconductor materials may be (e.g., but not limited to) SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0027] Substrate 202 may contain various doping configurations known in the art depending on design requirements. For example, different doping profiles (e.g., n-wells, p-wells) may be formed on substrate 202 in regions designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 has an n-type region 202N and a p-type region 202P. The n-type region 202N can be used to form an n-type device, such as an NMOS transistor (e.g., an NFET). The p-type region 202P can be used to form a p-type device, such as a PMOS transistor (e.g., a PFET). The n-type region 202N may be physically separated from the p-type region 202P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be placed between the n-type region 202N and the p-type region 202P. Substrate 202 typically has an isolation structure (e.g., a shallow trench isolation (STI) structure) 204 into which regions containing different device types are inserted.

[0028] In some embodiments, substrate 202 may include fin structures 206 electrically isolated from each other by isolation structure 204. In some embodiments, fin structures 206 extend along a first direction D1. In some embodiments, fin structures 206 have fin heights ranging from about 30 nanometers to about 65 nanometers. Fin structures 206 have fin structures 206N disposed in n-type region 202N and fin structures 206P disposed in p-type region 202P. In various embodiments, the upper portion of fin structure 206 may be formed of silicon germanium (SiGe), silicon carbide, pure germanium or substantially pure germanium, group III to V compound semiconductors, group II to VI compound semiconductors, or the like. For example, materials that can be used to form group III to V compound semiconductors include (but are not limited to) indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, aluminum indium arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like. In some embodiments, the upper portion of the fin structure 206P may be formed of silicon germanium (SiGe), while the upper portion of the fin structure 206N may be formed of a material similar to that of the substrate 202.

[0029] In some embodiments, a semiconductor layer (which may serve as a sacrificial gate layer 209 in subsequent operations) is formed over the substrate 202. In some embodiments, a dielectric layer (which may serve as a sacrificial dielectric layer 208 in subsequent operations) may be formed prior to the formation of the semiconductor layer. In some embodiments, the semiconductor layer is made of polycrystalline silicon, but this disclosure is not limited thereto. In some embodiments, the dielectric layer comprises silicon oxide (SiO), but this disclosure is not limited thereto. The dielectric layer may be formed to cover the sidewalls of the fin structure 206 and the top surface of the fin structure 206. In some embodiments, the dielectric layer is formed by a thermal oxidation operation. In these embodiments, the dielectric layer is formed over the fin structure 206 while exposing the upper surface of the isolation structure 204.

[0030] The semiconductor layer and dielectric layer are patterned to form a sacrificial gate structure 210, such as Figure 2 As shown in the diagram. The sacrificial gate structure 210 includes a sacrificial gate layer 209 and a sacrificial dielectric layer 208. The sacrificial gate structure 210 is disposed across the fin structure 206. In some embodiments, a patterned hard mask 213 may be formed over the semiconductor layer to define the location and size of the sacrificial gate structure 210. In some embodiments, the patterned hard mask 213 may comprise silicon nitride (SiN), but this disclosure is not limited thereto. The patterned hard mask 213 may comprise a single-layer structure or a multi-layer structure. For example, the patterned hard mask 213 may be... Figure 2The dual-layer structure shown is not limited thereto. In some embodiments, the dual-layer patterned hard mask 213 may include a first patterned layer 213a and a second patterned layer 213b. The first patterned layer 213a and the second patterned layer 213b may contain the same material or different materials, depending on the specific implementation. Furthermore, the thicknesses of the first patterned layer 213a and the second patterned layer 213b may be different. For example, the thickness of the first patterned layer 213a may be less than the thickness of the second patterned layer 213b.

[0031] The sacrificial gate structure 210 extends along a second direction D2 different from the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1. Furthermore, the first direction D1 and the second direction D2 are in the same horizontal plane. The sacrificial gate structure 210 covers a portion of the fin structure 206, such as... Figure 2 As shown in the diagram. In other words, the sacrificial gate structure 210 is at least partially positioned above the fin structure 206, and the portion of the fin structure 206 lying beneath the sacrificial gate structure 210 may be referred to as the channel region. The sacrificial gate structure 210 may also define the source / drain region of the fin structure 206 as, for example, the portion of the fin structure 206 adjacent to the channel region and on the opposite side of the channel region.

[0032] Figures 3 to 6 This is a cross-sectional view illustrating the semiconductor structure 20 constructed at different manufacturing stages according to one or more embodiments of the present invention. Furthermore, Figures 3 to 6 Is along a similar Figure 2 Cross-sectional views illustrating reference section II (n-type region 202N) and reference section II-II (p-type region 202P). Reference Figure 3 Spacers 212 are formed above the sidewalls of the sacrificial gate structure 210. The sacrificial gate structure 210 may be positioned between a pair of spacers 212. The spacers 212 may be formed by conformally depositing one or more insulating materials and subsequently etching the insulating materials. The insulating materials may be formed of low-k dielectric materials such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or similar materials, and may be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or similar methods. The insulating material is partially left on the sidewalls of the sacrificial gate structure 210 and the patterned hard mask 213 during etching (thus forming the spacers 212). After etching, the spacers 212 may have straight sidewalls (as illustrated in the figure) or may have curved sidewalls (not shown in the figure).

[0033] refer to Figure 4A source / drain (S / D) structure 218 is formed in the fin structure 206. The S / D structure 218 is formed in the fin structure 206 such that each sacrificial gate structure 210 is positioned between corresponding adjacent pairs of S / D structures 218. In some embodiments, the S / D structure 218 may extend into and penetrate the fin structure 206. In some embodiments, the S / D structure 218 is a strained S / D structure. In these embodiments, portions of the fin structure 206 exposed from the sacrificial gate structure 210 may be removed, thereby obtaining a plurality of grooves. Epitaxial growth operations may be performed to form strained material in the grooves of the fin structure 206. In some embodiments, the top surface of the S / D structure 218 may be higher than the top surface of the fin structure 206. In some embodiments, an etch-back operation is performed prior to the formation of the source / drain (S / D) structure 218. An etchback operation can be performed to etch a portion of the spacers 212, thereby enlarging the openings 212O between the spacers 212 for forming the source / drain (S / D) structure 218.

[0034] The material of the S / D structure 218 can be selected to apply stress in the respective channel regions. In some embodiments, the lattice constant of the S / D structure 218 may differ from the lattice constant of the substrate 202 and the lattice constant of the fin structure 206. In some embodiments, the S / D structure 218 may comprise Ge, SiGe, InAs, InGaAs, InSb, GaSb, InAlP, InP, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the spacer 212 is used to separate the S / D structure 218 from the sacrificial gate structure 210 by an appropriate lateral distance, such that the S / D structure 218 does not short-circuit the subsequently formed gate of the resulting FinFET.

[0035] refer to Figure 5 A dielectric material layer 220 is formed over the substrate 202. The dielectric material layer 220 may be deposited over the S / D structure 218, spacer 212, isolation structure 204, and patterned hard mask 213 (if present) or sacrificial gate structure 210. The dielectric material layer 220 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, the dielectric material layer 220 may be referred to as an interlayer dielectric (ILD).

[0036] Alternatively or additionally, a contact etch stop layer (CESL) 222 is formed over the substrate 202 prior to the formation of the dielectric material layer 220. The CESL 222 may be deposited over the S / D structure 218, spacer 212, isolation structure 204, and patterned hard mask 213 (if present) or sacrificial gate structure 210. The CESL 222 may be formed between the dielectric material layer 220 and the S / D structure 218, spacer 212, isolation structure 204, and patterned hard mask 213 (if present) or sacrificial gate structure 210. The CESL 222 may comprise a dielectric material having an etch rate lower than that of the material of the dielectric material layer 220, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0037] refer to Figure 6 A planarization process, such as chemical mechanical planarization (CMP), can be performed to make the top surface of the dielectric material layer 220 flush with the top surface of the patterned hard mask 213 (if present) or the top surface of the sacrificial gate structure 210. The planarization process may also remove portions of the patterned hard mask 213 on the sacrificial gate structure 210 and the spacers 212 along the sidewalls of the patterned hard mask 213. After the planarization process, a dielectric structure 230 comprising the dielectric material layer 220 and CESL 222 is formed. After the planarization process, the top surfaces of the sacrificial gate structure 210, the spacers 212, and the dielectric structure 230 are coplanar (within process variations). Therefore, the top surface of the sacrificial gate layer 209 of the sacrificial gate structure 210 is exposed through the dielectric structure 230. In some embodiments, the dielectric structure 230 has a thickness above the fin structure 206, wherein the thickness of the dielectric structure 230 is in the range of about 30 nanometers to about 65 nanometers.

[0038] In some embodiments, the sacrificial gate structure 210 may be replaced by a metal gate structure 250 by the operations described in operations 104 to 112, but this disclosure is not limited thereto.

[0039] Figure 7 This is a schematic diagram illustrating a semiconductor structure 20 constructed during a manufacturing stage according to one or more embodiments based on aspects of the present invention. Furthermore, Figure 8A Is along a similar Figure 7 The cross-sectional views illustrating the reference sections AA (n-type region 202N) and BB (p-type region 202P) are shown. Figure 8B Is along a similar Figure 7 The cross-sectional view of reference section CC is shown in the reference diagram. Figure 7 , Figure 8A and Figure 8B According to operation 104, the sacrificial gate layer 209 is removed to form a gate trench 210H exposing the sacrificial dielectric layer 208. In some embodiments, such as Figure 7 As shown, the gate trench 210H further exposes the isolation structure 204. In some embodiments, such as Figure 8B As shown, the fin structure 206 covered by the sacrificial dielectric layer 208 protrudes from the bottom of the gate trench 210H.

[0040] refer to Figure 8B The gate trench 210H may be defined by an insulating structure 214 along the cross section CC. In some embodiments, the gate trench 210H is surrounded by a dielectric structure 230 and spacers 212. In these embodiments, the insulating structure 214 may be either the dielectric structure 230 or the spacers 212. In some embodiments, the dielectric structure 230, the spacers 212, and other structures (i.e., cleaved polysilicon (CPO) structures) may be collectively referred to as the insulating structure 214. In some embodiments, the insulating structure 214 along the cross section CC may serve as a pattern for defining the location and size of the sacrificial gate structure 210. In some embodiments, the insulating structure 214 may comprise a dielectric material.

[0041] In some embodiments, when forming a non-planar device, by Figure 9 , Figure 10A , Figure 10B and Figure 11 The operations described herein are used to introduce, for example, ion implantation 900 (discussed in more detail below) surface treatments into the fin structure 206 beneath the sacrificial dielectric layer 208 (if present), but this disclosure is not limited thereto. In other embodiments, when forming a planar device, by means of a similar Figure 9 , Figure 10A , Figure 10B and Figure 11 The operation described herein is used to introduce, for example, a surface treatment of ion implantation 900 onto the substrate 202 below the sacrificial dielectric layer 208 (if present).

[0042] Figure 9 This is a schematic diagram illustrating a semiconductor structure 20 constructed in a manufacturing stage according to one or more embodiments based on aspects of the present invention. Figure 10A Is along a similar Figure 9 The cross-sectional views illustrating the reference sections AA (n-type region 202N) and BB (p-type region 202P) are shown. Figure 10B Is along a similar Figure 9 The cross-sectional view illustrating the reference section CC in the diagram. Furthermore, Figure 11 This is a top view illustrating a semiconductor structure 20 constructed according to aspects of the present invention in one or more embodiments during the manufacturing stage.

[0043] refer to Figure 9 , Figure 10A and Figure 10BAccording to operation 106, ion implantation 900 is performed on a portion of the fin structure 206 covered by a sacrificial dielectric layer 208 (if present) in the gate trench 210H. In some embodiments, ion implantation 900 may be referred to as a surface treatment, which is performed above the fin structure 206 below the sacrificial dielectric layer 208 (if present) in the gate trench 210H. In some embodiments, ion implantation 900 is performed above the substrate 202 when a planar device is formed. In some embodiments, ion implantation 900 is performed before the sacrificial dielectric layer 208 is removed. In some embodiments, when ion implantation 900 is performed before the sacrificial dielectric layer 208 is removed, the sacrificial dielectric layer 208 is configured as a buffer layer to mitigate the bombardment energy of ion implantation 900. In alternative embodiments, ion implantation 900 may be performed after the sacrificial dielectric layer 208 is removed. In these embodiments, ion implantation 900 may be performed directly on the fin structure 206 or the substrate 202.

[0044] The energy of ion implantation 900 should be low or within a range such that ion implantation 900 does not damage the channel region of fin structure 206 beneath sacrificial dielectric layer 208. In some embodiments, the energy of ion implantation 900 is in the range of about 0.1 keV to about 2 keV. In some embodiments, if the energy of ion implantation 900 is greater than 2 keV, then the dopant of ion implantation 900 can penetrate the channel region of fin structure 206. In these embodiments, fin structure 206 beneath sacrificial dielectric layer 208 will suffer severe damage. Therefore, the device performance of semiconductor structure 20 will be degraded. In some embodiments, if the energy of ion implantation 900 is less than 0.1 keV, then the dopant of ion implantation 900 may not be able to reach fin structure 206 beneath sacrificial dielectric layer 208. In these embodiments, the surface treatment above fin structure 206 may be insufficient to address gate length non-uniformity issues.

[0045] In some embodiments, ion implantation 900 includes a fluorination process or fluoride ion implantation. In some embodiments, the gas source for the fluorination process includes boron fluoride (BF2). In some embodiments, the dosage of boron fluoride ranges from about 5 × 10⁻⁶. 14 ions / cm 2 Up to approximately 5×10 15 ions / cm 2 The energy of boron fluoride is in the range of about 0.1 keV to about 1.5 keV in some embodiments. The operating temperature of boron fluoride is in the range of about 0 degrees Celsius to about 50 degrees Celsius in some embodiments. The operating temperature of boron fluoride is about room temperature in some embodiments. In some embodiments, the gas source for the fluorination process comprises silicon fluoride (SiF3). In some embodiments, the dosage of silicon fluoride ranges from about 1 × 10⁻⁶ keV to about 10⁻⁶ keV.14 ions / cm 2 Up to approximately 2×10 15 ions / cm 2 Within the range of [specific values]. In some embodiments, the energy of silicon fluoride is in the range of about 0.5 keV to about 2 keV. In some embodiments, the operating temperature of silicon fluoride is in the range of about 100 degrees Celsius to about 200 degrees Celsius. In some embodiments, the operating temperature of silicon fluoride is about 150 degrees Celsius.

[0046] Ion implantation 900 can be configured to disrupt the bonds between atoms of fin structure 206. In other words, the dopant of ion implantation 900 can disrupt the bonds between atoms of fin structure 206. For example, the fluorine dopant of ion implantation 900 can disrupt the bonds between silicon atoms of fin structure 206. After the ion implantation 900 treatment, the atoms of fin structure 206 may have dangling bonds. In some embodiments, the dopant from ion implantation 900 can pair with atoms of fin structure 206 having dangling bonds. For example, the fluorine dopant of ion implantation 900 can pair with silicon atoms of fin structure 206 having dangling bonds. A Si-shaped structure can be formed between fin structure 206 and sacrificial dielectric layer 208. x F y The fluorinated silicon compound. In some embodiments, at least a portion of the fin structure 206 is consumed to form the fluorinated silicon compound. In some embodiments, at least a portion of the atoms of the fin structure 206 having dangling bonds are not paired with the dopant from the ion implantation 900. In other embodiments, when forming a planar device, the ion implantation 900 may be configured to disrupt the bonds between the atoms of the substrate 202. In these embodiments, the atoms of the substrate 202 may have dangling bonds after the ion implantation 900 treatment.

[0047] refer to Figure 10A In some embodiments, ion implantation 900 may be configured to form doped regions 206F in the fin structure 206. In some embodiments, a dopant (i.e., a fluorine dopant) introduced by ion implantation 900 forms the doped regions 206F in the fin structure 206. In some embodiments, the concentration of the fluorine dopant in the doped regions 206F of the fin structure 206 may be substantially constant. In some other embodiments, the concentration of the fluorine dopant in the doped regions 206F may vary along the depth direction. For example, the concentration of the fluorine dopant in the doped regions 206F may increase along the depth direction from the upper surface away from the substrate 202 to near the bottom surface of the substrate 202. The concentration of the fluorine dopant in the doped regions 206F may decrease along the depth direction from the upper surface to the bottom surface. In some embodiments, the concentration of the fluorine dopant in the doped regions 206F may vary along the depth direction in a continuous or multi-stage manner.

[0048] In some embodiments, a dopant (i.e., a fluorine dopant) may also be introduced into the spacer 212 during ion implantation 900. In some embodiments, ion implantation 900 may be configured to form the doped spacer 212. In some embodiments, the top portion of the spacer 212 may contain a fluorine dopant after ion implantation 900. In some embodiments, the concentration of the fluorine dopant in the top portion of the spacer 212 may be substantially constant. In some other embodiments, the concentration of the fluorine dopant in the spacer 212 may vary along the depth direction. In some embodiments, the concentration of the fluorine dopant in the top portion of the spacer 212 is greater than the concentration of the fluorine dopant in the sidewall portions of the spacer 212. In some embodiments, the fluorine dopant in the spacer 212 may promote a reduction in the k-value (dielectric constant) of the spacer 212. In some embodiments, the spacer 212 contains a reduced k-value after ion implantation 900. In other words, the doped spacer 212 may have a reduced dielectric constant. In some embodiments, the k-value of the spacer 212 may decrease by about 3% to about 5%. In some embodiments, the concentration of fluorine dopant in spacer 212 is substantially less than the concentration of fluorine dopant in doped region 206F.

[0049] In some embodiments, a dopant may also be introduced into the dielectric structure 230 during ion implantation 900. In some embodiments, the top portion of the dielectric structure 230 may contain a fluorine dopant after ion implantation 900. In some embodiments, ion implantation 900 may be configured to form a doped dielectric structure 230. In some embodiments, the concentration of the fluorine dopant in the top portion of the dielectric structure 230 may be substantially constant. In some other embodiments, the concentration of the fluorine dopant in the dielectric structure 230 may vary along the depth direction. In some embodiments, the concentration of the fluorine dopant in the top portion of the dielectric structure 230 may be substantially the same as the concentration of the fluorine dopant in the top portion of the spacer 212. In some embodiments, the concentration of the fluorine dopant in the top portion of the dielectric structure 230 may be substantially the same as the concentration of the fluorine dopant in the doped region 206F of the fin structure 206.

[0050] Still referencing Figure 10AThe central region 206C of the fin structure 206 and the peripheral region 206A of the fin structure 206 surrounding the central region 206C may undergo varying degrees of ion implantation 900. For example, because the peripheral region 206A of the fin structure 206 is adjacent to the spacer 212, less fluorine dopant can reach the peripheral region 206A of the fin structure 206 due to the masking effect. In contrast, the central region 206C of the fin structure 206 is not masked by the spacer 212, and therefore, the central region 206C of the fin structure 206 may undergo more ion implantation 900. In some embodiments, more silicon fluoride compound may be formed in the central region 206C of the fin structure 206 and less silicon fluoride compound may be formed in the peripheral region 206A of the fin structure 206. In some embodiments, more silicon atoms in the central region 206C of the fin structure 206 are consumed to form silicon fluoride compound, and less silicon atoms in the peripheral region 206A of the fin structure 206 are consumed to form silicon fluoride compound. In some embodiments, since the source / drain (S / D) structure 218 is protected by the dielectric structure 230, the effect of ion implantation 900 on the source / drain (S / D) structure 218 is substantially small.

[0051] refer to Figure 10B The sidewalls and top surface of the fin structure 206 may undergo substantially the same degree of ion implantation 900 because, in the reference cross-section CC, the fin structure 206 is not shielded by the spacer 212 or the insulating structure 214. In other words, an equal number of fluorine dopants may be introduced into the sidewalls and top surface of the fin structure 206. In some embodiments, the amount of silicon fluoride compound formed on the sidewalls of the fin structure 206 may be substantially equal to the amount of silicon fluoride compound formed on the top surface of the fin structure 206. In some embodiments, the number of silicon atoms consumed to form silicon fluoride compound on the sidewalls of the fin structure 206 is substantially the same as the number of silicon atoms consumed to form silicon fluoride compound on the top surface of the fin structure 206. In some other embodiments, the sidewalls and top surface of the fin structure 206 may undergo different degrees of ion implantation 900. In these embodiments, the concentration of fluorine dopants in the top portion of the fin structure 206 may be greater than the concentration of fluorine dopants in the sidewall portion of the fin structure 206. In some embodiments, the concentration of fluorine dopant in the top portion of the fin structure 206 is substantially the same as the concentration of fluorine dopant in the dielectric structure 230. In some embodiments, the concentration of fluorine dopant in the sidewall portion of the fin structure 206 is substantially the same as the concentration of fluorine dopant in the spacer 212.

[0052] In some embodiments, a dopant may also be introduced into the insulating structure 214 during ion implantation 900. In some embodiments, the insulating structure 214 may contain a fluorine dopant after ion implantation 900. In some embodiments, ion implantation 900 may be configured to form a doped insulating structure 214. In some embodiments, the concentration of the fluorine dopant in the insulating structure 214 may be substantially constant. In some other embodiments, the concentration of the fluorine dopant in the insulating structure 214 may vary along the depth direction. In some embodiments, the concentration of the fluorine dopant in the insulating structure 214 may be substantially the same as the concentration of the fluorine dopant in the spacer 212. In some embodiments, the concentration of the fluorine dopant in the sidewall portion of the fin structure 206 is substantially the same as the concentration of the fluorine dopant in the insulating structure 214.

[0053] refer to Figure 11 Ion implantation 900 can have different incident angles, depending on the implementation. For example, ion implantation 900 can be performed on fin structure 206 with the center of fin structure 206 as the origin and with reference to eight compass directions (i.e., 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees). In some embodiments, as shown in region 900A, ion implantation 900 is performed on fin structure 206N(206) from the 0-degree direction and the 180-degree direction. In some embodiments, as shown in region 900B, ion implantation 900 is performed on fin structure 206N(206) from the 90-degree direction and the 270-degree direction. In some embodiments, as shown in region 900C, ion implantation 900 is performed on fin structure 206N(206) from the 45-degree direction, the 135-degree direction, the 225-degree direction, and the 315-degree direction. In some embodiments, as shown in region 900D, ion implantation 900 is performed on the fin structure 206 from the 0-degree direction, the 90-degree direction, the 180-degree direction, and the 270-degree direction.

[0054] Figures 12A to 15B The semiconductor structure 20 in various manufacturing stages according to one or more embodiments based on aspects of the present invention is described. Furthermore, Figure 12A , Figure 13A , Figure 14A and Figure 15A Is along a similar Figure 9 The cross-sectional view of the reference section AA (n-type region 202N) and the reference section BB (p-type region 202P) is shown in the figure. Figure 12B , Figure 13B , Figure 14B and Figure 15B Is along a similar Figure 9 The cross-sectional view of the reference section CC is shown in the figure.

[0055] refer to Figure 12A The sacrificial dielectric layer 208 is removed. In some embodiments, according to operation 108, the sacrificial dielectric layer 208 is removed to expose the fin structure 206 of the substrate 202 from the gate trench 210H. In some embodiments, removing the sacrificial dielectric layer 208 from the fin structure 206 may form a curved upper surface 206U of the fin structure 206. Since ion implantation 900 may form a silicon fluoride compound between the fin structure 206 and the sacrificial dielectric layer 208, the silicon fluoride compound may be removed together with the sacrificial dielectric layer 208 to leave the curved upper surface 206U of the fin structure 206. In other words, the surface treatment of ion implantation 900 may facilitate the formation of the curved upper surface 206U of the fin structure 206. The curved upper surface 206U of the fin structure 206 may create a shrinkage space for the material used to subsequently form the metal gate structure. In some embodiments, after the removal of the sacrificial dielectric layer 208, at least a portion of the doped region 206F of the fin structure 206 remains in the fin structure 206. In some embodiments, after the sacrificial dielectric layer 208 is removed, at least a portion of the sacrificial dielectric layer 208 remains at the corner formed between the sidewall surface of the fin structure 206, the sidewall surface of the spacer 212, and the upper surface of the isolation structure 204.

[0056] refer to Figure 12B Removing the sacrificial dielectric layer 208 can form a shrinking fin structure 206. For example, since the ion implantation 900 can form a silicon fluoride compound on the sidewalls and top surface of the fin structure 206, the silicon fluoride compound can be removed together with the sacrificial dielectric layer 208 to leave the shrinking fin structure 206.

[0057] refer to Figure 13A According to operation 110, an interface layer (IL) 240 is formed over the fin structure 206 of the substrate 202 in the gate trench 210H. In some embodiments, the IL 240 covers a portion of the fin structure 206 in the gate trench 210H. In some embodiments, the IL 240 may only cover the fin structure 206, while the spacer 212 or dielectric structure 230 is not covered by the IL 240. In some embodiments, the IL 240 is conformally formed over the fin structure 206. Therefore, the IL 240 may have a curved top surface similar in shape to the curved upper surface 206U of the fin structure 206. Reference Figure 13B IL 240 can cover the top surface and sidewalls of fin structure 206.

[0058] In some embodiments, IL 240 is formed by chemical oxidation. In some embodiments, IL 240 is formed by wet oxidation. IL 240 can be formed by forcing an oxidant to diffuse into and react with the fin structure 206. In some embodiments, IL 240 incorporates silicon consumed from the fin structure 206 and oxygen supplied from the environment or an oxidant. In some embodiments, IL 240 grows downward into and upward out of the fin structure 206. IL 240 may comprise an oxide-containing material such as SiO or SiON. In some embodiments, IL 240 is formed by pairing silicon atoms of the fin structure 206, which has dangling bonds, with oxygen atoms. Examples of oxidants may be (e.g., but not limited to) H3PO4, NH4OH, HCl, H2O2, and / or O3.

[0059] In some other embodiments, IL 240 may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar methods. IL 240 may be formed from an oxide-containing material such as silicon oxide, but is not limited thereto. In these embodiments, IL 240 may be formed to cover the fin structure 206, spacers 212, dielectric structure 230, and insulating structure 214. In some embodiments, IL 240 is conformally formed over the fin structure 206, spacers 212, dielectric structure 230, and insulating structure 214. The presence of IL 240 over the fin structure 206, spacers 212, dielectric structure 230, and insulating structure 214 can create shrinkage space for the material used to subsequently form the metal gate structure. For example, because IL 240 is formed over the sidewalls of spacers 212, the space between spacers 212 over the fin structure 206 is reduced. Furthermore, the space between spacers 212 over the isolation structure 204 is also reduced. Therefore, the subsequently formed metal gate structure may have a small base or may have essentially no base above the fin structure 206. Furthermore, the subsequently formed metal gate structure may have a small base or may have essentially no base above the isolation structure 204.

[0060] In some embodiments, when at least a portion of the sacrificial dielectric layer 208 remains at the corner between the sidewall surface of the fin structure 206, the sidewall surface of the spacer 212, and the upper surface of the isolation structure 204, the IL 240 may also be formed above a portion of the sacrificial dielectric layer 208. Therefore, a portion of the sacrificial dielectric layer 208 can be inserted between the fin structure 206, the spacer 212, the isolation structure 204, and the IL 240.

[0061] In some embodiments, such as Figure 13AAs shown, the thickness 240T of IL 240 can be consistently measured along a direction substantially perpendicular to the upper surface 202T of substrate 202. In some embodiments, the thickness of IL 240 can range from about 10.5 angstroms to about 11.5 angstroms. In some comparative embodiments, when operation 106 is omitted, the thickness of IL can be about 10 angstroms. Ion implantation 900 can promote the formation of dangling bonds in fin structure 206. Therefore, the thickness of IL 240 in this embodiment can be increased compared to the comparative embodiments due to the increase in dangling bonds in fin structure 206 by performing ion implantation 900.

[0062] In some embodiments, the curved upper surface of IL 240 can create a shrinkage space for the material used to form the metal gate structure 250. Therefore, the subsequently formed metal gate structure 250 can have smaller feet or may have essentially no feet. Thus, the method 10 for forming the semiconductor structure 20 alleviates the gate length non-uniformity problem and improves the device performance of the semiconductor structure 20.

[0063] In some embodiments, according to operation 112, a metal gate structure 250 is formed above IL 240 in the gate trench 210H. In some embodiments, the metal gate structure 250 is composed of... Figure 14A , Figure 14B , Figure 15A and Figure 15B The operations described herein are formed, but this disclosure is not limited thereto. The metal gate structure 250 may have a metal gate structure 250N disposed in the n-type region 202N and a metal gate structure 250P disposed in the p-type region 202P.

[0064] refer to Figure 14A and Figure 14B The metal gate structure 250 further includes a gate dielectric layer 252 formed over the IL240 in the gate trench 210H. In some embodiments, the gate dielectric layer 252 may comprise a single-layer structure or a multi-layer structure. For example, the gate dielectric layer 252 may be... Figure 14A and Figure 14BThe double-layer structure shown is not limited thereto. In some embodiments, the double-layer gate dielectric layer 252 may include a first high-k dielectric layer 252a and a second high-k dielectric layer 252b. The first high-k dielectric layer 252a and the second high-k dielectric layer 252b may contain a high-k dielectric material having a high dielectric constant (for example, greater than that of thermally oxidized silicon, approximately 3.9). The high-k dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), hafnium oxynitride (HfOxNy), other suitable metal oxides, or combinations thereof. The first high-k dielectric layer 252a and the second high-k dielectric layer 252b may contain different high-k dielectric materials. For example, the first high-k dielectric layer 252a may comprise hafnium oxide, while the second high-k dielectric layer 252b may comprise aluminum oxide and lanthanum oxide. In some embodiments, the gate dielectric layer 252 is conformally formed over the IL 240. Therefore, the gate dielectric layer 252 may have a curved top surface with a shape similar to the curved top surface of the IL 240. In some embodiments, the thickness of the gate dielectric layer 252 is consistently measured along a direction substantially perpendicular to the upper surface 202T of the substrate 202.

[0065] Still referencing Figure 14A and Figure 14BThe metal gate structure 250 further includes square work function metal layers 254 and 256 on the gate dielectric layer 252 in the gate trench 210H. In some embodiments, after forming the gate dielectric layer 252, the work function metal layer 254 is formed on the gate dielectric layer 252 in the p-type region 202P, and the work function metal layer 256 is formed on the gate dielectric layer in the n-type region 202N. The work function metal layers 254 and 256 may comprise a single-layer structure or a multi-layer structure. For the p-type region 202P, the work function metal layer 254 may comprise a single layer of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, or Co, or a multilayer of two or more of these materials, but is not limited thereto. For the n-type region 202N, the work function metal layer 256 may comprise a single layer of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, or TaSi, or multiple layers of two or more of these materials, but is not limited thereto. In some embodiments, work function metal layers 254 and 256 are sequentially formed over the gate dielectric layer 252 in the p-type region 202P and the n-type region 202N, respectively. In some embodiments, work function metal layers 254 and 256 are simultaneously formed over the gate dielectric layer 252 in the p-type region 202P and the n-type region 202N, respectively. In some embodiments, work function metal layers 254 and 256 are conformally formed over the gate dielectric layer 252. Therefore, work function metal layers 254 and 256 may have curved top surfaces similar in shape to the curved top surface of the gate dielectric layer 252. In some embodiments, the thickness of the work function metal layer 254 is consistently measured along a direction substantially perpendicular to the upper surface 202T of the substrate 202. In some embodiments, the thickness of the work function metal layer 256 is measured consistently along a direction substantially perpendicular to the upper surface 202T of the substrate 202.

[0066] refer to Figure 15A and Figure 15BThe metal gate structure 250 further includes forming a gap-fill metal layer 258 over the work function metal layers 254 and 256 to fill the gate trench 210H. For the p-type region 202P, the gap-fill metal layer 258 is formed on the work function metal layer 254. For the n-type region 202N, the gap-fill metal layer 258 is formed on the work function metal layer 256. The gap-fill metal layer 258 comprises any acceptable material with low resistance. For example, the gap-fill metal layer 258 may be formed from metals such as Ru, Co, Al, Cu, AlCu, W, combinations thereof, or similar materials, but is not limited to these materials. The gap-fill metal layer 258 may be deposited by ALD, CVD, PVD, or similar methods. In some embodiments, the gap-fill metal layer 258 is deposited by a non-conformal process. For example, the gap-fill metal layer 258 is deposited in a gap-fill manner. The gap-fill metal layer 258 may completely fill the remaining portion of the gate trench 210H. Since the work function metal layers 254 and 256 have curved top surfaces, the gap filling metal layer 258 can have curved bottom surfaces.

[0067] In some embodiments, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric layer 252, work function metal layers 254, 256, and gap-fill metal layer 258, which are located above the top surface of the dielectric structure 230. After the planarization process is completed, the top surfaces of the gate dielectric layer 252, work function metal layers 254, 256, gap-fill metal layer 258, dielectric structure 230, and spacer 212 are coplanar (within process variations). For the p-type region 202P, the remaining portions of the gate dielectric layer 252, work function metal layer 254, and gap-fill metal layer 258 in the gate trench 210H form a metal gate structure 250P. For the n-type region 202N, the remaining portions of the gate dielectric layer 252, work function metal layer 256, and gap-fill metal layer 258 in the gate trench 210H form a metal gate structure 250N. In the following description, metal gate structure 250P and metal gate structure 250N can be collectively referred to as metal gate structure 250.

[0068] In some embodiments, the thickness 258T of the gap-filling metal layer 258, measured along a direction D3 substantially parallel to the upper surface 202T of the substrate 202, varies along a direction D4 substantially perpendicular to the upper surface 202T of the substrate 202. Alternatively, direction D3 may be parallel to a first direction D1. In some embodiments, the gap-filling metal layer 258 has a central portion 258C and a peripheral portion 258P surrounding the central portion 258C. In some embodiments, viewed in a cross-sectional view across the fin structure 206, the bottom surface of the central portion 258C is lower than the bottom surface of the peripheral portion 258P. In some embodiments, the metal gate structure 250 has a height above the fin structure 206, wherein the height is measured along a direction D4 substantially perpendicular to the upper surface 202T of the substrate 202. In some embodiments, the height of the metal gate structure 250 is in the range of about 10 nanometers to about 20 nanometers.

[0069] Figure 16A and Figure 16B This describes a semiconductor structure 20 constructed during the manufacturing stage according to one or more embodiments based on aspects of the present invention. Furthermore... Figure 16A Is along a similar Figure 9 The cross-sectional view of reference section AA in the diagram is described, and Figure 16B Is along a similar Figure 9 The cross-sectional view of the reference section CC is shown in the figure.

[0070] refer to Figure 16A and Figure 16B It should be understood that substrate 202 may include various device regions, such as core logic region 202C and input / output region 202I. These various device regions may contain various devices. For example, core logic region 202C may contain logic devices and input / output region 202I may contain I / O FET devices. It should also be understood that different devices may require different components. In some embodiments, when I / O FET devices are required, the sacrificial dielectric layer 208 may act as an interface layer (IL). In other words, the sacrificial dielectric layer 208 is removed in a first region of substrate 202 (e.g., core logic region 202C) and retained in a second region of substrate 202 (e.g., input / output region 202I). The illustrated gate replacement process may be performed in the first region of substrate 202 (e.g., core logic region 202C), and another gate replacement process may be performed in the second region of substrate 202 (e.g., input / output region 202I) in which the sacrificial dielectric layer 208 is not removed.

[0071] In some embodiments, such as Figure 16AAs shown, the IL 240 in the core logic region 202C has a concave profile. In some embodiments, the concave profile of the IL 240 may define an upper boundary 240U below the upper surface of the fin structure 206 (or substrate 202). In some embodiments, the interface layer (i.e., the sacrificial dielectric layer 208) in the input / output region 202I has an upper boundary 208U above the upper surface of the fin structure 206 (or substrate 202). In some embodiments, the thickness of the interface layer (i.e., the sacrificial dielectric layer 208) in the input / output region 202I is greater than the thickness of the IL 240 in the core logic region 202C.

[0072] In this disclosure, a method for forming a semiconductor structure includes introducing a surface treatment onto a fin structure beneath a sacrificial dielectric layer. The surface treatment can facilitate the formation of dangling bonds in the fin structure (or substrate). In some embodiments, the thickness of the interface layer formed above the fin structure may be increased compared to comparative embodiments where no surface treatment is involved. The increased thickness of the interface layer is attributed to the increased dangling bonds in the fin structure (or substrate). The surface treatment can also facilitate the formation of a curved upper surface of the fin structure. The curved upper surface of the fin structure can create a shrinkage space for the material used to form a metal gate. Therefore, the metal gate formed thereon may have a smaller base or may have substantially no base. Furthermore, the metal gate formed thereon may have a shorter gate length. Therefore, the device performance of the semiconductor structure can be improved.

[0073] In some embodiments, a method includes: receiving a substrate, the substrate including a sacrificial gate structure disposed thereon, wherein the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer; removing the sacrificial gate layer to form a gate trench exposing the sacrificial dielectric layer; performing ion implantation on a portion of the substrate covered by the sacrificial dielectric layer in the gate trench; removing the sacrificial dielectric layer to expose the substrate from the gate trench; forming an interface layer over the substrate in the gate trench; and forming a metal gate structure over the interface layer in the gate trench.

[0074] In some embodiments, a method includes: receiving a semiconductor structure including a sacrificial gate structure extending across a fin structure and disposed between a pair of spacers, wherein the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer; removing the sacrificial gate layer to expose the sacrificial dielectric layer between the pair of spacers; introducing a plurality of dopants to form doped regions in the fin structure and a pair of doped spacers; removing the sacrificial dielectric layer and a first portion of the fin structure from a second portion of the fin structure; forming an interface layer over the second portion of the fin structure between the pair of doped spacers; and forming a metal gate structure over the interface layer between the pair of doped spacers.

[0075] In some embodiments, a semiconductor structure includes: a semiconductor substrate having a fin-like structure; an interface layer having a concave profile located above the semiconductor substrate; and a metal gate structure located above the interface layer, the metal gate structure including a gate dielectric layer, a work function metal layer, and a gap-filling metal layer, wherein the thickness of the gap-filling metal layer, measured along a first direction substantially parallel to the upper surface of the semiconductor substrate, varies along a second direction substantially perpendicular to the upper surface of the semiconductor substrate.

[0076] The foregoing has outlined the structures of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions should not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

[0077] Symbol Explanation

[0078] 10: Method

[0079] 20: Semiconductor Structure

[0080] 102: Operation

[0081] 104: Operation

[0082] 106: Operation

[0083] 108: Operation

[0084] 110: Operation

[0085] 112: Operation

[0086] 202: Substrate

[0087] 202C: Core Logic Area

[0088] 202I: Input / Output Area

[0089] 202N: n-type region

[0090] 202P: p-type region

[0091] 202T: Upper surface

[0092] 204: Isolation Structure

[0093] 206: Fin-like structure

[0094] 206A: Outer Area

[0095] 206C: Central Area

[0096] 206F: Doped region

[0097] 206N: Fin-like structure

[0098] 206P: Fin-like structure

[0099] 206U: Curved upper surface

[0100] 208: Sacrificial dielectric layer

[0101] 208U: Upper Boundary

[0102] 209: Sacrificial gate layer

[0103] 210: Sacrificial gate structure

[0104] 210H: Gate trench

[0105] 212: Spacer

[0106] 212O: Opening

[0107] 213: Patterned Hard Mask

[0108] 213a: First patterning layer

[0109] 213b: Second Patterning Layer

[0110] 214: Insulation Structure

[0111] 218: Source / Drain (S / D) Structure

[0112] 220: Dielectric material layer

[0113] 222: Contact Etching Stop Layer (CESL)

[0114] 230: Dielectric Structure

[0115] 240: Interface Layer (IL)

[0116] 240T: Thickness

[0117] 240U: Upper Boundary

[0118] 250: Metal gate structure

[0119] 250N: Metal gate structure

[0120] 250P: Metal gate structure

[0121] 252: Gate dielectric layer

[0122] 252a: First high-k dielectric layer

[0123] 252b: Second high-k dielectric layer

[0124] 254: Work function metal layer

[0125] 256: Work function metal layer

[0126] 258: Gap-filling metal layer

[0127] 258C: Central section

[0128] 258P: Peripheral Section

[0129] 258T: Thickness

[0130] 900: Ion Implantation

[0131] 900A: Area

[0132] 900B: Area

[0133] 900C: Area

[0134] 900D: Area

[0135] D1: First Direction

[0136] D2: Second Direction

[0137] D3: direction

[0138] D4: Direction.

Claims

1. A method comprising: A receiving substrate, the substrate including a sacrificial gate structure disposed thereon, wherein the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer; Remove the sacrificial gate layer to form a gate trench that exposes the sacrificial dielectric layer; Ion implantation is performed on a portion of the substrate covered by the sacrificial dielectric layer in the gate trench; The sacrificial dielectric layer is removed to expose the substrate from the gate trench, thereby forming a curved top surface of the substrate; An interface layer is formed over the substrate in the gate trench; and A metal gate structure is formed above the interface layer in the gate trench.

2. The method of claim 1, wherein the ion implantation comprises a fluorination process.

3. The method according to claim 2, wherein the gas source for the fluorination process comprises boron fluoride (BF2) and silicon fluoride (SiF3).

4. The method according to claim 3, wherein the dosage range of said boron fluoride (BF2) is from 5 × 10⁻⁶. 14 ions / cm 2 Up to 5×10 15 ions / cm 2 Within the range.

5. The method of claim 3, wherein the dosage of the silicon fluoride (SiF3) ranges from 1 × 10⁻⁶. 14 ions / cm 2 Up to 2×10 15 ions / cm 2 Within the range.

6. The method of claim 1, wherein the energy of the ion implantation is in the range of 0.1 keV to 2 keV.

7. The method of claim 1, wherein the ion implantation comprises a fluorination process that forms a silicon fluoride compound, wherein a portion of the substrate is consumed to form the silicon fluoride compound and the silicon fluoride compound, together with the sacrificial dielectric layer, is removed to expose the substrate from the gate trench.

8. The method of claim 1, wherein the interface layer is formed conformally over the curved top surface of the substrate.

9. The method of claim 1, wherein forming the metal gate structure further comprises: A gate dielectric layer is formed above the interface layer in the gate trench; A square functional metal layer on the gate dielectric layer in the gate trench; and A gap-filling metal layer is formed above the work function metal layer to fill the gate trench.

10. The method of claim 9, wherein the gate dielectric layer and the work function metal layer are formed conformally over the interface layer.

11. A method comprising: A receiving semiconductor structure, the semiconductor structure including a sacrificial gate structure that crosses a fin structure and is placed between a pair of spacers, wherein the sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer; Remove the sacrificial gate layer to expose the sacrificial dielectric layer between the pair of spacers; Multiple dopants are introduced to form the doped regions and a pair of doped spacers in the fin structure; Remove the sacrificial dielectric layer and the first portion of the fin structure from the second portion of the fin structure, wherein the second portion of the fin structure has a curved top surface; An interface layer is formed over the second portion of the fin structure between the pair of doped spacers; and A metal gate structure is formed over the interface layer between the pair of doped spacers.

12. The method of claim 11, wherein the plurality of dopants comprises fluorine.

13. The method of claim 11, wherein at least a portion of the doped region in the fin structure is removed along with the removal of the sacrificial dielectric layer and the first portion of the fin structure.

14. The method of claim 11, wherein the interface layer is formed conformally over the second portion of the fin structure.

15. The method of claim 11, wherein the pair of doped spacers have a reduced dielectric constant.

16. The method of claim 11, wherein the concentration of the plurality of dopants in the pair of doped spacers is substantially less than the concentration of the plurality of dopants in the doped region.

17. A semiconductor structure comprising: A semiconductor substrate having a fin-like structure, wherein the fin-like structure has a curved top surface; An interface layer, located above the semiconductor substrate, has a concave profile; and A metal gate structure located above the interface layer, the metal gate structure including a gate dielectric layer, a work function metal layer and a gap-filling metal layer, wherein the thickness of the gap-filling metal layer, measured along a first direction substantially parallel to the upper surface of the semiconductor substrate, varies along a second direction substantially perpendicular to the upper surface of the semiconductor substrate.

18. The semiconductor structure of claim 17, wherein the gap-filling metal layer has a central portion and a peripheral portion surrounding the central portion, and, viewed in a cross-sectional view across the fin structure, the bottom surface of the central portion is lower than the bottom surface of the peripheral portion.

19. The semiconductor structure of claim 17, wherein the thickness of the interface layer is measured consistently along the second direction.

20. The semiconductor structure of claim 17, wherein the thickness of the work function metal layer is measured consistently along the second direction.

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