Semiconductor device and method of forming the same

Abstract

In an embodiment, the semiconductor device includes: an isolation region on a substrate; a fin structure projecting from adjacent portions of the isolation region, the fin structure including a plurality of fins and mesas, a channel region of the fin structure having a first portion located in the fins and a second portion located in the mesas, the fins and mesas being of continuous semiconductor material, the mesas having a wider width than the fins; and a first gate structure on the fin structure extending along the first portion of the channel region in the fins and along the second portion of the channel region in the mesas. Embodiments of this application also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements on each material layer.

[0003] The semiconductor industry continuously improves the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device including: an isolation region located on a substrate; a fin structure protruding from adjacent portions of the isolation region, the fin structure including a plurality of fins and mesas, a channel region of the fin structure having a first portion located in the fins and a second portion located in the mesas, the fins and mesas being of a continuous semiconductor material, the mesas having a wider width than the fins; and a first gate structure located on the fin structure, the first gate structure extending along the first portion of the channel region in the fins and along the second portion of the channel region in the mesas.

[0005] Other embodiments of this application provide a semiconductor device including: a fin structure extending from a substrate, the fin structure including a continuous semiconductor material including a plurality of fins and mesas, the fins being connected to the mesas; and a transistor including: a source region located in the fin; a drain region located in the mesas; and a first gate structure located between the drain region and the source region, the first gate structure extending along the region of the fin structure where the fins are connected to the mesas.

[0006] Further embodiments of this application provide a method for forming a semiconductor device, comprising: patterning a semiconductor substrate to form a fin structure extending from the semiconductor substrate, the fin structure including a fin portion and a mesa portion, each of the fin portion and the mesa portion extending in a first direction in a top-down view; forming a source region and a drain region in the fin structure, the source region being disposed in the fin portion of the fin structure and the drain region being disposed in the mesa portion of the fin structure; and forming a first gate structure between the source region and the drain region, the first gate structure being disposed on a region of the fin structure where the fin portion connects to the mesa portion, the first gate structure extending in a second direction in a top-down view, the second direction being perpendicular to the first direction. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a FinFET is shown in a three-dimensional view according to some embodiments.

[0009] Figures 2A to 15D This is a view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 16 This is a view of a FinFET according to some embodiments.

[0011] Figures 17A to 17C This is a view of a FET according to some embodiments.

[0012] Figures 18A to 20D This is a view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0013] Figure 21 This is a view of a FinFET according to some embodiments.

[0014] Figure 22A , Figure 22B and Figure 22C These are various 3D diagrams and cross-sectional views of the results of etching steps according to some embodiments.

[0015] Figure 23A , 23B and Figure 23C It is based on some embodiments by Figures 22A to 22C The etching process produces various 3D images and cross-sectional views of the structure. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] According to various embodiments, the FinFET is formed from a fin structure comprising a larger fin (sometimes referred to as a "mesa") and smaller fins. The channel region of the FinFET has portions located within the larger and smaller fins, such that the gate structure of the FinFET extends over the larger and multiple smaller fins. A source region is formed in the smaller fins, and a drain region is formed in the larger fins. Therefore, the drain region of the FinFET can be formed to a larger size, allowing the FinFET to accommodate more hot carrier injection (HCI) in the drain region. This can thus improve the on / off current of the FinFET (e.g., I0). ON / I OFF Therefore, FinFETs are better suited for high-power applications, such as devices and vehicles.

[0019] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is shown. Some components of the FinFET (discussed below) are omitted for clarity. The FinFET can be electrically connected in a manner that operates as one transistor or multiple transistors. The FinFET includes a fin structure 62 extending from a substrate 50. The fin structure 62 includes a channel region for the FinFET. Isolation regions 66, such as shallow trench isolation (STI) regions, are disposed above the substrate 50 and between adjacent fin structures 62, protruding above and between adjacent isolation regions 66. Although the isolation regions 66 are described / shown as separate from the substrate 50, as used herein, the term "substrate" can be used alone to refer to the substrate 50 or a combination of the substrate 50 and the isolation regions 66. Additionally, the bottom of the fin structure 62 is shown as a single continuous material with the substrate 50, and the bottom of the fin structure 62 and / or the substrate 50 may comprise a single material or multiple materials. In this case, the fin structure 62 refers to the portion extending between adjacent isolation regions 66.

[0020] Gate structure 100 is located along the sidewall of fin structure 62 and above the top surface of fin structure 62. Gate structure 100 includes a gate dielectric 112 located on the sidewall and top surface of fin structure 62, and a gate electrode 114 located on the gate dielectric 112. Source / drain regions 98 are disposed on opposite sides of fin structure 62 relative to gate dielectric 112 and gate electrode 114. In embodiments forming multiple transistors, source / drain regions 98 may be shared among the individual transistors. In embodiments where a transistor is formed by multiple fin structures 62, adjacent source / drain regions 98 may be electrically connected, such as by merging source / drain regions 98 through epitaxial growth, or by coupling source / drain regions 98 through the same source / drain contact.

[0021] As will be described in more detail later, fin structure 62 includes fin 62A and fin 62B. Fin 62A has a smaller width than fin 62B. Fin 62B may be referred to as a "mesa". Some FinFETs are formed by multiple fins 62A and fin 62B, with fin 62A connected to fin 62B, and those FinFETs have a gate structure 100 extending along the portion of fin structure 62 in which fin 62A is connected to fin 62B. These FinFETs include gate structure 100, a source / drain region 98A in fin 62A (which may be coupled to serve as a source region), and a source / drain region 98B in fin 62B (which may be coupled to serve as a drain region).

[0022] Figure 1Several reference cross sections are also shown. Cross sections B / CB / C are along the longitudinal axis of the gate electrode 114 and, for example, perpendicular to the direction of current flow between the source / drain regions 98 of the FinFET. Cross section DD is perpendicular to cross section B / CB / C and along the longitudinal axis of the fin structure 62, and, for example, in the direction of current flow between the source / drain regions 98 of the FinFET. Cross sections E / FE / F are parallel to cross sections B / CB / C and extend through the source / drain regions 98 of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0023] Some embodiments described herein are described in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Moreover, some embodiments consider various aspects used in planar devices, such as planar FETs, nanostructured (e.g., nanosheets, nanowires, all-around gate, etc.) field-effect transistors (NSFETs), etc.

[0024] Figures 2A-15D This is a view of an intermediate stage in the manufacturing of FinFETs according to some embodiments. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15A It is a top-down view. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B and Figure 15B This is a cross-sectional view shown along the reference section BB in the corresponding "A" diagram, which is similar to... Figure 1 Reference sections B / CB / C are shown in the figure. Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C and Figure 15C This is a cross-sectional view shown along the reference section CC in the corresponding "A" diagram, which is similar to... Figure 1 Reference sections B / CB / C are shown in the figure. Figure 8D , Figure 9D , Figure 9G , Figure 9H , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D and Figure 15D This is a cross-sectional view shown along the reference section DD in the corresponding "A" diagram, which is similar to... Figure 1 The reference section DD in the diagram. Figure 9E and Figure 9F along Figure 1 The reference sections E / FE / F are shown in the figure.

[0025] FinFETs can be several types of devices. Figures 2A-15D An embodiment of a FinFET is shown as a device for low-power applications, such as a complementary metal-oxide-semiconductor (CMOS) device, where each FinFET has a single gate structure. In another embodiment (described in more detail below), a FinFET is a device for high-power applications, such as a double-diffused metal-oxide-semiconductor (DMOS) device or a laterally diffused metal-oxide-semiconductor (LDMOS) device, where the FinFET may have multiple gate structures.

[0026] exist Figures 2A-2C A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide or combinations thereof.

[0027] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an N-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a P-type FinFET. Although they are not shown separately, the n-type region 50N can be physically separated from the p-type region 50P, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. The structure shown can be applied to both the n-type region 50N and the p-type region 50P. Differences in the structure of the n-type region 50N and the p-type region 50P, if any, are described in each of the subsequent figures herein. Furthermore, any number of n-type regions 50N and p-type regions 50P can be provided.

[0028] A more detailed description will follow. Figures 3A-5C The process for forming fin structures 62 in substrate 50 is shown. Each fin structure 62 includes fin 62A and fin 62B, wherein fin 62A is connected to fin 62B. To form the fin structure 62, a first mask 52 is formed having a pattern of fin 62A (see...). Figures 3A-3C ), and form a second mask 56 with a pattern of fin 62B (see Figures 4A-4C In the illustrated embodiment, the first mask 52 is formed with multiple patterning processes, and the second mask 56 is formed with a single patterning process, such that the components of the second mask 56 are larger than the components of the first mask 52. The masks 52 and 56 are then used as a combined etching mask to pattern the fin structure 62 in the substrate 50 (see...). Figures 5A-5C ), so as to form fins 62A and 62B at the same time.

[0029] Although a single fin structure 62 with a single fin 62B is shown, it should be understood that multiple fin structures 62 can be formed, and a fin structure 62 may have multiple fins 62B. The fin structure 62 can be formed simultaneously with other structures. For example, the fin structure 62 can be patterned using the same etching steps used to pattern other structures (e.g., semiconductor strips) in the substrate 50.

[0030] exist Figures 3A-3C In this process, a first mask 52 is formed on a substrate 50. The first mask 52 can be formed from spacers, photoresists, etc., which have high etch selectivity relative to the etching of the substrate 50. Acceptable spacer materials include dielectric materials such as silicon nitride, aluminum oxide, aluminum nitride, tantalum nitride, titanium nitride, titanium oxide, etc., and combinations thereof, which can be formed using deposition processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). Acceptable photoresists include single-layer photoresists, double-layer photoresists, triple-layer photoresists, etc., which can be formed using spin coating techniques, etc.

[0031] In the illustrated embodiment, the first mask 52 includes spacers 54 formed using multiple photolithography processes, including multi-patterning processes such as dual-patterning processes. Typically, multi-patterning processes combine photolithography and self-alignment processes to allow the production of patterns with distances, for example, smaller than those otherwise obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate 50 and patterned using photolithography to form a mandrel (not shown separately). The sacrificial layer can be formed of a material with high etch selectivity relative to the etching of the substrate 50, such as amorphous silicon, polycrystalline silicon, silicon nitride, silicon oxide, etc., or combinations thereof, and can be formed using processes such as CVD, plasma-enhanced chemical vapor deposition (PECVD), etc. The sacrificial layer can be patterned using an acceptable etching process to form the mandrel. The etching can be anisotropic. In some embodiments, the etching is selective for the sacrificial layer, for example, selectively etching the material of the sacrificial layer at a faster rate than the material of the substrate 50. The spacers 54 are then formed alongside the mandrel using a self-alignment process. For example, in one embodiment, a spacer layer is formed over the mandrel. The spacer layer can be formed from any of the spacer materials discussed previously. The spacer layer can be patterned by an acceptable etching process to form spacers 54 next to the mandrel. The etching can be anisotropic. In some embodiments, the etching is selective to the spacer layer, for example, selectively etching the material of the spacer layer faster than the materials of the mandrel and substrate 50. The mandrel is then removed, leaving the spacers 54 above the substrate 50.

[0032] exist Figures 4A-4C In this process, a second mask 56 is formed on the substrate 50. The second mask 56 can be formed from a photoresist, spacers, etc., which have high etch selectivity relative to the etching of the substrate 50. Acceptable photoresists include single-layer photoresists, double-layer photoresists, triple-layer photoresists, etc., which can be formed by spin coating techniques, etc. Acceptable spacer materials include dielectric materials such as silicon nitride, aluminum oxide, aluminum nitride, tantalum nitride, titanium nitride, titanium oxide, etc., combinations thereof, which can be formed using deposition methods such as ALD, CVD, etc.

[0033] In the illustrated embodiment, the second mask 56 includes a photoresist 58 formed using a photolithography process, which includes a single-patterning process. Typically, a single-patterning process uses photolithography without combining it with a self-aligned process, thereby allowing patterning to be produced with fewer processing steps. The photoresist 58 can be formed from any of the photoresists discussed previously and can be patterned using acceptable photolithography techniques. The components of the second mask 56 are larger than those of the first mask 52.

[0034] The second mask 56 is formed above the first mask 52, such that portions of the first mask 52 and the second mask 56 overlap. Therefore, the components patterned in the substrate 50 using masks 52 and 56 will be continuous semiconductor material. Furthermore, the components of the first mask 52 and the second mask 56 extend in the same direction; for example, the components have parallel longitudinal axes.

[0035] exist Figures 5A-5C In this embodiment, masks 52 and 56 serve as combined etching masks to etch trenches in substrate 50, thereby patterning substrate 50 to form fin structures 62. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. The trenches patterned in substrate 50 can have different depths. For example, due to pattern loading effects, trenches between fins 62A can be shallower than trenches around fins 62B (e.g., trenches between adjacent fin structures 62). In the illustrated embodiment, masks 52 and 56 are consumed during the etching process or removed after the etching process but before subsequent processing. In another embodiment, masks 52 and 56 remain on the fin structures 62.

[0036] The width W1 of fin 62A is defined by the dimensions of the components of the first mask 52, and the width W2 of fin 62B is defined by the dimensions of the components of the second mask 56. Width W2 is greater than width W1. For example, width W1 can range from about 27 nm to about 35 nm, and width W2 can range from about 75 nm to about 115 nm. Fins 62A and 62B can be tapered, such that their widths W1 and W2 decrease in the direction extending away from the top surface of the substrate 50. In such an embodiment, the widths W1 of fin 62A and W2 of fin 62B refer to the width of the narrowest portion of fins 62A and 62B (sometimes referred to as the critical dimensions of fins 62A and 62B).

[0037] The width W2 of fin 62B is determined by the number and width W1 of fins 62A during the FinFET design process, wherein more fins 62A or a larger width W1 of fins 62A results in a larger width W2 of fin 62B. In the illustrated embodiment, fin structure 62 includes five fins 62A. In another embodiment, fin structure 62 may include any number of fins 62A ranging from about four to about eighty fins 62A. The width W2 is greater than the product of the width W1 and the number of fins 62A.

[0038] The total length of the fin structure 62 is determined by the width W2 of the fin 62B. Specifically, the fin structure 62 with a larger width W2 has a larger length. For example, the length of the fin structure 62 is in the range of about 154 nm to about 100,000 nm.

[0039] The previously described process is merely one example of how the fin structure 62 can be patterned. In some embodiments, next-generation lithography techniques such as extreme ultraviolet (EUV) lithography, deep ultraviolet (DUV) lithography, X-ray lithography, soft X-ray (SX) lithography, ion beam projection lithography, electron beam projection lithography, etc., are used to pattern the fin structure 62. The use of next-generation lithography techniques allows the fin structure 62 to be patterned by a single patterning lithography process, avoiding the use of multiple patterning lithography processes.

[0040] exist Figures 6A-6C In this structure, an STI region 66 is formed above the substrate 50 and between adjacent fins 62A and 62B. The STI region 66 is disposed around the lower portion of the fin structure 62, such that the upper portion of the fin structure 62 (e.g., fins 62A and 62B) protrudes between adjacent STI regions 66. In other words, the upper portion of the fin structure 62 extends above the top surface of the STI region 66. The STI region 66 separates components of adjacent devices.

[0041] The STI regions 66 can be formed by any suitable method. For example, an insulating material can be formed over the substrate 50 and between adjacent fins 62A, 62B. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or combinations thereof, and can be formed by a CVD process, such as high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed by any acceptable method can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In embodiments, the insulating material is formed such that excess insulating material covers the fin structure 62. Although each STI region 66 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50 and the fin structure 62. Subsequently, a filler material, such as those described above, can be formed over the liner.

[0042] A removal process is then applied to the insulating material to remove excess insulating material above the fin structure 62. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, or a combination thereof, may be utilized. The planarization process exposes the fin structure 62 such that, after the planarization process is completed, the top surface of the fin structure 62 and the insulating material are coplanar (within a process variation). In embodiments where the mask remains on the fin structure 62, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surface of the mask or the fin structure 62 is coplanar with the insulating material, respectively (within a process variation). The insulating material is then recessed to form the STI region 66. The insulating material is recessed such that the upper portion of the fin structure 62 protrudes between adjacent portions of the insulating material. In this embodiment, the insulating material is recessed such that the upper portions of fins 62A and fins 62B protrude between adjacent portions of the insulating material. In another embodiment (described in more detail below), the insulating material is selectively recessed (e.g., by masking portions of the insulating material during the recess) such that the upper portion of fin 62A protrudes between adjacent portions of the insulating material, but fin 62B does not protrude between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 66 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 66 can be formed as flat, convex, and / or concave by appropriate etching. The insulating material can be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin structure 62). For example, it can be removed using, for example, an oxide of diluted hydrofluoric acid (DHF).

[0043] As previously described, due to the pattern loading effect, the grooves between fins 62A can be shallower than the grooves between fins 62B / fin structures 62. Therefore, the bottom surface of the STI region 66 between fins 62A is disposed above the bottom surface of the STI region 66 between fins 62B, such that the STI region 66 between fins 62B is deeper by a depth D1 than the STI region 66 between fins 62A. The depth D1 can be in the range of approximately 25 nm to approximately 40 nm. Forming the STI region 66 within this range allows adjacent fin structures 62 to be adequately isolated from each other. Forming the STI region 66 at a depth outside this range may not allow adjacent fin structures 62 to be adequately isolated from each other.

[0044] The previously described method is merely one example of how the fin structure 62 and the STI region 66 can be formed. In some embodiments, the fin structure 62 can be formed using a mask and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be patterned in the dielectric layer to expose the underlying substrate 50. An epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed, causing the epitaxial structure to protrude from the dielectric layer to form the fin structure 62, and the recessed dielectric layer forming the STI region 66. The epitaxial structure can be a heteroepitaxial structure, a homoepitaxial structure, etc. In some embodiments of epitaxial growth of the epitaxial structure, the material for epitaxial growth can be doped in situ during growth, which may avoid prior and / or subsequent implantation, but in-situ and implantation doping can be used together.

[0045] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., the PMOS region) in the n-type region 50N (e.g., the NMOS region). In various embodiments, the upper portion of the fin structure 62 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or nearly pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0046] Furthermore, suitable wells can be formed in fins 62A, 62B and / or substrate 50 (not in Figures 2A-15D (Shown separately). In this embodiment, the well has a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well may be formed in the n-type region 50N, and an n-type well may be formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well may be formed in both the n-type region 50N and the p-type region 50P.

[0047] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask such as photoresist (not shown separately). For example, photoresist can be formed on the fin structure 62 and the STI region 66 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., and its implantation concentration in this region is about 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0048] After or before implantation of the p-type region 50P, a mask, such as photoresist (not shown separately), is formed over the fin structure 62 and STI region 66 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., and their implantation concentration in this region is approximately 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, such as through an acceptable ashing process.

[0049] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which may avoid implantation, but in-situ and implantation doping can be used together.

[0050] exist Figures 7A-7CIn this process, a pseudo-dielectric layer 72 is formed on fins 62A and 62B. The pseudo-dielectric layer 72 can be formed from a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown according to acceptable techniques. A pseudo-gate layer 74 is formed above the pseudo-dielectric layer 72, and a mask layer 76 is formed above the pseudo-gate layer 74. The pseudo-gate layer 74 can be deposited above the pseudo-dielectric layer 72 and then planarized, such as by CMP. The mask layer 76 can be deposited above the pseudo-gate layer 74. The pseudo-gate layer 74 can be formed from a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, metals, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The pseudo-gate layer 74 can be made from a material having high etch selectivity relative to the etching of insulating materials (e.g., STI region 66 and / or pseudo-dielectric layer 72). The mask layer 76 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the STI region 66, thereby extending the dummy dielectric layer 72 over the STI region 66 and between the dummy gate layer 74 and the STI region 66. In another embodiment, the dummy dielectric layer 72 covers only the fins 62A and 62B.

[0051] exist Figures 8A-8D In this process, the mask layer 76 can be patterned using acceptable photolithography and etching techniques to form a mask 86. The pattern of the mask 86 can then be transferred to the dummy gate layer 74 to form dummy gates 84. In some embodiments, the pattern of the mask 86 is also transferred to the dummy dielectric layer 72 using acceptable etching techniques to form a dummy dielectric 82. The dummy gates 84 cover the corresponding channel regions 68 of the fin structure 62. The pattern of the mask 86 can be used to physically separate each dummy gate 84 from its adjacent counterparts. The dummy gates 84 may also have a length direction substantially perpendicular to the length direction of the fins 62A, 62B. The mask 86 can be removed during the patterning of the dummy gates 84, or it can be removed in a subsequent process.

[0052] Each of the dummy gates 84 may extend over one or more fin structures 62 (not in Figures 2A-15D (Shown separately). A first subset 84A of dummy gates extends over fin 62A, a second subset 84B of dummy gates extends over fin 62B, and a third subset 84C of dummy gates extends over fins 62A and fin 62B. Specifically, each dummy gate 84C extends over fin structure 62 along the portion of fin 62A connected to fin 62B. As will be described in more detail later, dummy gates 84A, 84B, and 84C can be used to form devices that operate at different voltages.

[0053] exist Figures 9A-9D In this embodiment, gate spacers 92 are formed on the sidewalls of the dummy gate 84 and the mask 86. Gate spacers 92 can be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric materials. Acceptable dielectric materials include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations such as silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, etc.; multilayers thereof; etc. The dielectric materials can be formed by conformal deposition processes such as CVD, PECVD, ALD, etc. In the illustrated embodiment, each gate spacer 92 includes multiple layers, such as a first spacer layer 92A and a second spacer layer 92B. In some embodiments, the first spacer layer 92A and the second spacer layer 92B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-y (where x and y are in the range of 0 to 1). For example, the first spacer layer 92A may be formed of silicon carbonitride with a composition similar to or different from that of the second spacer layer 92B. Acceptable etching processes, such as dry etching, wet etching, or combinations thereof, may be performed to pattern the dielectric material. The etching may be anisotropic. During etching, the dielectric material has portions remaining on the sidewalls of the dummy gate 84 (thus forming the gate spacer 92). After etching, the gate spacer 92 may have straight sidewalls (as shown) or may have curved sidewalls (not shown). As will be described in more detail later, the dielectric material may also have portions remaining on the sidewalls of the fins 62A, 62B during etching (thus forming fin spacers).

[0054] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation of a well discussed previously, a mask, such as photoresist, can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the exposed fins 62A, 62B in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as photoresist, can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the exposed fins 62A, 62B in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. The LDD region may have an impurity concentration of about 10. 15 cm -3 To about 10 19 cm -3 Within a certain range. Annealing can be used to repair injected damage and reactivate injected impurities.

[0055] It should be noted that previously disclosed information typically describes the processes for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be employed, and additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0056] Then, source / drain regions 98 are formed in fins 62A and 62B. The source / drain regions 98 are formed in fins 62A and 62B such that each dummy gate 84 (and corresponding channel region 68) is positioned between corresponding adjacent pairs of source / drain regions 98. In some embodiments, the source / drain regions 98 may extend to, and may also penetrate, fins 62A and 62B. In some embodiments, gate spacers 92 are used to separate the source / drain regions 98 from the dummy gates 84 by an appropriate lateral distance such that the source / drain regions 98 are not short-circuited with the gate of the subsequently formed FinFET. The material of the source / drain regions 98 may be selected to apply stress in the corresponding channel regions 68, thereby improving performance. In the illustrated embodiment, the source / drain regions 98 are epitaxial regions in the fin structure 62 having a planar upper surface.

[0057] The source / drain regions 98 in the n-type region 50N can be formed by masking the p-type region 50P and etching the source / drain regions of the fins 62A, 62B in the n-type region 50N to form grooves in the fins 62A, 62B. The source / drain regions 98 in the n-type region 50N are then epitaxially grown in the grooves. The source / drain regions 98 can include any acceptable material, such as that suitable for an n-type FinFET. For example, if the fins 62A, 62B are silicon, the source / drain regions 98 in the n-type region 50N can include a material that applies tensile strain to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. As will be described in more detail later, some of the source / drain regions 98 in the n-type region 50N can have surfaces rising from the respective surfaces of the fins 62A, 62B and can have small facets.

[0058] The source / drain regions 98 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain regions of the fins 62A, 62B in the p-type region 50P to form grooves in the fins 62A, 62B. The source / drain regions 98 in the p-type region 50P are then epitaxially grown in the grooves. The source / drain regions 98 can comprise any acceptable material, such as that suitable for a p-type FinFET. For example, if the fins 62A, 62B are silicon, the source / drain regions 98 in the p-type region 50P can comprise a material that applies compressive strain to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. As will be described in more detail later, some of the source / drain regions 98 in the p-type region 50P can have surfaces rising from the corresponding surfaces of the fins 62A, 62B and can have facets.

[0059] The source / drain regions 98 and / or fins 62A, 62B can be implanted with dopants to form source / drain regions, similar to the previously discussed methods for forming LDD regions, followed by annealing. The source / drain regions can have approximately 10 19 cm -3 Peace Treaty 10 21 cm -3 The impurity concentration is within the range specified. The n-type and / or p-type impurities used for the source / drain regions can be any impurities discussed previously. In some embodiments, the source / drain regions 98 can be doped in situ during growth.

[0060] As described above, source / drain regions 98 are formed in fins 62A and 62B, such that each dummy gate 84 (and corresponding channel region 68) is disposed between corresponding adjacent pairs of source / drain regions 98. Figure 9E As shown, a first subset 98A of the source / drain regions is formed in each fin 62A of the fin structure 62. Figure 9F As shown, a second subset 98B of the source / drain regions is formed in the fin 62B of the fin structure 62. Therefore, each dummy gate 84A is located between adjacent source / drain regions 98A, each dummy gate 84B is located between adjacent source / drain regions 98B, and each dummy gate 84C is located between source / drain regions 98A and source / drain regions 98B.

[0061] The source / drain regions 98 have different structures depending on which fin of fins 62A and 62B they are formed in. Due to the epitaxial process used to form the source / drain regions 98A, the upper surface of the source / drain regions 98A has small facets extending laterally outward beyond the sidewalls of fin 62A. In the illustrated embodiment, these facets cause adjacent source / drain regions 98A to merge, such as Figure 9EAs shown. The fin structures 62 are spaced apart from each other such that the source / drain regions 98B remain separated after the epitaxial process is completed. In another embodiment (not shown separately), adjacent source / drain regions 98A also remain separated after the epitaxial process is completed. The spacer etching used to form the gate spacer 92 can be adjusted to form fin spacers 94 on the sidewalls of the fins 62A, 62B. In the illustrated embodiment, the fin spacers 94 cover a portion of the sidewalls of the fins 62A, 62B extending over the STI region 66, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to form the gate spacer 92 is adjusted so as not to form fin spacers 94, allowing the source / drain regions 98 to extend to the surface of the STI region 66.

[0062] When adjacent source / drain regions 98A are merged, source / drain regions 98A may have a non-planar top surface, while source / drain regions 98B have a planar top surface. Specifically, source / drain regions 98A may have a "wavy" top surface. In another embodiment, source / drain regions 98A have a planar top surface without a "wavy" top surface.

[0063] Although the source / drain region 98 is Figure 9D The cross-section has a flat top surface, but the source / drain region 98 can have different shapes in this cross-section. In some embodiments, the source / drain region 98 has a concave top surface, such as... Figure 9G As shown. In some embodiments, the source / drain region 98 has as shown Figure 9H The convex dome surface is shown. For example, the source / drain region 98 can have a concave dome surface in the n-type region 50N and a convex dome surface in the p-type region 50P. A diagram showing the application of... Figure 9D The following steps in the embodiments.

[0064] exist Figures 10A-10D In this process, a first ILD 104 is deposited over the source / drain region 98, the gate spacer 92, and the mask 86 (if present) or dummy gate 84. The first ILD 104 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable method may be used.

[0065] In some embodiments, a CESL 102 is formed between the first ILD 104 and the source / drain region 98, the gate spacer 92 and the mask 86 (if present) or the dummy gate 84. The CESL 102 may include a dielectric material with high etch selectivity relative to the etching of the first ILD 104, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0066] exist Figures 11A-11D In this process, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 104 flush with the top surface of the mask 86 (if present) or the dummy gate 84. This planarization process may also remove the mask 86 over the dummy gate 84, as well as portions of the gate spacer 92 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the mask 86 (if present) or the dummy gate 84, the gate spacer 92, the CESL 102, and the first ILD 104 are coplanar (within a process variation). Therefore, the top surfaces of the mask 86 (if present) or the dummy gate 84, the gate spacer 92, and the CESL 102 are exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 coplanar with the top surface of the mask 86.

[0067] exist Figures 12A-12D In one or more etching steps, the mask 86 (if present) and the dummy gate 84 are removed to form a recess 96. A portion of the dummy dielectric 82 in the recess 96 may also be removed. In some embodiments, only the dummy gate 84 is removed, while the dummy dielectric 82 remains and is exposed through the recess 96. In some embodiments, the dummy dielectric 82 is removed from the recess 96 in a first region of the die (e.g., a core logic region) and remains in the recess 96 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 84 at a rate faster than the first ILD 104 or the gate spacer 92. Each recess 96 exposes and / or covers the channel region 68 of the corresponding fin structure 62. During removal, the dummy dielectric 82 can be used as an etch stop layer while the dummy gate 84 is etched. The dummy dielectric 82 can then be optionally removed after the removal of the dummy gate 84.

[0068] exist Figures 13A-13D In this process, a gate dielectric 112 and a gate electrode 114 are formed to replace the gate. The gate dielectric 112 and the gate electrode 114 can be collectively referred to as the "gate structure". Each gate structure 100 extends along the sidewall of the channel region 68 of the fin structure 62.

[0069] Gate dielectric 112 includes one or more layers deposited in the recess 96, such as on the top surface and sidewalls of fins 62A, 62B and on the sidewalls of gate spacer 92. In some embodiments, gate dielectric 112 includes one or more dielectric layers, such as oxides, metal oxides, metal silicates, etc., or combinations thereof. For example, in some embodiments, gate dielectric 112 includes a silicon oxide interface layer formed by thermal or chemical oxidation and located on a high-k dielectric material, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Gate dielectric 112 may include a dielectric layer with a k value greater than about 7.0. Methods for forming gate dielectric 112 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of dummy dielectric 82 remains in the recess 96, gate dielectric 112 includes the material of dummy dielectric 82 (e.g., silicon oxide).

[0070] Gate electrode 114 is deposited over gate dielectric 112 and fills the remaining portion of recess 96. Gate electrode 114 may comprise a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 114 is shown, gate electrode 114 may comprise any number of pad layers, any number of power function adjustment layers, and filler material. Any combination of layers constituting gate electrode 114 may be deposited on gate dielectric 112 and in recess 96. After filling recess 96, a planarization process, such as CMP, may be performed to remove excess material from gate dielectric 112 and gate electrode 114 above the top surface of first ILD 104. The top surfaces of gate spacer 92, CESL 102, first ILD 104, gate dielectric 112, and gate electrode 114 are therefore coplanar (within process variations). Therefore, the remaining portion of the material of the gate dielectric 112 and the gate electrode 114 forms the replacement gate of the resulting FinFET.

[0071] The formation of the gate dielectric 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric 112 in each region is formed of the same material, and the formation of the gate electrode 114 can occur simultaneously, such that the gate electrode 114 in each region is formed of the same material. In some embodiments, the gate dielectric 112 in each region can be formed by different processes, such that the gate dielectric 112 can be made of different materials, and / or the gate electrode 114 in each region can be formed by different processes, such that the gate electrode 114 can be made of different materials. When different processes are used, the respective masking steps can be used to mask and expose appropriate regions.

[0072] A first subset 100A of the gate structure replaces the dummy gate 84A and extends over the fin 62A. Therefore, the first subset of each FinFET includes the gate structure 100A and a pair of source / drain regions 98A. A second subset 100B of the gate structure replaces the dummy gate 84B and extends over the fin 62B. Therefore, the second subset of each FinFET includes the gate structure 100B and a pair of source / drain regions 98B. A third subset 100C of the gate structure replaces the dummy gate 84C and extends over the fins 62A and 62B. Therefore, the third subset of each FinFET includes the gate structure 100C, the source / drain regions 98A, and the source / drain regions 98B.

[0073] exist Figures 14A-14D In this process, a second ILD 124 is deposited over the gate spacer 92, CESL 102, first ILD 104, gate dielectric 112, and gate electrode 114. In some embodiments, the second ILD 124 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 124 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0074] In some embodiments, an etch stop layer (ESL) 122 is formed between the second ILD 124 and the gate spacer 92, CESL 102, the first ILD 104, the gate dielectric 112, and the gate electrode 114. The ESL 122 may include a dielectric material having high etch selectivity relative to the etching of the second ILD 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0075] exist Figures 15A-15D In this configuration, gate contact 132 and source / drain contact 134 are formed as contact gate electrode 114 and source / drain region 98, respectively. Gate contact 132 is physically and electrically coupled to gate electrode 114. Source / drain contact 134 is physically and electrically coupled to source / drain region 98. In some embodiments, gate contact 132 is laterally offset from fin structure 62, such that gate contact 132 laterally overlaps with STI region 66 but not with fin structure 62.

[0076] As an example of forming the gate contact 132 and the source / drain contact 134, an opening for the gate contact 132 is formed through the second ILD 124 and ESL 122, and an opening for the source / drain contact 134 is formed through the second ILD 124, ESL 122, the first ILD 104, and CESL 102. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown), such as diffusion barrier layers and adhesive layers, and conductive material are formed within the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 124. The remaining pads and conductive material form the gate contact 132 and the source / drain contact 134 within the openings. The gate contact 132 and the source / drain contact 134 can be formed in different processes or in the same process.

[0077] Optionally, a metal-semiconductor alloy region 136 is formed at the interface between the source / drain region 98 and the source / drain contact 134. The metal-semiconductor alloy region 136 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon germanide region formed from both metal silicides and metal germanides. Before depositing the material for the source / drain contact 134, the metal-semiconductor alloy region 136 can be formed by depositing metal in the openings for the source / drain contact 134 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 98 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. After a thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings used for the source / drain contacts 134, such as from the surface of the metal-semiconductor alloy region 136. The material for the source / drain contacts 134 can then be formed on the metal-semiconductor alloy region 136.

[0078] Figure 16 This is a view of a FinFET according to some embodiments. Some components of the FinFET are omitted for clarity. Figure 16 yes Figures 15A-15DThe top-down view of the device more clearly shows how the multiple fin structures 62 are formed and how the fin structures 62 have multiple fins 62B. Specifically, the fin structures 62 may alternate between fins 62A and fins 62B along the length of the fin structures 62. The FinFET 200 is symmetrical along the length of the fin structures 62. Gate structure 100A extends above fins 62A of the multiple fin structures 62. Gate structure 100B extends above fins 62B of the multiple fin structures 62. Gate structure 100C extends above fins 62A and 62B of the multiple fin structures 62.

[0079] Gate structures 100A, 100B, and 100C are used for FinFETs operating at different voltages. Gate structure 100A is used for FinFETs operating in a low voltage range (e.g., from about 0.8 volts to about 3 volts), such as FinFETs used in core logic devices, because the channel region 68 in fin 62A has better gate control capability. Gate structure 100B is used for FinFETs operating in a high voltage range (e.g., from about 3 volts to about 12 volts), such as FinFETs used in input / output devices, because the channel region 68 in fin 62B can be driven to a higher voltage. Gate structure 100C is used for FinFETs operating in a dielectric voltage range (e.g., from about 2.5 volts to about 8 volts), such as FinFETs used in input / output devices where good gate control capability is still required.

[0080] In some embodiments, the FinFET interconnect (e.g., via a metallization layer in the interconnect structure above) allows source / drain region 98A to function as the source region and source / drain region 98B to function as the drain region. In certain types of devices, such as those operating in a dielectric voltage range or a high voltage range, the drain terminal operates at a higher voltage than the source terminal, which can result in poorer hot carrier injection (HCI) at the drain region compared to the source region, thus degrading the performance of such devices. Because the portions of the channel region 68 in the source / drain regions 98B and fin 62B are larger, they can withstand higher voltages than their smaller counterparts (e.g., portions of the channel region 68 in the source / drain regions 98A and fin 62A), thereby reducing hot carrier injection at the drain region. This can thus increase the device's on / off current (e.g., I0). ON / I OFF ).

[0081] The length of the channel region 68 below the gate structure 100 can range from about 86 nm to about 1000 nm, wherein a longer channel length is used for devices with a higher operating voltage. In some embodiments, the length of the channel region 68 below the gate structure 100C is greater than the length of the channel region 68 below the gate structure 100B, and the length of the channel region 68 below the gate structure 100B is greater than the length of the channel region 68 below the gate structure 100A.

[0082] Return to Figure 13A and Figure 13D The channel region 68 beneath the gate structure 100C has portions located in fin 62A and fin 62B. The gate structure 100C overlaps with the portion of the channel region 68 in fin 62A by a distance D2, and with the portion of the channel region 68 in fin 62B by a distance D3. Distances D2 and D3 are determined by the operating voltage of the FinFET, wherein a smaller distance D2 and a larger distance D3 are used for devices with a larger operating voltage. Distance D2 can be approximately 85% to approximately 99% of the length of the channel region 68 beneath the gate structure 100C, and distance D3 can be approximately 1% to approximately 15% of the length of the channel region 68 beneath the gate structure 100C. In an example where the gate structure 100C is part of a FinFET having an operating voltage in the range of about 3 volts to about 5 volts, the length of the channel region 68 below the gate structure 100C can be in the range of about 240 nm to about 500 nm, the distance D2 can be in the range of about 200 nm to about 495 nm, and the distance D3 can be in the range of about 5 nm to about 75 nm. In another example where the gate structure 100C is part of a FinFET having an operating voltage in the range of about 5 volts to about 8 volts, the length of the channel region 68 below the gate structure 100C can be in the range of about 500 nm to about 1000 nm, the distance D2 can be in the range of about 425 nm to about 990 nm, and the distance D3 can be in the range of about 10 nm to about 150 nm. In yet another example where the gate structure 100C is part of a FinFET having an operating voltage in the range of about 8 volts to about 12 volts, the length of the channel region 68 below the gate structure 100C can be greater than about 750 nm, the distance from D2 can be greater than about 625 nm, and the distance from D3 can be greater than about 100 nm.

[0083] Figures 17A-17C This is a view of a FET according to some embodiments. This embodiment is similar to... Figures 15A-15CIn this embodiment, the insulating material of the STI region 66 is recessed only around fin 62A and not around fin 62B. Therefore, fin 62A protrudes between adjacent STI regions 66, but the top surface of fin 62B is coplanar with the top surface of STI region 66. Thus, a first subset of the devices (e.g., devices including gate structure 100A) is a FinFET with gate structure 100 extending along the sidewalls of fins 62A, 62B; a second subset of the devices (e.g., devices including gate structure 100B) is a planar FET, wherein gate structure 100 does not extend along the sidewalls of fins 62A, 62B; and a third subset of the devices (e.g., devices including gate structure 100C) is a hybrid device comprising both a FinFET aspect and a planar FET aspect.

[0084] Figures 18A-20D This is a view of an intermediate stage in the manufacturing of FinFETs according to some embodiments. Figure 18A , Figure 19A and Figure 20A It is a top-down view. Figure 18B , Figure 19B and Figure 20B It is a cross-sectional view shown along the reference section BB in the corresponding "A" diagram, which is similar to... Figure 1 Reference sections B / CB / C are shown in the figure. Figure 18C , Figure 19C and Figure 20C It is a cross-sectional view shown along the reference section CC in the corresponding "A" diagram, which is similar to... Figure 1 Reference sections B / CB / C are shown in the figure. Figure 18D , Figure 19D and Figure 20D It is a cross-sectional view shown along the reference section DD in the corresponding "A" diagram, which is similar to... Figure 1 The reference cross section DD is shown in the figure. In this embodiment, the FinFET is a device for high-power applications, such as a double-diffused metal-oxide-semiconductor (DMOS) device or a laterally diffused metal-oxide-semiconductor (LDMOS) device, wherein each FinFET may have multiple gate structures. Figures 18A-20D FinFETs can be formed in conjunction with Figures 2A-15D The FinFET can be formed on the same substrate 50, or it can be formed on a different substrate 50.

[0085] Figures 18A-18D As shown Figures 9A-9DSimilar intermediate manufacturing stages, for example, after the formation of the dummy gate 84 and source / drain regions 98. In this embodiment, the FinFET is not formed in separate n-type and p-type regions of the substrate 50. Moreover, wells with a plurality of carriers of different conductivity types (e.g., p-type wells and n-type wells) can be formed in the same fin structure 62. Specifically, a well 50W with a plurality of carriers of the first conductivity type is formed in fin 62A. A Furthermore, a trap 50W with a majority of opposite second conductivity types of charge carriers is formed in fin 62B. B Such a trap can be formed using masking and injection steps, in a manner similar to the traps previously described.

[0086] Furthermore, no source / drain regions are formed between all the dummy gates 84. Specifically, source / drain regions are not formed between dummy gates 84C and dummy gates 84B. Therefore, each pair of source / drain regions 98A and 98B is separated by dummy gates 84C and 84B. Gate spacers 92 in the regions where the source / drain regions are omitted are separated by a distance D4, and gate spacers 92 in the regions where the source / drain regions are formed are separated by a distance D5, wherein distance D5 is different from distance D4. Distances D4 and D5 are each in the range of about 118 nm to about 200 nm.

[0087] As described above, the source / drain region 98 can be an epitaxially grown structure, in-situ doped during growth, or it can be a dopant-implanted region of fins 62A and 62B to form the source / drain region 98. In some embodiments, the source / drain region 98 is a non-epitaxial structure, for example, a dopant-implanted region of fins 62A and 62B, which can have a lower carrier concentration, making them more suitable for high-power applications. In such embodiments, the source / drain region 98 is a doped region of a fin structure 62 having a planar upper surface.

[0088] Figures 19A-19D As shown Figures 13A-13D Similar intermediate manufacturing stages, such as after replacing the dummy gate 84 with gate structure 100. In this embodiment, each subset of FinFETs includes multiple gate structures 100 (e.g., gate structure 100C and gate structure 100B), source / drain regions 98A and 98B. Including gate structure 100B together with the FinFET can improve the gate control capability of the FinFET, making them more suitable for high-power applications. No source / drain regions are formed between gate structures 100C and 100B of this FinFET. Multiple gate structures 100 can be used for FinFETs operating over very high voltage ranges (e.g., greater than about 12 volts).

[0089] The gate dielectric 112 of gate structures 100C and 100B can be formed to a thickness determined based on the desired operating voltage and gate control capability of the FinFET. In some embodiments, the gate dielectric 112 of gate structure 100C has a first thickness T1, and the gate dielectric 112 of gate structure 100B has a second thickness T2, wherein the second thickness T2 is different from the first thickness T1. The first thickness T1 and the second thickness T2 each have a thickness of approximately... to approximately Within the range.

[0090] The channel region 68 may have a first portion 68B located below the gate structure 100B and a second portion 68C located below the gate structure 100C. The first portion 68B and the second portion 68C of the channel region 68 may have different lengths. Specifically, the second portion 68C of the channel region 68 may be longer than the first portion 68B of the channel region 68. For example, the second portion 68C of the channel region 68 may have a length in the range of about 500 nm to about 6000 nm, and the first portion 68B of the channel region 68 may have a length in the range of about 86 nm to about 1000 nm. Figures 18A-20D FinFETs are formed in conjunction with Figures 2A-15D When the FinFET is on the same substrate 50 as the FinFET, the gate structure 100 of the FinFET for high-power applications has a larger width than the gate structure 100 of the FinFET for low-power applications.

[0091] Figures 20A-20D As shown Figures 15A-15D This is similar to an intermediate manufacturing stage. In this embodiment, different gate contacts 132 are formed to the gate structure 100 of each FinFET. For example, a first subset 132C of gate contacts is formed to the gate structure 100C, and a second subset 132B of gate contacts is formed to the gate structure 100B. Therefore, the gate structure 100 of each FinFET can be controlled independently.

[0092] In some embodiments, the FinFET is an LDMOS device, wherein the source / drain region 98A (e.g., source region), the source / drain region 98B (e.g., drain region), and the well 50W B It has carriers of the majority of the first conductivity type, and the well is 50W. A Carriers exhibiting a majority of second conductivity types different from the first conductivity type. When the FinFET is an n-type LDMOS device, the source / drain region 98A (e.g., source region), source / drain region 98B (e.g., drain region), and well 50W... B Each n-type region has a 50W well. AIt is a p-type region. An n-type LDMOS device can be operated by coupling the gate contact 132C of the device to a high voltage and coupling the gate contact 132B of the device to a relatively low voltage. When the FinFET is a p-type LDMOS device, the source / drain region 98A (e.g., the source region), the source / drain region 98B (e.g., the drain region), and the well 50W... B Each p-type region has a 50W well. A It is an n-type region. A p-type LDMOS device can be operated by coupling the device's gate contact 132C to a low voltage and coupling the device's gate contact 132B to a relatively high voltage. As described above, because the source / drain regions 98B (e.g., the drain region) and portions of the channel region 68 in the fin 62B are larger, they can withstand higher voltages than their smaller counterparts (e.g., portions of the channel region 68 in the source / drain regions 98A and fin 62A), making them more suitable for high-power applications. In some embodiments, the high and low voltages can be + / - 5 volts (for a total voltage difference of 10 volts), or even + / - 8 volts (for a total voltage difference of 16 volts).

[0093] Figure 21 This is a view of a FinFET according to some embodiments. Some components of the FinFET are omitted for clarity. Figure 21 yes Figures 20A-20D A top-down view of the device more clearly shows how the FinFET 200 has multiple gate structures 100 (e.g., gate structure 100C and gate structure 100B). The FinFET 200 is symmetrical along the length of the fin structure 62. In this embodiment, the FinFET 200 has a single gate structure 100C and a single gate structure 100B. In another embodiment, the FinFET may have another number of gate structures 100B. For example, the FinFET may have a single gate structure 100C and multiple gate structures 100B, such as two gate structures 100B, three gate structures 100B, etc. The number of gate structures 100B can be determined based on the desired operating voltage and gate control capability of the FinFET.

[0094] The implementation can achieve advantages. As previously mentioned, in certain types of devices, such as those operating in a dielectric voltage range or a high voltage range, the drain terminal operates at a higher voltage than the source terminal. This can result in poorer hot carrier injection (HCI) at the drain region than at the source region, thus degrading the performance of such devices. The FinFET includes multiple fins 62A and 62B, with fins 62A connected to fins 62B, and fins 62B being wider than fins 62A. Because the source / drain regions 98B and portions of the channel region 68 in fins 62B are larger, they can withstand higher voltages than their smaller counterparts (e.g., portions of the channel region 68 in source / drain regions 98A and fins 62A), thereby reducing hot carrier injection at the drain region. This can thus increase the device's on / off current (e.g., I0). ON / I OFF Therefore, the resulting FinFET is more suitable for high-power applications, such as devices and vehicles.

[0095] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gates, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by stacks of alternating layers of patterned channel layers and sacrificial layers. A dummy gate structure and source / drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate structure, the sacrificial layer can be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to the embodiments described above, and the replacement gate structure can partially or completely fill the opening left by the removal of the sacrificial layer, and the replacement gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts to the replacement gate structure and source / drain regions can be formed in a manner similar to the embodiments described above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, the entire contents of which are incorporated herein by reference.

[0096] The following example, No. 2016 / 0365414, illustrates the formation of nanostructure devices.

[0097] exist Figure 22A , Figure 22B and Figure 22C In this process, essentially only the second layer 28 of the superlattice 24 is etched. Due to this etching step, the sidewalls of the etched second layer 28d are offset inwards towards the fin from the sidewalls of the corresponding first layer 26. This etching produces a fourth modified superlattice 24d. In some embodiments, such as Figure 22A , Figure 22B and Figure 22CThe etching result shown can be a function of the materials of the first layer 26 and the second layer 28, the orientation of the sidewalls, and the etchant used for etching. For example, continuing with this specific example, each first layer 26 is Si. 0.50 Ge 0.50 The layers are Si, and each second layer 28 is a Si layer. The buffer layer 22, the first layer 26, and the second layer 28 are epitaxially grown on the (110) surface of the bulk Si substrate, and the sidewalls of the first layer 26 and the second layer 28 are (111) crystal surfaces. Furthermore, the etchant can be a wet etchant, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., which are selective for the (111) crystal surface of the Si second layer 28. These conditions can produce etchants from Si... 0.50 Ge 0.50 The first layer 26 (111) crystal sidewall surface is etched inwardly offset to the second layer 28d (111) crystal sidewall surface.

[0098] Figure 23A , Figure 23B and Figure 23C Showing that in the process of undergoing Figure 22A , Figure 22B and Figure 22C The structure following the etching steps described herein and after further processing steps (such as forming the gate dielectric 42 and gate electrode 44 in the opening through ILD0 40, depositing ILD (ILD1) 46 over ILD0 40 and gate electrode 44, and forming contacts 48 through ILD1 46 and ILD0 40 to the epitaxial source / drain region 38). Figure 23C As shown, the gate dielectric 42 conforms to the etched sidewalls in the fourth modified superlattice 24d. Furthermore, since the second layer 28d has been etched, the gate electrode 44 can extend at least partially between or closer to the surface of the first layer 26.

[0099] Furthermore, FinFET / NSFET devices can be interconnected via the metallization layer in the interconnect structure described above. This interconnect structure can be formed during back-end process (BEOL) fabrication. Additional components such as passive devices and memories (e.g., magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase-change random access memory (PCRAM), etc.) can be integrated with the interconnect structure during the BEOL process, resulting in a die comprising both logic and memory devices on the same semiconductor substrate.

[0100] In some embodiments, the device includes: an isolation region on a substrate; a fin structure projecting from adjacent portions of the isolation region, the fin structure including a plurality of fins and mesas, a channel region of the fin structure having a first portion located in the fins and a second portion located in the mesas, the fins and mesas being of a continuous semiconductor material, the mesas having a wider width than the fins; and a first gate structure on the fin structure extending along the first portion of the channel region in the fins and along the second portion of the channel region in the mesas. In some embodiments, the device further includes: a first well located in the fins; a first source / drain region located in the first well, the first source / drain region adjacent to the first portion of the channel region in the fins; a second well located in the mesas, the first well and the second well having a plurality of carriers of a first conductivity type; and a second source / drain region located in the second well, the second source / drain region adjacent to the second portion of the channel region in the mesas, the first source / drain region and the second source / drain region having a plurality of carriers of a second conductivity type opposite to the first conductivity type. In some embodiments of the device, the channel region of the fin structure has a third portion located in the mesa. The device further includes a second gate structure located on the fin structure, the second gate structure extending along the third portion of the channel region in the mesa. In some embodiments, the device further includes: a first well located in the fin, the first well having a plurality of carriers of a first conductivity type; a first source / drain region located in the first well, the first source / drain region adjacent to the first portion of the channel region in the fin; a second well located in the mesa; and a second source / drain region located in the second well, the second source / drain region adjacent to the third portion of the channel region in the mesa, the first source / drain region, the second source / drain region, and the second well having a plurality of carriers of a second conductivity type, the second conductivity type being opposite to the first conductivity type. In some embodiments of the device, the isolation region has a first portion located between the fins and a second portion surrounding the mesa, the first portion having a first depth, the second portion having a second depth, the second depth being greater than the first depth. In some embodiments of the device, the difference between the first depth and the second depth is in the range of 25 nm to 40 nm. In some embodiments of the device, the first gate structure extends along the sidewall of the fin and along the sidewall of the mesa. In some embodiments of the device, the first gate structure extends along the sidewall of the fin but not along the sidewall of the mesa.

[0101] In some embodiments, the device includes: a fin structure extending from a substrate, the fin structure comprising a continuous semiconductor material, including a plurality of fins and mesas, the fins being connected to the mesas; and a transistor including: a source region located in the fin; a drain region located in the mesas; and a first gate structure located between the drain region and the source region, the first gate structure extending along a region of the fin structure connected to the mesas. In some embodiments of the device, the source region and drain region are doped regions of the fin structure having planar upper surfaces. In some embodiments of the device, the source region and drain region are epitaxial regions in the fin structure having small planar upper surfaces. In some embodiments of the device, the transistor is a complementary metal-oxide-semiconductor (CMOS) device. In some embodiments of the device, the transistor is a double-diffused metal-oxide-semiconductor (DMOS) device or a laterally diffused metal-oxide-semiconductor (LDMOS) device.

[0102] In one embodiment, the method includes: patterning a semiconductor substrate to form a fin structure extending from the semiconductor substrate, the fin structure including a fin portion and a mesa portion, each of the fin portion and the mesa portion extending in a first direction in a top-down view; forming a source region and a drain region in the fin structure, the source region being disposed in the fin portion of the fin structure and the drain region being disposed in the mesa portion of the fin structure; and forming a first gate structure between the source region and the drain region, the first gate structure being disposed on a region of the fin structure where the fin portion connects to the mesa portion, the first gate structure extending in a second direction in a top-down view, the second direction being perpendicular to the first direction. In some embodiments, the method further includes: forming a second gate structure between the first gate structure and the drain region, the second gate structure being disposed on a region of the fin structure in the mesa portion, the second gate structure extending in the second direction in a top-down view. In some embodiments of the method, patterning the semiconductor substrate includes: forming a first mask on the semiconductor substrate, a first portion of the first mask having a first width; forming a second mask on the semiconductor substrate, a second portion of the second mask having a second width greater than the first width, a portion of the first mask overlapping the second mask; and using the first mask and the second mask as a combined etch mask to etch the semiconductor substrate to form a fin structure. In some embodiments of the method, the first portion of the first mask is a spacer, and the second portion of the second mask is photoresist. In some embodiments of the method, patterning the semiconductor substrate includes: patterning the semiconductor substrate using extreme ultraviolet (EUV) lithography. In some embodiments, the method further includes: forming an isolation region around the fin structure, the isolation region having a first portion surrounding a fin portion of the fin structure and a second portion surrounding a mesa portion of the fin structure, the first portion having a first depth and the second portion having a second depth greater than the first depth. In some embodiments of the method, the difference between the first depth and the second depth is in the range of 25 nm to 40 nm.

[0103] The components of several embodiments have been outlined above to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: The isolation region is located on the substrate; A fin structure protrudes from between adjacent portions of the isolation region. The fin structure includes a plurality of fins and mesa. The channel region of the fin structure has a first portion located in the fins and a second portion located in the mesa. The fins and mesa are made of a continuous semiconductor material. The mesa has a wider width than the fins. as well as A first gate structure is located on the fin structure, the first gate structure extending along a first portion of the channel region in the fin and along a second portion of the channel region in the mesa.

2. The semiconductor device according to claim 1, further comprising: The first well is located within the fin; A first source / drain region is located in the first well, and the first source / drain region is adjacent to a first portion of the channel region in the fin; A second well is located in the mesa, and the first well and the second well have a majority of charge carriers of a first conductivity type; as well as A second source / drain region is located in the second well, the second source / drain region being adjacent to a second portion of the channel region in the mesa, the first source / drain region and the second source / drain region having a majority of carriers of a second conductivity type, the second conductivity type being opposite to the first conductivity type.

3. The semiconductor device according to claim 1, wherein, The channel region of the fin structure has a third portion located within the mesa, and the semiconductor device further includes: A second gate structure is located on the fin structure and extends along a third portion of the channel region in the mesa.

4. The semiconductor device according to claim 3, further comprising: A first well, located in the fin, has a plurality of charge carriers of a first conductivity type; A first source / drain region is located in the first well, and the first source / drain region is adjacent to a first portion of the channel region in the fin; The second well is located within the platform; as well as A second source / drain region is located in the second well, the second source / drain region being adjacent to a third portion of the channel region in the mesa, the first source / drain region, the second source / drain region and the second well having a plurality of carriers of a second conductivity type, the second conductivity type being opposite to the first conductivity type.

5. The semiconductor device according to claim 1, wherein, The isolation area has a first portion located between the fins and a second portion surrounding the platform, the first portion having a first depth and the second portion having a second depth greater than the first depth.

6. The semiconductor device according to claim 5, wherein, The difference between the first depth and the second depth is in the range of 25nm to 40nm.

7. The semiconductor device according to claim 1, wherein, The first gate structure extends along the sidewall of the fin and along the sidewall of the mesa.

8. The semiconductor device according to claim 1, wherein, The first gate structure extends along the sidewall of the fin but not along the sidewall of the mesa.

9. A semiconductor device, comprising: A fin structure extending from a substrate, the fin structure comprising a continuous semiconductor material including a plurality of fins and mesas, the fins being connected to the mesas; as well as Transistors, including: The source region is located within the fin; The drain region is located within the mesa; and A first gate structure is located between the drain region and the source region, and the first gate structure extends along the region where the fin of the fin structure is connected to the mesa.

10. The semiconductor device according to claim 9, wherein, The source region and the drain region are doped regions of the fin structure having a planar upper surface.

11. The semiconductor device according to claim 9, wherein, The source region and the drain region are extensional regions in the fin structure having a small planar upper surface.

12. The semiconductor device according to claim 9, wherein, The transistor is a complementary metal-oxide-semiconductor device.

13. The semiconductor device according to claim 9, wherein, The transistor is a double-diffused metal-oxide-semiconductor device or a laterally diffused metal-oxide-semiconductor device.

14. A method of forming a semiconductor device, comprising: A patterned semiconductor substrate is used to form a fin structure extending from the semiconductor substrate, the fin structure including a fin portion and a mesa portion, each of the fin portion and the mesa portion extending in a first direction in a top-down view; An isolation region is formed around the fin structure, the isolation region having a first portion surrounding the fin portion of the fin structure and a second portion surrounding the platform portion of the fin structure, the first portion having a first depth and the second portion having a second depth greater than the first depth; A source region and a drain region are formed in the fin structure, the source region being disposed in the fin portion of the fin structure, and the drain region being disposed in the mesa portion of the fin structure; as well as A first gate structure is formed between the source region and the drain region. The first gate structure is disposed on the region where the fin portion of the fin structure is connected to the mesa portion. The first gate structure extends in a second direction in a top-down view, and the second direction is perpendicular to the first direction.

15. The method of claim 14, further comprising: A second gate structure is formed between the first gate structure and the drain region, the second gate structure being disposed on the region of the fin structure in the mesa portion, and the second gate structure extending in the second direction in a top-down view.

16. The method of claim 14, wherein, Patterning the semiconductor substrate includes: A first mask is formed on the semiconductor substrate, and a first component of the first mask has a first width; A second mask is formed on the semiconductor substrate, a second part of the second mask having a second width, the second width being greater than the first width, and a portion of the first mask overlapping the second mask; The semiconductor substrate is etched using the first mask and the second mask as a combined etching mask to form the fin structure.

17. The method according to claim 16, wherein, The first component of the first mask is a spacer, and the second component of the second mask is photoresist.

18. The method according to claim 14, wherein, Patterning the semiconductor substrate includes using extreme ultraviolet lithography to pattern the semiconductor substrate.

19. The method of claim 14, wherein, The fin portion and the mesa portion are formed of a continuous semiconductor material, and the width of the mesa portion is greater than the width of each fin portion.

20. The method of claim 14, wherein, The difference between the first depth and the second depth is in the range of 25nm to 40nm.

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