A novel triggering mode thyristor structure and a manufacturing method thereof

Abstract

The application discloses a novel trigger type thyristor structure and a manufacturing method thereof. The thyristor structure comprises a main body structure, an electrode structure and an isolation structure. The main body structure comprises a first emitter, a first base region, a second base region and a second emitter which are sequentially stacked. The electrode structure comprises a first electrode and a second electrode which are located on both sides of the main body structure and cooperate to drive the main body structure to conduct. The isolation structure comprises a gate member and a third base region which is located on at least one side of the main body structure and contacts the first emitter and the second base region. The third base region has the same doping element characteristics as the second base region. The gate member is in contact with the third base region, and the gate member injects current into the third base region to trigger the main body structure to conduct. The thyristor structure has the effects of increasing the contact area of the emitter and reducing the on-state voltage drop, and is suitable for a thyristor.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and more specifically, to a novel triggering method for a thyristor structure and its fabrication method. Background Technology

[0002] A thyristor is a high-power semiconductor device with a four-layer structure containing three PN junctions. Thyristors are used in various electrical appliances such as refrigerators, air conditioners, electric fans, hair straighteners, smart toilets, industrial equipment, and the national power grid, making them important power semiconductor devices.

[0003] In related technologies, such as Figure 1 As shown, a thyristor 10' typically includes a control electrode 701 and a first electrode 101, a first emitter 201, a first base region 301, a second base region 401, a second emitter 501, and a second electrode 601 stacked sequentially. The control electrode 701 is located on the side of the first emitter 201 away from the second electrode 601 and is in contact with the first emitter 201. Because the control electrode 701 is located on the same side as the first electrode 101, the contact area between the first electrode 101 and the first emitter 201 is relatively reduced. This results in an increased on-state voltage drop after the thyristor is turned on, which is detrimental to the stable and efficient operation of the thyristor. Summary of the Invention

[0004] The purpose of this invention is to provide a novel triggering method for a thyristor structure and its fabrication method, which can improve at least one of the problems mentioned above in the related art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, the application provides a novel thyristor structure with a new triggering mode, which comprises a main body structure, an electrode structure and an isolation structure. The main body structure comprises a first emitter layer, a first base region, a second base region and a second emitter layer arranged in sequence in a first direction; wherein the first emitter layer comprises a first emitter electrode, and the second emitter layer comprises a second emitter electrode. The electrode structure comprises a first electrode and a second electrode located on both sides of the main body structure in the first direction; the first electrode is configured to cooperate with the second electrode to drive the main body structure to conduct. The isolation structure comprises a third base region and a gate member; the third base region covers at least one side of the main body structure, and is in contact with the first emitter electrode in the first direction and in contact with the second base region in a second direction; the third base region has the same doping element characteristics as the second base region; the gate member is in contact with the third base region, and is configured to inject current into the third base region to trigger the main body structure to conduct. Wherein the first emitter electrode is in contact with the first electrode and the first base region respectively, and the second emitter electrode is in contact with the second electrode and the second base region respectively; the first direction and the second direction are arranged in cross; the first emitter electrode, the first base region, the second base region and the second emitter electrode are in sequence P emitter, N base region, P base region and N emitter; or the first emitter electrode, the first base region, the second base region and the second emitter electrode are in sequence N emitter, P base region, N base region and P emitter.

[0007] In some embodiments, the element doping concentration in the third base region is greater than the element doping concentration in the second base region.

[0008] In some embodiments, the third base region is in contact with the first base region.

[0009] In some embodiments, the gate member is located on a side of the third base region away from the second emitter electrode.

[0010] In some embodiments, the thyristor structure further comprises an isolation groove between the third base region and the first emitter electrode; the third base region and the first emitter electrode are isolated by the isolation groove.

[0011] In some embodiments, the gate member comprises a first trigger electrode, and the first trigger electrode, the third base region, the second emitter electrode and the second electrode jointly constitute a diode structure.

[0012] In some embodiments, the gate member further comprises an auxiliary base region, and the first trigger electrode, the auxiliary base region, the third base region, the second emitter electrode and the second electrode jointly constitute a triode structure.

[0013] In some embodiments, the first emitter layer further comprises a third emitter, which is in contact with the first electrode and the first emitter respectively in the first direction. The second emitter layer further comprises a fourth emitter, which is in contact with the second base region and the second electrode respectively in the first direction, and in contact with the second emitter in the second direction. The first trigger electrode covers the auxiliary base region and the third base region in the second direction.

[0014] In some embodiments, the third base region is arranged around the main structure.

[0015] In another aspect, the application further provides a method for manufacturing a silicon controlled rectifier structure. The method comprises:

[0016] manufacturing a second emitter layer;

[0017] manufacturing a second base region, a first base region and a first emitter layer in sequence on one side of the second emitter layer in the first direction to form a main structure;

[0018] manufacturing a third base region on at least one side of the main structure in the second direction;

[0019] manufacturing a gate member on the side of the third base region away from the second emitter layer;

[0020] manufacturing a first electrode on the side of the first emitter layer away from the second emitter layer; and

[0021] manufacturing a second electrode on the side of the second emitter layer away from the second base region.

[0022] The silicon controlled rectifier structure and the manufacturing method thereof have at least the following beneficial effects.

[0023] The silicon controlled rectifier structure can effectively increase the contact area between the first electrode and the first emitter, thereby effectively increasing the emission area of the first emitter and improving the working stability. In addition, the increase of the contact area between the first electrode and the first emitter and the increase of the carrier diffusion area increase the maintaining current. The increase of the contact area between the first electrode and the first emitter also reduces the contact resistance therebetween, which can avoid the consumption of this part of resistance in the working process of the silicon controlled rectifier structure, thereby effectively reducing the on-state voltage drop of the silicon controlled rectifier structure. Moreover, the increase of the third base region increases the invalid part occupied by the third base region in the process of triggering the main structure to conduct, thereby increasing the total trigger current and improving the anti-interference ability of the silicon controlled rectifier structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0025] Figure 1 A schematic diagram of a structure of a thyristor in the related art;

[0026] Figure 2 A schematic diagram of a structure of a thyristor according to some embodiments;

[0027] Figure 3 A schematic diagram of a structure of a thyristor according to some embodiments;

[0028] Figure 4 A schematic diagram of a structure of a thyristor according to some embodiments;

[0029] Figure 5 A schematic diagram of a structure of a thyristor according to some embodiments;

[0030] Figure 6 A schematic diagram of a structure of a thyristor according to some embodiments;

[0031] Figure 7 A top view of Figure 2 A top view of DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present application.

[0033] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as an open, inclusive meaning, i.e. "comprises, but not limited to". In the description of the specification, the terms "some embodiments", "some examples" or "exemplary" are intended to mean that the particular feature, structure, material or characteristic being described in connection with such embodiments or examples includes in at least one embodiment or example of the application. The appearance of such terms in various places in the specification is not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0034] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0035] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0036] Some embodiments of the present application provide a new type of silicon controlled rectifier structure, as shown in Figure 2 The silicon controlled rectifier structure 10 includes a main body structure, an electrode structure, and an isolation structure. The electrode structure includes a first electrode 1 and a second electrode 6 located on both sides of the main body structure in a first direction X. The first electrode 1 is configured to cooperate with the second electrode 6 to drive the main body structure to conduct. That is, under the cooperation of the first electrode 1 and the second electrode 6, the main body structure can form or maintain a conducting state.

[0037] The main body structure includes a first emitter layer 2, a first base region 3, a second base region 4, and a second emitter layer 5 arranged in sequence along the first direction. The first emitter layer 2 includes a first emitter 21 in contact with the first electrode 1 and the first base region 3, respectively. The second emitter layer 5 includes a second emitter 51 in contact with the second base region 4 and the second electrode 6, respectively.

[0038] The first emitter 21, the first base region 3, the second base region 4, and the second emitter 51 can form a four-layer structure of PNPN type or NPNP type. For example, as shown in Figure 3 , Figure 5 and Figure 6 , the first emitter 21, the first base region 3, the second base region 4, and the second emitter 51 are in sequence P emitter, N base region, P base region, and N emitter, thereby forming a four-layer structure of PNPN type. For another example, as shown in Figure 4 , the first emitter 21, the first base region 3, the second base region 4, and the second emitter 51 are in sequence N emitter, P base region, N base region, and P emitter, thereby forming a four-layer structure of NPNP type.

[0039] When the main structure consists only of a four-layer structure of type PNPN, the first electrode 1 is the anode and the second electrode 6 is the cathode; when the main structure consists only of a four-layer structure of type NPNP, the first electrode 1 is the cathode and the second electrode 6 is the anode.

[0040] Taking the PNPN type four-layer structure as an example, the working principle of the thyristor structure 10 will be explained below.

[0041] like Figure 3 As shown, a J1 junction is formed between the first emitter 21 (i.e., the P-emitter) and the first base region 3 (i.e., the N-base region), a J2 junction is formed between the first base region 3 and the second base region 4 (i.e., the P-base region), and a J3 junction is formed between the second base region 4 and the second emitter 51 (i.e., the N-emitter). When the first electrode 1 is the anode and the second electrode 6 is the cathode, the J1 and J3 junctions are forward-biased, and the J2 junction is reverse-biased. At this time, almost all of the external voltage falls on the J2 junction, and the current flowing through it is very small, so the thyristor structure 10 is in the off state. When the voltage increases to the breakdown voltage of the J2 junction, the J2 junction undergoes an avalanche multiplication effect, generating a large number of electrons and holes in the J2 junction region. Electrons entering the N-base region recombine with holes injected into the P-emitter region through the J1 junction; while holes entering the P-base region recombine with electrons injected into the N-emitter region through the J3 junction. After avalanche breakdown, electrons entering the N-base region and holes entering the P-base region cannot recombine completely, leading to electron accumulation in the N-base region and hole accumulation in the P-base region. This results in an increase in the potential of the P-base region and a decrease in the potential of the N-base region, effectively counteracting the applied voltage. As accumulation increases, the voltage drops rapidly, exhibiting negative resistance characteristics (voltage decreases, current increases). When the voltage drops until avalanche breakdown completely stops, if the accumulation in the N-base and P-base regions can still be maintained, the P-base region is positive relative to the N-base region. That is, J2 is forward biased. At this time, junctions J1, J2, and J3 are all forward biased, and the thyristor structure 10 is in the conducting state.

[0042] Therefore, before the voltage applied to the thyristor structure 10 reaches breakdown, the J2 junction is in reverse orientation, and the current flowing through it is very small. When avalanche breakdown occurs, the current flowing through the J2 junction increases sharply, which can cause the thyristor structure 10 to enter the conducting state. The inventors have discovered that by increasing the current flowing through the J2 junction, for example, by the presence of leakage current, displacement current caused by the rate of voltage rise, illumination, or by injecting current through the control electrode in the P-base region or N-base region, the main structure can be made to conduct.

[0043] For the aforementioned thyristor structure 10, the isolation structure includes a third base region 7 and a gate component 8.

[0044] The third base region 7 covers at least one side of the main body structure, and is in contact with the first emitter 21 in the first direction X and in contact with the second base region 4 in the second direction Y. The first direction X and the second direction Y are arranged in a cross manner. For example, the first direction X and the second direction Y are perpendicular to each other.

[0045] The third base region 7 has the same doping element characteristics as the second base region 4. That is, when the second base region 4 is an N base region, the third base region 7 is also an N base region; when the second base region 4 is a P base region, the third base region 7 is also a P base region. In this way, the third base region 7 and the second base region 4 can form a carrier conduction.

[0046] For example, the doping element of the N base region is phosphorus arsenic tellurium bismuth.

[0047] For example, the doping element of the P base region is boron aluminum gallium indium thallium.

[0048] The gate member 8 is in contact with the third base region 7, and the gate member 8 is configured to inject current into the third base region 7 to trigger the main body structure to conduct. That is, without the gate member 8, the main body structure cannot form a conducting state under the cooperation of the first electrode 1 and the second electrode 6; when the gate member 8 injects current into the third base region 7, the main body structure can form a conducting state under the cooperation of the first electrode 1 and the second electrode 6, and maintain the conducting state.

[0049] In this way, since the gate member 8 is arranged on the third base region 7, the problem of reducing the contact area between the first electrode and the first emitter caused by arranging the gate member on the first emitter layer in the related art can be avoided. On the contrary, the thyristor structure 10 provided by the present application can effectively increase the contact area between the first electrode and the first emitter, thereby effectively increasing the emission area of the first emitter and improving the working stability. In addition, since the contact area between the first electrode and the first emitter is increased, the carrier diffusion area is increased, so that the maintained current is increased. The increase of the contact area between the first electrode and the first emitter also leads to the decrease of the contact resistance therebetween, which can avoid the consumption of this part of resistance in the working process of the thyristor structure 10, thereby effectively reducing the on-state voltage drop of the thyristor structure 10. Moreover, since the third base region 7 is added, the invalid part occupied by the third base region 7 increases during the process of triggering the main body structure to conduct, so that the total trigger current is increased, thereby improving the anti-interference ability of the thyristor structure 10.

[0050] In some embodiments, the element doping concentration in the third base region 7 is greater than the element doping concentration in the second base region 4. In the case that the second base region 4 is an N base region, the third base region 7 is an N+ base region; in the case that the second base region 4 is a P base region, the third base region 7 is a P+ base region. In this way, the diffusion of carriers in the third base region 7 to the second base region 4 is more facilitated, and the triggering of the main body structure by the gate member 8 is more facilitated, so that the main body structure is turned on.

[0051] In some examples, the third base region 7 covers one side of the main body structure. In other examples, the third base region 7 covers at least two sides of the main body structure. For example, the third base region 7 covers opposite sides of the main body structure. For another example, please refer to Figure 7 , the third base region 7 is arranged around the main body structure, that is, the third base region 7 covers any side of the main body structure, and in this case, the overall structure has better stability.

[0052] In some embodiments, the third base region 7 is also in contact with the first base region 3.

[0053] For example, in the first direction X, the thickness of the first base region 3 is greater than the thicknesses of the first emitter 21, the second base region 4, and the second emitter 51, which is conducive to turning on the main body structure.

[0054] By arranging the third base region 7 in contact with the first base region 3, on the one hand, it can avoid a large height difference between the main body structure and the isolation structure, so that the overall structure of the silicon controlled rectifier structure 10 has better stability; on the other hand, the third base region 7 is in contact with the first base region 3 and the second base region 4 at the same time, which can further improve the contact stability between the third base region 7 and the main body structure.

[0055] In some embodiments, the gate member 8 is located on the side of the third base region 7 away from the second emitter 51. In this way, the gate member 8 can be avoided to be located on the outer circumferential side of the third base region 7, so that the overall area occupied is relatively large, which is not conducive to the placement of the silicon controlled rectifier structure 10.

[0056] In some examples, the silicon controlled rectifier structure 10 further comprises an isolation groove 9 between the third base region 7 and the first emitter layer 2; the third base region 7 and the first emitter layer 2 are arranged in isolation through the isolation groove 9. In the case that the third base region 7 is arranged around the main body structure, the isolation groove 9 is also arranged around the first electrode 1.

[0057] For example, the part between the third base region 7 and the first emitter layer 2 located in the isolation groove 9 is provided with a passivation layer, which can make the third base region 7 and the first emitter layer 2 form independent voltage regions, so as to avoid large interference between them.

[0058] For example, glass material can be filled into the isolation groove 9 to form a glass groove.

[0059] In some embodiments, such as Figures 2-4 As shown, the gate component 8 includes a first trigger electrode 81, which, together with the third base region 7, the second emitter 51, and the second electrode 6, forms a diode structure. In this case, the PN junction formed between the first trigger electrode 81, the third base region 7, and the second emitter 51, along with the second electrode 6, allows the diode structure to conduct. This allows current to be injected into the second base region 4, thereby enabling the main structure to conduct.

[0060] In some examples, such as Figure 3 As shown, the main structure includes a PNPN type four-layer structure, with the first electrode 1 as the anode, the second electrode 6 as the cathode, the third base region as the P+ base region, and the first trigger electrode 81 connected to a positive voltage. A positive trigger signal from the first trigger electrode 81 can cause the main structure to conduct.

[0061] In other examples, such as Figure 4 As shown, the main structure includes an NPNP-type four-layer structure, with the first electrode 1 as the cathode, the second electrode 6 as the anode, the third base region as an N+ base region, and the first trigger electrode 81 connected to a negative voltage. A negative trigger signal from the first trigger electrode 81 can cause the main structure to conduct.

[0062] In some embodiments, such as Figures 5-6 As shown, the gate component 8 also includes an auxiliary base region 82 located below the first trigger electrode 81. The first trigger electrode 81, the auxiliary base region 82, the third base region 7, the second emitter 51, and the second electrode 6 together constitute a transistor structure. At this time, the PN junction formed by the first trigger electrode 81, the auxiliary base region 82, and the third base region 7 cooperates to inject current into the second base region 4, thereby making the main structure conduct.

[0063] In some examples, such as Figure 5 As shown, the main structure includes a PNPN type four-layer structure, the first electrode 1 is the anode, the second electrode 6 is the cathode, the third base region 7 is the P+ base region, the auxiliary base region 82 is the N base region, and the first trigger electrode 81 is connected to a negative voltage, which can make the main structure conduct.

[0064] In some embodiments, such as Figure 6 As shown, the first emitter layer 2 further includes a third emitter 22, which is in contact with the first electrode 1 and the first emitter 21, respectively. The second emitter layer 5 further includes a fourth emitter 52, which is in contact with the second base region 4 and the second electrode 6 in the first direction X, and in contact with the second emitter 51 in the second direction Y.

[0065] The first trigger electrode 81 at least partially covers the third base region 7 and the auxiliary base region 82. For example, the first trigger electrode 81 entirely covers part of the third base region 7 and all of the auxiliary base region 82. Since a PN junction can be formed between the auxiliary base region 82 and the third base region 7, and the first trigger electrode 81 covers the third base region 7 and the auxiliary base region 82 at the same time, the gate member 8 forms a PN junction and has a shorted emitter structure.

[0066] In some examples, the first trigger electrode 81 is a unitary structure covering the third base region 7 and the auxiliary base region 82. In other examples, as shown in Figure 6 The gate member 8 includes a second trigger electrode 83 in parallel with the first trigger electrode 81, and the second trigger electrode 83 is directly in contact with the third base region 7.

[0067] Referring to Figure 6 , the first emitter 21, the first base region 3, the second base region 4, and the second emitter 51 form a PNPN four-layer structure, which is referred to as a first controllable unit. The third emitter 22 is an N emitter, and the fourth emitter 52 is a P emitter. In this case, the third emitter 22, the first emitter 21, the first base region 3, the second base region 4, and the fourth emitter 52 form an NPNP four-layer structure, which is referred to as a second controllable unit. The third base region 7 is a P+ base region, and the auxiliary base region 82 is an N base region. In this case, the gate member 8 and the third base region 7 can be referred to as a third controllable unit.

[0068] When the first electrode 1 is an anode, the second electrode 6 is a cathode, and the first trigger electrode 81 is connected to a positive voltage, the first controllable unit is turned on, as in the case shown in Figure 5 , and the thyristor structure 10 is turned on.

[0069] When the first electrode 1 is an anode, the second electrode 6 is a cathode, and the first trigger electrode 81 is connected to a negative voltage, the second electrode 2 corresponds to a control electrode of the third controllable unit. When the current of the second electrode 6 is large enough, the third controllable unit is turned on, which causes the potential of the first trigger electrode 81 to suddenly increase to the potential of the second electrode 6. The current of the first trigger electrode 81 originally flows from the third base region 7 to the shorted region of the third controllable unit, and then flows in the opposite direction. The increased current causes the second emitter 51 to start injecting electrons, and the first controllable unit is turned on.

[0070] When the first electrode 1 is a cathode, the second electrode 6 is an anode, and the first trigger electrode 81 is connected to a negative voltage, the current of the first trigger electrode 81 flows from the third base region 7 to the short-circuit region of the third controllable unit, and this part of the current is a hole current. When the current is large enough, the auxiliary base region 82 begins to inject electrons. These electrons will be swept into the first base region 3 by the electric field of the space charge layer of the PN junction between the second base region 4 and the first base region 3 after passing through the third base region 7 and the second base region 4. Thus, the potential of the first base region 3 is more negative than that of the second base region 4, which causes the PN junction between the second base region 4 and the first base region 3 to inject more holes into the first base region 3, thereby causing the second controllable unit to conduct.

[0071] When the first electrode 1 is a cathode, the second electrode 6 is an anode, and the first trigger electrode 81 is connected to a positive voltage, the current flows from the first trigger electrode 81 to the second electrode 6 through the third base region 7, the second base region 4, and the fourth emitter 52 in sequence. When the current is large enough, the PN junction between the second base region 4 and the first base region 3 becomes forward biased, thereby causing the second controllable unit to conduct. Thus, the first electrode 1, the second electrode 6, and the first trigger electrode 81 can all cause the silicon controlled rectifier structure 10 to conduct when different combinations of voltage polarities are applied, thereby enriching the use scenarios of the present application.

[0072] In some embodiments, the present application also provides a manufacturing method of a silicon controlled rectifier structure. Please refer to Figure 2 The manufacturing method comprises the following steps:

[0073] S1: manufacturing the second emitter layer 5.

[0074] S2: manufacturing the second base region 4, the first base region 3, and the first emitter layer 2 in sequence on one side of the second emitter layer 5 in the first direction X based on the second emitter layer 5 to form a main body structure.

[0075] S3: manufacturing the third base region 7 on at least one side of the main body structure in the second direction Y.

[0076] For example, as Figure 7 shown in the figure, the third base region 7 can be manufactured around the main body structure, and an isolation groove 9 is left between the third base region 7 and the first emitter layer 2.

[0077] S4: manufacturing the gate member 8 on the side of the third base region 7 away from the second emitter layer 5.

[0078] It should be noted that, in the case where the gate member 8 comprises the first trigger electrode 81 and the auxiliary base region 82, the auxiliary base region 82 needs to be manufactured on the side of the third base region 7 away from the second emitter layer 5 first, and then the first trigger electrode 81 is manufactured on the auxiliary base region 82.

[0079] S5: fabricate the first electrode 1 on the side of the first emitting layer 2 away from the second emitting layer 5.

[0080] It should be noted that, in the case that the first emitting layer 2 comprises the first electrode 21 and the third electrode 22, the first electrode 1 covers the first electrode 21 and the third electrode 22 simultaneously.

[0081] S6: fabricate the second electrode 6 on the side of the second emitting layer 5 away from the second base region 4.

[0082] It should be noted that, in the case that the second emitting layer 5 comprises the second electrode 51 and the fourth electrode 52, the second electrode 6 covers the second electrode 51 and the fourth electrode 52 simultaneously.

[0083] The method for fabricating the silicon controlled rectifier structure 10 provided by the present application has the same technical effects as the silicon controlled rectifier structure 10, which will not be described here.

[0084] Although the preferred embodiments of the present application have been described, those skilled in the art who are familiar with the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0085] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A novel thyristor structure of a new triggering mode, characterized in that, The application relates to a novel trigger mode thyristor structure. The main body structure comprises a first emitting layer, a first base area, a second base area and a second emitting layer arranged in sequence along a first direction; the first emitting layer comprises a first emitter, and the second emitting layer comprises a second emitter; The electrode structure comprises a first electrode and a second electrode arranged on both sides of the main body structure along the first direction; the first electrode is configured to cooperate with the second electrode to drive the main body structure to conduct; The isolation structure comprises a third base area and a gate member; the third base area covers at least one side of the main body structure, is arranged in contact with the first emitter along the first direction and is arranged in contact with the second base area along a second direction; the third base area and the second base area have the same doping element characteristics; the gate member is arranged in contact with the third base area, and is configured to inject current into the third base area to trigger the main body structure to conduct; wherein, The first emitter is in contact with the first electrode and the first base area respectively, and the second emitter is in contact with the second electrode and the second base area respectively; the first direction and the second direction are arranged in cross. The first emitter, the first base area, the second base area and the second emitter are sequentially a P emitter, an N base area, a P base area and an N emitter; or the first emitter, the first base area, the second base area and the second emitter are sequentially an N emitter, a P base area, an N base area and a P emitter.

2. A novel thyristor structure of a trigger mode according to claim 1, characterized in that, The element doping concentration in the third base area is greater than the element doping concentration in the second base area.

3. A novel thyristor structure of a trigger mode according to claim 2, characterized in that, The third base area is arranged in contact with the first base area.

4. A novel thyristor structure of a trigger mode according to claim 3, characterized in that, The gate member is located on a side of the third base area away from the second emitter.

5. A novel thyristor structure of a trigger mode according to claim 4, characterized in that, The thyristor structure further comprises an isolation groove between the third base area and the first emitter, and the third base area and the first emitter are arranged in isolation through the isolation groove.

6. A novel triac structure with a trigger mode according to any one of claims 1-5, characterized in that, The gate member comprises a first trigger electrode, and the first trigger electrode, the third base area, the second emitter and the second electrode jointly form a diode structure.

7. A novel thyristor structure of a trigger mode according to claim 6, characterized in that, The gate member further comprises an auxiliary base area, and the first trigger electrode, the auxiliary base area, the third base area, the second emitter and the second electrode jointly form a triode structure.

8. The novel trigger mode thyristor structure according to claim 7, wherein The first emitting layer further comprises a third emitter arranged in contact with the first electrode and the first emitter respectively; The second emitting layer further comprises a fourth emitter arranged in contact with the second base area and the second electrode respectively, and the fourth emitter is arranged in contact with the second emitter; The first trigger electrode is at least partially arranged above the auxiliary base area and the third base area.

9. A novel triac structure with a trigger mode according to any one of claims 1-5, characterized in that, The third base area surrounds the main body structure.

10. The method for manufacturing a novel trigger mode thyristor structure according to any one of claims 1-9, characterized in that, The second emitting layer is manufactured; The second base area, the first base area and the first emitting layer are sequentially manufactured on one side of the second emitting layer along the first direction to form the main body structure; The third base area is manufactured on at least one side of the main body structure along the second direction. ​ A gate member is formed on the side of the third base region distal from the second emitter layer; A first electrode is formed on the side of the first emitter layer distal from the second emitter layer; and A second electrode is formed on the side of the second emitter layer distal from the second base region.

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