Common-mode current control method for non-isolated photovoltaic inverter of type H5

Abstract

The application discloses a common-mode current control method of a H5 type non-isolated photovoltaic inverter, which comprises the following steps: under bus voltage, the switching tube S5 is not driven, the voltage between the voltage dividing resistors of the detection branch is sampled to obtain a first sampling voltage, the first sampling voltage is compared with a first threshold value, if the first sampling voltage is smaller than the first threshold value, it is determined that the switching tube S5 is not short-circuited, and grid connection is allowed; otherwise, grid connection is not allowed. The common-mode current control method reduces the common-mode current of the H5 type non-isolated photovoltaic inverter caused by the parasitic capacitance of a photovoltaic module to the ground.

Description

Technical Field

[0001] This invention relates to a common-mode current control method for an H5 type non-isolated photovoltaic inverter. Background Technology

[0002] Currently, low-power single-phase inverters typically employ non-isolated photovoltaic grid-connected inverters, which offer advantages such as high conversion efficiency, high power density, and low cost. (Refer to...) Figure 1 As shown, in a transformerless, non-isolated H5 topology photovoltaic grid-connected inverter system, a common-mode resonant circuit is formed due to the direct electrical connection between the grid and the photovoltaic array, and the parasitic capacitance Cm between the photovoltaic array and the ground. This circuit consists of the parasitic capacitance, filter elements, and grid impedance. The varying common-mode voltage Vcm across the parasitic capacitance can excite this resonant circuit, generating a corresponding common-mode current. The presence of this common-mode current causes grid current distortion, electromagnetic interference, additional system losses, and safety hazards. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a common-mode current control method for H5 type non-isolated photovoltaic inverters, thereby reducing the common-mode current caused by the parasitic capacitance of photovoltaic modules to the ground.

[0004] The technical solution adopted in this invention is as follows:

[0005] A common-mode current control method for an H5 type non-isolated photovoltaic inverter, the photovoltaic inverter including an H5 inverter circuit, the H5 inverter circuit including switching transistors S1, S2, S3, S4 and S5, wherein the switching transistors S1 and S2 are connected to form a first inverter bridge arm, the switching transistors S3 and S4 are connected to form a second inverter bridge arm, and the collector of the switching transistor S5 is electrically connected to the positive DC bus; the photovoltaic inverter also includes a detection branch, one end of the detection branch is electrically connected to the emitter of the switching transistor S5 and the other end is electrically connected to the negative DC bus; the detection branch includes multiple voltage divider resistors connected in series;

[0006] The common-mode current control method includes: under the bus voltage, the switch S5 is not driven, the voltage between the voltage divider resistors of the detection branch is sampled to obtain a first sampled voltage, the first sampled voltage is compared with a first threshold, if the first sampled voltage is less than the first threshold, it is determined that the switch S5 has no short-circuit fault and grid connection is allowed; otherwise, grid connection is not allowed.

[0007] In some preferred embodiments, the following steps are further included before grid connection:

[0008] Under the bus voltage, the switch S5 is driven to sample the voltage between the voltage divider resistors of the detection branch to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that the switch S5 is conducting normally and grid connection is allowed; otherwise, grid connection is not allowed.

[0009] In some preferred embodiments, the second threshold is greater than the first threshold.

[0010] In some preferred embodiments, the detection branch includes a plurality of first resistors and second resistors connected in series, and a resistor divider sampling terminal is connected between the first resistors and the second resistors to obtain the first sampling voltage and the second sampling voltage through the resistor divider sampling terminal.

[0011] In some preferred embodiments, the resistance value of the first resistor is greater than the resistance value of the second resistor.

[0012] In some preferred embodiments, a plurality of first resistors are connected in series between the emitter of the switching transistor S5 and the resistor divider sampling terminal, and a second resistor is connected between the resistor divider sampling terminal and the negative DC bus. The resistance value of the first resistors is more than 40 times greater than the resistance value of the second resistor.

[0013] In some preferred embodiments, the bases of the switching transistors S1, S2, S3, S4 and S5 and the resistor divider sampling terminals are all electrically connected to the MCU chip.

[0014] In some preferred embodiments, diodes are connected in reverse parallel to each of the switching transistors S1, S2, S3, S4 and S5.

[0015] The present invention adopts the above solution, which has the following advantages compared with the prior art:

[0016] The method of this invention detects the state of the switching transistor S5 of the H5 topology before the inverter is connected to the grid to determine whether there is a short circuit fault. This can effectively avoid the common-mode current problem caused by the parasitic capacitance of the photovoltaic module to the ground in the non-isolated photovoltaic inverter due to the short circuit of the switching transistor S5, reduce the common-mode current caused by the parasitic capacitance of the photovoltaic module to the ground in the non-isolated photovoltaic inverter, and also achieve the function of early detection, prevention and alarm. Attached Figure Description

[0017] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a topology diagram of the H5 type non-isolated photovoltaic inverter system.

[0019] Figure 2 This is a schematic diagram of the connection of the detection branch.

[0020] Figure 3 The waveform is the test waveform when the S5 transistor is not driven.

[0021] Figure 4 Test waveform when driving S5 transistor. Detailed Implementation

[0022] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art. It should be noted that the description of these embodiments is for the purpose of aiding understanding the present invention, but does not constitute a limitation thereof. Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] Figure 1 The diagram shows a transformerless, non-isolated H5 topology photovoltaic grid-connected inverter system. Because there is a direct electrical connection between the grid Vg and the photovoltaic array 1, and because there is a parasitic capacitance Cm between the photovoltaic array 1 and the ground PE, a common-mode resonant circuit is formed, consisting of the parasitic capacitance Cm, filter elements, and grid impedance. The changing common-mode voltage Vcm on the parasitic capacitance Cm can excite this resonant circuit to generate a corresponding common-mode current Icm.

[0024] Reference Figure 1 As shown, this non-isolated photovoltaic inverter includes an H5 inverter circuit, which includes switching transistors S1, S2, S3, S4, and S5. Switches S1 and S2 are connected to form the first inverter bridge arm, and switches S3 and S4 are connected to form the second inverter bridge arm. The first and second inverter bridge arms are connected in parallel between the positive DC bus 201 and the negative DC bus 202. The midpoints of the first and second inverter bridge arms serve as AC output terminals, connected to the grid Vg. The collector of switch S5 is electrically connected to the positive DC bus 201, and the collectors of switches S1 and S2 are electrically connected to the emitter of switch S5, respectively. The photovoltaic inverter also includes a detection branch 21, one end of which is electrically connected to the emitter of switch S5, and the other end is electrically connected to the negative DC bus 202. This detection branch includes multiple voltage divider resistors R1, R2, R3, and R4 connected in series. The output terminal PV+ of the photovoltaic array is connected to the positive DC bus 201, and the output terminal PV- is connected to the negative DC bus; a bus capacitor Cbus is connected in parallel between the positive DC bus 201 and the negative DC bus 202.

[0025] Combination Figure 1 As shown, the detection branch includes multiple first resistors (R1, R2, and R3) and a second resistor R4 connected in series. A resistor divider sampling terminal 211 is connected between the first resistors R3 and the second resistor R4. The resistance of the first resistor is greater than the resistance of the second resistor. Under a certain bus voltage, the sampling voltage Vc can be obtained through the resistor divider network of R1, R2, R3, and R4. Specifically, in this embodiment, multiple first resistors R1, R2, and R3 are connected in series between the emitter of the switching transistor S5 and the resistor divider sampling terminal 211. A second resistor R4 is connected between the resistor divider sampling terminal 211 and the negative DC bus. The resistance of the first resistors (R1, R2, and R3) is more than 40 times greater than the resistance of the second resistor R4.

[0026] The bases of switching transistors S1, S2, S3, S4, and S5, and the voltage divider sampling terminal 211 are all electrically connected to the MCU chip 203. Each of the switching transistors S1, S2, S3, S4, and S5 has a diode connected in reverse parallel.

[0027] The principle of reducing common-mode current in this embodiment is explained as follows. In the formulas below, Cbus represents the bus capacitance; Vc represents the voltage value of the resistor divider network sampled by the resistor divider sampling terminal 211; Va represents the voltage of point a of the inverter bridge to point 0 of the DC negative bus; Vb represents the voltage of point b of the inverter bridge to point 0 of the DC negative bus; VL1 represents the inductor voltage drop on L1; VL2 represents the inductor voltage drop on L2; Vg represents the grid voltage; Icm represents the resonant current in the common-mode resonant circuit; L1 represents the inverter inductance on line L; L2 represents the inverter inductance on line N; Cm represents the parasitic capacitance of the photovoltaic array to the ground; Vcm represents the common-mode voltage generated across the parasitic capacitance; Vbus represents the BUS voltage.

[0028] According to Kirchhoff's voltage law, the voltage equation for the common-mode circuit can be written as follows:

[0029] -Va+VL1+Vg+Vcm=0 (1)

[0030] -Vb-VL2+Vcm=0 (2)

[0031] The common-mode voltage Vcm is obtained by adding equations (1) and (2); since VL1 = VL2;

[0032] Get Vcm=0.5*(Va+Vb-Vg)=0.5*(Va+Vb)-0.5*Vg (3)

[0033] The common-mode current Icm flowing through the parasitic capacitance is:

[0034] Icm=Cm*dCm / dt (4)

[0035] As shown in equation (4), the common-mode current is proportional to the rate of change of the common-mode voltage. Since Vg is the mains frequency voltage, the common-mode current generated by Vg on the parasitic capacitance can generally be ignored. Va and Vb are PWM high-frequency pulse voltages, and the common-mode current is mainly generated by these excitations. Therefore, the common-mode voltage of the grid-connected inverter in engineering can be approximately expressed as:

[0036] Vcm=0.5*(Va+Vb) (5)

[0037] From the above analysis, it can be seen that if Vcm can be made to a constant value, the common-mode current can be basically eliminated. That is, the PWM switching sequence used by the inverter bridge should ensure that the sum of the voltages at points Va and Vb relative to zero satisfies the following:

[0038] Va + Vb = constant (6)

[0039] 1) When the H5 topology is intact;

[0040] During the positive half-cycle of the grid current, when S5, S1, and S4 are turned on, the common-mode voltage is:

[0041] Vcm=0.5*(Va+Vb)=0.5*(Vpv+0)=0.5*Vpv (7)

[0042] When S1 is on and S5 and S4 are off, the common-mode voltage is:

[0043] Vcm=0.5*(Va+Vb)=0.5*(0.5*Vpv+0.5*Vpv)=0.5*Vpv (8)

[0044] From equations (7) and (8), we can see that the common-mode voltage Vcm = 0.5 * Vpv. When the PV voltage is constant, the common-mode voltage is a constant value, so the common-mode current will not be generated by the PWM high-frequency pulse voltage.

[0045] 2) When the S5 transistor (CE terminal) of the H5 topology is short-circuited (the H5 topology cannot work properly when the S5 transistor is open-circuited);

[0046] During the positive half-cycle of the grid current, when transistor S5 is short-circuited and transistors S1 and S4 are conducting, the common-mode voltage is:

[0047] Vcm=0.5*(Va+Vb)=0.5*(Vpv+0)=0.5*Vpv (9)

[0048] When S5 is short-circuited, S1 is on, and S4 is off, the common-mode voltage is:

[0049] Vcm=0.5*(Va+Vb)=0.5*(Vpv+0.5*Vpv)=0.75*Vpv (10)

[0050] As can be seen from equations (9) and (10), if their common-mode voltages are not equal, then the common-mode current will be generated by the PWM high-frequency pulse voltage.

[0051] It can be seen that if the collector and emitter of transistor S5 cannot conduct, the H5 topology cannot work properly and will not be connected to the grid; if the collector and emitter of transistor S5 are short-circuited, the H5 topology can work properly, but if it is connected to the grid at this time, it will generate a large common-mode current.

[0052] Therefore, this embodiment detects whether there is a short circuit fault in transistor S5 before grid connection. The photovoltaic inverter can only be allowed to connect to the grid after confirming that there is no short circuit at the collector-emitter junction of transistor S5. Specifically: Under the bus voltage, transistor S5 is not driven, and the voltage between the voltage divider resistors of the detection branch is sampled to obtain a first sample voltage. The first sample voltage is compared with a first threshold. If the first sample voltage is less than the first threshold, it is determined that transistor S5 has no short circuit fault, and grid connection is allowed; otherwise, grid connection is not allowed. Further, before grid connection, the following steps are included: Under the bus voltage, transistor S5 is driven, and the voltage between the voltage divider resistors of the detection branch is sampled to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that transistor S5 is conducting normally, and grid connection is allowed; otherwise, grid connection is not allowed. Specifically, the first and second sample voltages are obtained through the resistor voltage divider sampling terminals. The second threshold is greater than the first threshold.

[0053] Specific examples are as follows:

[0054] (1) Under a certain bus voltage, the sampling voltage Vc can be obtained through the voltage divider network of resistors R1, R2, R3, and R4; the sampling voltage Vc is sent to the MCU.

[0055] Vc=Vbus*R4 / (R1+R2+R3+R4) (11)

[0056] (2) Under a certain bus voltage, the ratio of resistors R1, R2, R3, and R4 is pre-designed. Before the inverter bridge opens the loop voltage, the S5 transistor is tested. The S5 transistor is not driven and the drive balance is low. (The drive balance of S1, S2, S3, and S4 is low). The MCU reads the Vc voltage value. If Vc < 0.5V, the S5 transistor is determined to be normal and there is no short circuit.

[0057] (3) Under a certain bus voltage, the ratio of resistors R1, R2, R3, and R4 is pre-designed. Before the inverter bridge opens the loop voltage, the S5 transistor is tested. The S5 transistor is driven and the drive balance is high. (The drive balance of S1, S2, S3, and S4 is low). The MCU reads the Vc voltage value. If Vc > 1V, it is determined that the S5 transistor is conducting normally.

[0058] (4) Allow photovoltaic inverters to be connected to the grid.

[0059] If the judgment result is opposite in step (2) or (3), the photovoltaic inverter is not allowed to be connected to the grid, or the photovoltaic inverter cannot work normally.

[0060] By following the steps above, it is possible to detect whether the S5 transistor in the H5 topology is short-circuited or unable to conduct; this can effectively avoid the common-mode current problem caused by the parasitic capacitance of the photovoltaic module to the ground in non-isolated photovoltaic inverters due to the short circuit of the S5 transistor.

[0061] Simulation Example

[0062] The values ​​of the voltage divider resistors R1, R2, R3, and R4 are selected according to... Figure 2 As shown, Ra, Rb, Rc, Rd and Re (5 PCS 220kΩ) are the equivalent resistances of R1, R2 and R3, and Rf (1 PCS 4.99kΩ) is the equivalent resistance of R4, forming a resistor voltage divider network; the resistor voltage divider sampling terminal 211 sends the voltage value Vc to the MCU for sampling.

[0063] The preset PV voltage is 350Vdc. Before the inverter bridge open-loop voltage is tested, the S5 transistor is checked. The S5 transistor is not driven, and the drive balance is low (S1 / S2 / S3 / S4 drive balance is low). The S5 transistor is not conducting. At this time, the MCU reads the voltage value of the resistor divider network, Vc = 34.23mV < 0.5V (indicating that the S5 transistor is normal and there is no short circuit); the test waveform is as follows. Figure 3 As shown.

[0064] The preset PV voltage is 350Vdc. Before the inverter bridge open-loop voltage is tested, transistor S5 is checked. When transistor S5 is driven, the drive balance is high (while the drive balance of S1 / S2 / S3 / S4 is low), and transistor S5 is turned on. At this time, the MCU reads the voltage value of the resistor divider network, Vc = 1.60V > 1V (indicating that transistor S5 is conducting normally); the test waveform is as follows. Figure 4 As shown.

[0065] Through the above theoretical analysis and test verification, it is possible to effectively detect whether the S5 transistor in the H5 topology is short-circuited or unable to conduct. This can avoid common-mode current problems caused by parasitic capacitance of photovoltaic modules to the ground in non-isolated photovoltaic inverters due to S5 transistor short circuits. It can also proactively detect whether key components and their functions in the inverter bridge are abnormal, thus achieving early detection, prevention, and alarm functions.

[0066] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are preferred embodiments. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and they should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A common-mode current control method for an H5 type non-isolated photovoltaic inverter, the photovoltaic inverter comprising an H5 inverter circuit, the H5 inverter circuit comprising switching transistors S1, S2, S3, S4 and S5, wherein switching transistors S1 and S2 are connected to form a first inverter bridge arm, switching transistors S3 and S4 are connected to form a second inverter bridge arm, and the collector of switching transistor S5 is electrically connected to the positive DC bus; characterized in that, The photovoltaic inverter also includes a detection branch, one end of which is electrically connected to the emitter of the switching transistor S5 and the other end is electrically connected to the negative DC bus; the detection branch includes multiple voltage divider resistors connected in series. The common-mode current control method includes: under the bus voltage, the switch S5 is not driven, the voltage between the voltage divider resistors of the detection branch is sampled to obtain a first sampled voltage, the first sampled voltage is compared with a first threshold, if the first sampled voltage is less than the first threshold, it is determined that the switch S5 has no short-circuit fault and grid connection is allowed; otherwise, grid connection is not allowed.

2. The common-mode current control method according to claim 1, characterized in that, The following steps are included before grid connection: Under the bus voltage, the switch S5 is driven to sample the voltage between the voltage divider resistors of the detection branch to obtain a second sample voltage. The second sample voltage is compared with a second threshold. If the second sample voltage is greater than the second threshold, it is determined that the switch S5 is conducting normally and grid connection is allowed. No, grid connection is not allowed.

3. The common-mode current control method according to claim 2, characterized in that, The second threshold is greater than the first threshold.

4. The common-mode current control method according to claim 1, characterized in that, The detection branch includes multiple first resistors and second resistors connected in series. A resistor voltage divider sampling terminal is connected between the first resistors and the second resistors. The first sampling voltage and the second sampling voltage are obtained through the resistor voltage divider sampling terminal.

5. The common-mode current control method according to claim 4, characterized in that, The resistance of the first resistor is greater than the resistance of the second resistor.

6. The common-mode current control method according to claim 4, characterized in that, Multiple first resistors are connected in series between the emitter of the switching transistor S5 and the resistor divider sampling terminal, and a second resistor is connected between the resistor divider sampling terminal and the negative DC bus. The resistance value of the first resistor is more than 40 times greater than the resistance value of the second resistor.

7. The common-mode current control method according to claim 4, characterized in that, The bases of the switching transistors S1, S2, S3, S4 and S5 and the resistor divider sampling terminals are all electrically connected to the MCU chip.

8. The common-mode current control method according to claim 1, characterized in that, Each of the switching transistors S1, S2, S3, S4 and S5 is connected in parallel with a diode in reverse.

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