A capacitor array and method applied to a 12-bit successive approximation analog-to-digital converter

Abstract

The application provides a capacitor array and method applied to a 12-bit successive approximation analog-to-digital converter, wherein the differential capacitor array comprises a first capacitor array and a plurality of cascaded second capacitor arrays, and is used for successive approximation conversion of more bits; a bridging capacitor is arranged between the first capacitor array and the plurality of second capacitor arrays; the equivalent weight of the maximum capacitor of the adjacent lower-level capacitor array is one fourth of the minimum capacitor of the upper-level capacitor array; two unit capacitors are arranged before the bridging capacitor and are switched in coordination, so that the equivalent weight of the highest bit capacitor after the bridging is unchanged, and the capacitor values of the first capacitor array and the second capacitor array on both sides of the bridging capacitor are sequentially decreased; the capacitor array under the capacitor configuration adopted by the application and the 2C U Compared with the bridging capacitor architecture, the application can save the area of 70 unit capacitors and significantly reduce the switching power consumption of the capacitors.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, specifically relating to a capacitor array and method for use in a 12-bit successive approximation analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) are widely used in various industrial applications, such as measurement, servo systems, and communications. Typically, medium-precision ADCs (10-bit to 12-bit) are the most common. For this level of precision, successive approximation ADCs (AADCs) are the best choice due to their simple structure, low power consumption, and ease of manufacturing. In successive approximation ADCs, the capacitor array is one of the most important modules, determining the chip's area and power consumption.

[0003] There are two main types of capacitor arrays: direct binary capacitor arrays and segmented binary capacitor arrays. For example, in a 12-bit analog-to-digital converter (ADC), the capacitor in the most significant bit is 2048 times the capacitor in the least significant bit, resulting in a total of 4096 capacitors in the circuit, posing a significant challenge to layout design. Therefore, direct binary capacitor arrays are generally only used in ADCs with fewer than 8 bits. The other type is segmented binary capacitor arrays. This technology uses series capacitors to achieve smaller capacitors with larger ones. For example, in an 8-bit capacitor array, the number of unit capacitors (CUs) from the most significant bit to the least significant bit in the direct binary array is 128, 64, 32, 16, 8, 4, 2, 1, respectively, totaling approximately 256 capacitors. Using a 4+4 segmented array, the number of unit capacitors from the most significant bit to the least significant bit is 8, 4, 2, 1; 8, 4, 2, 1. The second segment (8, 4, 2, 1) is connected in series with the first segment via CUs, forming equivalent capacitances of 1 / 2, 1 / 4, 1 / 8, and 1 / 16. At this point, the total number of capacitors is approximately 32, which simplifies the layout design.

[0004] For successive approximation analog-to-digital converters (ADCs) operating at megahertz speeds and above, redundant capacitors are often required for error correction. In this case, the bridging capacitor needs to be larger than the core count (CU). One approach is to use a fractional capacitor, such as 1.2CU, to provide 20% redundancy. However, this non-integer capacitor degrades the overall layout matching. Therefore, a more common industrial solution is to use 2CU for bridging, which provides an additional 100% redundancy. However, the area of ​​the second capacitor is doubled, and consequently, the switching power consumption also doubles. Therefore, both fractional and integer 2CU bridging have significant limitations. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a capacitor array and method for a 12-bit successive approximation analog-to-digital converter, which significantly reduces the area of ​​the capacitors and reduces the switching power consumption of the capacitors.

[0006] This invention is achieved through the following technical solution:

[0007] A capacitor array for use in a 12-bit successive approximation analog-to-digital converter, characterized in that it includes a comparator and a differential capacitor array;

[0008] Each differential capacitor array comprises a first capacitor array and multiple cascaded second capacitor arrays, and the equivalent weight of the maximum capacitance of an adjacent lower-level capacitor array is one-quarter of the minimum capacitance of the upper-level capacitor array; the first capacitor array and the multiple second capacitor arrays are connected by bridging capacitors, and the bridging capacitors are P groups of bridging capacitors C. BRI and N sets of bridging capacitors C BRI ;

[0009] The first capacitor array consists of 16 groups of binary capacitors, and the second capacitor array consists of 12 groups of binary capacitors. The capacitance values ​​of the first and second capacitor arrays decrease sequentially on both sides of the bridging capacitor.

[0010] The first capacitor array includes a first P-group capacitor array and a first N-group capacitor array, wherein the upper plate of the first P-group capacitor array and the P-group bridging capacitor C BRI The upper plates of all capacitors are connected to the positive input of the comparator. The upper plates of the first N-group capacitor array and the N-group bridge capacitors C BRI The upper plates are all connected to the inverting input of the comparator;

[0011] The second capacitor array includes a second P-group capacitor array and a second N-group capacitor array. The upper plate of the second P-group capacitor array is connected to a P-group bridging capacitor C. BRI The lower electrode of the second N-group capacitor array is connected to the upper electrode of the N-group capacitor array via N-group bridging capacitors C. BRI The lower electrode plate.

[0012] Furthermore, both the first capacitor array and the multiple second capacitor arrays include redundant capacitors for correcting quantization errors.

[0013] Furthermore, the capacitor switching in the first capacitor array adopts a bidirectional switching method.

[0014] Furthermore, the first P-group capacitor array includes capacitor C 1X Capacitor C 2X Capacitor C 3X Capacitor C 4X Capacitor C 5X Capacitor C 6X Capacitor C 6RX Capacitor C7 and capacitor C 8A ;

[0015] The capacitor C 1X 32CU Capacitor C 2X 16C U Capacitor C 3X 8C U Capacitor C 4X 4 CU Capacitor C 5X For 2C U Capacitor C 6X Capacitor C 6RX Capacitor C7 and capacitor C 8A All are C U .

[0016] Furthermore, the capacitor C 6RX These are redundant capacitors.

[0017] Furthermore, the first N groups of capacitor arrays include capacitor C 1Y Capacitor C 2Y Capacitor C 3Y Capacitor C 4Y Capacitor C 5Y Capacitor C 6Y Capacitor C 6RY Capacitor C7 and capacitor C 8B ;

[0018] The capacitor C 1Y 32C U Capacitor C 2Y 16C U Capacitor C 3Y 8C U Capacitor C 4Y 4 CU Capacitor C 5Y For 2C U Capacitor C 6Y Capacitor C 6RY Capacitor C7 and capacitor C 8A All are 8C U The capacitor C 6RY These are redundant capacitors.

[0019] Furthermore, both the second P-group capacitor array and the second N-group capacitor array include capacitor C. 8B Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 11R and capacitor C 12 ;

[0020] The capacitor C 8B 8C U The capacitor C9 is 8C. U Capacitor C 10 For 4C UCapacitor C 11 For 2C U Capacitor C 11R For 2C U Capacitor C 12 C U .

[0021] Furthermore, the capacitor C 11R These are redundant capacitors.

[0022] Furthermore, the P-group bridging capacitor C BRI and P group bridging capacitor C BRI The capacitance values ​​are all C. U .

[0023] A method for using a capacitor array in a 12-bit successive approximation analog-to-digital converter includes the following steps:

[0024] Under the control of an external clock, the comparator begins to compare. If the result of the comparator is 1, the lower plate of the capacitors in the first P-group capacitor array that are closest to the comparator is switched from power supply to ground, and the lower plate of the capacitors in the first N-group capacitor array that are closest to the comparator is switched from power supply to ground. If the result is 0, the lower plate of the capacitors in the first P-group capacitor array that are closest to the comparator is switched from ground to power supply, and the lower plate of the capacitors in the first N-group capacitor array that are closest to the comparator is switched from power supply to ground.

[0025] Under external clock control, the comparator compares the capacitors of the first P-group capacitor array and the first N-group capacitor array one by one, and compares the capacitors of the first capacitor array that are closest to the P-group bridge capacitor C. BRI and N sets of bridging capacitors C BRI After the capacitor is grounded or connected to a power supply, during the next comparison by the comparator under the control of an external clock, the capacitor C closest to the P group bridge capacitor in the second capacitor array... BRI and N sets of bridging capacitors C BRI The lower plate of the capacitor in the second P-group capacitor array is switched from power supply to ground, and is located near the N-group bridging capacitor C in the first capacitor array. BRI and N sets of bridging capacitors C BRI The lower plate of the capacitor in the second P group of capacitor array is switched from ground to power.

[0026] Under external clock control, the comparator pairs the bridge capacitor C in the second capacitor array closest to group P. BRI and N sets of bridging capacitors C BRI The capacitors are switched between power supply and ground until the last capacitor has been switched, thus ending the quantization process.

[0027] Compared with the prior art, the present invention has the following beneficial technical effects:

[0028] This invention provides a capacitor array and method for a 12-bit successive approximation analog-to-digital converter. The differential capacitor array includes a first capacitor array and multiple cascaded second capacitor arrays for successive approximation conversion of more bits. The first capacitor array and the multiple second capacitor arrays are connected by bridging capacitors, and the equivalent weight of the largest capacitor in an adjacent lower-level capacitor array is one-quarter of the smallest capacitor in the upper-level capacitor array. Two unit capacitors are added before the bridging capacitors for switching, thereby ensuring that the equivalent weight of the highest-order bit capacitor remains unchanged after bridging, compensating for insufficient weight. The first capacitor array consists of 16 groups of binary capacitors, and the second capacitor array consists of 12 groups of binary capacitors. The capacitance values ​​of the first and second capacitor arrays on both sides of the bridging capacitor decrease sequentially. The capacitor array configuration used in this application differs from the 2C configuration used in the prior art. U Compared to the bridged capacitor architecture, this application can save the area of ​​70 capacitor units, while significantly reducing the switching power consumption of the capacitors. Attached Figure Description

[0029] Figure 1 This is a capacitor array diagram for a 12-bit successive approximation analog-to-digital converter in a specific embodiment of the present invention;

[0030] Figure 2 This refers to the capacitor array used in existing technologies. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] This invention provides a capacitor array for use in a 12-bit successive approximation analog-to-digital converter, such as... Figure 1 As shown, it includes a comparator and a differential capacitor array;

[0035] Each differential capacitor array comprises a first capacitor array and multiple cascaded second capacitor arrays, and the equivalent weight of the maximum capacitance of an adjacent lower-level capacitor array is one-quarter of the minimum capacitance of the upper-level capacitor array; the first capacitor array and the multiple second capacitor arrays are connected by bridging capacitors, and the bridging capacitors are P groups of bridging capacitors C. BRI and N sets of bridging capacitors C BRI ;

[0036] The first capacitor array consists of 16 groups of binary capacitors, and the second capacitor array consists of 12 groups of binary capacitors. The capacitance values ​​of the first and second capacitor arrays on both sides of the bridging capacitor decrease sequentially.

[0037] Specifically, in the existing multi-segment bridging capacitor array, the bridging capacitor is 2CU. The capacitors before and after the bridging capacitor are independent, and the equivalent weight of the largest capacitor after bridging is required to be equal to half of the weight of the smallest capacitor before bridging to satisfy the overall binary relationship.

[0038] Furthermore, such as Figure 2 As shown, to ensure that the effective weight of the largest capacitor after bridging is equal to half the weight of the smallest capacitor before bridging to satisfy the overall binary relationship, that is, the effective weight of capacitor C8 must be half that of capacitor C7. At this point, the capacitance values ​​of capacitors C8, C9, C10, C11, and C12 are 16CU, 8CU, 4CU, 2CU, and 1CU, respectively, for a total of 39CU. To make the effective weight of capacitor C8 half that of capacitor C7, capacitor C... ADD=23CU, the total capacitance after bridging is 62CU. The series capacitance of the bridging capacitor and the second capacitor after it is 124 / 64, where capacitor C8 accounts for 16 / 62. Therefore, the equivalent capacitance of capacitor C8 before bridging is:

[0039]

[0040] Capacitor C8 is the largest capacitor in the second segment of the capacitor array. In this application, to reduce the capacitance value of capacitor C8 and thus the area of ​​the overall capacitor array, capacitor C8 is split into capacitor C8A and capacitor C8B. Capacitor C8A is located before the bridging capacitor, and capacitor C8B is located after the bridging capacitor. The capacitance value of capacitor C8A is 1CU, therefore its weight is 1; the capacitance value of capacitor C8B is 8CU, and the bridging capacitor is 1CU. The total capacitance after bridging is 31CU. The equivalent capacitance value of capacitor C8B before bridging is:

[0041]

[0042] To ensure that the actual weight of capacitor C8 remains 1 / 2, capacitors C8A and C8B are switched. Assuming capacitor C8A remains stationary, capacitor C8B at the end of the second P-group capacitor array switches from ground to power supply each time, and capacitor C8B at the end of the second N-group capacitor array switches from power supply to ground each time. Therefore, capacitor C8B effectively forms a weight of twice the 1 / 4 CU weight, resulting in a weight of 1 / 2 CU.

[0043] Based on this switching, since the weight of capacitor C8A is 1CU, if capacitor C8A at the end of the first P group capacitor array switches from power supply to ground, capacitor C8A at the end of the first N group capacitor array remains unchanged. This is equivalent to switching 1CU in reverse on the 1 / 2CU weight formed by the combination of capacitor C8B at the end of the second P group capacitor array and the end of the second N group capacitor array.

[0044] In summary, when capacitor C8A remains constant, switching C8B at the end of the second P-group capacitor array from ground to power, and switching C8B at the end of the second N-group capacitor array from power to ground, is equivalent to switching 1 / 2CU from ground to power. Conversely, when capacitor C8A at the end of the first P-group capacitor array switches from power to ground, and capacitor C8A at the end of the first N-group capacitor array remains constant, switching C8B at the end of the second P-group capacitor array from ground to power, and switching C8B at the end of the second N-group capacitor array from power to ground, is equivalent to switching 1 / 2CU from power to ground. Therefore, C8A and C8B together form the same 1 / 2CU weight as in the traditional structure, while the total capacitance value is significantly reduced.

[0045] The first capacitor array includes a first P-group capacitor array and a first N-group capacitor array, wherein the upper plate of the first P-group capacitor array and the P-group bridging capacitor CBRI The upper plates of all capacitors are connected to the positive input of the comparator. The upper plates of the first N-group capacitor array and the N-group bridge capacitors C BRI The upper plates are all connected to the inverting input of the comparator;

[0046] The second capacitor array includes a second P-group capacitor array and a second N-group capacitor array. The upper plate of the second P-group capacitor array is connected to a P-group bridging capacitor C. BRI The lower electrode of the second N-group capacitor array is connected to the upper electrode of the N-group capacitor array via N-group bridging capacitors C. BRI The lower electrode plate.

[0047] Furthermore, both the first capacitor array and the plurality of second capacitor arrays include redundant capacitors to provide additional capacitance on top of the binary gradient descent capacitor array to correct for quantization errors that may occur at higher bits.

[0048] Furthermore, the capacitors in the first capacitor array adopt a bidirectional switching method. Furthermore, the capacitors in the second capacitor array can also adopt a bidirectional switching method, which can accurately ensure that the common-mode output voltage is constant. However, since the second capacitor array has low-order capacitors with small weights, its influence on the common-mode output voltage can be ignored. Therefore, the second capacitor array is not divided into x and y parts. Its switching method is monotonic switching, that is, the capacitors of the P group of the second capacitor array or the N group of the second capacitor array switch from ground to power supply.

[0049] A preferred embodiment of the present invention is that the first P-group capacitor array includes capacitor C. 1X Capacitor C 2X Capacitor C 3X Capacitor C 4X Capacitor C 5X Capacitor C 6X Capacitor C 6RX Capacitor C7 and capacitor C 8A ;

[0050] The capacitor C 1X 32C U Capacitor C 2X 16C U Capacitor C 3X 8C U Capacitor C 4X 4 CU Capacitor C 5X For 2C U Capacitor C 6X Capacitor C 6RX Capacitor C7 and capacitor C 8A All are C U Specifically, the capacitor C 6RX These are redundant capacitors.

[0051] Furthermore, the first N groups of capacitor arrays include capacitor C 1Y Capacitor C 2Y Capacitor C 3Y Capacitor C 4Y Capacitor C 5Y Capacitor C 6Y Capacitor C 6RY Capacitor C7 and capacitor C 8B ;

[0052] The capacitor C 1Y 32C U Capacitor C 2Y 16C U Capacitor C 3Y 8C U Capacitor C 4Y 4 CU Capacitor C 5Y For 2C U Capacitor C 6Y Capacitor C 6RY Capacitor C7 and capacitor C 8A All are 8C U The capacitor C 6RY These are redundant capacitors.

[0053] Furthermore, both the second P-group capacitor array and the second N-group capacitor array include capacitor C. 8B Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 11R and capacitor C 12 ;

[0054] The capacitor C 8B 8C U The capacitor C9 is 8C. U Capacitor C 10 For 4C U Capacitor C 11 For 2C U Capacitor C 11R For 2C U Capacitor C 12 C U Specifically, the capacitor C 11R These are redundant capacitors.

[0055] Furthermore, the P-group bridging capacitor C BRI and P group bridging capacitor C BRI The capacitance values ​​are all C. U .

[0056] This invention provides a method for using a capacitor array in a 12-bit successive approximation analog-to-digital converter, comprising the following steps:

[0057] Under the control of an external clock, the comparator begins to compare. If the result of the comparator is 1, the lower plate of the capacitors in the first P-group capacitor array that are closest to the comparator is switched from power supply to ground, and the lower plate of the capacitors in the first N-group capacitor array that are closest to the comparator is switched from power supply to ground. If the result is 0, the lower plate of the capacitors in the first P-group capacitor array that are closest to the comparator is switched from ground to power supply, and the lower plate of the capacitors in the first N-group capacitor array that are closest to the comparator is switched from power supply to ground.

[0058] Under external clock control, the comparator compares the capacitors of the first P-group capacitor array and the first N-group capacitor array one by one, and compares the capacitors of the first capacitor array that are closest to the P-group bridge capacitor C. BRI and N sets of bridging capacitors C BRI After the capacitor is grounded or connected to a power supply, during the next comparison by the comparator under the control of an external clock, the capacitor C closest to the P group bridge capacitor in the second capacitor array... BRI and N sets of bridging capacitors C BRI The lower plate of the capacitor in the second P-group capacitor array is switched from power supply to ground, and is located near the N-group bridging capacitor C in the first capacitor array. BRI and N sets of bridging capacitors C BRI The lower plate of the capacitor in the second P group of capacitor array is switched from ground to power.

[0059] Under external clock control, the comparator pairs the bridge capacitor C in the second capacitor array closest to group P. BRI and N sets of bridging capacitors C BRI The capacitors are switched between power supply and ground until the last capacitor has been switched, thus ending the quantization process.

[0060] Specifically, during the sampling process, only the C values ​​of the first P group of capacitor arrays and the first N group of capacitor arrays are considered. 1X -C 6RY Participating in sampling, its lower plate is connected to the input signal; the C of the second P-group capacitor array 8B The lower plate is connected to the power supply, and the C of the second Nth group of capacitor array 8B The lower plate is connected to ground, and all other capacitors are grounded. The capacitors in the first P group and the first N group in the diagram are connected to ground. 6RX C 6RY The C of the second P group capacitor array and the second N group capacitor array 11R The purpose of this redundant capacitor is to provide additional capacitance on top of the binary gradient descent capacitor array to correct for quantization errors that may occur in the higher bits.

[0061] After sampling is complete, the first P group of capacitor array CiX (i = 1, 2, 3, 4, 5, 6, 6R) The lower plate of the capacitor is connected to the power supply, C iY (i = 1, 2, 3, 4, 5, 6, 6R) The lower plate of the capacitor is connected to ground; the first N-group capacitor array C iX (i = 1, 2, 3, 4, 5, 6, 6R) The lower plate of the capacitor is connected to ground, C iY The lower plate of capacitors (i = 1, 2, 3, 4, 5, 6, 6R) is connected to the power supply. The lower plates of the remaining capacitors are connected to ground and remain stationary. In this way, during the i-th comparison at the highest bit (i = 1, 2, 3, 4, 5, 6, 6R), the capacitors of the first P-group capacitor array and the first N-group capacitor array can be switched from power supply to ground or from ground to power supply, ensuring the common-mode stability of the output voltage.

[0062] For the low-order capacitor, if C i (i = 9, 10, 11, 12) can also be broken down into C. ix and C iy Bidirectional switching can be performed to accurately ensure that the common-mode output voltage is constant; however, since the second P-group capacitor array and the second N-group capacitor array are low-order capacitors with small weights, their influence on the common-mode output voltage can be ignored. Therefore, the capacitors of the first N-group capacitor array are not split into x and y parts, and their switching strategy is monotonic switching, that is, the capacitors of the second P-group capacitor array and the second N-group capacitor array can only switch from ground to power supply.

[0063] Under the control of an external clock, the comparator begins its first comparison. If the comparator's result is 1, then the capacitors of the first P-group capacitor array are... 1X When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 1X The lower plate of the capacitor is switched from ground to power; if the result is 0, the lower plate of capacitor C1Y in the first P group of capacitor array is switched from ground to power, and capacitor C in the first N group of capacitor array is switched from ground to power. 1Y The lower plate of the capacitor is switched from the power supply to ground.

[0064] Under the control of an external clock, the comparator begins its second comparison. If the comparator's result is 1, then the capacitors of the first P-group array are... 2X When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 2X The lower plate of the capacitor is switched from ground to power; if the result is 0, then the capacitor C of the first P-group capacitor array is switched. 2Y When the lower plate of the capacitor is switched from ground to power, the capacitor C of the first Nth group of capacitor array... 2Y The lower plate of the capacitor is switched from the power supply to ground.

[0065] Under the control of an external clock, the comparator begins its third comparison. If the comparator's result is 1, then the capacitors of the first P-group capacitor array are... 3X When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 3X The lower plate of the capacitor is switched from ground to power; if the result is 0, then the capacitor C of the first P-group capacitor array is switched. 3Y When the lower plate of the capacitor is switched from ground to power, the capacitor C of the first Nth group of capacitor array... 3Y The lower plate of the capacitor is switched from the power supply to ground.

[0066] Under the control of an external clock, the comparator begins its fourth comparison. If the comparator's result is 1, then the capacitors in the first P-group capacitor array are... 4X When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 4X The lower plate of the capacitor is switched from ground to power; if the result is 0, then the capacitor C of the first P-group capacitor array is switched. 4Y When the lower plate of the capacitor is switched from ground to power, the capacitor C of the first Nth group of capacitor array... 4Y The lower plate of the capacitor is switched from the power supply to ground.

[0067] Under the control of an external clock, the comparator begins its fifth comparison. If the comparator's result is 1, then the capacitors of the first P-group capacitor array are... 5X When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 5X The lower plate of the capacitor is switched from ground to power; if the result is 0, then the capacitor C of the first P-group capacitor array is switched. 5Y When the lower plate of the capacitor is switched from ground to power, the capacitor C of the first Nth group of capacitor array... 5Y The lower plate of the capacitor is switched from the power supply to ground.

[0068] Under the control of an external clock, the comparator begins its sixth comparison. If the comparator's result is 1, then the capacitors of the first P-group capacitor array are... 6X When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 6X The lower plate of the capacitor is switched from ground to power; if the result is 0, then the capacitor C of the first P-group capacitor array is switched. 6Y When the lower plate of the capacitor is switched from ground to power, the capacitor C of the first Nth group of capacitor array... 6Y The lower plate of the capacitor is switched from the power supply to ground.

[0069] Under the control of an external clock, the comparator begins its 7th comparison. If the comparator's result is 1, then the capacitors of the first P-group array are... 6RX When the lower plate of the capacitor is switched from power supply to ground, the capacitor C of the first Nth group of capacitor array... 6RXThe lower plate of the capacitor is switched from ground to power; if the result is 0, then the capacitor C of the first P-group capacitor array is switched. 6RY When the lower plate of the capacitor is switched from ground to power, the capacitor C of the first Nth group of capacitor array... 6RY The lower plate of the capacitor is switched from the power supply to ground.

[0070] Under the control of an external clock, the comparator begins its 8th comparison. If the comparator's result is 1, the lower plate of capacitor C7 in the first N-group capacitor array is switched from ground to power. If the result is 0, the lower plate of capacitor C7 in the first P-group capacitor array is switched from ground to power.

[0071] Under the control of an external clock, the comparator begins its 9th comparison and sets the capacitor C at the end of the first P-group capacitor array. 8B The lower plate is switched from power supply to ground, and the capacitor C at the end of the first N-group capacitor array is switched off. 8B The lower electrode plate switches from ground to power.

[0072] If the comparator result is 1, then the capacitor C division is no longer performed. 8B Switching to other values; if the result is 0, then switch the C of the first P group of capacitor array. 8A The lower plate of the capacitor is switched from ground to power.

[0073] Under the control of an external clock, the comparator begins its 10th comparison. If the comparator's result is 1, the lower plate of capacitor C9 in the second N-group capacitor array is switched from ground to power. If the result is 0, the lower plate of capacitor C9 in the second P-group capacitor array is switched from ground to power.

[0074] Under the control of an external clock, the comparator begins to perform operations 11 to 20, switching the remaining capacitors in the same way as in operation 10.

[0075] The capacitor array described in this application consists of 58 capacitors with a total capacitance of 318C. U Compared to existing 2C technologies U The improvement in the bridged capacitor architecture is significant; in this application, the bridge capacitor C BRI =2C U C8 = 16C U The equivalent weight of C8 is 1 / 2, which is different from the 2C in the prior art. U The bridged capacitor architecture's capacitor array contains a total of 388 capacitors. U In comparison, this invention saves the area of ​​70 capacitor units.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A capacitor array for use in a 12-bit successive approximation analog-to-digital converter, characterized in that, Includes comparators and differential capacitor arrays; Each differential capacitor array includes a first capacitor array and multiple cascaded second capacitor arrays, and the equivalent weight of the maximum capacitance of the adjacent lower-level capacitor array is one-quarter of the minimum capacitance of the upper-level capacitor array. The first capacitor array and the multiple second capacitor arrays are all connected by bridging capacitors, and the bridging capacitors are P groups of bridging capacitors C. BRI and N sets of bridging capacitors C BRI ; The first capacitor array consists of 16 groups of binary capacitors, and the second capacitor array consists of 12 groups of binary capacitors. The capacitance values ​​of the first and second capacitor arrays decrease sequentially on both sides of the bridging capacitor. The first capacitor array includes a first P-group capacitor array and a first N-group capacitor array, wherein the upper plate of the first P-group capacitor array and the P-group bridging capacitor C BRI The upper plates of all capacitors are connected to the positive input of the comparator. The upper plates of the first N-group capacitor array and the N-group bridge capacitors C BRI The upper plates are all connected to the inverting input of the comparator; The second capacitor array includes a second P-group capacitor array and a second N-group capacitor array. The upper plate of the second P-group capacitor array is connected to a P-group bridging capacitor C. BRI The lower electrode of the second N-group capacitor array is connected to the upper electrode of the N-group capacitor array via N-group bridging capacitors C. BRI The lower electrode plate; The first P-group capacitor array includes capacitor C 1X Capacitor C 2X Capacitor C 3X Capacitor C 4X Capacitor C 5X Capacitor C 6X Capacitor C 6RX Capacitor C7 and capacitor C 8A ; The capacitor C 1X 32C U Capacitor C 2X 16C U Capacitor C 3X 8C U Capacitor C 4X 4 CU Capacitor C 5X For 2C U Capacitor C 6X Capacitor C 6RX Capacitor C7 and capacitor C 8A All are C U ; The capacitor C 6RX For redundant capacitors; The first N groups of capacitor arrays include capacitor C 1Y Capacitor C 2Y Capacitor C 3Y Capacitor C 4Y Capacitor C 5Y Capacitor C 6Y Capacitor C 6RY And capacitor C7; The capacitor C 1Y 32C U Capacitor C 2Y 16C U Capacitor C 3Y 8C U Capacitor C 4Y 4 CU Capacitor C 5Y For 2C U Capacitor C 6Y Capacitor C 6RY Capacitor C7 and capacitor C 8A All are 8C U The capacitor C 6RY For redundant capacitors; Both the second P-group capacitor array and the second N-group capacitor array include capacitor C. 8B Capacitor C9, Capacitor C 10 Capacitor C 11 Capacitor C 11R and capacitor C 12 ; The capacitor C 8B 8C U The capacitor C9 is 8C. U Capacitor C 10 For 4C U Capacitor C 11 For 2C U Capacitor C 11R For 2C U Capacitor C 12 C U ; The capacitor C 11R The P-group bridging capacitors C are redundant capacitors. BRI and P group bridging capacitor C BRI The capacitance values ​​are all C. U .

2. The capacitor array for a 12-bit successive approximation analog-to-digital converter according to claim 1, characterized in that, Both the first capacitor array and the multiple second capacitor arrays include redundant capacitors for correcting quantization errors.

3. The capacitor array for a 12-bit successive approximation analog-to-digital converter according to claim 1, characterized in that, The capacitor switching in the first capacitor array adopts a bidirectional switching method.

4. A method for using a capacitor array in a 12-bit successive approximation analog-to-digital converter, characterized in that, A capacitor array for a 12-bit successive approximation analog-to-digital converter according to any one of claims 1-3 includes the following steps: Under the control of an external clock, the comparator begins to compare. If the result of the comparator is 1, the lower plate of the capacitors in the first P-group capacitor array that are closest to the comparator is switched from power supply to ground, and the lower plate of the capacitors in the first N-group capacitor array that are closest to the comparator is switched from power supply to ground. If the result is 0, the lower plate of the capacitors in the first P-group capacitor array that are closest to the comparator is switched from ground to power supply, and the lower plate of the capacitors in the first N-group capacitor array that are closest to the comparator is switched from power supply to ground. Under external clock control, the comparator compares the capacitors of the first P-group capacitor array and the first N-group capacitor array one by one, and compares the capacitors of the first capacitor array that are closest to the P-group bridge capacitor C. BRI and N sets of bridging capacitors C BRI After the capacitor is grounded or connected to a power supply, during the next comparison by the comparator under the control of an external clock, the capacitor C closest to the P group bridge capacitor in the second capacitor array... BRI and N sets of bridging capacitors C BRI The lower plate of the capacitor in the second P-group capacitor array is switched from power supply to ground, and is located near the N-group bridging capacitor C in the first capacitor array. BRI and N sets of bridging capacitors C BRI The lower plate of the capacitor in the second P group of capacitor array is switched from ground to power. Under external clock control, the comparator pairs the bridge capacitor C in the second capacitor array closest to group P. BRI and N sets of bridging capacitors C BRI The capacitors are switched between power supply and ground until the last capacitor has been switched, thus ending the quantization process.

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