Data processing method and device, driver, and display device

Abstract

A data processing method comprises: receiving a first data signal and a first clock signal from at least one driver; wherein the first data signal comprises a clock signal segment and a compensated data signal segment, the clock signal segment precedes the compensated data signal segment, and the clock signal segment is separated from the compensated data signal segment by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; when the phase error of the clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset time length, delaying one of the compensated data signal segment in the first data signal and the first clock signal, so that the time interval between the start time of the first valid signal of the compensated data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than the second preset time length.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a data processing method and device, a driver, and a display device. Background Art

[0002] Self-luminous devices have the advantages of high brightness, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, and high luminous efficiency. They are widely used in various terminal display products with high-resolution color screens. Summary of the invention

[0003] On the one hand, a data processing method is provided. The data processing method comprises: receiving a first data signal and a first clock signal from at least one driver; wherein the first data signal comprises a clock signal segment and a compensation data signal segment, the order of the clock signal segment is before the compensation data signal segment, and the clock signal segment and the compensation data signal segment are separated by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; and, when the phase error of the clock signal segment in the first data signal compared with the first clock signal is greater than or equal to a second preset time length, delaying one of the compensation data signal segment in the first data signal and the first clock signal, so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero, and less than the second preset time length.

[0004] In some embodiments, the delaying of one of the compensation data signal segment in the first data signal and the first clock signal comprises: registering one of the first data signal and the first clock signal according to a second clock signal so that a phase error of the clock signal segment compared to the first clock signal is less than a second preset duration. The frequency of the second clock signal is greater than the frequency of the first clock signal.

[0005] In some embodiments, delaying one of the compensation data signal segment in the first data signal and the first clock signal includes: performing N signal inversion processes on one of the first clock signal and the first data signal so that a phase error of the clock signal segment compared to the first clock signal is less than a second preset duration, where N is an even number greater than zero.

[0006] In some embodiments, the second preset duration is greater than zero and less than or equal to half of a pulse width of the first clock signal.

[0007] In some embodiments, the phase error amount is an overlap duration between a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal.

[0008] In some embodiments, the phase error amount is a difference between a pulse width of the first clock signal and an overlap time length between a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal.

[0009] In some embodiments, the data processing method also includes: performing logical operations on the clock signal segments in the first clock signal and the first data signal to obtain a pulse overlap characterization signal; wherein the pulse overlap characterization signal includes: a first pulse overlap characterization signal and a second pulse overlap characterization signal; the first pulse overlap characterization signal is configured to characterize that the pulses of the clock signal segments in the first data signal overlap with the pulses of the first clock signal, and the second pulse overlap characterization signal is configured to characterize that the clock signal segments in the first data signal do not overlap with the pulses of the first clock signal; based on the duration of the first pulse overlap characterization signal, the phase error amount between the pulses of the clock signal segments in the first data signal and the pulses of the first clock signal is obtained.

[0010] In some embodiments, when the phase error is the overlap duration of a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal, the logic operation is an AND operation. When the phase error is the difference between the pulse width of the first clock signal and the overlap duration of a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal, the logic operation is an XOR operation.

[0011] In some embodiments, before receiving the first data signal and the first clock signal from at least one driver, the data processing method further includes: transmitting a request instruction to the at least one driver, wherein the request instruction is configured to instruct the at least one driver to transmit the first data signal and the first clock signal.

[0012] In some embodiments, the data processing method also includes: in response to the first clock signal, obtaining compensation data according to the compensation data signal segment in the first data signal; receiving a frame of image data, and obtaining a second data signal according to the compensation data and the frame of image data; and transmitting the second data signal to the at least one driver.

[0013] On the other hand, a data processing method is provided. The data processing method includes: receiving a third clock signal from a data processing device, obtaining a first clock signal according to the third clock signal; obtaining a compensated data signal segment; obtaining a first data signal according to the first clock signal and the compensated data signal segment; wherein the first data signal includes a clock signal segment and the compensated data signal segment; the order of the clock signal segment is before the compensated data signal segment; the clock signal segment and the compensated data signal segment are separated by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; the phase error of the clock signal segment in the first data signal compared to the first clock signal is zero; and transmitting the first data signal and the first clock signal to the data processing device.

[0014] In some embodiments, transmitting the first data signal and the first clock signal to the data processing device includes: transmitting the first data signal and the first clock signal to the data processing device in response to a request instruction from the data processing device.

[0015] In some embodiments, obtaining the compensation data signal segment includes: obtaining the compensation data signal segment according to a sensing signal from a display panel.

[0016] In some embodiments, the data processing method further includes: receiving a second data signal from the data processing device; and transmitting a third data signal to a display panel according to the second data signal to compensate for the display of the display panel.

[0017] In another aspect, a data processing device is provided. The data processing device includes a first communication interface and a first processor. The first communication interface is configured to receive a first clock signal and a first data signal from at least one driver. The first data signal includes a clock signal segment and a compensation data signal segment, the clock signal segment precedes the compensation data signal segment, the clock signal segment is separated from the compensation data signal segment by a first preset time length, and the clock signal segment and the first clock signal have the same period and duty cycle.

[0018] The first processor is configured to delay one of a compensation data signal segment in the first data signal and the first clock signal when a phase error amount of a clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset duration, so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than the second preset duration.

[0019] In some embodiments, the first processor includes a register. The register is configured to register one of the first data signal and the first clock signal according to a second clock signal, so that the phase error of the clock signal segment compared to the first clock signal is less than a second preset duration. The frequency of the second clock signal is greater than the frequency of the first clock signal.

[0020] In some embodiments, the first processor includes a signal inversion processor. The signal inversion processor is configured to perform N signal inversion processes on one of the first clock signal and the first data signal so that the phase error of the clock signal segment compared to the first clock signal is less than a second preset duration. Wherein N is an even number greater than zero.

[0021] In some embodiments, the first processor further includes: a logic operation processor configured to perform a logic operation on the first clock signal and the clock signal segments in the first data signal to obtain a pulse overlap characterization signal.

[0022] Among them, the pulse overlap characterization signal includes: a first pulse overlap characterization signal and a second pulse overlap characterization signal; the first pulse overlap characterization signal is configured to characterize that the pulses of the clock signal segment in the first data signal overlap with the pulses of the first clock signal, and the second pulse overlap characterization signal is configured to characterize that the clock signal segment in the first data signal does not overlap with the pulses of the first clock signal.

[0023] The logic operation processor is further configured to obtain a phase error between a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal according to a duration of the first pulse overlapping the characterization signal.

[0024] In another aspect, a data processing device is provided, wherein the data processing device is a chip, and the chip is configured to implement the data processing method as described in any of the above embodiments.

[0025] On the other hand, a driver is provided. The driver includes a second communication interface and a second processor. The second communication interface is configured to receive a third clock signal from a data processing device. The second processor is configured to obtain a first clock signal according to the third clock signal, and obtain a compensated data signal segment, and obtain a first data signal according to the first clock signal and the compensated data signal segment. Wherein, the first data signal includes a clock signal segment and a compensated data signal segment; the order of the clock signal segment is before the compensated data signal segment; the clock signal segment and the compensated data signal segment are separated by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; the phase error of the clock signal segment in the first data signal compared to the first clock signal is zero. The second communication interface is also configured to transmit the first data signal and the first clock signal to the data processing device.

[0026] In some embodiments, the second processor includes: an analog-to-digital converter, a clock signal processor, and a data signal processor. The analog-to-digital converter is configured to obtain the compensated data signal segment. The clock signal processor is configured to obtain the first clock signal according to the third clock signal. The data signal processor is configured to obtain the first data signal according to the first clock signal and the compensated data signal segment.

[0027] In another aspect, a display device is provided. The display device comprises: a data processing device as described in any of the above embodiments, at least one driver as described in any of the above embodiments, a circuit board, and a display panel. The circuit board is coupled to the data processing device and at least one of the drivers. The display panel is coupled to at least one of the drivers.

[0028] In another aspect, a non-transitory computer-readable storage medium is provided. The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed on a processor, the processor executes one or more steps in the data processing method described in any of the above embodiments.

[0029] In another aspect, a computer program product is provided, wherein the computer program product comprises computer program instructions, and when the computer program instructions are executed on a computer, the computer program instructions cause the computer to execute one or more steps of the data processing method as described in any of the above embodiments.

[0030] In another aspect, a computer program is provided. When the computer program is executed on a computer, the computer program enables the computer to execute one or more steps of the data processing method described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0032] Figure 1 is a structural diagram of a display device according to some embodiments;

[0033] Figure 2 is a structural diagram of a sub-pixel according to some embodiments;

[0034] Figure 3 is a structural diagram of a pixel circuit according to some embodiments;

[0035] Figure 4 is another structural diagram of a display device according to some embodiments;

[0036] Figure 5A is another structural diagram of a display device according to some embodiments;

[0037] Figure 5B is another structural diagram of a display device according to some embodiments;

[0038] Figure 6 is a flow chart of a data processing method according to some embodiments;

[0039] Fig. 7A is a timing diagram of a first clock signal and a first data signal according to some embodiments;

[0040] Figure 7B is another timing diagram of a first clock signal and a first data signal according to some embodiments;

[0041] Fig. 8A is another timing diagram of a first clock signal and a first data signal according to some embodiments;

[0042] Figure 8B is another timing diagram of a first clock signal and a first data signal according to some embodiments;

[0043] Fig. 9 is a timing diagram of a first clock signal and a second clock signal according to some embodiments;

[0044] Fig.10is a timing diagram of a first data signal according to some embodiments;

[0045] FIG. 11A to FIG. 11C is another structural diagram of a display device according to some embodiments;

[0046] Fig.12 is another flow chart of a data processing method according to some embodiments;

[0047] Fig.13 is a timing diagram of a first clock signal and a third clock signal according to some embodiments;

[0048] Fig.14 is another structural diagram of a display device according to some embodiments;

[0049] Fig.15A is a structural diagram of a data processing device according to some embodiments;

[0050] Fig. 15B is another structural diagram of a data processing device according to some embodiments;

[0051] Fig.16 is another structural diagram of a display device according to some embodiments. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0057] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] Embodiments of the present disclosure provide a display device. Exemplarily, the display device may be any device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, the display device may be one of a variety of electronic devices, and the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. The embodiments of the present disclosure do not impose any special restrictions on the specific form of the above-mentioned display device.

[0061] In some embodiments, Figure 1 As shown, the display device 200 includes a display panel 100. The display panel 100 has an active area (AA) and a peripheral area S. The peripheral area S is at least located on one side outside the AA area.

[0062] The display panel 100 includes a plurality of sub-pixels P disposed in the AA region. For example, the plurality of sub-pixels P may be arranged in an array. Figure 1 Sub-pixels P arranged in a row in the X direction are called the same pixel. Figure 1 The sub-pixels P arranged in a row in the Y direction are called pixels in the same column.

[0063] Exemplarily, the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; for example, the first color, the second color, and the third color are three primary colors; for example, the first color, the second color, and the third color are red, green, and blue, respectively; that is, the plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0064] In some embodiments, Figure 2 As shown, each sub-pixel P includes a pixel circuit 101 and a light emitting device L. The pixel circuit 101 is coupled to the light emitting device L.

[0065] For example, the light emitting device L may be an OLED (Organic Light Emitting Diode) or an LED (Light Emitting Diode).

[0066] It should be noted that the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, and can be designed according to actual conditions. Exemplarily, the pixel circuit is composed of electronic devices such as thin film transistors (Thin Film Transistor, referred to as TFT), capacitors (Capacitance, referred to as C), etc. For example, the pixel circuit may include two thin film transistors (a switching transistor and a driving transistor) and a capacitor to form a 2T1C structure; of course, the pixel circuit may also include more than two thin film transistors (multiple switching transistors and a driving transistor) and at least one capacitor, for example, refer to Figure 3 , the pixel circuit may include a capacitor and three transistors (two switching transistors and one driving transistor) to form a 3T1C structure.

[0067] In some embodiments, Figure 1 As shown, the display panel 100 further includes a plurality of gate lines GL and a plurality of data lines DL. Figure 1 The data lines DL extend in the X direction. Figure 1 The gate line GL is configured to transmit a scan signal, and the data line DL is configured to transmit a data signal, and the data signal transmitted on the data line is a data signal for display. Exemplarily, each pixel circuit 101 is coupled to at least one gate line GL and one data line DL, and the gate line GL and the data line DL provide a working signal to the pixel circuit 101, so that the pixel circuit 101 generates a drive signal, and transmits the drive signal to the light-emitting device L to drive the light-emitting device L to emit light. Exemplarily, each row of pixel circuits is coupled to two gate lines; for example, one of the two gate lines transmits a first scan signal (G1) to the pixel circuit, and the other gate line transmits a second scan signal (G2) to the pixel circuit.

[0068] In some embodiments, Figure 1 As shown, the display panel 100 further includes a plurality of sensing lines SL. For example, the plurality of sensing lines SL are arranged along Figure 1 The pixel circuit 101 is coupled to the sensing line SL. The driver 400 is coupled to the plurality of sensing lines SL. The display panel 100 transmits the sensing signal to the driver 400 through the sensing line SL. It can be understood that the sensing signal includes information of the driving transistor of the pixel circuit (e.g., the threshold voltage, mobility, etc. of the driving transistor).

[0069] For example, Figure 3 As shown, the control electrode (gate) of a switch transistor M1 is used to receive a first scan signal G1 from a gate line GL1. The first electrode of the switch transistor M1 is coupled to the data line DL to receive the data signal Vdata transmitted on the data line DL. The second electrode of the switch transistor M1 is coupled to the control electrode of the drive transistor M2, and the second electrode of the drive transistor M2 is coupled to the first voltage terminal V1, for example, the first voltage of the first voltage terminal V1 is a high voltage (VDD), and the first electrode (source) of the drive transistor M2 is coupled to the first electrode of the light-emitting device L. The second electrode of the light-emitting device L is coupled to the second voltage terminal V2, for example, the second voltage of the second voltage terminal V2 is a low voltage (VSS). The first end of the storage capacitor Cst is coupled to the second electrode of the switch transistor M1 and the control electrode of the drive transistor M2, and the second end of the storage capacitor Cst is coupled to the first electrode of the drive transistor M2 and the first electrode of the light-emitting device L. The control electrode of the sensing transistor M3 (i.e., another switch transistor) is used to receive a second scan signal G2 from a gate line GL2. The first electrode of the sensing transistor M3 is coupled to the second end of the storage capacitor Cst, the second electrode of the driving transistor M2 and the first electrode of the light emitting device L, and the second electrode of the sensing transistor M3 is coupled to the sensing line SL. In this case, when the driving transistor M2 is turned on, the sensing line is discharged through the sensing transistor M3, so that the voltage of the second electrode of the driving transistor M2 changes.

[0070] Thus, after the driving transistor M2 is turned on, the detection circuit is discharged through the sensing transistor M3 or the capacitor or parasitic capacitor set on the sensing line is charged through the sensing transistor M3, so that the source voltage Vs of the driving transistor M2 changes. When the source voltage Vs of the driving transistor M2 is equal to the difference between the gate voltage Vg of the driving transistor M2 and the threshold voltage Vth of the driving transistor, the driving transistor M2 will be cut off, and the source voltage Vs of the driving transistor M2 will no longer change. In this case, after the driving transistor M2 is cut off, the source voltage after the cut-off (that is, the source voltage Vb after the driving transistor M2 is cut off) can be obtained from the source of the driving transistor M2 through the turned-on sensing transistor M3. After obtaining the cut-off source voltage Vb, the threshold voltage of the driving transistor M2 can be obtained (for example, Vth=Vdata-Vb). For example, the sensing signal contains information about the threshold voltage of the driving transistor in the pixel circuit.

[0071] In some embodiments, Figure 1 As shown, the display device 200 further includes a data processing device 300 , a driver 400 and a circuit board 500 . The circuit board 500 is coupled to the data processing device 300 and the driver 400 .

[0072] Exemplarily, the driver 400 is coupled to the display panel 100, for example, the driver 400 is bonded to the display panel 100. Exemplarily, the driver 400 may adopt a source driver (Source IC, S-IC). Exemplarily, the driver 400 may adopt a COF (Chip On Film) process, that is, the driver 400 is disposed on an FPC (Flexible Printed Circuit Board) and bonded to the display panel 100 through the FPC.

[0073] The driver 400 is configured to provide a signal to the display panel 100. For example, the signal may be a data signal; for example, a plurality of data lines DL in the display panel 100 may transmit the data signal. Exemplarily, each pixel in the display panel may realize a corresponding grayscale display according to the data signal, so that the display panel displays an image corresponding to the data signal.

[0074] Exemplarily, the data processing device 300 may adopt a timing controller (TCON), a system-on-a-Chip (SoC), or a FPGA (Field-Programmable Gate Array).

[0075] Exemplarily, the circuit board 500 may be a PCB (Printed Circuit Board), ie, XPCB.

[0076] In some embodiments, Figure 5A As shown, the circuit board 500 includes a plurality of transmission channels 501. Each driver 400 is coupled to a plurality of transmission channels 501. The driver 400 transmits signals to the data processing device 300 through the plurality of transmission channels 501. For example, the transmission channels 501 may be signal lines. Figure 5A As shown, the multiple transmission channels 501 coupled to each driver 400 are respectively coupled to the data processing device 300 .

[0077] In other embodiments, Figure 5B As shown, the circuit board 500 further includes a plurality of transmission master channels 502. Each transmission master channel 502 is coupled to the data processing device 300. A plurality of transmission channels 501 are coupled to one transmission master channel 502, and the one transmission master channel 502 transmits the same signal as the plurality of transmission channels 501 coupled thereto. For example, the transmission channels 501 for transmitting the first clock signal, to which the plurality of drivers 400 are respectively coupled, are coupled to one transmission master channel 502 for transmitting the first clock signal. In this way, the number of interfaces of the data processing device 300 can be reduced.

[0078] Each transmission channel transmits one signal; for example, when the driver transmits two signals to the data processing device, the driver is coupled to the two transmission channels, one of the two transmission channels transmits one of the two signals, and the other of the two transmission channels transmits the other of the two signals.

[0079] It is understandable that the position at which the driver is coupled to the circuit board will affect the distance between the driver and the data processing device, making the distance between the driver and the data processing device different, and the lengths of the various transmission channels to which the driver is coupled may also be different. In this case, the driver transmits different signals through different transmission channels. Since the lengths of the various transmission channels are different, the phases of different signals received by the data processing device will be different, that is, there will be phase differences between different signals, which can easily lead to errors in the process of the data processing device processing the signals from the driver.

[0080] The embodiment of the present disclosure provides a data processing method. The data processing method can be applied to a data processing device (such as the data processing device 300 in the text). Figure 6 As shown, the data processing method includes:

[0081] S10 , receiving a first data signal and a first clock signal from at least one driver. For example, the data processing device 300 receives a first data signal and a first clock signal from at least one driver 400 .

[0082] Exemplarily, the data processing device may process the first data signal and the first clock signal corresponding to one driver at a time. For example, in the case where at least one driver is a plurality of drivers, the plurality of drivers sequentially transmit the corresponding first data signal and the first clock signal to the data processing device, for example, the plurality of drivers output serially, and the data processing device sequentially processes the received first data signal and the first clock signal. Alternatively, exemplarily, the data processing device may process the first data signal and the first clock signal of at least one driver at the same time. For example, in the case where at least one driver is a plurality of drivers, the plurality of drivers may output the first data signal and the first clock signal at the same time, for example, the plurality of drivers output in parallel, and the data processing device synchronously processes the received first data signals and the first clock signals of the plurality of drivers.

[0083] The first data signal includes a clock signal segment and a compensation data signal segment. The clock signal segment precedes the compensation data signal segment, and the clock signal segment and the compensation data signal segment are separated by a first preset time length.

[0084] Exemplarily, in the process of receiving the first data signal, the data processing device receives the clock signal segment before the compensated data signal segment because the clock signal segment is in an order before the compensated data signal segment. In addition, the clock signal segment is separated from the compensated data signal by a first preset time length, that is, the time length between the end time of the clock signal segment and the start time of the compensated data signal is the first preset time length. Therefore, after the data processing device receives the clock signal segment in the first data signal, it receives the compensated data signal segment in the first data signal after the first preset time length.

[0085] It should be noted that the first preset duration can be designed according to actual conditions and is not limited here. For example, the first preset duration can be the duration of a clock cycle; or, the first preset duration can be the duration of a pulse; or, the first preset duration can be zero, so that the end time of the clock signal segment and the start time of the compensation data signal are the same time, that is, the clock signal segment and the compensation data signal are continuous. Exemplarily, within the range of the first preset duration, the first data signal is a low-level signal (e.g., a DC low-level signal).

[0086] Wherein, the clock signal segment and the first clock signal have the same period and duty cycle. Exemplarily, the first clock signal includes multiple pulses, and the multiple pulses are periodically distributed; the clock signal segment includes at least two pulses, and at least two pulses are continuously distributed according to the distribution period of the multiple pulses in the first clock signal. The pulse width in the first clock signal is the same as the pulse width in the clock signal segment. It should be noted that the pulse described in the text refers to a high-level signal, and one pulse refers to a high-level signal segment.

[0087] S20. When a phase error of a clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset duration, delay one of the compensation data signal segment in the first data signal and the first clock signal so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than the second preset duration.

[0088] Exemplarily, the second preset duration is greater than zero and less than or equal to half of the pulse width of the first clock signal; that is, the second preset duration is greater than zero and less than or equal to half of the pulse width of the clock signal segment. For example, the second preset duration is half of the pulse width of the first clock signal.

[0089] It should be noted that the sampling trigger edge of the pulse refers to the data processing device sampling the compensation data signal segment at the moment of the sampling trigger edge of the pulse of the first clock signal, and analyzing the sampled data to obtain the compensation data; exemplarily, the sampling trigger edge of the pulse can be the rising edge or the falling edge of the pulse.

[0090] Understandably, reference Fig. 7A and Figure 7B , after the end time of the clock signal segment CK of the first data signal DataA, a first preset time length T passes, and the end time of the first preset time length T is the start time of the compensation data signal segment DataO of the first data signal DataA. Exemplarily, the compensation data signal segment includes a plurality of valid signals, and the duration of each valid signal is greater than the pulse width of the first clock signal and less than or equal to the duration of one cycle of the first clock signal; for example, referring to Fig. 8A and Figure 8B , the valid signal of the compensation data signal segment is the DC signal (e.g., DC high level signal and DC low level signal) in the compensation data signal segment. For example, before the start time and after the end time of the valid signal, the compensation data signal segment also includes an invalid signal, for example, the invalid signal is before the start time and after the end time of the valid signal; for example, reference Fig. 8A and Figure 8BThe invalid signal of the compensation data signal segment is a portion of the non-DC signal connected to the DC signal, such as the oblique line portion.

[0091] Exemplarily, the phase error is the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal. For example, for the first data signal and the first clock signal output by the driver, the high level signal of the clock signal segment in the first data signal and the low level signal of the first clock signal are in the same time period, for example, Fig. 7A Part (A) and Fig. 8A Part (A) of the figure shows the first clock signal ACLK and the first data signal DataA output by the driver. The rising edge of the pulse of the clock signal segment CK and the falling edge of the pulse of the first clock signal ACLK are at the same time, that is, the overlapping time length of the high level signal of the clock signal segment and the low level signal of the first clock signal is one pulse width, and the high level signal (pulse) of the clock signal segment and the high level signal (pulse) of the first clock signal do not overlap. In this way, the phase difference between the clock signal segment and the first clock signal in the first data signal output by the driver is 180 degrees, that is, half of the cycle of the first clock signal. For example, the initial phase difference between the clock signal segment and the first clock signal is 180 degrees. Exemplarily, the starting time of the first valid signal of the compensation data signal segment output by the driver and the sampling trigger edge of a pulse in the first clock signal can be at the same time, or can have a certain time interval (for example, the time interval is less than the second preset time length) to ensure that the sampling trigger edge of the first clock signal corresponds to the time period in which the valid signal of the compensation data signal segment can be correctly obtained. In this case, the phase error between the pulse of the clock signal segment in the first data signal output by the driver and the pulse of the first clock signal is zero.

[0092] In this case, each driver transmits the first clock signal and the first data signal to the data processing device through the corresponding transmission channel (e.g., signal line) on the circuit board. The lengths of different transmission channels are different, so that the transmission time of the signal is different. There is a deviation between the rising edge of the pulse of the clock signal segment in the first data signal received by the data processing device from the driver and the falling edge of the pulse of the first clock signal, so that the pulse of the clock signal segment overlaps with the pulse of the first clock signal. For example, Fig. 7A Part (B) and Fig. 8A Part (B) shows the first clock signal ACLK and the first data signal DataA received by the data processing device. The pulse of the clock signal segment CK has an overlapping part u with the pulse of the first clock signal ACLK, and the duration of the overlapping part is the phase error amount.

[0093] In another exemplary embodiment, the phase error is the difference between the pulse width of the first clock signal and the overlapping time length of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal. For example, for the first data signal and the first clock signal output by the driver, the high level signal of the clock signal segment in the first data signal and the high level signal of the first clock signal are in the same time period, for example, Figure 7B Part (A) and Figure 8B Part (A) of the diagram shows the first clock signal ACLK and the first data signal DataA output by the driver. The rising edge of the pulse of the clock signal segment CK is aligned with the rising edge of the pulse of the first clock signal ACLK (i.e., at the same time), that is, the overlapping time length of the high-level signal of the clock signal segment and the high-level signal of the first clock signal is one pulse width, and the high-level signal (pulse) of the clock signal segment does not overlap with the low-level signal (pulse) of the first clock signal. In this way, the phase difference between the clock signal segment in the first data signal output by the driver and the first clock signal is 0 degrees, that is, the clock signal segment is in phase with the first clock signal. For example, the initial phase difference between the clock signal segment and the first clock signal is 0 degrees. At this time, the starting time of the first valid signal of the compensation data signal segment output by the driver is at the same time as the sampling trigger edge of a pulse in the first clock signal, or there may be a certain time interval (for example, the time interval is less than the second preset time length) to ensure that the sampling trigger edge of the first clock signal corresponds to the time period in which the valid signal of the compensation data signal segment can be correctly obtained. In this case, the phase error between the pulse of the clock signal segment in the first data signal output by the driver and the pulse of the first clock signal is zero.

[0094] In this case, each driver transmits the first clock signal and the first data signal to the data processing device through a corresponding transmission channel (e.g., a signal line) on the circuit board. Different transmission channels have different lengths, so that the transmission time of the signal is different. There is a deviation between the rising edge of the pulse of the clock signal segment in the first data signal received by the data processing device from the driver and the rising edge of the pulse of the first clock signal, so that the overlapping part of the pulse of the clock signal segment and the pulse of the first clock signal (e.g., reference Figure 7B Part (B) and Figure 8B Part (B) shows that the data processing device receives the first clock signal ACLK and the first data signal DataA, and the overlapping part u) of the pulse of the clock signal segment CK and the pulse of the first clock signal ACLK is less than a pulse width. At this time, the difference between the pulse width and the duration of the overlapping part is the phase error amount.

[0095] If there is a phase error between the first data signal and the first clock signal, that is, the clock signal segment in the first data signal has a large phase deviation from the first clock signal, so that the starting time of the first valid signal in the compensation data signal segment has a large phase deviation from the sampling trigger edge of the pulse of the first clock signal, so that the sampling trigger edge of the first clock signal does not correspond to the valid signal in the compensation data signal segment, then when the data processing device samples the compensation data signal segment, the sampled data may be an invalid signal, or not the starting data of the compensation data signal segment, resulting in errors in the sampling result of the data processing device, and then errors in the compensation data obtained by analysis, and the compensation of the display panel (for example, compensation for the threshold voltage of the driving transistor of the pixel circuit) is inaccurate, which is prone to display defects (such as the Mura phenomenon).

[0096] On this basis, when the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than zero and less than the second preset time length, the compensation data signal segment in the first data signal or the first clock signal is delayed so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is shorter, for example Fig. 7A , Figure 7B , Fig. 8A and Figure 8B Part (C) in FIG. 1 shows that after the compensation data signal segment or the first clock signal in the first data signal is delayed, the time interval w between the start time of the first valid signal of the compensation data signal segment DataO and the sampling trigger edge of the first pulse of the first clock signal ACLK located after the start time of the first valid signal is less than Fig. 7A , Figure 7B , Fig. 8A and Figure 8BPart (B) in the figure shows the time interval w between the start time of the first valid signal of the compensated data signal segment DataO and the sampling trigger edge of the first pulse located after the start time of the first valid signal in the first clock signal ACLK without delay processing, which reduces the phase deviation between the start time of the valid signal of the compensated data signal segment and the sampling trigger edge of the first pulse located after the start time of the first valid signal in the first clock signal; the phase error amount of the clock signal segment in the first data signal compared with the first clock signal is also correspondingly smaller, for example, less than the second preset time length, thereby reducing the phase error amount of the clock signal segment in the first data signal compared with the first clock signal. Moreover, when the time interval between the start time of the first valid signal of the compensated data signal segment and the sampling trigger edge of the first pulse located after the start time of the first valid signal in the first clock signal is equal to zero, the start time of the first valid signal of the compensated data signal segment and the sampling trigger edge of the first pulse located after the start time of the first valid signal in the first clock signal are at the same time. At this time, the clock signal segment in the first data signal has no phase error with the first clock signal; the phase error amount of the clock signal segment in the first data signal compared with the first clock signal is approximately zero or equal to zero. In this case, when the sampling trigger edge of the first pulse after the start time of the first valid signal in the first clock signal arrives, the start signal of the compensation data signal segment can be correctly obtained to avoid data errors.

[0097] Therefore, an embodiment of the present disclosure provides a data processing method, which receives a first data signal and a first clock signal from at least one driver, and when the phase error of the clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset time length, delays one of the compensation data signal segment in the first data signal and the first clock signal, so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero, and less than the second preset time length. In this way, in the process of sampling the compensation data signal segment, when the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal arrives, the start signal of the compensation data signal segment can be obtained, data errors can be avoided, the display panel can be correctly compensated, and display defects can be avoided, thereby improving the display effect.

[0098] Exemplarily, delaying a compensation data signal segment in a first data signal and one of the first clock signals includes: registering one of the first data signal and the first clock signal according to a second clock signal so that a phase error amount of the clock signal segment compared to the first clock signal is less than a second preset duration.

[0099] Among them, reference Fig. 9 , the frequency of the second clock signal BCLK is greater than the frequency of the first clock signal ACLK.

[0100] It can be understood that, according to the second clock signal, the first data signal is stored to obtain a delayed first data signal. The phase error of the clock signal segment in the delayed first data signal compared to the first clock signal is less than the second preset duration. For example, the first data signal is stored, referring to Fig.10 , delay the first data signal DataA(a) to obtain a delayed first data signal DataA(b), the first data signal DataA(b) is delayed by a time length q compared with the first data signal DataA(a), accordingly, the clock signal segment in the first data signal DataA(b) is delayed by a time length q compared with the clock signal segment in the first data signal DataA(a), and the compensation data signal segment in the first data signal DataA(b) is delayed by a time length q compared with the compensation data signal segment in the first data signal DataA(a).

[0101] Alternatively, the first clock signal is registered according to the second clock signal to obtain a delayed first clock signal, wherein the phase error of the clock signal segment in the first data signal compared to the delayed first clock signal is less than a second preset duration.

[0102] It should be noted that the second clock signal may be generated inside the data processing device. The data processing device controls the duration of registering one of the first data signal and the first clock signal according to the number of pulse periods of the second clock signal.

[0103] For example, the data processing device may register one of the first data signal and the first clock signal for a third preset time period. For example, the phase of the clock signal segment after registration is delayed by a third preset time period compared to the phase of the original clock signal segment. For example, the phase of the first clock signal after registration is delayed by a third preset time period compared to the phase of the original first clock signal.

[0104] For example, the frequency of the clock signal segment is the same as the frequency of the first clock signal, and therefore, the frequency of the second clock signal is also greater than the frequency of the clock signal segment.

[0105] Exemplarily, the second clock signal has multiple pulses, and the duration for which the compensation data signal segment in the first data signal and one of the first clock signals are stored (e.g., a third preset duration) is at least one cycle of the second clock signal; for example, the storage duration is equal to one cycle of the second clock signal.

[0106] It should be noted that the duration of the cycle of the second clock signal can be designed according to actual conditions, such as the phase error of the clock signal segment in the first data signal compared to the first clock signal, and is not specifically limited here.

[0107] Exemplarily, the data processing device may register one of the first data signal and the first clock signal once, and output the delayed first data signal or the first clock signal according to the second clock signal, and the delay duration of the first data signal or the first clock signal is one cycle of the second clock signal. Alternatively, the data processing device may register one of the first data signal and the first clock signal multiple times, and the duration of each registration is one cycle of the second clock signal, and the delay duration of the first data signal or the first clock signal output after the last registration is multiple cycles of the second clock signal, and the number of cycles is the same as the number of registrations. Therefore, the delay duration of the first data signal or the first clock signal by the data processing device is at least one cycle of the second clock signal.

[0108] Also exemplarily, delaying one of the compensation data signal segment in the first data signal and the first clock signal includes:

[0109] Performing N signal inversion processing on one of the first clock signal and the first data signal so that the phase error of the clock signal segment compared with the first clock signal is less than a second preset duration, wherein N is an even number greater than zero.

[0110] Exemplarily, the signal inversion process may adopt a negation operation, that is, the data processing device performs N negation operations on one of the first data signal and the first clock signal.

[0111] For example, the first clock signal is subjected to N signal inversion processes to obtain a delayed first clock signal, and the phase error of the clock signal segment in the first data signal compared to the delayed first clock signal is less than the second preset duration; the period and duty cycle of the delayed first clock signal do not change. Alternatively, the first data signal is subjected to N signal inversion processes to obtain a delayed first data signal, and the phase error of the clock signal segment in the delayed first data signal compared to the first clock signal is less than the second preset duration; the information of the delayed first data signal does not change.

[0112] It should be noted that the number of times of signal inversion processing can be designed according to actual conditions, such as the required delay time, and is not specifically limited here. For example, N can be 2 or 4.

[0113] In some embodiments, the data processing method further includes: performing a logic operation on the first clock signal and the clock signal segments in the first data signal to obtain a pulse overlap characterization signal.

[0114] The pulse overlap characterization signal includes: a first pulse overlap characterization signal and a second pulse overlap characterization signal. The first pulse overlap characterization signal is configured to characterize that the pulse of the clock signal segment in the first data signal overlaps with the pulse of the first clock signal, and the second pulse overlap characterization signal is configured to characterize that the pulse of the clock signal segment in the first data signal does not overlap with the pulse of the first clock signal.

[0115] According to the duration of the first pulse overlapping the characterization signal, the phase error between the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal is obtained.

[0116] Exemplarily, when the phase error amount is the overlapping time length of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal, the logical operation is an AND operation.

[0117] For example, a low-level signal is represented by 0, and a high-level signal is represented by 1. In this case, if the result of the logic operation is 0, the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal have no overlap, and at this time, the low-level signal of the clock signal segment overlaps with the high-level signal of the first clock signal. If the result of the logic operation is 1, the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal overlap, and the duration of the logic operation result being 1 represents the overlapping duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal. Exemplarily, the phase error amount can be the duration of the logic operation result being 1. For example, the first pulse overlap characterization signal is 1, and the second pulse overlap characterization signal is 0.

[0118] Exemplarily, when the phase error amount is the difference between the pulse width of the first clock signal and the overlapping time length of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal, the logical operation is an exclusive OR operation.

[0119] In this case, if the result of the logic operation is 0, the low-level signal of the clock signal segment has no overlap with the high-level signal of the first clock signal. At this time, the pulse of the clock signal segment in the first data signal overlaps with the pulse of the first clock signal. In this way, if the result of the logic operation is 1, the low-level signal of the clock signal segment overlaps with the high-level signal of the first clock signal, and the pulse of the clock signal segment in the first data signal has no overlap with the pulse of the first clock signal. At this time, the pulse of the clock signal segment in the first data signal has a phase deviation with the pulse of the first clock signal. The duration of the logic operation result of 1 represents the duration of the non-overlap of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal. Exemplarily, the phase error amount can be the difference between the pulse width and the duration of the logic operation result of 1. For example, the first pulse overlap characterization signal is 0, and the second pulse overlap characterization signal is 1.

[0120] Exemplarily, after receiving the first data signal and the first clock signal from the driver, the data processing device performs a logic operation on the clock signal segment in the first data signal and the first clock signal, and obtains the phase error amount between the clock signal segment in the first data signal and the first clock signal according to the result of the logic operation. When the phase error amount is greater than or equal to the second preset time length, one of the first clock signal or the first data signal is delayed. For example, one of the first clock signal or the first data signal is registered, or one of the first clock signal or the first data signal is subjected to signal inversion processing, so that one of the first clock signal or the first data signal is delayed. After the delay processing, it is necessary to perform a logic operation on the clock signal segment in the first data signal and the first clock signal, and obtain the phase error amount between the clock signal segment in the first data signal and the first clock signal according to the result of the operation. When the phase error amount is less than the second preset time length, the first data signal and the first clock signal do not need to be delayed any further.

[0121] It can be understood that the first data signal and the first clock signal are subjected to logical operation to confirm whether the first data signal and the first clock signal need to be delayed; after the first data signal or the first clock signal is delayed, the first data signal and the first clock signal need to be subjected to logical operation again to confirm whether the first data signal and the first clock signal do not need to be delayed any further.

[0122] In some embodiments, before receiving the first data signal and the first clock signal from at least one driver, the data processing method further includes: transmitting a request instruction to at least one driver. The request instruction is configured to instruct the at least one driver to transmit the first data signal and the first clock signal. For example, referring to Fig.11A and Fig. 11B, the data processing device 300 transmits a request instruction Data_request to at least one driver 400 .

[0123] Exemplarily, in the case where at least one driver is a plurality of drivers, the plurality of drivers sequentially perform data transmission with the data processing device. The plurality of drivers are arranged sequentially; for example, the first driver among the plurality of drivers is the first driver among the plurality of drivers to perform data transmission with the data processing device. In this case, reference Fig. 11B and Fig. 11C The display device 200 includes m drivers, where m is an integer greater than 2. The first driver 400(1) receives a request instruction Data_request from the data processing device 300, and transmits a corresponding first data signal DataA(1) and a first clock signal ACLK(1) to the data processing device 300. After the first driver 400(1) completes the transmission of the first data signal DataA(1) and the first clock signal ACLK(1), the first driver 400(1) transmits the request instruction Data_request to the second driver 400(2), and the second driver 400(2) transmits the corresponding first data signal DataA(1) to the data processing device 300. aA(2) and the first clock signal ACLK(2). After the second driver 400(2) completes the transmission of the first data signal DataA(2) and the first clock signal ACLK(2), the second driver 400(2) transmits the request instruction Data_request to the third driver 400(3). The third driver 400(3) transmits the corresponding first data signal DataA(3) and the first clock signal ACLK(3) to the data processing device 300, and so on, until the last driver 400(m) receives the request instruction and transmits the corresponding first data signal DataA(m) and the first clock signal ACLK(m) to the data processing device 300.

[0124] For example, reference Fig. 11B , the plurality of drivers 400 may directly transmit the first data signal and the first clock signal in series to the data processing device 300 through their respective corresponding transmission channels; Fig. 11C , multiple drivers 400 can transmit the first data signal and the first clock signal in series to the transmission main channel corresponding to the first data signal and the first clock signal through their respective corresponding transmission channels, and the data processing device 300 receives the first clock signal and the first data signal through the transmission main channel corresponding to the first data signal and the first clock signal.

[0125] In some embodiments, the data processing method further includes:

[0126] In response to the first clock signal, the compensation data is obtained according to the compensation data signal segment in the first data signal.

[0127] A frame of image data is received, and a second data signal is obtained according to the compensation data and the frame of image data.

[0128] The second data signal is transmitted to at least one driver.

[0129] It can be understood that the data processing device samples the compensation data signal segment in the first data signal at the sampling trigger edge of the pulse of the first clock signal in response to the first clock signal, obtains the valid signal in the compensation data signal segment, and obtains the compensation data according to the valid signal. In this case, after receiving a frame of image data, a second data signal is obtained according to the frame of image data and the compensation data, and the second data signal contains the compensated image data. The data processing device transmits the second data signal to at least one driver, so that the at least one driver can transmit the data signal to the data line in the display panel according to the second data signal, and the pixel circuit drives the light-emitting device to work according to the data signal from the data line to achieve compensation for the display.

[0130] Exemplarily, when the display panel displays an image corresponding to a frame of image data, the sensing line senses the information of the driving transistor of each pixel circuit to obtain a sensing signal, and the sensing line transmits the sensing signal to the driver, and the driver obtains a compensation data signal segment. The driver transmits the first data signal containing the compensation data signal segment to the data processing device, and when the next frame of the image of the frame arrives, the data processing device compensates the next frame of image data to obtain the second data information corresponding to the next frame of image data, so as to realize compensation for displaying the next frame of image. It can be understood that the compensation data used for compensating a frame of image data is sensed when the display panel displays the image corresponding to the previous frame of image data of the frame of image data.

[0131] The embodiment of the present disclosure provides a data processing method. The data processing method is applied to a driver, for example, the driver is the driver 400 in the text. For example, the driver is a source driver. Fig.12 As shown, the data processing method includes:

[0132] S30, receiving a third clock signal from the data processing device.

[0133] S40. Obtain a first clock signal according to the third clock signal.

[0134] For example, the third clock signal has a different frequency than the first clock signal. Fig.13 , the frequency of the third clock signal (CLK) is greater than the frequency of the first clock signal (ACLK).

[0135] Exemplarily, the signals transmitted between the data processing device and the driver (such as the first clock signal, the third clock signal and the first data signal, etc.) can be transmitted differentially. For example, the signals transmitted between the data processing device and the driver can be differential signals, which can reduce interference to the signals during transmission.

[0136] S50: Obtain a compensation data signal segment.

[0137] Exemplarily, obtaining the compensated data signal segment includes: obtaining the compensated data signal segment according to a sensing signal from a display panel.

[0138] S60: Obtain a first data signal according to the first clock signal and the compensated data signal segment.

[0139] Among them, the first data signal includes a clock signal segment and a compensation data signal segment, the clock signal segment is before the compensation data signal segment, the clock signal segment and the compensation data signal segment are separated by a first preset time length, and the clock signal segment and the first clock signal have the same period and duty cycle.

[0140] It should be noted that the first preset duration can be designed according to actual conditions and is not limited here. For example, the first preset duration can be zero.

[0141] The phase error of the clock signal segment in the first data signal compared to the first clock signal is zero. For example, the rising edge of the pulse of the clock signal segment in the first data signal is at the same time as the falling edge of the pulse of the first clock signal, and the falling edge of the pulse of the clock signal segment in the first data signal is at the same time as the rising edge of the pulse of the first clock signal; or, the rising edge of the pulse of the clock signal segment in the first data signal is at the same time as the rising edge of the pulse of the first clock signal, and the falling edge of the pulse of the clock signal segment in the first data signal is at the same time as the falling edge of the pulse of the first clock signal.

[0142] S70. Transmit a first data signal and a first clock signal to a data processing device.

[0143] The driver outputs the first data signal and the first clock signal synchronously, and the phase error between the pulse of the clock signal segment in the first data signal output by the driver and the pulse of the first clock signal is zero.

[0144] Exemplarily, transmitting the first data signal and the first clock signal to the data processing device includes: transmitting the first data signal and the first clock signal to the data processing device in response to a request instruction from the data processing device.

[0145] For example, in the case where the display device includes a driver, the driver receives a request instruction from the data processing device and transmits a corresponding first data signal and a first clock signal to the data processing device. For example, in the case where the display device includes multiple drivers, the multiple drivers sequentially transmit data with the data processing device. Among them, the multiple drivers are arranged in sequence; for example, the first driver among the multiple drivers is the first driver among the multiple drivers to perform data transmission with the data processing device. In this case, the first driver receives a request instruction from the data processing device and transmits a corresponding first data signal and a first clock signal to the data processing device. After the first data signal and the first clock signal of the first driver are transmitted, the first driver transmits the request instruction to the second driver, and the second driver transmits the corresponding first data signal and the first clock signal to the data processing device. After the first data signal and the first clock signal of the second driver are transmitted, the second driver transmits the request instruction to the third driver, and so on, until the last driver receives the request instruction and transmits the corresponding first data signal and the first clock signal to the data processing device.

[0146] In this case, since the first data signal output by the driver includes a clock signal segment, after receiving the first data signal and the first clock signal, the data processing device can process according to the clock signal segment and the first clock signal to obtain the phase error between the clock signal segment and the first clock signal. The data processing device can delay the first clock signal and the first data signal to avoid errors in the processing of the compensation data signal segment in the first data signal.

[0147] In some embodiments, the data processing method further includes: receiving a second data signal from the data processing device; and transmitting a third data signal to the display panel according to the second data signal to compensate for the display of the display panel.

[0148] It can be understood that the driver transmits the third data signal to the data line in the display panel according to the second data signal, and the pixel circuit in the display panel drives the light-emitting device to work according to the third data signal received, so that the sub-pixel displays the corresponding grayscale and compensates the display. For example, the compensation data signal segment contains information about the driving transistor in the pixel circuit (such as the threshold voltage and mobility of the driving transistor), the data processing device obtains the compensation data according to the compensation data signal segment, and obtains the second data signal according to the compensation data and a frame of image data. The second data signal can compensate the data signal (data voltage) to be displayed of the pixel circuit based on the information of the driving transistor in each pixel circuit. The driver obtains the third data signal according to the second data signal, and transmits the third data signal to the display panel, and drives the pixel circuit through the third data signal (i.e., the compensated data signal), thereby realizing the compensation function for each sub-pixel of the display panel.

[0149] In addition, reference Fig. 7A , Figure 7B , Fig. 8A and Figure 8B , before a driver transmits the clock signal segment CK and the compensated data signal segment DataO in the first data signal DataA, the first data signal DataA output by the driver also includes a high impedance signal (Hi-Z). The high impedance signal (Hi-Z) indicates that the driver and the data processing device have not started to communicate yet, and at this time, the driver is in a high impedance state. After the high impedance signal ends, the driver and the data processing device start to communicate normally, that is, the driver transmits the clock signal segment and the compensated data signal segment in the first clock signal and the first data signal to the data processing device. It can be understood that in the high impedance signal segment of the first data signal of a driver, the signal received by the data processing device is not a signal from the driver, and the signal received by the data processing device is not a valid signal for the driver, for example, the data processing device receives the clock signal segment and the compensated data signal segment from the previous driver of the driver, and after the high impedance signal segment of the driver ends, the data processing device receives the clock signal segment and the compensated data signal segment from the driver. Exemplarily, the first data signal received by the data processing device may not include the high impedance signal segment.

[0150] An embodiment of the present disclosure provides a data processing device. The data processing device can implement the data processing methods in some of the above embodiments. For example, the data processing device is a timing controller.

[0151] like Fig.14 As shown, the data processing device 300 includes: a first communication interface 310 and a first processor 320 .

[0152] The first communication interface 310 is configured to receive a first clock signal and a first data signal from at least one driver. The first data signal includes a clock signal segment and a compensation data signal segment. The clock signal segment precedes the compensation data signal segment. The clock signal segment and the compensation data signal segment are separated by a first preset time length. The clock signal segment and the first clock signal have the same period and duty cycle.

[0153] The first processor 320 is configured to delay one of the compensation data signal segment in the first data signal and the first clock signal when the phase error of the clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset duration, so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than the second preset duration.

[0154] In some embodiments, Fig.14 As shown, the first processor 320 includes a register 321. The register 321 is configured to register one of the first data signal and the first clock signal according to the second clock signal, so that the phase error of the clock signal segment compared to the first clock signal is less than the second preset duration. The frequency of the second clock signal is greater than the frequency of the first clock signal. Exemplarily, the register responds to the second clock signal, registers one of the first data signal and the first clock signal and then outputs it, and the output first data signal or the first clock signal is delayed.

[0155] Exemplarily, the number of registers is at least one. Fig.15A , one of the first data signal DataA and the first clock signal ACLK can pass through a register 321, and the register 321 stores one of the first data signal DataA and the first clock signal ACLK. The register 321 outputs the delayed first data signal DataA or the first clock signal ACLK according to the second clock signal BCLK, and the delay time of the first data signal DataA or the first clock signal ACLK is one cycle of the second clock signal BCLK. Or, referring to Fig. 15B, one of the first data signal DataA and the first clock signal ACLK may pass through the plurality of registers 321 in sequence, one of the plurality of registers 321 delays the first data signal or the first clock signal stored therein to output to the next register of the register according to the second clock signal, until the last register delays the first data signal or the first clock signal stored therein to output according to the second clock signal, and the delay time length of the first data signal DataA or the first clock signal ACLK is multiple cycles of the second clock signal BCLK, for example, the number of the multiple cycles is the same as the number of registers. Therefore, the delay time length of the first data signal or the first clock signal by the data processing device is at least one cycle of the second clock signal.

[0156] It should be noted that any circuit or device capable of implementing the above-mentioned register function can be used as the register in the embodiments of the present disclosure, and no specific limitation is made herein.

[0157] In some embodiments, Fig.14 As shown, the first processor 320 includes a signal inversion processor 322. The signal inversion processor 322 is configured to perform N signal inversion processes on one of the first clock signal and the first data signal so that the phase error of the clock signal segment compared to the first clock signal is less than a second preset duration. Wherein N is an even number greater than zero.

[0158] It should be noted that any circuit or device capable of implementing the above-mentioned signal inversion function can be used as the signal inversion processor in the embodiments of the present disclosure, and no specific limitation is made herein.

[0159] Exemplarily, the signal inversion processor 322 may include a NOT gate, for example, the number of the NOT gates is N. For example, the first clock signal or the first data signal may pass through N NOT gates in sequence to achieve signal delay.

[0160] In some embodiments, Fig.14 As shown, the first processor 320 further includes a logic operation processor 323. The logic operation processor 323 is configured to perform logic operations on the first clock signal and the clock signal segments in the first data signal to obtain a pulse overlap characterization signal.

[0161] The pulse overlap characterization signal includes: a first pulse overlap characterization signal and a second pulse overlap characterization signal. The first pulse overlap characterization signal is configured to characterize that the pulse of the clock signal segment in the first data signal overlaps with the pulse of the first clock signal, and the second pulse overlap characterization signal is configured to characterize that the clock signal segment in the first data signal does not overlap with the pulse of the first clock signal.

[0162] The logic operation processor 323 is further configured to obtain a phase error between a pulse of the clock signal segment in the first data signal and a pulse of the first clock signal according to a duration of the first pulse overlapping the characterization signal.

[0163] In this case, after receiving the first data signal and the first clock signal from the driver, the data processing device performs a logic operation on the clock signal segment in the first data signal and the first clock signal, and obtains the phase error between the clock signal segment in the first data signal and the first clock signal according to the result of the logic operation. When the phase error is greater than or equal to the second preset duration, one of the first clock signal or the first data signal is delayed. For example, one of the first clock signal or the first data signal is transmitted to a register, or one of the first clock signal or the first data signal is transmitted to a signal inversion processor, so that one of the first clock signal or the first data signal is delayed. After the delay processing, the logic processor performs a logic operation on the clock signal segment in the first data signal and the first clock signal, and obtains the phase error between the clock signal segment in the first data signal and the first clock signal according to the result of the operation. When the phase error is less than the second preset duration, the first data signal and the first clock signal are output.

[0164] Exemplarily, the data processing device also includes a compensation data processor, which can process the first data signal and the first clock signal output by the logic operation processor after delay processing. The compensation data processor can respond to the first clock signal and obtain compensation data according to the compensation data signal segment in the first data signal.

[0165] It can be understood that the first data signal and the first clock signal need to pass through a logic operation processor to confirm whether the first data signal and the first clock signal need to be delayed; after delaying the first data signal or the first clock signal, the first data signal and the first clock signal need to pass through a logic operation processor to confirm whether the first data signal and the first clock signal no longer need to be delayed.

[0166] It should be noted that any circuit or device capable of implementing the above logic operation function can be used as the logic operation processor in the embodiments of the present disclosure, and the specific details are not limited here. For example, the logic operation processor can include an AND gate or an XOR gate.

[0167] Exemplarily, the first communication interface is further configured to receive a frame of image data. The data processing device further includes a compensation data processor. The compensation data processor is configured to obtain compensation data according to the compensation data signal segment in the first data signal in response to the first clock signal, and obtain the second data signal according to the compensation data and the frame of image data. Exemplarily, the first communication interface is further configured to transmit the second data signal to at least one driver.

[0168] Exemplarily, the first communication interface may include a first input interface (Rx) for receiving a signal and a first output interface (Tx) for outputting a signal.

[0169] It should be noted that the beneficial effects of the above-mentioned data processing device are the same as the beneficial effects of the data processing methods described in some of the above-mentioned embodiments, and will not be repeated here.

[0170] The embodiment of the present disclosure provides a data processing device. The data processing device can be a chip (for example, Figure 4 The chip is configured to implement the data processing method in some of the above embodiments. Exemplarily, the chip can be a programmable device. For example, the programmable device is a CPLD (Complex Programmable Logic Device), an EPLD (Erasable Programmable Logic Device) or an FPGA.

[0171] It should be noted that the beneficial effects of the above-mentioned data processing device are the same as the beneficial effects of the data processing methods described in some of the above-mentioned embodiments, and will not be repeated here.

[0172] An embodiment of the present disclosure provides a driver. The driver can implement the data processing method in some of the above embodiments. For example, the driver is a source driver.

[0173] like Fig.16 As shown, the driver 400 includes a second communication interface 410 and a second processor 420 .

[0174] The second communication interface is configured to receive a third clock signal from the data processing device.

[0175] The second processor is configured to obtain the first clock signal according to the third clock signal, and obtain a compensated data signal segment, and obtain the first data signal according to the first clock signal and the compensated data signal segment.

[0176] The first data signal includes a clock signal segment and a compensated data signal segment. The clock signal segment precedes the compensated data signal segment, the clock signal segment and the compensated data signal segment are separated by a first preset time length, and the clock signal segment and the first clock signal have the same period and duty cycle. The phase error of the clock signal segment in the first data signal compared to the first clock signal is zero.

[0177] The second communication interface is further configured to transmit the first data signal and the first clock signal to the data processing device.

[0178] Exemplarily, the second communication interface may include a second input interface (Rx') for receiving a signal and a second output interface (Tx') for outputting a signal.

[0179] In some embodiments, Fig.16 As shown, the second processor 420 includes an analog-to-digital converter ADC, a clock signal processor 421 and a data signal processor 422 .

[0180] The analog-to-digital converter is configured to obtain the compensation data signal segment. Exemplarily, the analog-to-digital converter is configured to obtain the compensation data signal segment according to the sensing signal from the display panel. Exemplarily, the second communication interface is further configured to receive the sensing signal from the display panel.

[0181] The clock signal processor is configured to obtain the first clock signal according to the third clock signal.

[0182] The data signal processor is configured to obtain a first data signal according to the first clock signal and the compensated data signal segment.

[0183] It should be noted that the beneficial effects of the above-mentioned driver are the same as the beneficial effects of the data processing method described in some of the above-mentioned embodiments, and will not be repeated here.

[0184] Some embodiments of the present disclosure provide a non-transitory computer-readable storage medium, which stores computer program instructions. When the computer program instructions are executed on a processor, the processor executes one or more steps of the data processing method described in any of the above embodiments.

[0185] Exemplarily, the above-mentioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or magnetic tapes, etc.), optical disks (e.g., CDs (Compact Disks), DVDs (Digital Versatile Disks), etc.), smart cards and flash memory devices (e.g., EPROMs (Erasable Programmable Read-Only Memory), cards, sticks or key drives, etc.). The various computer-readable storage media described in the present disclosure may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0186] Some embodiments of the present disclosure further provide a computer program product, which includes computer program instructions, and when the computer program instructions are executed on a computer, the computer program instructions cause the computer to execute one or more steps in the data processing method described in the above embodiments.

[0187] Some embodiments of the present disclosure further provide a computer program. When the computer program is executed on a computer, the computer program enables the computer to execute one or more steps in the data processing method described in the above embodiments.

[0188] The beneficial effects of the above-mentioned computer-readable storage medium, computer program product and computer program are the same as the beneficial effects of the data processing methods described in some of the above-mentioned embodiments, and will not be repeated here.

[0189] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data processing method, comprising: Receive a first data signal and a first clock signal from at least one driver; wherein the first data signal includes a clock signal segment and a compensation data signal segment, the clock signal segment precedes the compensation data signal segment, and the clock signal segment is separated from the compensation data signal segment by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; When the phase error of the clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset time length, delay one of the compensation data signal segment in the first data signal and the first clock signal, so that the time interval between the start time of the first valid signal of the compensation data signal segment and the sampling trigger edge of the first pulse of the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than the second preset time length; The phase error is the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal; Alternatively, the phase error amount is a difference between a pulse width of the first clock signal and an overlapping time length of a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal.

2. The data processing method according to claim 1, wherein: The delaying one of the compensation data signal segment in the first data signal and the first clock signal comprises: registering one of the first data signal and the first clock signal according to a second clock signal so that a phase error of the clock signal segment compared to the first clock signal is less than a second preset duration; The frequency of the second clock signal is greater than the frequency of the first clock signal.

3. The data processing method according to claim 1, wherein: The delaying one of the compensation data signal segment in the first data signal and the first clock signal comprises: Perform N signal inversion processing on one of the first clock signal and the first data signal so that the phase error of the clock signal segment compared to the first clock signal is less than a second preset duration; wherein N is an even number greater than zero.

4. The data processing method according to any one of claims 1 to 3, wherein: The second preset duration is greater than zero and less than or equal to half of a pulse width of the first clock signal.

5. The data processing method according to any one of claims 1 to 3, further comprising: Performing a logic operation on the first clock signal and the clock signal segments in the first data signal to obtain a pulse overlap characterization signal; The pulse overlap characterization signal includes: a first pulse overlap characterization signal and a second pulse overlap characterization signal; the first pulse overlap characterization signal is configured to characterize that the pulse of the clock signal segment in the first data signal overlaps with the pulse of the first clock signal, and the second pulse overlap characterization signal is configured to characterize that the clock signal segment in the first data signal does not overlap with the pulse of the first clock signal; According to the duration of the first pulse overlapping the characterization signal, a phase error between a pulse of the clock signal segment in the first data signal and a pulse of the first clock signal is obtained.

6. The data processing method according to claim 5, wherein: In the case where the phase error amount is the overlapping time length of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal, the logical operation is an AND operation; When the phase error is a difference between a pulse width of the first clock signal and an overlapping time length of a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal, the logic operation is an exclusive OR operation.

7. The data processing method according to any one of claims 1 to 3, wherein: Before receiving the first data signal and the first clock signal from at least one driver, the data processing method further includes: A request instruction is transmitted to the at least one driver, wherein the request instruction is configured to instruct the at least one driver to transmit the first data signal and the first clock signal.

8. The data processing method according to any one of claims 1 to 3, further comprising: In response to the first clock signal, obtaining compensation data according to the compensation data signal segment in the first data signal; receiving a frame of image data, and obtaining a second data signal according to the compensation data and the frame of image data; The second data signal is transmitted to the at least one driver.

9. A data processing method, comprising: receiving a third clock signal from a data processing device, and obtaining a first clock signal according to the third clock signal; obtaining a compensated data signal segment; A first data signal is obtained according to the first clock signal and the compensated data signal segment; wherein the first data signal includes a clock signal segment and the compensated data signal segment; the order of the clock signal segment is before the compensated data signal segment; the clock signal segment and the compensated data signal segment are separated by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; the phase error amount of the clock signal segment in the first data signal compared with the first clock signal is zero, so that the time interval between the starting time of the first valid signal of the compensated data signal segment and the sampling trigger edge of the first pulse of the first clock signal located after the starting time of the first valid signal is greater than or equal to zero and less than a second preset time length; The phase error is the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal; or, the phase error is the difference between the pulse width of the first clock signal and the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal; The first data signal and the first clock signal are transmitted to the data processing device.

10. The data processing method according to claim 9, wherein: The transmitting the first data signal and the first clock signal to the data processing device comprises: In response to a request instruction from the data processing device, the first data signal and the first clock signal are transmitted to the data processing device.

11. The data processing method according to claim 9 or 10, wherein: The obtaining of the compensation data signal segment comprises: The compensation data signal segment is obtained according to the sensing signal from the display panel.

12. The data processing method according to claim 9 or 10, further comprising: receiving a second data signal from the data processing device; According to the second data signal, a third data signal is transmitted to the display panel to compensate for the display of the display panel.

13. A data processing device, comprising: A first communication interface is configured to receive a first clock signal and a first data signal from at least one driver; wherein the first data signal includes a clock signal segment and a compensation data signal segment, the clock signal segment is prior to the compensation data signal segment, the clock signal segment is separated from the compensation data signal segment by a first preset time length, and the clock signal segment and the first clock signal have the same period and duty cycle; A first processor is configured to delay one of a compensation data signal segment in the first data signal and the first clock signal when a phase error amount of a clock signal segment in the first data signal compared to the first clock signal is greater than or equal to a second preset time length, so that a time interval between a start time of a first valid signal of the compensation data signal segment and a sampling trigger edge of a first pulse in the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than the second preset time length; The phase error is the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal; Alternatively, the phase error amount is a difference between a pulse width of the first clock signal and an overlapping time length of a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal.

14. The data processing apparatus according to claim 13, wherein: The first processor comprises: a register; the register is configured to register one of the first data signal and the first clock signal according to a second clock signal, so that the phase error of the clock signal segment compared with the first clock signal is less than a second preset duration; wherein the frequency of the second clock signal is greater than the frequency of the first clock signal; or, The first processor includes: a signal inversion processor; the signal inversion processor is configured to perform N signal inversion processes on one of the first clock signal and the first data signal so that the phase error of the clock signal segment compared to the first clock signal is less than a second preset duration; N is an even number greater than zero.

15. The data processing apparatus according to claim 14, wherein: The first processor further includes: a logic operation processor; The logic operation processor is configured to perform a logic operation on the first clock signal and the clock signal segments in the first data signal to obtain a pulse overlap characterization signal; The pulse overlap characterization signal includes: a first pulse overlap characterization signal and a second pulse overlap characterization signal; the first pulse overlap characterization signal is configured to characterize that the pulse of the clock signal segment in the first data signal overlaps with the pulse of the first clock signal, and the second pulse overlap characterization signal is configured to characterize that the clock signal segment in the first data signal does not overlap with the pulse of the first clock signal; The logic operation processor is further configured to obtain a phase error between a pulse of a clock signal segment in the first data signal and a pulse of the first clock signal according to a duration of the first pulse overlapping the characterization signal.

16. A data processing device, wherein: The data processing device is a chip; the chip is configured to implement the data processing method according to any one of claims 1 to 8.

17. A driver comprising: a second communication interface configured to receive a third clock signal from the data processing device; a second processor configured to obtain a first clock signal according to the third clock signal, and to obtain a compensated data signal segment, and to obtain a first data signal according to the first clock signal and the compensated data signal segment; The first data signal includes a clock signal segment and the compensated data signal segment; the clock signal segment is prior to the compensated data signal segment; the clock signal segment and the compensated data signal segment are separated by a first preset time length; the clock signal segment and the first clock signal have the same period and duty cycle; the phase error of the clock signal segment in the first data signal compared with the first clock signal is zero, so that the time interval between the start time of the first valid signal of the compensated data signal segment and the sampling trigger edge of the first pulse of the first clock signal located after the start time of the first valid signal is greater than or equal to zero and less than a second preset time length; The phase error is the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal; or, the phase error is the difference between the pulse width of the first clock signal and the overlap duration of the pulse of the clock signal segment in the first data signal and the pulse of the first clock signal; The second communication interface is further configured to transmit the first data signal and the first clock signal to the data processing device.

18. The driver according to claim 17, wherein: The second processor comprises: an analog-to-digital converter configured to obtain the compensated data signal segment; a clock signal processor, configured to obtain the first clock signal according to the third clock signal; The data signal processor is configured to obtain the first data signal according to the first clock signal and the compensated data signal segment.

19. A display device comprising: The data processing device according to any one of claims 13 to 15, or the data processing device according to claim 16; At least one actuator as claimed in claim 17 or 18; A circuit board is coupled to the data processing device and at least one of the drivers; and a display panel is coupled to at least one of the drivers.

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