Solid-state imaging device and imaging apparatus

Abstract

The present application improves the sensitivity of a pixel of a solid-state imaging device that performs time delay integration. The solid-state imaging device includes a plurality of photoelectric conversion elements and a predetermined number of transistors. In the solid-state imaging device, the photoelectric conversion elements are arranged at a predetermined pitch along a predetermined direction. The photoelectric conversion elements each arranged at the predetermined pitch have a dimension along the predetermined direction that does not exceed the predetermined pitch. Furthermore, in the solid-state imaging device, the predetermined number of transistors are arranged between the plurality of photoelectric conversion elements, and the transistors generate a signal commensurate with the amount of charge generated by any one of the plurality of photoelectric conversion elements.

Description

Technical Field

[0001] This technology relates to solid-state imaging elements. More specifically, this technology relates to solid-state imaging elements and imaging devices that integrate digital signals. Background Technology

[0002] TDI (Time Delay Integration) sensors are already used in the fields of factory automation (FA) and aerial photography. TDI sensors perform a TDI process, which integrates the amount of charge as the time of transition is adjusted according to the subject's movement speed. For example, a solid-state imaging element has been proposed in which adjacent rows share a single floating diffusion layer, and the respective charges of the two rows are transferred to the floating diffusion layer at different times (see, for example, Patent Document 1 listed below). The TDI process is achieved through this charge transfer. Photoelectric conversion elements and multiple transistors, such as transfer transistors, are arranged in each pixel within a row.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Translation of PCT Patent No. 2014-510447 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] In the TDI process, the aforementioned conventional techniques improve brightness and reduce noise. However, in the aforementioned solid-state imaging elements, even if the light-receiving area of ​​the photoelectric conversion element is increased, reducing the floating diffusion layer area and the number of transistors in order to improve pixel sensitivity may lead to performance degradation of the solid-state imaging element.

[0008] This technology was designed in view of the above circumstances, and the purpose of this technology is to improve the pixel sensitivity of solid-state imaging elements that perform TDI.

[0009] Solutions to technical problems

[0010] This technology was developed to solve the aforementioned problems, and its first aspect is a solid-state imaging element comprising a plurality of photoelectric conversion elements and a predetermined number of transistors. The photoelectric conversion elements are arranged at a predetermined spacing along a predetermined direction, and the dimension of each photoelectric conversion element along the predetermined direction does not exceed the predetermined spacing. The transistors are arranged between the plurality of photoelectric conversion elements and generate a signal commensurate with the amount of charge generated by any of the photoelectric conversion elements. Compared to the case without spacing, this has the effect of increasing the light-receiving area of ​​the photoelectric conversion elements.

[0011] Furthermore, in the first aspect, any one of the plurality of photoelectric conversion elements can be arranged in the pixel circuit that generates the pixel signal. The predetermined number of transistors can be arranged in the pixel circuit and the amplification circuit that amplifies the pixel signal. This serves to amplify the pixel signal.

[0012] Furthermore, in the first aspect, the predetermined number of transistors may include a pair of differential transistors that differentially amplify a predetermined reference signal and the pixel signal. The amplification circuit may include a pair of transistors and a capacitor connected in series to a power supply. The gate of one of the pair of transistors may be connected to a floating diffusion layer. The capacitor may be inserted between a connection node between the pair of transistors and the gate of one of the pair of differential transistors. This serves to mitigate the coupling between the gate-source capacitance and the floating diffusion layer.

[0013] Furthermore, in the first aspect, the solid-state imaging element may further include a floating diffusion layer and a transfer transistor. The floating diffusion layer is disposed between the plurality of photoelectric conversion elements. The transfer transistor transfers charge from any of the plurality of photoelectric conversion elements to the floating diffusion layer. The predetermined number of transistors may include discharge transistors that discharge charge from the floating diffusion layer. Any of the plurality of photoelectric conversion elements, the floating diffusion layer, the transfer transistor, and the discharge transistor may be arranged in the pixel circuit. This serves to generate the pixel signal.

[0014] Furthermore, in the first aspect, the predetermined number of transistors may include gain control transistors that control the analog gain relative to the voltage of the floating diffusion layer. The gain control transistors may be arranged in the pixel circuit. This serves to control the analog gain.

[0015] Furthermore, in the first aspect, the predetermined number of transistors may include a reset transistor that initializes the floating diffusion layer. The reset transistor may be arranged in the pixel circuit. This serves to initialize the floating diffusion layer.

[0016] Furthermore, in the first aspect, the solid-state imaging element may also include an analog-to-digital converter that converts pixel signals, commensurate with the amount of light received by each of the plurality of photoelectric conversion elements, into digital signals. This serves to generate the digital signals.

[0017] Furthermore, in the first aspect, the solid-state imaging element may also include a time-delay integration circuit that performs time-delay integration processing on the digital signal. This has the effect of improving brightness and reducing noise by using the time-delay integration processing.

[0018] Furthermore, in the first aspect, the plurality of photoelectric conversion elements and the predetermined number of transistors can be arranged in a predetermined light-receiving chip. The analog-to-digital converter can be arranged in a predetermined circuit chip. This has the effect of promoting pixel miniaturization by using a stacked structure.

[0019] Furthermore, a second aspect of this technology is a camera device comprising a plurality of photoelectric conversion elements, a predetermined number of transistors, and a signal processing circuit. The photoelectric conversion elements are arranged along a predetermined direction at a predetermined spacing, and the dimension of each photoelectric conversion element along the predetermined direction does not exceed the predetermined spacing. The transistors are arranged between the plurality of photoelectric conversion elements and generate a signal commensurate with the amount of charge generated by any of the photoelectric conversion elements. The signal processing circuit processes a digital signal commensurate with the amount of light received by each of the plurality of photoelectric conversion elements. This has the effect of processing the digital signal of the pixel with improved sensitivity. Attached Figure Description

[0020] Figure 1 This is a block diagram illustrating an example of the configuration of a camera device according to the first embodiment of the present technology.

[0021] Figure 2 This is a diagram illustrating an example of the use of the camera system according to the first embodiment of this technology.

[0022] Figure 3 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element according to a first embodiment of the present technology.

[0023] Figure 4 This is a block diagram illustrating an example of the configuration of an optical receiver chip according to the first embodiment of the present technology.

[0024] Figure 5 This is a block diagram illustrating an example of the configuration of a circuit chip according to the first embodiment of the present technology.

[0025] Figure 6 This is a diagram illustrating an example of the configuration of the pixel AD (analog-to-digital) conversion unit in the first embodiment of the present technology.

[0026] Figure 7 This is a block diagram illustrating an example of the configuration of an ADC (Analog-to-Digital Converter) according to a first embodiment of the present technology.

[0027] Figure 8 This is a circuit diagram illustrating an example of the configuration of the differential input circuit and positive feedback circuit of the first embodiment of this technology.

[0028] Figure 9 This is a circuit diagram illustrating an example of the configuration of the pixel circuit and the amplifier circuit of the first embodiment of the present technology.

[0029] Figure 10This is a plan view illustrating an example layout of the pixel elements of a first embodiment of the present technology.

[0030] Figure 11 This is a block diagram illustrating an example of the configuration of a signal processing circuit according to the first embodiment of the present invention.

[0031] Figure 12 This is a circuit diagram illustrating an example of the configuration of the operational circuit of the first embodiment of this technology.

[0032] Figure 13 This is a diagram illustrating an example of TDI processing in a first embodiment of the present technology.

[0033] Figure 14 This is a flowchart illustrating an operational example of the camera system according to the first embodiment of the present technology.

[0034] Figure 15 This is a circuit diagram illustrating an example of the configuration of the pixel circuit and the amplifier circuit in the second embodiment of the present technology.

[0035] Figure 16 This is a circuit diagram illustrating an example of the configuration of the differential input circuit, positive feedback circuit, and FD shared block in the third embodiment of this technology.

[0036] Figure 17 This is a circuit diagram illustrating an example of the configuration of the FD shared block in the third embodiment of this technology.

[0037] Figure 18 This is a plan view illustrating an example layout of the pixel elements of the third embodiment of the present technology. Detailed Implementation Plan

[0038] The following describes the mode of implementing this technology (hereinafter referred to as the implementation mode). The description will be given in the following order.

[0039] 1. First implementation scheme (example of multiple photoelectric conversion elements arranged at intervals)

[0040] 2. Second embodiment (in which multiple photoelectric conversion elements are arranged at intervals and in which the reset transistor is removed)

[0041] 3. Third implementation scheme (an example in which multiple pixels share a floating diffusion layer)

[0042] <1. First Implementation Plan>

[0043] [Example of camera device configuration]

[0044] Figure 1This is a block diagram illustrating an example configuration of a camera device 100 according to a first embodiment of the present technology. The camera device 100 is a device for capturing image data and includes an optical unit 110, a solid-state imaging element 200, a storage unit 120, a control unit 130, and a communication unit 140.

[0045] The optical unit 110 converges the incident light and guides it onto the solid-state imaging element 200. The solid-state imaging element 200 captures image data. The solid-state imaging element 200 provides the image data to the storage unit 120 via signal line 209.

[0046] The storage unit 120 stores image data. The control unit 130 controls the solid-state imaging element 200 to capture image data. The control unit 130 provides the solid-state imaging element 200 with a vertical synchronization signal VSYNC, for example, indicating the timing of image capture, via the signal line 208.

[0047] The communication unit 140 reads image data from the storage unit 120 and sends the image data to an external device.

[0048] Figure 2 This is a diagram illustrating an example of the use of the camera device 100 in the first embodiment of the present technology. As shown, the camera device 100 is used in a factory having a belt conveyor 510, etc.

[0049] The belt conveyor 510 moves the subject 511 at a constant speed along a predetermined direction. The camera device 100 is fixed near the belt conveyor 510 and generates image data by capturing images of the subject 511. The image data is used, for example, to inspect for defects or for other purposes. This achieves FA (Automatic Facilitation).

[0050] It should be noted that although the camera device 100 captures images of the subject 511 moving at a constant speed, the technology is not limited to this configuration. For example, in aerial photography, images can be captured by moving the camera device 100 at a constant speed relative to the subject.

[0051] [Example of solid-state imaging element configuration]

[0052] Figure 3 This is a diagram illustrating an example of the stacked structure of a solid-state imaging element 200 according to a first embodiment of the present invention. The solid-state imaging element 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via connections such as vias. It should be noted that not only vias can be used to connect the chips, but copper connectors and bumps can also be used to connect the chips.

[0053] Figure 4This is a block diagram illustrating an example of the configuration of an optical receiver chip 201 according to the first embodiment of the present technology. The optical receiver chip 201 includes a pixel array section 210 and peripheral circuitry 212.

[0054] Multiple pixel circuits 220 are arranged in a two-dimensional grid pattern in the pixel array section 210. Furthermore, the pixel array section 210 is divided into multiple pixel blocks 211. For example, each pixel block 211 has four rows × two columns of pixel circuits 220 arranged in each block. In addition, multiple transistors are disposed outside each pixel circuit 220. However, for ease of explanation, these transistors are omitted in the figures.

[0055] For example, the peripheral circuit 212 includes a circuit for supplying DC voltage, etc.

[0056] Figure 5 This is a block diagram illustrating an example of the configuration of the circuit chip 202 according to the first embodiment of the present invention. The circuit chip 202 includes a DAC (digital-to-analog converter) 251, a pixel driving circuit 252, a timecode generation unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255. Furthermore, the circuit chip 202 also includes a control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257.

[0057] DAC251 generates a reference signal using a digital-to-analog (DA) converter within a given AD conversion cycle. For example, a sawtooth ramp signal can be used as the reference signal. DAC 251 provides the reference signal to the pixel AD converter 254.

[0058] The time code generation unit 253 generates a time code representing the time in the AD conversion cycle. The time code generation unit 253 is implemented, for example, by a counter. For example, a Gray code counter is used as this counter. The time code generation unit 253 provides the time code to the pixel AD conversion unit 254.

[0059] The pixel driving circuit 252 drives the individual pixel circuits 220 to generate analog pixel signals.

[0060] The pixel AD conversion unit 254 performs AD conversion to convert the analog signals (i.e., pixel signals) of each pixel circuit 220 into digital signals. The pixel AD conversion unit 254 is divided into multiple clusters 300. A cluster 300 is set for each pixel block 211, and the cluster 300 converts the analog signals in the corresponding pixel block 211 into digital signals.

[0061] The pixel AD conversion unit 254 generates image data in which the digital signals have been arranged by AD conversion as a frame, and provides the image data to the signal processing circuit 400.

[0062] The vertical scanning circuit 255 drives the pixel AD conversion unit 254 to perform AD conversion.

[0063] The signal processing circuit 400 performs given signal processing on the frame. This signal processing includes various processes such as CDS (Correlated Double Sampling) processing and TDI processing. The signal processing circuit 400 then provides the processed frame to the image processing circuit 260.

[0064] The image processing circuit 260 performs given image processing on the frame from the signal processing circuit 400. This image processing includes image recognition, black mark correction, image correction, and de-mosaic processing. The image processing circuit 260 then provides the processed frame to the output circuit 257.

[0065] The output circuit 257 outputs the image-processed frame to an external device.

[0066] The control circuit 256 synchronously controls the operating timing of each of the following circuits in DAC 251, pixel driving circuit 252, vertical scanning circuit 255, signal processing circuit 400, image processing circuit 260 and output circuit 257 in sync with the vertical synchronization signal VSYNC.

[0067] [Example of pixel AD conversion unit configuration]

[0068] Figure 6 This diagram illustrates an example of the configuration of the pixel AD conversion unit 254 according to the first embodiment of the present technology. Multiple ADCs 310 are arranged in the pixel AD conversion unit 254 in a two-dimensional grid pattern. ADCs 310 are arranged for each pixel circuit 220. In the case of providing N rows (where N is an integer) × M columns (where M is an integer) of pixel circuits 220, N × M ADCs 310 are arranged.

[0069] Each cluster 300 has the same number of ADCs 310 as the pixel circuits 220 in the pixel block 211. If the pixel circuits 220 are arranged in four rows and two columns in the pixel block 211, then the ADCs 310 are also arranged in four rows and two columns in the cluster 300.

[0070] The ADC 310 performs an analog-to-digital (AD) conversion on the analog pixel signal generated by the corresponding pixel circuit 220. During the AD conversion, the ADC 310 compares the pixel signal with a reference signal and retains the time code obtained when the comparison result is inverted. The ADC 310 then outputs the retained time code as a digital signal converted from the analog signal.

[0071] Furthermore, repeater sections 360 are arranged for each column of cluster 300. When the number of columns in cluster 300 is M / 2, M / 2 repeater sections 360 are arranged. Repeater sections 360 transmit time codes. Repeater sections 360 transmit time codes from time code generation section 253 to ADC 310. Furthermore, repeater sections 360 transmit digital signals from ADC 310 to signal processing circuit 400. This transmission of digital signals is called "readout" of digital signals.

[0072] Furthermore, in the diagram, the numbers in parentheses illustrate an example of the order in which the digital signals from the ADC 310 are read. For instance, the first row and odd-numbered columns are read out first, and the first row and even-numbered columns are read out second. The second row and odd-numbered columns are read out third, and the second row and even-numbered columns are read out fourth. From here on, the digital signals in each row and even-numbered column are read out in a similar alternating manner.

[0073] It should be noted that although an ADC 310 is arranged for each pixel circuit 220, this technology is not limited to this configuration. Multiple pixel circuits 220 can share a single ADC 310.

[0074] [Example of ADC configuration]

[0075] Figure 7 This is a block diagram illustrating an example configuration of an ADC 310 according to a first embodiment of the present technology. The ADC 310 includes a differential input circuit 320, a positive feedback circuit 330, a latch control circuit 340, and a plurality of latch circuits 350.

[0076] Furthermore, an amplifier circuit 230 is arranged between the pixel circuit 220 and the ADC 310. The amplifier circuit 230 amplifies the pixel signal from the pixel circuit 220 and provides the amplified pixel signal to the ADC 310. The circuit including the pixel circuit 220 and the amplifier circuit 230 serves as a pixel.

[0077] In addition, a pixel circuit 220, an amplifier circuit 230 and a portion of a differential input circuit 320 are arranged in the optical receiver chip 201, and the remaining portion of the differential input circuit 320 and subsequent circuits are arranged in the circuit chip 202.

[0078] The differential input circuit 320 compares the pixel signal from the amplifier circuit 230 with the reference signal from the DAC 251. The differential input circuit 320 provides a comparison result signal, representing the comparison result, to the positive feedback circuit 330.

[0079] The positive feedback circuit 330 adds a portion of the output to the input (comparison result signal) and provides the result signal as the output signal VCO to the latch control circuit 340.

[0080] The latch control circuit 340, based on the control signal xWORD from the vertical scanning circuit 255, causes the multiple latch circuits 350 to hold the time code obtained when the output signal VCO reverses.

[0081] The latch circuit 350 holds the time code from the repeater section 360 under the control of the latch control circuit 340. The number of latch circuits 350 is equal to the number of bits in the time code. For example, in the case of a 15-bit time code, 15 latch circuits are arranged in the ADC 310. Furthermore, the repeater section 360 reads the held time code as a digital signal converted from the analog signal.

[0082] Using the configuration shown in the figure, ADC 310 converts the pixel signal from amplifier circuit 230 into a digital signal.

[0083] [Example of differential input circuit and positive feedback circuit configuration]

[0084] Figure 8 This is a circuit diagram illustrating an example of the configuration of the pixel circuit 220, the differential input circuit 320, and the positive feedback circuit 330 in the first embodiment of the present technology.

[0085] The differential input circuit 320 includes pMOS (p-channel metal-oxide-semiconductor) transistors 321, 324, and 326. Furthermore, the differential input circuit 320 includes nMOS (n-channel MOS) transistors 322, 323, 325, 327, and 328. Specifically, nMOS transistors 322, 323, 325, and 328 are disposed in the optical receiver chip 201, while the remaining transistors are disposed in the circuit chip 202.

[0086] nMOS transistors 322 and 325 form a differential pair, and the sources of these transistors are connected together to the drain of nMOS transistor 323. Furthermore, the drain of nMOS transistor 322 is connected to the drain of pMOS transistor 321 and the gates of pMOS transistors 321 and 324. The drain of nMOS transistor 325 is connected to the drain of pMOS transistor 324 and the gate of pMOS transistor 326. Additionally, a reference signal REF from DAC 251 is input to the gate of nMOS transistor 322.

[0087] A given bias voltage Vb is applied to the gate of the nMOS transistor 323, and a given ground voltage is applied to the source of the nMOS transistor 323.

[0088] The pixel signal SIG from the amplifier circuit 230 is input to the gate of the nMOS transistor 325.

[0089] pMOS transistors 321, 324, and 326 form a current mirror circuit. A power supply voltage VDDH is applied to the sources of pMOS transistors 321, 324, and 326. The power supply voltage VDDH is higher than the power supply voltage VDDL, which will be described later.

[0090] A power supply voltage VDDL is applied to the gate of nMOS transistor 327. Furthermore, the drain of nMOS transistor 327 is connected to the drain of pMOS transistor 326, and the source of nMOS transistor 327 is connected to positive feedback circuit 330.

[0091] nMOS transistor 328 short-circuites the gate and drain of nMOS transistor 325 according to the auto-zero signal AZ from pixel drive circuit 252.

[0092] The positive feedback circuit 330 includes pMOS transistors 331, 332, 334, and 335, and nMOS transistors 333, 336, and 337. PMOS transistors 331, 332, and 333 are connected in series to the power supply voltage VDDL. Furthermore, a drive signal INI2 from the vertical scan circuit 255 is input to the gate of pMOS transistor 331. The connection node between pMOS transistors 332 and 333 is connected to the source of nMOS transistor 327.

[0093] A ground voltage is applied to the source of the nMOS transistor 333, and a drive signal INI1 from the vertical scan circuit 255 is input to the gate of the nMOS transistor 333.

[0094] pMOS transistors 334 and 335 are connected in series to the power supply voltage VDDL. Furthermore, the drain of pMOS transistor 335 is connected to the gate of pMOS transistor 332 and the drains of nMOS transistors 336 and 337. A control signal TESTVCO from the vertical scan circuit 255 is input to the gates of pMOS transistors 335 and 337. Additionally, the gates of pMOS transistors 334 and 336 are connected to the connection node between pMOS transistors 332 and 333.

[0095] The output signal VCO is output from the connection node between pMOS transistor 335 and nMOS transistor 337. Additionally, a ground voltage is applied to the sources of nMOS transistors 336 and 337.

[0096] It should be noted that the differential input circuit 320 and the positive feedback circuit 330 are not limited to... Figure 8 The circuit shown is provided as a reference. Figure 7 The functions described herein are sufficient.

[0097] [Examples of amplifier and pixel circuit configurations]

[0098] Figure 9 This is a circuit diagram illustrating an example of the configuration of the pixel circuit 220 and the amplifier circuit 230 in the first embodiment of the present technology.

[0099] The pixel circuit 220 includes a discharge transistor 221, a photoelectric conversion element 222, a transfer transistor 223, a reset transistor 224, a capacitor 225, a gain control transistor 226, and a floating diffusion layer 227. An nMOS transistor, for example, is used as the discharge transistor 221, the transfer transistor 223, the reset transistor 224, and the gain control transistor 226.

[0100] The discharge transistor 221 discharges the charge accumulated in the photoelectric conversion element 222 according to the drive signal OFG from the pixel driving circuit 252. The photoelectric conversion element 222 generates charge through photoelectric conversion.

[0101] The transfer transistor 223 transfers charge from the photoelectric conversion element 222 to the floating diffusion layer 227 according to the transfer signal TG from the pixel driving circuit 252.

[0102] The reset transistor 224 initializes the floating diffusion layer 227 according to the reset signal RST from the pixel driving circuit 252.

[0103] Capacitor 225 is inserted between the connection node between reset transistor 224 and gain control transistor 226 and the ground terminal.

[0104] Gain control transistor 226 controls the analog gain relative to the voltage of floating diffusion layer 227 according to control signal FDG from pixel driving circuit 252. By using analog gain to reduce the voltage of floating diffusion layer 227 and outputting the reduced voltage, the amount of signal processed by pixel circuit 220 (i.e., saturation signal amount) can be increased.

[0105] The floating diffusion layer 227 accumulates the transferred charge and generates a voltage commensurate with the amount of charge.

[0106] In addition, the amplifier circuit 230 includes nMOS transistors 231 and 232 and a capacitor 233. nMOS transistors 231 and 232 are connected in series between the power supply and ground terminals. The gate of the power supply-side nMOS transistor 231 is connected to the floating diffusion layer 227. A given bias voltage VB2 is applied to the gate of the ground-side nMOS transistor 232.

[0107] Furthermore, the connection node between nMOS transistors 231 and 232 is connected to the differential input circuit 320 via capacitor 233. The gate-source capacitance of the nMOS transistor 325 on the pixel signal side of the differential pair in the differential input circuit 320 is denoted as Cgs, and the capacitance value of capacitor 233 is set to be much larger than the gate-source capacitance Cgs. Assuming a direct connection between the floating diffusion layer 227 and the gate of the nMOS transistor 325, the floating diffusion layer 227 may fluctuate significantly due to the coupling between the gate-source capacitance Cgs and the floating diffusion layer 227, which prolongs the AD conversion cycle. However, this effect caused by coupling can be mitigated by increasing capacitor 233.

[0108] It should be noted that the pixel circuit 220 and the amplifier circuit 230 are not limited to... Figure 9 The circuit shown is provided as a reference. Figure 7 The functions described herein are sufficient.

[0109] Figure 10 This is a plan view illustrating an example layout of the elements of a pixel according to a first embodiment of the present technology. It is assumed that the optical axis of the incident light is the Z-axis, a given axis perpendicular to the Z-axis is the X-axis, and an axis perpendicular to both the Z-axis and the X-axis is the Y-axis.

[0110] In the light-receiving surface (i.e., in the XY plane), multiple photoelectric conversion elements 222 are arranged in a two-dimensional lattice pattern of N rows and M columns. The dimension of each photoelectric conversion element 222 in the Y-axis direction is denoted as Y1. In the XY plane, M photoelectric conversion elements 222 are arranged adjacent to each other without spacing in the X-axis direction. Hereinafter, a group of M photoelectric conversion elements 222 arranged along the X-axis direction and a corresponding group of digital signals are referred to as a "row". At the same time, N photoelectric conversion elements 222 are arranged along the Y-axis direction with a spacing of Y2. In other words, N rows are arranged with a spacing of Y2.

[0111] Here, we assume the following relationship exists between size Y1 and spacing Y2:

[0112] Y1≤Y2...Formula 1

[0113] In the figure, the spacing Y2 is equal to the size Y1. It should be noted that, as shown in Equation 1, the spacing Y2 can be increased to be greater than the size Y1. When increasing the spacing Y2 to be greater than the size Y1, the spacing Y2 is set to an integer multiple of Y1. The larger the spacing Y2, the larger the size of the lower ADC310 in the Y-axis direction can be increased. Therefore, the pixels in the X-axis direction can be miniaturized by additionally reducing the size of the ADC 310 in the X-axis direction.

[0114] Furthermore, a transistor arrangement region 241 is provided in the spacing region 240 between every two of the N photoelectric conversion elements 222 in the Y-axis direction. A predetermined number of transistors, a floating diffusion layer 227, and capacitors 233 and 225 are arranged in the transistor arrangement region 241. The predetermined number of transistors includes a discharge transistor 221, a reset transistor 224, a gain control transistor 226, and nMOS transistors 231, 232, 322, 323, and 325. In other words, Figure 8 The transistors in the differential input circuit 320 shown are Figure 9 The transistors in the pixel circuit 220 and amplifier circuit 230 shown are arranged in the transistor arrangement region 241. These transistors are generated by, as shown in the reference... Figure 9 The signal (pixel signal or signal obtained by amplifying a pixel signal) generated by any of the plurality of photoelectric conversion elements 222 is proportional to the amount of charge. In addition, a transmission transistor 223 is arranged between the transistor arrangement region 241 and the photoelectric conversion element 222.

[0115] Here, we assume a comparative example in which N rows and M columns of photoelectric conversion elements 222 are arranged without spacing along the X and Y axes, and various transistors such as discharge transistors 221 and floating diffusion layers 227 are arranged around the photoelectric conversion elements 222. In this comparative example, the more transistors there are, the smaller the light-receiving area of ​​the photoelectric conversion elements 222.

[0116] Conversely, as shown in the figure, if N photoelectric conversion elements 222 are arranged at predetermined intervals along the Y-axis, the light-receiving area can be increased compared to the comparative example, because transistors and the like can be arranged within the spacing region 240. This increased light-receiving area improves pixel sensitivity. Furthermore, more transistors can be arranged compared to the comparative example, allowing additional circuits such as amplifier circuits 230 to be arranged in addition to the pixel circuit 220.

[0117] [Example of signal processing circuit configuration]

[0118] Figure 11This is a block diagram illustrating an example configuration of a signal processing circuit 400 according to a first embodiment of the present technology. The signal processing circuit 400 includes multiple selectors 405, multiple arithmetic circuits 410, a CDS frame memory 440, and a TDI frame memory 450.

[0119] For each column of cluster 300, in other words, for each repeater section 360, selectors 405 are arranged. If two columns of ADCs 310 are arranged in cluster 300, selectors 405 are arranged for every two columns. Furthermore, operational circuits 410 are arranged for each column of ADCs 310. If M columns of ADCs 310 are provided, M / 2 selectors 405 and M operational circuits 410 are arranged.

[0120] As described above, the repeater section 360 alternately outputs digital signals in odd and even columns.

[0121] Under the control of the control circuit 256, the selector 405 selects the destination of the digital signal. When the repeater section 360 outputs an odd number of signals, the selector 405 outputs the digital signal corresponding to the odd number of signals to the arithmetic circuit 410. Simultaneously, when an even number of signals is output, the selector 405 outputs the digital signal corresponding to the even number of signals to the arithmetic circuit 410.

[0122] The arithmetic circuit 410 performs CDS processing and TDI processing on the digital signal from the selector 405.

[0123] Here, the digital signal includes P-phase level and D-phase level. The P-phase level represents the level when the reset signal RST initializes the pixel circuit 220. Simultaneously, the D-phase level represents the level corresponding to the exposure amount when charge is transferred via the transmission signal TG. The P-phase level is also called the reset level, and the D-phase level is also called the signal level.

[0124] In CDS processing, M arithmetic circuits 410 maintain a P-phase frame configured with P-phase levels in the CDS frame memory 440. Then, the M arithmetic circuits 410 calculate the difference between the P-phase level and the D-phase level for each pixel and generate a CDS frame with differential data. Simultaneously, in TDI processing, the M arithmetic circuits 410 maintain a frame processed by CDS in the TDI frame memory 450 and update the TDI frame memory 450 with accumulated sum data.

[0125] In addition, M arithmetic circuits 410 provide CDS frames and TDI frames processed by TDI to image processing circuit 260.

[0126] [Example of operational circuit construction]

[0127] Figure 12This is a circuit diagram illustrating an example configuration of the arithmetic circuit 410 according to a first embodiment of the present invention. The arithmetic circuit 410 includes a TDI circuit 420 and a CDS circuit 430. The TDI circuit 420 includes a buffer 421, a selector 422, an adder 423, and a switch 424. The CDS circuit 430 includes a selector 431, a buffer 432, a selector 433, a subtractor 434, and a switch 435. The operation between the respective selectors 422, 431, and 433 and the respective switches 424 and 425 is controlled, for example, by a control circuit 256.

[0128] Selector 431 selects a digital signal from selector 405 or a digital signal from TDI frame memory 450, and outputs the selected signal to buffer 421.

[0129] Buffer 421 delays the signal from selector 431 and outputs the delayed signal. It should be noted that buffer 421 is an example of the second buffer defined in the claims.

[0130] Selector 422 selects a digital signal from buffer 421 or a digital signal with a decimal value of "0", and outputs the selected signal to adder 423.

[0131] Adder 423 adds the digital signal from selector 422 and the digital signal from buffer 432 together. Adder 423 provides the digital signal representing the sum as accumulated sum data to switch 424.

[0132] Switch 424 opens or closes the path between adder 423 and TDI frame memory 450.

[0133] Buffer 432 delays the signal from CDS frame memory 440 and outputs the delayed signal. It should be noted that buffer 432 is an example of the first buffer as defined in the claims.

[0134] Selector 433 selects a digital signal or a digital signal with a decimal value of "0" from buffer 432 and outputs the selected signal to subtractor 434.

[0135] Subtractor 434 calculates the difference between the digital signal from buffer 421 and the digital signal from selector 433. Subtractor 434 provides the digital signal representing this difference as differential data to switch 435.

[0136] Switch 435 opens or closes the path between subtractor 434 and CDS frame memory 440.

[0137] Using the configuration shown in the figure, the CDS circuit 430 can perform CDS processing. Furthermore, the TDI circuit 420 can perform TDI processing.

[0138] Figure 13 This diagram illustrates an example of TDI processing according to a first embodiment of the present technology. For example, assume that the CDS frame memory 440 and TDI frame memory 450 are initialized, and frame F1 is captured first, followed by frames F2, F3, F4, F5, F6, F7, and F8 in turn. Frame F5 and subsequent frames are omitted in the diagram. Furthermore, the arrows in the diagram indicate the direction of movement of the subject. As shown, assume the subject moves along the Y-axis and moves one row at a time in the direction of increasing row address. The gray areas between rows in the diagram represent the row spacing regions. Assume the size of the spacing region is one row.

[0139] In the TDI processing, the signal processing circuit 400 adds the lines L1 of frame F1, L2 of frame F3, L3 of frame F5, and L4 of frame F7 after CDS processing. As mentioned above, the subject moves one line at a time, and the size of the spacing area is one line. Therefore, the patterns of the lines to be added are identical. The signal processing circuit 400 outputs the added lines as the last line of the TDI frame.

[0140] Furthermore, in the TDI processing, the signal processing circuit 400 adds line L1 of frame F2, line L2 of frame F4, line L3 of frame F6, and line L4 of frame F8 after CDS processing. The signal processing circuit 400 outputs the added line as the penultimate line of the TDI frame. Similarly, other lines are generated by adding the four lines from frame F3 and subsequent frames.

[0141] When the subject is moving rapidly, exposure time needs to be reduced to prevent camera shake. Reducing exposure time results in a darker image. However, TDI (Time Difference Editing) processing can improve brightness by adding multiple rows with the same pattern. Furthermore, the more rows to add, the more noise is reduced due to the smoothing effect. The increased brightness and reduced noise improve frame (i.e., image data) quality compared to not performing TDI processing.

[0142] It should be noted that although the signal processing circuit 400 adds four rows, the number of rows added is not limited to four; two or more rows are sufficient. Furthermore, although the signal processing circuit 400 integrates the first four rows of the first eight frames, this technique is not limited to this configuration. For example, if the subject moves in the opposite direction, the signal processing circuit 400 only needs to integrate the first four rows of the first eight frames, starting from the last row.

[0143] Furthermore, although there is a spacing region of one row size between rows, rows with the same pattern can be added together by adding them every other frame, such as frame F1, frame F3, frame F5, and frame F7. It should be noted that when the row spacing region is set to two or three rows in size, it is only necessary to add them every two or three frames.

[0144] [Operational Example of a Solid-State Imaging Element]

[0145] Figure 14 This is an example flowchart illustrating an operational example of the solid-state imaging element 200 according to a first embodiment of the present technology. For example, the operation begins when a given application for capturing frames is executed.

[0146] The pixel driving circuit 252 of the solid-state imaging element 200 drives all pixels and simultaneously begins the exposure of these pixels (step S901). This control method of simultaneously exposing all pixels is called the global shutter scheme.

[0147] ADC 310 converts the P-phase level from analog to digital form just before the exposure ends (step S902). Then, at the end of the exposure, ADC 310 converts the D-phase level from analog to digital form, and the arithmetic circuit 410 performs CDS processing (step S903).

[0148] Image processing circuit 260 performs given image processing on the frame after CDS processing (step S904), and arithmetic circuit 410 performs TDI processing (step S905). Image processing circuit 260 performs given image processing on the frame after TDI processing (step S906), and output circuit 257 outputs the processing result (step S907). After step S907, solid-state imaging element 200 terminates the processing of captured frames. When two or more frames are captured consecutively, steps S901 to S907 are repeated synchronously with vertical synchronization signal VSYNC.

[0149] As described above, according to the first embodiment of this technology, a plurality of photoelectric conversion elements 222 are arranged at predetermined intervals along the Y-axis direction, and transistors are arranged between them. This allows the receiving area of ​​the photoelectric conversion elements 222 to be expanded compared to the case where no interval is set. This improves pixel sensitivity.

[0150] <2. Second Implementation Plan>

[0151] In the first embodiment described above, a reset transistor 224 is disposed in the pixel circuit 220 to initialize the floating diffusion layer 227. In this configuration, the circuit size on the light receiver chip 201 side increases due to the increase in the number of pixels. The pixel circuit 220 of the second embodiment differs from that of the pixel circuit of the first embodiment in that the reset transistor 224 is removed.

[0152] Figure 15 This is a circuit diagram illustrating an example configuration of the pixel circuit 220 and the amplifier circuit 230 in the second embodiment of this technology. The pixel circuit 220 in the second embodiment differs from that in the first embodiment in that it does not include a reset transistor 224. In the second embodiment, for example, the floating diffusion layer 227 is initialized by the pixel driving circuit 252 turning on the discharge transistor 221 and the transmission transistor 223. The removal of the reset transistor 224 reduces the circuit size of the light receiving chip 201.

[0153] As described above, according to the second embodiment of this technology, since the pixel driving circuit 252 initializes the floating diffusion layer 227 by turning on the discharge transistor 221 and the transmission transistor 223, the reset transistor 224 can be removed. This reduces the circuit size of the light receiving chip 201.

[0154] <3. Third Implementation Plan>

[0155] In the first embodiment described above, an amplifier circuit 230 and other circuits are added to the row spacing area. In this configuration, the circuit size on the light receiving chip 201 side increases due to the increase in the number of pixels. The pixel circuit 220 of the third embodiment differs from the pixel circuit of the first embodiment in that multiple pixels share a floating diffusion layer 227.

[0156] Figure 16 This is a circuit diagram illustrating an example configuration of the differential input circuit 320, positive feedback circuit 330, and FD shared block 235 according to the third embodiment of this technology. Multiple pixels sharing the floating diffusion layer 227 are arranged in the FD shared block 235. On a one-to-one basis, the FD shared block 235 is connected to the ADC 310, which includes the differential input circuit 320 and the positive feedback circuit 330. That is, multiple pixels also share the ADC 310.

[0157] Figure 17 This is a circuit diagram illustrating an example configuration of the FD common block 235 according to the third embodiment of the present technology. The FD common block 235 includes discharge transistors 221 and 236, photoelectric conversion elements 222 and 237, transmission transistors 223 and 238, and a floating diffusion layer 227.

[0158] The connection configuration of the discharge transistor 221, photoelectric conversion element 222, transmission transistor 223, and floating diffusion layer 227 is similar to that of the first embodiment. However, it should be noted that a transmission signal TG1 is input to the transmission transistor 223 and a drive signal OFG1 is input to the discharge transistor 221.

[0159] The discharge transistor 236 discharges the charge accumulated in the photoelectric conversion element 237 according to the drive signal OFG2 from the pixel driving circuit 252. The photoelectric conversion element 237 generates charge through photoelectric conversion.

[0160] The transfer transistor 238 transfers charge from the photoelectric conversion element 237 to the floating diffusion layer 227 according to the transfer signal TG2 from the pixel driving circuit 252.

[0161] A circuit including discharge transistor 221, photoelectric conversion element 222, transmission transistor 223, and floating diffusion layer 227 is used as one pixel. Furthermore, a circuit including discharge transistor 236, photoelectric conversion element 237, transmission transistor 238, and floating diffusion layer 227 is also used as one pixel. That is, the floating diffusion layer 227 is shared by two pixels. The sharing of the floating diffusion layer 227 by multiple pixels reduces the circuit size of the light receiving chip 201 for each pixel.

[0162] It should be noted that although the floating diffusion layer 227 is shared by two pixels, the number of pixels sharing the floating diffusion layer 227 can be more than three.

[0163] Figure 18 This is a plan view illustrating an example layout of the pixel elements according to the third embodiment of the present invention. Rows of N photoelectric conversion elements 222 are arranged in the X-axis direction with a spacing of 1 row in the Y-axis direction. Rows of N floating diffusion layers 227 are arranged between the rows including the photoelectric conversion elements 222. A transistor arrangement region 241 is then provided between the photoelectric conversion elements 222 and 237. Discharge transistors 221, floating diffusion layers 227, and other elements are arranged in the transistor arrangement region 241. Furthermore, a transmission transistor 223 is arranged between the transistor arrangement region 241 and the photoelectric conversion elements 222, and a transmission transistor 238 is arranged between the transistor arrangement region 241 and the photoelectric conversion elements 237.

[0164] It should be noted that when there are three or more pixels sharing the floating diffusion layer 227, only a spacing of two or more rows is required between the rows including the photoelectric conversion element 222. The larger the spacing between the rows including the photoelectric conversion element 222, the larger the size of the lower ADC 310 in the Y direction can be, which makes it easier to miniaturize pixels in the X-axis direction.

[0165] As described above, according to the third embodiment of the present technology, a circuit sharing the floating diffusion layer 227 is provided between rows including the floating diffusion layer 227, which enables a reduction in the circuit size of the light receiving chip 201 for each pixel compared to the case where the floating diffusion layer 227 is not shared.

[0166] It should be noted that the above embodiments illustrate examples for implementing this technology, and the subject matter of the embodiments corresponds to the subject matter of the invention defined in the claims. Similarly, the subject matter of the invention defined in the claims corresponds to the subject matter with the same name in the embodiments of this technology. However, it should be noted that this technology is not limited to the embodiments and can be implemented by various modifications to the embodiments.

[0167] It should be noted that the beneficial effects described in this specification are illustrative and not limiting, and other beneficial effects may also exist.

[0168] It should be noted that this technology may also have the following configuration.

[0169] (1) A solid-state imaging element, comprising:

[0170] A plurality of photoelectric conversion elements are arranged at a predetermined interval along a predetermined direction, wherein the dimension of each photoelectric conversion element along the predetermined direction does not exceed the predetermined interval; and

[0171] A predetermined number of transistors are arranged among the plurality of photoelectric conversion elements and are adapted to generate a signal commensurate with the amount of charge generated by any of the photoelectric conversion elements.

[0172] (2) The solid-state imaging element according to feature (1), wherein,

[0173] Any one of the plurality of photoelectric conversion elements is arranged in the pixel circuit that generates the pixel signal, and

[0174] The predetermined number of transistors are arranged in the pixel circuit and the amplifier circuit that amplifies the pixel signal.

[0175] (3) The solid-state imaging element according to feature (2), wherein,

[0176] The predetermined number of transistors includes a pair of differential transistors, which differentially amplify the predetermined reference signal and the pixel signal.

[0177] The amplifier circuit includes a capacitor connected in series with the power supply and a pair of transistors, and

[0178] The gate of one of the pair of transistors is connected to the floating diffusion layer, and the capacitor is inserted between the connection node between the pair of transistors and the gate of one of the pair of differential transistors.

[0179] (4) The solid-state imaging element according to feature (2) or (3) further includes:

[0180] A floating diffusion layer is disposed between the plurality of photoelectric conversion elements; and

[0181] A transfer transistor adapted to transfer charge from any of the plurality of photoelectric conversion elements to the floating diffusion layer, wherein,

[0182] The predetermined number of transistors includes discharge transistors that discharge charge from the floating diffusion layer, and

[0183] The pixel circuit includes any one of the plurality of photoelectric conversion elements, the floating diffusion layer, the transmission transistor, and the discharge transistor.

[0184] (5) A solid-state imaging element according to any one of features (2) to (4), wherein

[0185] The predetermined number of transistors includes gain control transistors that control the analog gain relative to the voltage of the floating diffusion layer, and

[0186] The gain control transistor is arranged in the pixel circuit.

[0187] (6) The solid-state imaging element according to feature (5), wherein,

[0188] The predetermined number of transistors includes a reset transistor that initializes the floating diffusion layer, and

[0189] The reset transistor is arranged in the pixel circuit.

[0190] (7) The solid-state imaging element according to any one of features (1) to (6) further comprises:

[0191] An analog-to-digital converter is adapted to convert pixel signals, commensurate with the amount of light received by each of the plurality of photoelectric conversion elements, into digital signals.

[0192] (8) The solid-state imaging element according to feature (7) further includes:

[0193] A time delay integration circuit, which is adapted to perform time delay integration processing on the digital signal.

[0194] (9) The solid-state imaging element according to feature (7) or (8), wherein,

[0195] The plurality of photoelectric conversion elements and the predetermined number of transistors are arranged in a predetermined optical receiving chip, and

[0196] The analog-to-digital converter is arranged in a predetermined circuit chip.

[0197] (10) A camera device, comprising:

[0198] Multiple photoelectric conversion elements are arranged along a predetermined direction at a predetermined interval, and the size of each photoelectric conversion element along the predetermined direction does not exceed the predetermined interval.

[0199] A predetermined number of transistors, arranged among the plurality of photoelectric conversion elements, and adapted to generate a signal commensurate with the amount of charge generated by any of the photoelectric conversion elements; and

[0200] A signal processing circuit is used to process digital signals that are commensurate with the amount of light received by each of the plurality of photoelectric conversion elements.

[0201] List of reference numerals

[0202] 100: Camera device

[0203] 110: Optics Department

[0204] 120: Storage Department

[0205] 130: Control Department

[0206] 140: Ministry of Communications

[0207] 200: Solid-state camera element

[0208] 201: Optical Receiver Chip

[0209] 202: Circuit Chip

[0210] 210: Pixel array section

[0211] 211: pixel block

[0212] 212: Peripheral Circuits

[0213] 220: Pixel Circuit

[0214] 221,236: Discharge transistors

[0215] 222,237: Photoelectric conversion element

[0216] 223, 238: Transmission transistors

[0217] 224: Reset transistor

[0218] 225, 233: Capacitors

[0219] 226: Gain Control Transistor

[0220] 227: Floating Diffusion Layer

[0221] 230: Amplifier Circuit

[0222] 231, 232, 322, 323, 325, 327, 328, 333, 336, 337: nMOS transistors

[0223] 235:FD shared block

[0224] 240: Spacing area

[0225] 241: Transistor Placement Area

[0226] 251:DAC

[0227] 252: Pixel driving circuit

[0228] 253: Timecode Generation Department

[0229] 254: Pixel AD conversion unit

[0230] 255: Vertical Scan Circuit

[0231] 256: Control Circuit

[0232] 257: Output Circuit

[0233] 260: Image processing circuit

[0234] 300: cluster

[0235] 310:ADC

[0236] 320: Differential Input Circuit

[0237] 321, 324, 326, 331, 332, 334, 335: pMOS transistors

[0238] 330: Positive Feedback Circuit

[0239] 340: Latch control circuit

[0240] 350: Latch circuit

[0241] 360: Repeater Department

[0242] 400: Signal processing circuit

[0243] 405, 422, 431, 433: Selectors

[0244] 410: Operational circuit

[0245] 420: TDI circuit

[0246] 421, 432: Buffer

[0247] 423: Adder

[0248] 424, 435: Switches

[0249] 430: CDS Circuit

[0250] 434: Subtractor

[0251] 440: CDS Frame Memory

[0252] 450: TDI Frame Memory

[0253] 510: Belt Conveyor

[0254] 511: Subject.

Claims

1. A solid-state imaging element, comprising: Multiple photoelectric conversion elements are arranged at a predetermined interval along a predetermined direction, wherein the dimension of each photoelectric conversion element along the predetermined direction does not exceed the predetermined interval; and A predetermined number of transistors are arranged among the plurality of photoelectric conversion elements and generate a signal commensurate with the amount of charge generated by any one of the photoelectric conversion elements, wherein, Any one of the plurality of photoelectric conversion elements is arranged in the pixel circuit that generates the pixel signal, and The predetermined number of transistors are arranged in the pixel circuit and the amplification circuit that amplifies the pixel signal, wherein, The predetermined number of transistors includes a pair of differential transistors, which differentially amplify the predetermined reference signal and the pixel signal. The amplifier circuit includes a capacitor connected in series with the power supply and a pair of transistors, and The gate of one of the pair of transistors is connected to the floating diffusion layer, and the capacitor is inserted between the connection node between the pair of transistors and the gate of one of the pair of differential transistors.

2. The solid-state imaging element according to claim 1, further comprising: A floating diffusion layer is disposed between the plurality of photoelectric conversion elements; and A transfer transistor adapted to transfer charge from any of the plurality of photoelectric conversion elements to the floating diffusion layer, wherein, The predetermined number of transistors includes discharge transistors that discharge charge from the floating diffusion layer, and The pixel circuit includes any one of the plurality of photoelectric conversion elements, the floating diffusion layer, the transmission transistor, and the discharge transistor.

3. The solid-state imaging element according to claim 1, wherein, The predetermined number of transistors includes gain control transistors that control an analog gain relative to the voltage of a floating diffusion layer disposed between the plurality of photoelectric conversion elements, and The gain control transistor is arranged in the pixel circuit.

4. The solid-state imaging element according to claim 3, wherein, The predetermined number of transistors includes a reset transistor that initializes the floating diffusion layer, and The reset transistor is arranged in the pixel circuit.

5. The solid-state imaging element according to any one of claims 1 to 4, further comprising: The analog-to-digital converter converts pixel signals, which are commensurate with the amount of light received by each of the plurality of photoelectric conversion elements, into digital signals.

6. The solid-state imaging element according to claim 5, further comprising: A time delay integration circuit, which is adapted to perform time delay integration processing on the digital signal.

7. The solid-state imaging element according to claim 5, wherein, The plurality of photoelectric conversion elements and the predetermined number of transistors are arranged in a predetermined optical receiving chip, and The analog-to-digital converter is arranged in a predetermined circuit chip.

8. A camera device, comprising: Multiple photoelectric conversion elements are arranged along a predetermined direction at a predetermined interval, wherein the dimension of each photoelectric conversion element along the predetermined direction does not exceed the predetermined interval; A predetermined number of transistors are arranged among the plurality of photoelectric conversion elements and generate a signal commensurate with the amount of charge generated by any of the photoelectric conversion elements; and The signal processing circuit processes digital signals commensurate with the amount of light received by each of the plurality of photoelectric conversion elements. In this embodiment, any one of the plurality of photoelectric conversion elements is arranged in the pixel circuit that generates the pixel signal, and The predetermined number of transistors are arranged in the pixel circuit and the amplifier circuit that amplifies the pixel signal. The predetermined number of transistors includes a pair of differential transistors, which differentially amplify the predetermined reference signal and the pixel signal. The amplifier circuit includes a capacitor connected in series with the power supply and a pair of transistors, and The gate of one of the pair of transistors is connected to the floating diffusion layer, and the capacitor is inserted between the connection node between the pair of transistors and the gate of one of the pair of differential transistors.

Images