A multi-phase parallel rapid acquisition system and method for navigation system

Abstract

The present invention discloses a multi-phase parallel rapid acquisition system and method for use in a navigation system. The system comprises a peripheral circuit and an internal logic circuit. The peripheral circuit includes a general control processor and an analog-to-digital conversion module. The internal logic circuit includes an interface module for read-write access control with the general control processor, a system configuration module for implementing system configuration, a channel parameter storage module for storing satellite acquisition parameters, a control module for scheduling various modules, a data preprocessing module for implementing intermediate frequency carrier stripping, downsampling, and requantization, a data storage module for storing data required for acquisition, an internal code generator for generating internal codes, a code storage module for storing codes required for acquisition, and a multi-phase parallel detection module for implementing parallel detection of 32 phases. The present invention can improve acquisition efficiency and, compared with existing software receivers, can reduce overhead and save resources.

Description

Technical Field

[0001] The present invention relates to the field of navigation terminal applications, and in particular to a multi-phase parallel fast capture system and method applied to a navigation system. Background Art

[0002] Taking a typical GPS satellite signal as an example, signal capture is the first step in signal processing within a GPS receiver. Only after signal capture is it possible to start subsequent processing processes such as signal tracking, navigation message extraction, and pseudorange calculation.

[0003] For GPS systems, signals transmitted by different satellites have the same carrier frequency band and modulation method. What distinguishes different satellites is their pseudo-random codes. Signal acquisition is a problem not only for GPS systems but for all Code Division Multiple Access (CDMA) systems. The reasons for this are as follows:

[0004] 1. Because all GPS satellites transmit signals using the same carrier frequency and channel timing, the signal received by the GPS receiver antenna is inevitably a mixture of all possible satellite signals. Only by knowing which satellites the current signal originates can the receiver track and demodulate it. From this perspective, acquisition is the first step in signal processing within a GPS receiver.

[0005] 2. After the navigation message and pseudo-random code are multiplied in the GPS system, the original signal bandwidth is widened from 50Hz to 2.046MHz or 20.46MHz for C / A code and P code respectively. z According to Shannon's theorem (C = B*log²(1+S / N), the signal power can be reduced to a very low level while maintaining the noise power. In actual GPS systems, the signal power received at the receiver antenna is quite weak, often significantly lower than the background noise level, or even completely "swamped" by the noise. In such cases, the weak GPS signal must be extracted from the noise through both acquisition and tracking.

[0006] 3. According to the characteristics of GPS signals, the strong autocorrelation of pseudo-random codes must be utilized to achieve signal tracking and demodulation of navigation messages. However, the premise for signal tracking is to first find the correct random code phase. The randomness of the receiver's power-on moment determines the randomness of the received signal phase, so the pseudo-random code phase of the signal must be captured and informed by the signal.

[0007] 4. In the GPS system, since the satellite is constantly orbiting the earth, the Doppler effect is bound to occur. Another function of the capture is to extract the carrier frequency of the signal. Let's analyze the generation of the Doppler effect: As mentioned in the previous chapter, the orbit of the GPS satellite is a near-circular orbit. We can approximately regard it as a circle (the eccentricity of the satellite orbit is only about 0.01), with a radius of 26,560 km and a satellite period of about 11 hours and 58 minutes. Therefore, the average angular velocity of the satellite can be calculated as

[0008] w=2π / (11×3600+58×60)≈1.4585×10 -4 rad / s

[0009] The average speed of the satellite is:

[0010]

[0011] According to the Doppler effect, such high-speed movement will inevitably cause the signal received by the receiver to produce Doppler frequency shift. When a satellite orbits the earth, its relative radial velocity component relative to a certain point on the earth's surface cannot reach the maximum of 3874m / s. This issue has been analyzed in detail in relevant literature, and the conclusion is that the maximum radial velocity v between the satellite and the receiver on the earth's surface is dm It is about 929m / s, and the maximum possible Doppler shift calculated is:

[0012]

[0013] Where, f r The carrier frequency of the L1 band is 1575.42 MHz.

[0014] In addition to Doppler shift caused by high-speed satellite motion, the receiver's own clock crystal oscillator deviation can also cause the downconverted IF carrier frequency to deviate from its theoretical value. For example, a 1ppm deviation in a 16.368MHz crystal oscillator will result in a carrier frequency deviation of approximately 1.6kHz.

[0015] Based on the above analysis of the Doppler effect and crystal oscillator deviation, it is particularly important to extract the current carrier frequency of the signal before subsequent signal processing. This also confirms from another perspective that signal capture is the first and most critical step in signal processing within a GPS receiver.

[0016] Signal acquisition in GPS receivers can be viewed as a three-dimensional search process, such as Figure 1As shown, the first dimension is searching from the direction of the satellite (PRN code); the second dimension is searching from the direction of the pseudo-random code phase; and the third dimension is searching from the direction of the Doppler frequency shift.

[0017] Searching in the direction of the PRN code means searching for satellite signals that the receiver can currently receive. If the receiver has no knowledge of the GPS satellite distribution in the sky when it powers on, it needs to search for 32 PRN codes, meaning it searches for all 32 satellites in the sky. This startup method is also called a "cold start," and it takes the longest time to search for PRN codes. To avoid this "random search," many GPS receivers store the positioning results and ephemeris from the last time they were used. This allows them to determine the currently visible satellites and their corresponding parameters based on the stored data from the previous use. This is known as a "hot start." However, a hot start requires that the interval between uses be no more than two hours or that the receiver be no more than 300 km away; otherwise, the experienced values will become invalid. A warm start, when the experienced values are invalid, uses the stored ephemeris to estimate the current zenithal satellites. The time taken for a warm start is between that of a hot start and a cold start.

[0018] To search from the pseudo-random code phase, we first need to generate a local pseudo-code. By adjusting different local pseudo-code phases, we correlate the local pseudo-code with the input signal. Assuming that the local carrier frequency is consistent with the signal's carrier, the strongest correlation value can be generated only when the local pseudo-random code phase and the signal's pseudo-random code phase are aligned. Once the peak value generated by the correlation between a local pseudo-code phase and the signal exceeds a predetermined threshold, we can conclude that the correct signal pseudo-random code phase has been found.

[0019] Searching from the carrier frequency perspective requires generating a local carrier, continuously adjusting the carrier frequency, and multiplying the carrier signal with the input signal. Assuming code phase alignment, if the local carrier and the input signal's carrier are close, the high-frequency components of the input signal will be removed, resulting in a peak when the pseudo-code is correlated. By searching for the peak, the carrier frequency of the signal can be found.

[0020] In actual signal capture, the pseudocode phase search and carrier frequency search are performed and completed simultaneously. If only the pseudocode phase search is completed while the carrier component still exists, then after multiplying the input signal with the local pseudocode, although the pseudocode is stripped, it is still a high-frequency signal relative to the integration time, and integrating the high-frequency signal will not produce a very high peak. Conversely, if only the carrier frequency search is completed while the pseudocode still exists, then although the input signal becomes a low-frequency signal after multiplying it with the local carrier, the presence of the pseudocode means that the signal is still a spread-spectrum signal, and a high peak will still not appear after passing through the integrator. Only after the pseudocode and carrier stripping are completed simultaneously, a low-frequency continuous wave signal is obtained, and a relatively high peak will appear after passing through the integrator.

[0021] Existing receivers generally use software receivers to capture satellite signals. However, software receivers operate according to the CPU instruction sequence and can only process input data sequentially based on a single phase, i.e., single-phase serial capture. This not only has low capture efficiency and long capture time, but also usually requires a large number of FFT acceleration units, resulting in high resource overhead. Summary of the Invention

[0022] The purpose of the present invention is to provide a multi-phase parallel fast acquisition system and method for use in a navigation system, so as to solve the problems of low capture efficiency and high resource overhead of existing receivers when capturing satellite signals.

[0023] To achieve the above object, the technical solution of the present invention is:

[0024] A multi-phase parallel fast acquisition system for a navigation system includes a peripheral circuit and an internal logic circuit, wherein the peripheral circuit includes:

[0025] A universal control processor and an analog-to-digital conversion module, wherein the analog-to-digital conversion module is used to convert module signals into digital signals;

[0026] The internal logic circuit includes:

[0027] Interface module for read and write access control with the general control processor;

[0028] System configuration module, used to implement system configuration;

[0029] Channel parameter storage module, used to store satellite acquisition parameters;

[0030] Control module, used to schedule various modules;

[0031] Data pre-processing module, used to implement intermediate frequency carrier stripping, downsampling and re-quantization;

[0032] A data storage module, used for storing the data required for capture;

[0033] An internal code generator, used for generating an internal code;

[0034] A code storage module is used to store the codes required for capture;

[0035] The multi-phase parallel detection module is used to realize parallel detection of 32 phases.

[0036] Furthermore, as an optimal technical solution, the peripheral circuit also includes a PRM chip, and the internal logic circuit also includes a PRM chip control interface module. The PRM chip controls the code storage module through the PRM chip control interface module, so that the code storage module operates in military code or long code mode.

[0037] Furthermore, as a preferred technical solution, the multi-phase parallel detection module includes:

[0038] Integration submodule, used to complete correlation and coherence integration;

[0039] Search submodule, used to complete carrier Doppler search;

[0040] a stripping submodule, for completing incoherent integration and code Doppler stripping;

[0041] The maximum value module is used to select 4 maximum values from the maximum values of 32 channels.

[0042] A multi-phase parallel rapid acquisition method applied to a navigation system comprises the following steps:

[0043] Step 1: Initialize the configuration information of all satellites to be captured;

[0044] Step 2: Determine whether the current satellite to be captured is valid. If so, start multi-phase parallel capture of the current satellite; otherwise, switch to the next satellite.

[0045] Step 3: After completing the multi-phase parallel capture of the current satellite, store the capture results;

[0046] Step 4: Determine whether the current satellite is the last satellite. If so, end the capture; otherwise, poll the next satellite.

[0047] Step 5: Repeat steps 2-4 until all satellites are polled and the signals of all valid satellites are captured.

[0048] Furthermore, as a preferred technical solution, in step 2, the specific process of multi-phase parallel capture is:

[0049] Step 2-1-1: Correlate each of the 32 data channels with a 32-bit wide correlator, perform coarse carrier stripping through a digital down-conversion process, and perform coherent integration on the stripped results.

[0050] Step 2-1-2: After the coherent integration results of each two channels of data are spectrally shifted, FIR filtering is performed, and then the filtering results are added to merge the data of the two channels of signals into one channel, thereby obtaining 16 channels of data;

[0051] Step 2-1-3: Time-multiplex one FFT module for every 4 channels of data to obtain 4 channels of FFT data, and implement data caching through double buffering;

[0052] Step 2-1-4: After the FFT data is output, it is restored to 32 channels of data. The corresponding points of the modulus values output by the FFT are summed and superimposed, and the results are stored in the corresponding buffers.

[0053] Step 2-1-5: Calculate the maximum value and the frequency number corresponding to the maximum value among the 256 frequency points of each data channel. Then, calculate the largest 4 values from the 32 maximum values and record their corresponding frequency numbers and channel numbers to complete the multi-phase parallel capture of a capture unit.

[0054] Furthermore, as a preferred technical solution, in step 2, the specific process of multi-phase parallel capture is:

[0055] Step 2-2-1: Multiply the input intermediate frequency signal with the in-phase and quadrature components output by the local carrier generator, and filter out the high-frequency components through a low-pass filter to obtain the baseband complex signal;

[0056] Step 2-2-2: Perform FFT on the complex signal obtained in step 2-2-2;

[0057] Step 2-2-3: Perform FFT on the pseudo-code signal output by the local pseudo-code generator and take its conjugate;

[0058] Step 2-2-4: Multiply the results obtained in step 2-2-2 and step 2-2-3, and perform IFFT on the product;

[0059] Step 2-2-5: Take the modulus of the IFFT result obtained in step 2-2-4 and then square it, and perform threshold judgment on the result. If a peak value exceeding the threshold value appears, it means that the signal capture is completed. The position corresponding to the peak is the pseudo code phase, and the frequency value of the local carrier at this time is the carrier frequency of the signal; if there is no peak value exceeding the threshold, reset the local carrier frequency and repeat steps 2-2-1 to 2-2-4.

[0060] Furthermore, as a preferred technical solution, in step 2-2-3, the FFT value of the local pseudocode can be calculated in advance and stored in the memory of the receiver.

[0061] Furthermore, as a preferred technical solution, assuming that the number of sampling points used for capture is N, then the condition satisfied by N is that N is an integer power of 2.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] (1) The present invention can capture 32 phases at a time by adopting a multi-phase parallel detection module, truly realizing multi-phase parallel rapid capture. Compared with existing software receivers, the capture rate is greatly improved. Moreover, the present invention can be implemented based on logic hardware platforms such as FPGA, CPLD, and ASIC, and has great adaptability. Theoretically, if there are sufficient resources, the logic circuit of the present invention can be replicated to achieve an exponential increase in capture speed. For scenarios with requirements for capture time, the present invention can play a decisive role.

[0064] (2) Compared with the existing software receiver with single-phase serial capture, the present invention can capture 32 phases at a time. Through time division multiplexing, only four FFT units are needed. The existing software receiver requires 32 FFT acceleration units even with multi-core parallel capture. Therefore, the present invention can greatly reduce overhead and save resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 Schematic diagram of the captured three-dimensional search;

[0066] Figure 2 Schematic diagram of the structure of the multi-phase parallel capture system of the present invention;

[0067] Figure 3 Schematic diagram of the structure of the multi-phase parallel detection module of the present invention;

[0068] Figure 4 This is a flow chart of the multi-phase parallel capture method of the present invention;

[0069] Figure 5 This is an implementation block diagram of an existing software receiver;

[0070] Figure 6 This is a diagram of a fast capture structure based on cyclic correlation of the present invention;

[0071] Figure 7 This is a schematic diagram of frequency shifting. DETAILED DESCRIPTION

[0072] The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0073] Example

[0074] like Figure 2 As shown, the multi-phase parallel fast acquisition system for a navigation system described in this embodiment includes a peripheral circuit and an internal logic circuit. The peripheral circuit includes:

[0075] A universal control processor and an analog-to-digital conversion module, wherein the analog-to-digital conversion module is used to convert module signals into digital signals;

[0076] The internal logic circuit includes:

[0077] The interface module is used for read and write access control with the general control processor; the interface module here refers to the AHB (Advanced High Performance Bus) interface module.

[0078] System configuration module, used to implement system configuration;

[0079] Channel parameter storage module, used to store satellite acquisition parameters;

[0080] Control module, used to schedule various modules;

[0081] Data pre-processing module, used to implement intermediate frequency carrier stripping, downsampling and re-quantization;

[0082] A data storage module, used for storing the data required for capture;

[0083] An internal code generator, used for generating an internal code;

[0084] A code storage module is used to store the codes required for capture;

[0085] The multi-phase parallel detection module is used to realize parallel detection of 32 phases.

[0086] Furthermore, as a preference, the peripheral circuit of this embodiment also includes a PRM chip, and the internal logic circuit also includes a PRM chip control interface module. The PRM chip controls the code storage module through the PRM chip control interface module, so that the code storage module operates in military code or long code mode.

[0087] In order to better realize the present invention, Figure 3 As shown, this embodiment provides a specific multi-phase parallel detection module structure, which specifically includes:

[0088] Integration submodule, used to complete correlation and coherence integration;

[0089] Search submodule, used to complete carrier Doppler search;

[0090] a stripping submodule, for completing incoherent integration and code Doppler stripping;

[0091] The maximum value module is used to select 4 maximum values from the maximum values of 32 channels.

[0092] Specifically, the capture unit has a total of 32 channels, each of which is correlated by a 32-bit wide correlator. After a digital down-conversion, the coarse carrier (Stride) is stripped, and the result after the stride carrier stripping is coherently integrated (Coh). The Coh results of the two branches are spectrally shifted and then FIR filtered. The filtering results are added to merge the data of the two branches into one channel, thus obtaining 16 channels of data.

[0093] Then, every 4 channels of data are time-multiplexed into one FFT module, thereby obtaining 4 channels of FFT data, which are then buffered in a ping-pong buffer (also called a double buffer).

[0094] After the FFT data is output, it is restored to 32 channels of data, divided into two channels for non-coherent integration operation and stored in the non-coherent integration buffer.

[0095] After NCS is completed, the maximum value and the frequency point number corresponding to the maximum value are calculated from the 256 frequency points of each data channel. Then, the largest 4 values are obtained from the 32 maximum values, and their corresponding frequency point numbers and channel numbers are recorded, ending the search process of a capture unit.

[0096] In this embodiment, a 32-bit-wide correlator can be used to correlate the sampled data with the local code. The detection module reads 96 data sampling points and the 32-bit code per clock cycle for correlation. Data sliding is achieved by sampling a segment of data using different starting bits. Each of the 32 channels uses a segment with a starting point difference of one sampling point. Since the data sampling rate is twice the code rate, data at one sampling point is redundant when calculating the correlation value. Therefore, only data separated by one sampling point need to be sequentially sampled. Each time the data is read, 32 sampling points per channel are multiplied and accumulated with the 32-bit code. In this way, a correlation operation of 32 phases and a length of 64 samples is completed per clock cycle. The next data segment consists of 96 sampling points from the 65th sampling point onwards, and correlation operations are performed on the next 32 phases.

[0097] In this embodiment, the DDC (Digital Down Converter) module performs coarse carrier stripping and performs coherent integration (Coh) on the result. The DDC is a numerically controlled oscillator (NCO) and a complex multiplier, while the Coh is an accumulator. After each frequency step, the NCO frequency and phase are reset to continue the calculation for the next frequency step.

[0098] In this embodiment, the FIR and spectrum shifting employ a 6th-order symmetrical FIR low-pass filter. Only three coefficient multiplications are performed, one of which is amplified to 1. Two multipliers are used to right-shift the product to complete the fractional product, followed by two additions to complete the filtering operation. Fs is the data sampling frequency. One channel is shifted to Fs / 4, and the other to -Fs / 4, with the center frequencies of the two channels separated by Fs / 2. The coherent integration results of the two channels are spectrum shifted and then added, merging the data from the two channels into one.

[0099] After the FIR, the data is summed up in pairs, resulting in 16 channels of data. This data is then buffered in a ping-pong buffer and then subjected to the FFT. This design has four FFT modules, requiring at least four RAMs per ping-pong buffer. To meet throughput requirements, a pause function is implemented for operations preceding this step. If one RAM is full and the FFT operation on the other RAM is not yet complete, the data operations preceding the FFT are paused.

[0100] When the coherent integration buffer data is ready, it is read and sent to the FFT module, and then each channel of data is restored to its original two channels according to the frequency point output by the FFT. Since the FFT is not a sequential output, it is necessary to store the data in the corresponding address according to the output frequency point. The frequency point value binID calculation formula is as follows:

[0101] In the frequency band [Fs / 8, Fs*3 / 8]: binID = fftout_cnt[LSB:MSB] – HalfBinNum

[0102] In the frequency band [Fs*5 / 8, Fs*7 / 8]: binID = fftout_cnt[LSB:MSB] – HalfBinNum*5

[0103] As attached Figure 7As shown, power is the power value of each frequency point. In the above formula, binID is the frequency point value when the frequency point is moved to zero frequency; fftout_cnt is the frequency point index value after the FFT module output, MSB is the highest bit of the frequency point index value fftout_cnt, and LSB is the lowest bit of the frequency point index value fftout_cnt, that is, the bit width of the frequency point index value fftout_cnt is MSB-LSB+1, the index value bit forward expression is fftout_cnt[MSB:LSB], and the bit reverse expression is fftout_cnt[LSB:MSB]; HalfBinNum is 1 / 8 of the data sampling frequency Fs, that is, HalfBinNum=Fs / 8, see the attached Figure 7 The above formula means that the frequency points at [Fs / 8, Fs*3 / 8] and [Fs*5 / 8, Fs*7 / 8] are moved to zero frequency.

[0104] The NCS operation sums the modulus values of corresponding points from multiple FFT outputs, storing the NCS results in a non-coherent integration buffer. Because the effective FFT bandwidth is 1 / 2, and the non-coherent integration buffer only requires one read and one write operation, the non-coherent integration buffer uses one RAM memory to store four parallel non-coherent data channels.

[0105] like Figure 4 As shown, this embodiment provides a multi-phase parallel fast acquisition method applied to a navigation system, comprising the following steps:

[0106] Step 1: Initialize the configuration information of all satellites to be captured;

[0107] Step 2: Determine whether the current satellite to be captured is valid. If so, start multi-phase parallel capture of the current satellite; otherwise, switch to the next satellite.

[0108] Step 3: After completing the multi-phase parallel capture of the current satellite, store the capture results;

[0109] Step 4: Determine whether the current satellite is the last satellite. If so, end the capture; otherwise, poll the next satellite.

[0110] Step 5: Repeat steps 2-4 until all satellites are polled and the signals of all valid satellites are captured.

[0111] Specifically, in step 2 of this embodiment, the specific process of multi-phase parallel capture is:

[0112] Step 2-1-1: Correlate each of the 32 data channels with a 32-bit wide correlator, perform coarse carrier stripping through a digital down-conversion module, and perform coherent integration on the stripped results.

[0113] Step 2-1-2: After the coherent integration results of each two channels of data are spectrally shifted, FIR filtering is performed, and then the filtering results are added to merge the data of the two channels of signals into one channel, thereby obtaining 16 channels of data;

[0114] Step 2-1-3: Time-multiplex one FFT module for every 4 channels of data to obtain 4 channels of FFT data, and implement data caching through double buffering;

[0115] Step 2-1-4: After the FFT data is output, it is restored to 32 channels of data. The corresponding points of the modulus values output by the FFT are summed and superimposed, and the results are stored in the corresponding buffers.

[0116] Step 2-1-5: Calculate the maximum value and the frequency number corresponding to the maximum value among the 256 frequency points of each data channel. Then, calculate the largest 4 values from the 32 maximum values and record their corresponding frequency numbers and channel numbers to complete the multi-phase parallel capture of a capture unit.

[0117] like Figure 5 As shown, the existing technology usually designs software receivers based on a cyclically correlated capture algorithm, and the execution of software instructions is based on CPU sequence. The processing of input data can only be based on sequential capture of a single phase, which has low capture efficiency and long capture time.

[0118] The essence of GPS satellite signal acquisition is to find correlation, then compare the correlation result with the corresponding threshold to determine whether the satellite signal has been successfully captured. If it is successfully captured, the Doppler frequency shift and code phase parameters are extracted and passed to the subsequent tracking loop. For discrete digital signals, the correlation can be written as:

[0119]

[0120] We know that if the signal x(n) is input into a linear time-invariant (LTI) system, assuming that the impulse response of the system is h(n), then the output y(n) can be expressed as a time domain convolution or a frequency domain Fourier transform:

[0121]

[0122] Y(K)=X(K)H(K) (5-3)

[0123] Observe that the form of Equation (5-1) is similar to the convolution of a discrete-time system, so it can be analyzed in a similar way. Perform a discrete Fourier transform on Equation (5-1) to obtain:

[0124]

[0125]

[0126] Where X -1 (K) represents the inverse discrete Fourier transform (IFFT). If x(m) is a real number, then x * (m) = x(m), so we can get: X * (K) = X(K), where X * (K) represents the conjugate of X(K). Similarly, we can deduce that: Z(K)=H -1 (K)*X(K). So we have the following relationship:

[0127] Z(K)=H(K)X * (K)=H * (K)X(K)

[0128] Therefore, the time domain correlation function z(n) can be obtained by Fourier transforming Z(K), that is:

[0129]

[0130] Through the above analysis, to complete signal capture, it is only necessary to replace x(n) in the correlation function with the GPS signal sampling sequence and h(n) with the local C / A code sequence. In actual processing, the discrete Fourier transform (DFT) is generally implemented using the fast Fourier transform (FFT). To this end, this embodiment designs a capture algorithm structure based on cyclic correlation, such as Figure 6 As shown, the corresponding loop-related capture steps are:

[0131] Step 2-2-1: Multiply the input intermediate frequency signal with the in-phase and quadrature components output by the local carrier generator, and filter out the high-frequency components through a low-pass filter to obtain the baseband complex signal I(n)+jQ(n);

[0132] Step 2-2-2: Perform FFT on the complex signal obtained in step 2-2-2;

[0133] Step 2-2-3: Perform FFT on the pseudo-code signal output by the local pseudo-code generator and take its conjugate;

[0134] Step 2-2-4: Multiply the results obtained in step 2-2-2 and step 2-2-3, and perform IFFT on the product;

[0135] Step 2-2-5: Take the modulus of the IFFT result obtained in step 2-2-4 and then square it, and perform threshold judgment on the result. If a peak value exceeding the threshold value appears, it means that the signal capture is completed. The position corresponding to the peak is the pseudo code phase, and the frequency value of the local carrier at this time is the carrier frequency of the signal; if there is no peak value exceeding the threshold, reset the local carrier frequency and repeat steps 2-2-1 to 2-2-4.

[0136] The cyclic correlation-based acquisition structure employs a direct search method at the carrier frequency. At the code phase, two FFTs and one IFFT are required to determine the correlation values corresponding to all sampling points within a C / A code cycle. Assuming that one C / A code cycle (1ms) is used for acquisition, and the number of sampling points used is N, the IFFT result in the fourth step of the cyclic correlation-based fast acquisition process provides the correlation results corresponding to all N pseudo-code phases. Therefore, the total computation required is approximately equivalent to three FFTs, or 3Nlog2N multiplications and additions. Therefore, to further reduce acquisition time, the FFT values of the local pseudo-code can be pre-calculated and stored in the receiver's memory.

[0137] The cyclic correlation-based capture algorithm reduces computational complexity and thus capture time. However, in actual application, the FFT transform is performed on N sampling points. Due to the recursive nature of the FFT butterfly operation, the algorithm's highest efficiency is achieved only when N is an integer power of 2. Therefore, before using this capture method, the input signal must be preprocessed. Common methods, such as the average grouping method, can effectively resolve the mismatch between the number of sampling points and the FFT processing, achieving optimal capture efficiency.

[0138] This invention can be directly transplanted to a logical hardware receiver and can be flexibly configured according to the system capture time requirements. However, the existing software receiver, because the software is executed sequentially, even if multi-core parallel capture is used, the maximum capture rate is far lower than that of the logical hardware receiver due to the limited number of cores.

[0139] By adopting the above-mentioned system structure and method, the present invention can capture 32 phases at a time, compared with the existing software receiver with single-phase serial capture. Through time division multiplexing, only four FFT units are needed. The existing software receiver requires 32 FFT acceleration units even for multi-core parallel capture. Therefore, the present invention can greatly reduce overhead and save resources.

[0140] In addition, the present invention can be implemented based on logic hardware platforms such as FPGA, CPLD, and ASIC. Theoretically, if there are sufficient resources, the logic circuit of the present invention can be replicated to achieve an exponential increase in the capture speed. For scenarios with requirements on capture time, the present invention can play a decisive role.

[0141] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made thereto. Therefore, such modifications and improvements, without departing from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. A multi-phase parallel rapid acquisition method applied to a navigation system, characterized in that: The following steps are involved: Step 1: Initialize the configuration information of all satellites to be captured; Step 2: Determine whether the current satellite to be captured is valid. If so, start multi-phase parallel capture of the current satellite; otherwise, switch to the next satellite. Step 3: After completing the multi-phase parallel capture of the current satellite, store the capture results; Step 4: Determine whether the current satellite is the last satellite. If so, end the capture; otherwise, poll the next satellite. Step 5: Repeat steps 2-4 until all satellites are polled and the signals of all valid satellites are captured; In step 2, the specific process of multi-phase parallel capture is as follows: Step 2-1-1: Correlate each of the 32 data channels with a 32-bit wide correlator, perform coarse carrier stripping through a digital down-conversion process, and perform coherent integration on the stripped results. Step 2-1-2: After the coherent integration results of each two channels of data are spectrally shifted, FIR filtering is performed, and then the filtering results are added to merge the data of the two channels of signals into one channel, thereby obtaining 16 channels of data; Step 2-1-3: Time-multiplex one FFT module for every 4 channels of data to obtain 4 channels of FFT data, and implement data caching through double buffering; Step 2-1-4: After the FFT data is output, it is restored to 32 channels of data. The corresponding points of the modulus values output by the FFT are summed and superimposed, and the results are stored in the corresponding buffers. Step 2-1-5: Calculate the maximum value and the frequency number corresponding to the maximum value among the 256 frequency points of each data channel. Then, calculate the largest 4 values from the 32 maximum values and record their corresponding frequency numbers and channel numbers to complete the multi-phase parallel capture of a capture unit.

2. The multi-phase parallel rapid acquisition method for a navigation system according to claim 1, characterized in that: In step 2, the specific process of multi-phase parallel capture is as follows: Step 2-2-1: Multiply the input intermediate frequency signal with the in-phase and quadrature components output by the local carrier generator, and filter out the high-frequency components through a low-pass filter to obtain the baseband complex signal; Step 2-2-2: Perform FFT on the complex signal obtained in step 2-2-2; Step 2-2-3: Perform FFT on the pseudo-code signal output by the local pseudo-code generator and take its conjugate; Step 2-2-4: Multiply the results obtained in step 2-2-2 and step 2-2-3, and perform IFFT on the product; Step 2-2-5: Take the modulus of the IFFT result obtained in step 2-2-4 and then square it, and perform threshold judgment on the result. If a peak value exceeding the threshold value appears, it means that the signal capture is completed. The position corresponding to the peak is the pseudo code phase, and the frequency value of the local carrier at this time is the carrier frequency of the signal; if there is no peak value exceeding the threshold, reset the local carrier frequency and repeat steps 2-2-1 to 2-2-4.

3. The multi-phase parallel rapid acquisition method for a navigation system according to claim 2, characterized in that: In step 2-2-3, the FFT value of the local pseudo code can be calculated in advance and stored in the memory of the receiver.

4. The multi-phase parallel rapid acquisition method for a navigation system according to claim 2, characterized in that: Assume that the number of sampling points used for capture is N, then the condition satisfied by N is that N is an integer power of 2.

5. A system for implementing the multi-phase parallel rapid acquisition method for a navigation system according to any one of claims 1 to 4, characterized in that: It includes peripheral circuits and internal logic circuits, and the peripheral circuits include: A universal control processor and an analog-to-digital conversion module, wherein the analog-to-digital conversion module is used to convert module signals into digital signals; The internal logic circuit includes: Interface module for read and write access control with the general control processor; System configuration module, used to implement system configuration; Capture configuration module, used to store the capture parameters of different satellites; Control module, used to schedule various modules; Data pre-processing module, used to implement intermediate frequency carrier stripping, downsampling and re-quantization; Data cache module, used to cache the data needed for capture; Internal pseudo code generator module, used to generate pseudo code internally; Pseudo code buffer storage module, used to cache the pseudo code required for capture; Multi-phase parallel detection module, used to achieve parallel detection of 32 phases; The multi-phase parallel detection module includes: Integration submodule, used to complete correlation and coherence integration; Search submodule, used to complete carrier Doppler search; a stripping submodule, for completing incoherent integration and code Doppler stripping; The maximum value module is used to select 4 maximum values from the maximum values of 32 channels.

6. The multi-phase parallel rapid acquisition system for a navigation system according to claim 5, characterized in that: The peripheral circuit further includes a PRM chip, and the internal logic circuit further includes a PRM chip control interface module. The PRM chip controls the code storage module through the PRM chip control interface module, so that the code storage module operates in military code or long code mode.

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