Low power consumption, high transient response, capacitor-free low dropout linear regulator

Abstract

The present invention discloses a low-power, high-transient-response, and capacitor-free low-dropout linear regulator. The regulator comprises a gate DC bias network for providing the gate bias voltage required for the operation of a power amplifier transistor; a drain DC bias network for providing the drain bias voltage required for the operation of the power amplifier transistor; an input impedance matching network comprising a microstrip line, a DC-blocking capacitor, and an RC parallel circuit; and an output impedance matching network comprising a harmonic control network and an elliptical low-pass filter matching network. The harmonic control network selects two frequency points outside the passband for second harmonic control; and the elliptical low-pass filter matching network is based on an improved sixth-order Chebyshev low-pass filter, generating two transmission zeros outside the operating band to achieve conversion from fundamental impedance to second harmonic impedance. This invention enables the power amplifier to achieve high efficiency and high gain within an operating bandwidth exceeding quintuple frequency.

Description

Technical Field

[0001] The invention belongs to the technical field of linear regulators, and in particular relates to a low-power consumption, high-transient response, and off-chip capacitor-free low-voltage difference linear regulator. Background Art

[0002] With the continuous advancement of integrated circuit design and process technology, more and more circuits are being integrated. Typically, a large-scale mixed-signal chip contains multiple different digital and analog circuit modules. The analog circuit modules need to serve the digital modules. For example, an analog power management module is needed to provide a stable voltage for the digital modules. The most commonly used power management module is the LDO (low dropout regulator).

[0003] The increasing frequency of digital modules presents challenges for analog module design. For example, in ADC (analog-to-digital converter) applications, analog LDOs are required to charge and discharge capacitor arrays during the regulation phase. During this phase, switching times are measured in nanoseconds, and the LDO response recovery time is measured in microseconds. This is difficult to achieve with traditional LDO circuits. Due to the characteristics of the ADC, the LDO must have high transient response and high load capacity. Furthermore, considering the integration of mixed-analog and digital circuits, the LDO must also be compact and have low static power consumption.

[0004] However, traditional LDO designs require multiple chip pins to be reserved for the LDO. Application engineers must select external large capacitors with specific ESR (equivalent series resistance) and capacitance ranges to ensure stable LDO operation and optimize the circuit output's load transient characteristics. However, the presence of these large external capacitors prevents traditional LDOs from being fully integrated on-chip, increasing PCB area and hindering their application in mixed-analog integrated circuits.

[0005] With the development of integrated circuits, research on Capless-LDO (low-dropout linear regulator without external capacitors) has made some progress. Classic Capless-LDOs mostly use a buffer-driven error amplifier and a P-type power output stage structure. The buffer stage is used to reduce the output impedance of the error amplifier, thereby raising the secondary pole and ensuring the stability of the LDO. Its output impedance is

[0006]

[0007] This formula shows that in low-power applications, a small quiescent current I D This will produce a small transconductance g m, further generating a large error amplifier output impedance r o , resulting in a very small pole spacing, making it difficult to ensure LDO stability. Therefore, this buffer-driven capless-LDO structure is not suitable for low-power applications. Furthermore, the buffer stage's weak driving capability results in poor LDO transient response, making it unable to meet the requirements of today's higher-speed mixed-analog circuits. Summary of the Invention

[0008] Therefore, in response to existing needs and the shortcomings of current technologies, it is necessary to conduct research and improve to provide a solution to address these needs and improve the shortcomings of existing technologies. Therefore, the present invention proposes an LDO circuit without external capacitors, which has the characteristics of low power consumption, high transient response, low static power consumption, and easy integration.

[0009] To achieve the above objectives, the present invention provides a low-power, high-transient-response, low-dropout linear regulator with no external capacitors, which can be used in digital-analog hybrid integrated circuits and is stable over the full load range. It achieves high transient response (switching time of 1 nanosecond, recovery time of less than 1 microsecond) while meeting low power consumption (quiescent current of less than 5 microamperes). Specifically, it includes a direct-drive error amplifier, an N-type power output stage, an adaptive impedance transient enhancement circuit, and a compensation capacitor, wherein:

[0010] The direct drive error amplifier includes two input terminals, the two input terminals are directly connected to the reference voltage and the feedback voltage node formed by the resistor in the N-type power output stage, and the output terminal is connected to the control terminal of the N-type power adjustment stage, and drives the N-type power adjustment stage according to the voltage difference between the feedback voltage of the output voltage and the reference voltage;

[0011] The N-type power output stage has an input end directly connected to the output end of the direct drive error amplifier, and an output end thereof is the output end of the entire linear regulator;

[0012] The adaptive impedance transient enhancement circuit has an input terminal directly connected to the gate terminal of the NMOS current mirror in the direct drive error amplifier, and an output terminal directly connected to the output terminal of the N-type power output stage;

[0013] The compensation capacitor has its input end directly connected to the feedback voltage node formed by the resistor of the N-type power output stage, and its output end directly connected to the input end of the N-type power output stage, forming a compensation network with the feedback resistor circuit of the N-type power output stage.

[0014] Preferably, the direct drive error amplifier adopts a differential input and push-pull output structure, and the push-pull output structure generates a rail-to-rail voltage signal.

[0015] Preferably, the direct drive error amplifier adopts an improved OTA architecture, which improves the current mirror of the traditional OTA architecture into a nonlinear current mirror, and connects a cross-coupling pair in parallel to the diode-connected MOS load.

[0016] Preferably, the direct-drive error amplifier includes one reference voltage Vref, two bias voltages Vb and Vp, eight PMOS transistors: M4-M7, M11-M14, and five NMOS transistors: M1-M3, M8, and M9, wherein M1 constitutes an NMOS tail current source, M2 and M3 constitute an NMOS differential pair, M4-M7, M11, and M12 constitute a nonlinear current mirror, and M13 and M14 constitute a cross-coupling pair. When the circuit is in a static state, all MOS transistors operate in a saturation state. When the load changes, the gate voltage of M3 changes, wherein M4 and M5 will operate in a linear region, realizing nonlinearization of the current transfer ratio of the current mirror, while the other MOS transistors remain in a saturation region.

[0017] The gate terminal of M1 is connected to the bias voltage Vb, the gate terminal of M2 is connected to the feedback voltage Vfb, the gate terminal of M3 is connected to the reference voltage Vref, the gate terminals of M11 and M12 are connected to the bias voltage Vp, the source terminals of M1, M8 and M9 are grounded, the source terminals of M4-M7, M13 and M14 are connected to the DC power supply anode VDD, the drain terminal of M1 is connected to the source terminals of M2 and M3, the drain terminal of M2 is connected to the drain terminal of M11, the gate terminal of M4, the gate terminal of M6 and the gate terminal of M14, the drain terminal of M3 is connected to the drain terminal of M12, the gate terminal of M5, the gate terminal of M7 and the gate terminal of M13, the drain terminal of M4 is connected to the source terminal of M11 and the drain terminal of M13, the drain terminal of M5 is connected to the source terminal of M12 and the drain terminal of M14, the drain terminal of M6 is connected to the gate terminal and drain terminal of M8, and the drain terminal of M7 is connected to the drain terminal of M9.

[0018] Preferably, the N-type power output stage includes an NMOS power adjustment tube M10 and two polysilicon resistors R1 and R2, which together constitute an NMOS common-drain amplifier. When lightly loaded, M10 operates in the subthreshold region, and when heavily loaded, M10 operates in the saturation region.

[0019] Preferably, the gate end of the NMOS power adjustment tube M10 is the control end or input end of the N-type power output stage, the drain end of M10 is connected to the DC power supply anode VDD, the source end is connected to the upper end of the resistor R1, forming an output voltage node Vo, the lower end of the resistor R1 is connected to the upper end of the resistor R2, forming a feedback voltage node Vfb, and the lower end of the resistor R2 is grounded.

[0020] Preferably, the adaptive impedance transient enhancement circuit is composed of an NMOS leakage tube M15, and its input is connected to a voltage signal with a variation trend opposite to that of the linear regulator output voltage.

[0021] Preferably, the specific connection relationship of the adaptive impedance transient enhancement circuit is: the gate terminal of the NMOS leakage tube M15 is connected to the output terminal of the adaptive bias circuit, the source terminal of M15 is grounded, and the drain terminal is connected to the output voltage node Vo of the N-type power output stage, wherein the adaptive bias circuit is composed of M4, M6, M8, and M11 in the direct drive error amplifier.

[0022] Preferably, the compensation capacitor is based on the principle of Miller compensation.

[0023] Preferably, the anode of the compensation capacitor is connected to the output end of the direct drive error amplifier, and the cathode is connected to the feedback voltage node Vo of the N-type power output stage.

[0024] The beneficial effects of the present invention include at least the following: compared with existing low-dropout linear regulators, the present invention reduces the number of circuit branches and improves the driving capability of the error amplifier by adopting a direct-drive error amplifier, thereby achieving improved transient response capability under the premise of equal power consumption; by adopting an N-type power output stage, the output stage pole is raised, reducing the impact of load changes on the pole, thereby increasing bandwidth and improving transient response.

[0025] The present invention also completes the specific circuit design based on a 130nm CMOS process. Using a transconductance operational amplifier to form a direct-drive error amplifier, the invention enhances the slew rate and bandwidth by using a nonlinear current mirror to improve the current transfer ratio, building on the traditional OTA circuit. Cross-coupling is introduced to increase the gain and gain-bandwidth product for the load, improving the transient performance of the circuit. An adaptive impedance transient enhancement circuit is used to increase the slew rate of the output node when transitioning from a heavy load to a light load. Compensation capacitors are used to achieve loop stability.

[0026] The advantages of the present invention compared with the prior art are further described from the aspects of low power consumption and high transient response:

[0027] Low power consumption: Power consumption is the product of power supply voltage, current, and time. Considering that in mixed-analog / digital circuit applications, static time is much greater than dynamic time, and that power supply voltage is a constant value affected by chip technology, design requirements for power consumption translate into requirements for total static current. Total static current is the sum of the currents in each circuit branch during static operation.

[0028] Compared to existing technologies, this invention utilizes a direct-drive error amplifier, which simplifies the number of circuit branches and requires less current to achieve equivalent drive capability. Furthermore, the use of nonlinear current mirror technology within the error amplifier allows the circuit to achieve improved performance while consuming less quiescent current. This reduces total quiescent current and achieves low power consumption.

[0029] High transient response: Transient response refers to the deviation of the voltage at the output of the power supply from the set value and the time it takes to recover to the set value at the moment when the load current jumps. The key factors affecting transient response mainly depend on two points: loop bandwidth (small signal) and slew rate (large signal). Obviously, the higher the loop bandwidth, the more complete the harmonic components allowed to pass through the loop. The better the rising edge of the step signal is maintained, the better the transient response; and the role of the slew rate is: when the load jumps, the higher the slew rate, the faster the charging and discharging speed of the power regulator and the load will be, so the transient response will be better. The definition of these two indicators is:

[0030]

[0031]

[0032] Compared to existing technologies, this invention utilizes a direct-drive LDO architecture, reducing the number of poles and increasing the output node slew rate during light-to-heavy load transitions. It also employs an N-type power output stage, raising the position of the circuit's secondary pole, thereby increasing bandwidth. Furthermore, it employs an adaptive impedance transient enhancement circuit to increase the output node slew rate during heavy-to-light load transitions. This improves the circuit's transient response performance in terms of both bandwidth (for small signals) and slew rate (for large signals). BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to make the purpose, technical solutions and beneficial effects of the present invention more clear, the present invention provides the following drawings for illustration:

[0034] Figure 1 1 is a schematic structural diagram of a low-power, high-transient-response, low-dropout linear regulator without external capacitors according to an embodiment of the present invention;

[0035] Figure 2 This is the LDO circuit diagram after the classic OTA circuit in the prior art;

[0036] Figure 3 This is a small signal diagram of the cross-coupling in the low-power, high-transient-response, off-chip-capacitor-free low-dropout linear regulator according to an embodiment of the present invention;

[0037] Figure 4 The invention discloses an improved low-power, high-transient, and no-external-capacitor LDO circuit diagram of a low-power, high-transient-response, and no-external-capacitor low-dropout linear regulator according to an embodiment of the invention. DETAILED DESCRIPTION

[0038] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] See also Figure 1 , which is a schematic diagram of the structure of a low-power, high-transient-response, low-dropout linear regulator without external capacitors according to an embodiment of the present invention, Figure 4The corresponding circuit diagram includes a direct drive error amplifier 10, an N-type power output stage 20, an adaptive impedance transient enhancement circuit 30 and a compensation capacitor 40, wherein:

[0040] The direct drive error amplifier 10 includes two input terminals, which are directly connected to a reference voltage and a feedback voltage node formed by a resistor in the N-type power output stage 20, and an output terminal thereof is connected to a control terminal of the N-type power adjustment stage. The direct drive error amplifier 10 drives the N-type power adjustment stage according to the voltage difference between the feedback voltage of the output voltage and the reference voltage.

[0041] An N-type power output stage 20, whose input terminal is directly connected to the output terminal of the direct drive type error amplifier 10, and whose output terminal is the output terminal of the entire linear regulator;

[0042] An adaptive impedance transient enhancement circuit 30 , whose input terminal is directly connected to the gate terminal of the NMOS current mirror in the direct drive error amplifier 10 , and whose output terminal is directly connected to the output terminal of the N-type power output stage 20 ;

[0043] The compensation capacitor 40 has its input directly connected to the feedback voltage node formed by the resistor of the N-type power output stage 20 , and its output directly connected to the input of the N-type power output stage 20 , forming a compensation network with the feedback resistor circuit of the N-type power output stage 20 .

[0044] The direct drive error amplifier 10 adopts a differential input and a push-pull output structure, and the push-pull output structure generates a rail-to-rail voltage signal.

[0045] The direct drive error amplifier 10 adopts an improved OTA architecture. Based on the traditional OTA architecture, the current mirror thereof is improved into a nonlinear current mirror, and a cross-coupling pair is connected in parallel to the diode-connected MOS load.

[0046] The direct drive error amplifier 10 includes a reference voltage Vref, two bias voltages Vb and Vp, eight PMOS transistors: M4-M7, M11-M14, and five NMOS transistors: M1-M3, M8, and M9. M1 forms an NMOS tail current source, M2 and M3 form an NMOS differential pair, M4-M7, M11, and M12 form a nonlinear current mirror, and M13 and M14 form a cross-coupled pair. When the circuit is in a static state, all MOS transistors operate in a saturated state. When the load changes, the gate voltage of M3 changes, and M4 and M5 operate in a linear region, realizing a nonlinear current transfer ratio of the current mirror. The other MOS transistors remain in a saturated region.

[0047] The gate terminal of M1 is connected to the bias voltage Vb, the gate terminal of M2 is connected to the feedback voltage Vfb, the gate terminal of M3 is connected to the reference voltage Vref, the gate terminals of M11 and M12 are connected to the bias voltage Vp, the source terminals of M1, M8 and M9 are grounded, the source terminals of M4-M7, M13 and M14 are connected to the DC power supply anode VDD, the drain terminal of M1 is connected to the source terminals of M2 and M3, the drain terminal of M2 is connected to the drain terminal of M11, the gate terminal of M4, the gate terminal of M6 and the gate terminal of M14, the drain terminal of M3 is connected to the drain terminal of M12, the gate terminal of M5, the gate terminal of M7 and the gate terminal of M13, the drain terminal of M4 is connected to the source terminal of M11 and the drain terminal of M13, the drain terminal of M5 is connected to the source terminal of M12 and the drain terminal of M14, the drain terminal of M6 is connected to the gate terminal and drain terminal of M8, and the drain terminal of M7 is connected to the drain terminal of M9.

[0048] N-type power output stage 20 includes an NMOS power regulator M10 and two polysilicon resistors R1 and R2, which together form an NMOS common-drain amplifier. Under light loads, M10 operates in the subthreshold region, and under heavy loads, M10 operates in the saturation region. The gate of NMOS power regulator M10 serves as the control terminal or input of N-type power output stage 20. Its drain is connected to the DC power supply anode VDD. Its source is connected to the upper end of resistor R1, forming an output voltage node Vo. The lower end of resistor R1 is connected to the upper end of resistor R2, forming a feedback voltage node Vfb. The lower end of resistor R2 is grounded.

[0049] Adaptive impedance transient enhancement circuit 30 comprises an NMOS bleeder M15, whose input receives a voltage signal that varies inversely with the linear regulator's output voltage. This NMOS bleeder M15 and an adaptive bias circuit shared with the direct-drive error amplifier 10 are constructed by directly connecting a current mirror to a diode-connected transistor. When the load changes from heavy to light, the direct-drive error amplifier 10 generates an increased current, which is replicated by the current mirror and flows into the diode-connected transistor. To accommodate the increased current, the gate-source voltage of the diode-connected transistor increases, generating a large bias for the NMOS bleeder, increasing the bleeder's current and improving transient response.

[0050] The specific connection relationship of the adaptive impedance transient enhancement circuit 30 is as follows: the gate terminal of the NMOS leakage tube M15 is connected to the output terminal of the adaptive bias circuit, the source terminal of M15 is grounded, and the drain terminal is connected to the output voltage node Vo of the N-type power output stage 20. Among them, the adaptive bias circuit is composed of M4, M6, M8, and M11 in the direct drive error amplifier 10.

[0051] Compensation capacitor 40 is based on the principle of Miller compensation and is used to stabilize the circuit and balance overshoot voltage and overcharge recovery time. The anode of compensation capacitor 40Cc is connected to the output of direct drive error amplifier 10, and the cathode is connected to the feedback voltage node Vo of N-type power output stage 20.

[0052] The direct drive error amplifier 10 and the N-type power output stage 20 of the present invention form a negative feedback when the circuit is in a static state. Under the action of the direct drive error amplifier 10, the two input terminals of the direct drive error amplifier 10 will form a virtual short. Since one terminal is connected to a fixed voltage V ref , so the node voltage between the feedback resistors R1 and R2 is also equal to this voltage value. Under the action of voltage division, the output voltage is

[0053]

[0054] When the load changes, the LDO of the present invention will respond and adjust. Extreme load changes can be divided into two categories: light load to heavy load and heavy load to light load. When a light load changes to a heavy load, the output current suddenly increases, causing the output voltage to drop, i.e., an undershoot. At this time, the negative terminal voltage of the direct-drive error amplifier 10 also drops, and its output voltage increases. The gate voltage of the power regulator NMOS increases, the output current increases, and the output voltage recovers. In contrast, the heavy load to light load phenomenon will cause overcharging.

[0055] The following are specific embodiments of the low-power, high-transient-response, low-dropout linear regulator with no external capacitors designed by the present invention based on a 130nm CMOS process, and in conjunction with the accompanying drawings, further describe the technical solution of the present invention, but the present invention is not limited to these embodiments.

[0056] See also Figure 4 The present invention provides a low-power, high-transient-response, low-voltage-dropout linear regulator circuit with no external capacitors, comprising a direct-drive error amplifier 10, an N-type power output stage 20, an adaptive impedance transient enhancement circuit 30, and a compensation capacitor 40.

[0057] The direct drive error amplifier 10 is based on the traditional OTA circuit and introduces nonlinear current mirror technology and cross-coupling pair technology to meet the requirements.

[0058] Conventional OTA circuits Figure 2 , its gain-bandwidth product is:

[0059]

[0060] Where M is the current transfer ratio, which is numerically equal to the ratio of the drain-source current flowing through transistors M4 and M6. In traditional OTAs, M is equal to the size ratio of transistors M4 and M6. I1 is the drain-source current of the tail current source transistor M1, and V ov3 、V ov7 are the overdrive voltages of transistors M3 and M7, respectively, and gm5 is the transconductance of transistor M5.

[0061] The slew rate is:

[0062]

[0063] Among them, C GS10 is the gate capacitance of transistor M10.

[0064] It can be seen from the formula that there is an irreconcilable contradiction between static power and transient response.

[0065] Therefore, the present invention adopts the following technical solutions to improve the traditional OTA:

[0066] Nonlinear current mirror: This invention replaces the current mirror (M4-M7) inside the OTA with a nonlinear current mirror (M4-M7, M11, M12). When the circuit is in a static state, M4 operates in the saturation region, and the current transfer ratio M is equal to the size ratio of M4 to M6, meeting the low power consumption requirement. When the circuit is in a dynamic state, M4 easily enters the linear region, and the current transfer ratio M will change. The deeper the linearity of M4, the larger the M value.

[0067] Cross-coupled pairs: This is a negative conductance technology, from see Figure 3 It can be seen that after adopting the cross-coupling pair, transistors M5 and M14 can be equivalent to a voltage-controlled voltage source and output impedance respectively, where V in is the small signal input voltage of the M5 gate. Due to the differential relationship of the input signal, the small signal input voltage of the M14 gate is -V in gm is the small signal transconductance of the transistor, r o is the small signal output impedance of the transistor. The conductance of M14 and M5 is g m5 With g m14 The direction is opposite, then it can be equivalent to M5 transconductance g m5 Reduce, combined with the previous formula, g m5 When it decreases, the circuit amplification factor increases, the main pole decreases, and the gain-bandwidth product increases.

[0068] Through these two improvements, the current transfer ratio M and transconductance g were successfully improved. m5 , which enables low power consumption and high transient response to coexist.

[0069] The direct drive error amplifier 10 includes M1~M9, M11~M14, among which M1~M9 are traditional OTA circuits, M1 is a tail current source, M2 and 3 are differential pair tubes, M4 and 5 are loads connected by diodes, M6 and 7 are current sources controlled by the gate voltage of M4 and 5, and M8 and 9 are current mirrors; the introduction of M11 and 12 realizes the nonlinearity of the gate voltage change of M4 and 5, and forms a nonlinear current mirror with M6 and 7, and M13 and 14 are introduced cross-coupling pairs.

[0070] The N-type power output stage 20 includes an NMOS power regulator M10 and feedback resistors R1 and R2, which together form a common-drain amplifier.

[0071] The use of a direct drive error amplifier 10 and an N-type power stage can increase the slew rate when the load changes from light to heavy. To solve the problem of insufficient slew rate when the load changes from heavy to light, the present invention proposes the following technical solutions:

[0072] Adaptive impedance transient enhancement technology: When a heavy load changes to a light load, the gate voltage of M15 increases, and the charge on the output point load capacitance can be quickly discharged through the conductive channel of M15, thereby accelerating the recovery of the output voltage.

[0073] The adaptive impedance transient enhancement circuit 30 is based on the direct drive error amplifier 10 , and draws the gate voltage of M8 as a control signal, with the drain connected to the source of M10 .

[0074] The compensation capacitor 40 comprises Cc, which is connected across the gate terminal of M10 and the connection point of the two compensation resistors.

[0075] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made in form and details without departing from the scope defined by the claims of the present invention.

Claims

1. A low-power, high-transient-response, low-dropout linear regulator with no external capacitors, characterized in that: It includes a direct drive error amplifier, an N-type power output stage, an adaptive impedance transient enhancement circuit and a compensation capacitor, wherein: The direct drive error amplifier includes two input terminals, the two input terminals are directly connected to the reference voltage and the feedback voltage node formed by the resistor in the N-type power output stage, and the output terminal is connected to the control terminal of the N-type power adjustment stage, and drives the N-type power adjustment stage according to the voltage difference between the feedback voltage of the output voltage and the reference voltage; The N-type power output stage has an input end directly connected to the output end of the direct drive error amplifier, and an output end thereof is the output end of the entire linear regulator; The adaptive impedance transient enhancement circuit has an input terminal directly connected to the gate terminal of the NMOS current mirror in the direct drive error amplifier, and an output terminal directly connected to the output terminal of the N-type power output stage; The compensation capacitor has an input end directly connected to a feedback voltage node formed by the resistor of the N-type power output stage, and an output end directly connected to the input end of the N-type power output stage, forming a compensation network with the feedback resistor circuit of the N-type power output stage; The direct drive error amplifier adopts a differential input and push-pull output structure, and the push-pull output structure generates a rail-to-rail voltage signal; The direct drive error amplifier adopts an improved OTA architecture. Based on the traditional OTA architecture, the current mirror is improved into a nonlinear current mirror, and a cross-coupled pair is connected in parallel to the diode-connected MOS load. The direct drive error amplifier includes a reference voltage Vref, two bias voltages Vb and Vp, eight PMOS transistors: M4-M7, M11-M14, and five NMOS transistors: M1-M3, M8, and M9, wherein M1 constitutes an NMOS tail current source, M2 and M3 constitute an NMOS differential pair, M4-M7, M11, and M12 constitute a nonlinear current mirror, and M13 and M14 constitute a cross-coupling pair. When the circuit is in a static state, all MOS transistors operate in a saturation state. When the load changes, the gate voltage of M3 changes, wherein M4 and M5 will operate in a linear region, realizing a nonlinear current transfer ratio of the current mirror, while the other MOS transistors remain in a saturation region. The gate terminal of M1 is connected to the bias voltage Vb, the gate terminal of M2 is connected to the feedback voltage Vfb, the gate terminal of M3 is connected to the reference voltage Vref, the gate terminals of M11 and M12 are connected to the bias voltage Vp, the source terminals of M1, M8 and M9 are grounded, the source terminals of M4-M7, M13 and M14 are connected to the DC power supply anode VDD, the drain terminal of M1 is connected to the source terminals of M2 and M3, the drain terminal of M2 is connected to the drain terminal of M11, the gate terminal of M4, the gate terminal of M6 and the gate terminal of M14, the drain terminal of M3 is connected to the drain terminal of M12, the gate terminal of M5, the gate terminal of M7 and the gate terminal of M13, the drain terminal of M4 is connected to the source terminal of M11 and the drain terminal of M13, the drain terminal of M5 is connected to the source terminal of M12 and the drain terminal of M14, the drain terminal of M6 is connected to the gate terminal and the drain terminal of M8, and the drain terminal of M7 is connected to the drain terminal of M9; The N-type power output stage includes an NMOS power adjustment tube M10 and two polysilicon resistors R1 and R2, which together constitute an NMOS common-drain amplifier. Under light load, M10 operates in the subthreshold region, and under heavy load, M10 operates in the saturation region. The gate terminal of the NMOS power adjustment tube M10 is the control terminal or input terminal of the N-type power output stage, the drain terminal of M10 is connected to the DC power supply anode VDD, the source terminal is connected to the upper end of the resistor R1, forming an output voltage node Vo, the lower end of the resistor R1 is connected to the upper end of the resistor R2, forming a feedback voltage node Vfb, and the lower end of the resistor R2 is grounded; The anode of the compensation capacitor is connected to the output end of the direct drive error amplifier, and the cathode is connected to the feedback voltage node Vo of the N-type power output stage.

2. The low-power, high-transient-response, low-dropout linear regulator without external capacitor according to claim 1, characterized in that: The adaptive impedance transient enhancement circuit is composed of an NMOS leakage tube M15, and its input is connected to a voltage signal with a trend opposite to that of the output voltage of the linear regulator.

3. The low-power, high-transient-response, low-dropout linear regulator with no external capacitor according to claim 2, characterized in that: The specific connection relationship of the adaptive impedance transient enhancement circuit is as follows: the gate terminal of the NMOS leakage tube M15 is connected to the output terminal of the adaptive bias circuit, the source terminal of M15 is grounded, and the drain terminal is connected to the output voltage node Vo of the N-type power output stage. The adaptive bias circuit is composed of M4, M6, M8, and M11 in the direct drive error amplifier.

4. The low-power, high-transient-response, low-dropout linear regulator without external capacitor according to claim 1, characterized in that: The compensation capacitor is based on the principle of Miller compensation.

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