Display panel and display device

Abstract

The present application discloses a display panel, an integrated chip and a display device, wherein the display panel comprises: a first display area and a second display area; a pixel circuit, wherein the pixel circuit comprises a first pixel circuit and a second pixel circuit, wherein the first pixel circuit is used to provide a driving current for a light-emitting element in the first display area, and the second pixel circuit is used to provide a driving current for a light-emitting element in the second display area; the pixel circuit receives a bias adjustment signal, wherein the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, wherein the first pixel circuit receives the first bias adjustment signal, and the second pixel circuit receives the second bias adjustment signal; wherein the voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, and V1≠V2. The present application adjusts the bias states of the first display area and the second display area respectively, so that different display areas can achieve better display effects.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, an integrated chip for providing signals for the display panel, and a display device including the display panel. Background Art

[0002] With the advancement of display technology, new display panels, such as organic light-emitting diode (OLED) and micro LED (micro LED), are emerging and gaining widespread popularity among consumers. Furthermore, as display panels integrate increasingly comprehensive functions, different areas of the display panel may require different functions. To achieve these functions, it may be necessary to design the display panel differently for each area.

[0003] The pixel circuit is a very critical component in the display panel. It plays an important role in providing driving current for the light-emitting elements of the display panel. When different areas of the display panel require different display functions or display effects, it is often necessary to differentiate the pixel circuit design in different areas. Therefore, how to differentiate the pixel circuit design according to the display function or display effect of different areas in the display panel is a hot research topic in this field at the current stage. Summary of the Invention

[0004] In view of this, the present application provides a display panel, an integrated chip for providing signals to the display panel, and a display device including the display panel, which are used to adjust the pixel circuit in different areas according to the different requirements of different areas in the display panel to realize the functions of each area of ​​the display panel.

[0005] In one aspect, the present application provides a display panel, comprising:

[0006] a first display area and a second display area;

[0007] A pixel circuit, the pixel circuit including a first pixel circuit and a second pixel circuit, the first pixel circuit being used to provide a driving current for a light-emitting element in a first display area, and the second pixel circuit being used to provide a driving current for a light-emitting element in a second display area;

[0008] The pixel circuit receives a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal. The first pixel circuit receives the first bias adjustment signal to adjust the bias state of the first pixel circuit, and the second pixel circuit receives the second bias adjustment signal to adjust the bias state of the second pixel circuit; wherein,

[0009] The voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, wherein V1≠V2.

[0010] Another aspect of the present application provides an integrated chip for providing a bias adjustment signal for the above-mentioned display panel, wherein:

[0011] The integrated chip provides a first bias adjustment signal for the first pixel circuit to adjust the bias state of the first pixel circuit, and the integrated chip provides a second bias adjustment signal for the second pixel circuit to adjust the bias state of the second pixel circuit; wherein,

[0012] The voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, wherein V1≠V2.

[0013] Another aspect of the present application provides a display device, comprising the above-mentioned display panel.

[0014] The above-mentioned display panel, integrated chip and display device provided by the present application, wherein the display panel includes a first display area and a second display area, a first pixel circuit for providing a driving current to the light-emitting element in the first display area receives a first bias adjustment signal, and a second pixel circuit for providing a driving current to the light-emitting element in the second display area receives a second bias adjustment signal, and the voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal. Because the bias adjustment signal is a signal received by the pixel circuit for adjusting the bias state of the driving transistor, the magnitude of the bias adjustment signal affects the adjustment process of the bias state of the driving transistor. If the first display area and the second display area in the panel have different requirements for the pixel circuit in order to achieve different functions, resulting in different bias states of the driving transistor, different bias adjustment signals are required to adjust the bias states of the driving transistors in the pixel circuits corresponding to the first display area and the second display area respectively, thereby facilitating the optimization of the functions of the different display areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a display panel provided in an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0017] Figure 3 is a schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0019] Figure 5is a schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0020] Figure 6 This is a schematic diagram of a wiring connection method provided in an embodiment of the present application;

[0021] Figure 7 is a schematic diagram of another display panel provided in an embodiment of the present application;

[0022] Figure 8 is a schematic diagram of another display panel provided in an embodiment of the present application;

[0023] Figure 9 This is a schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] It should be noted that the following description sets forth specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways than those described herein, and those skilled in the art may make similar generalizations without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0026] One aspect of the present application provides a display panel, which may be an organic light emitting diode display panel, a micro light emitting diode display panel, or other types of display panels.

[0027] refer to Figure 1 , Figure 1 10 is a schematic diagram of a display panel provided in an embodiment of the present application, wherein the display panel 10 includes a first display area 101 and a second display area 102; a pixel circuit, the pixel circuit includes a first pixel circuit 110 and a second pixel circuit 120, the first pixel circuit 110 is used to provide a driving current for the light-emitting element of the first display area 101, and the second pixel circuit 120 is used to provide a driving current for the light-emitting element of the second display area 102; the pixel circuit receives a bias adjustment signal, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, the first pixel circuit 110 receives the first bias adjustment signal for adjusting the bias state of the first pixel circuit 110, and the second pixel circuit 120 receives the second bias adjustment signal for adjusting the bias state of the second pixel circuit 120; wherein the voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, wherein V1≠V2.

[0028] Through the above design, the display panel 10 includes a first display area 101 and a second display area 102. A first pixel circuit 110 for providing a driving current to the light-emitting elements in the first display area 101 receives a first bias adjustment signal, and a second pixel circuit 120 for providing a driving current to the light-emitting elements in the second display area 102 receives a second bias adjustment signal. The voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal. Because the bias adjustment signal is a signal received by the pixel circuit for adjusting the bias state of the driving transistor, the magnitude of the bias adjustment signal affects the adjustment process of the bias state of the driving transistor. If the first display area 101 and the second display area 102 in the panel have different requirements for the pixel circuit to achieve different functions, resulting in different bias states of the driving transistor, different bias adjustment signals are required to adjust the bias states of the driving transistors in the pixel circuits corresponding to the first display area 101 and the second display area 102, respectively, thereby facilitating the optimization of the functions of the different display areas.

[0029] It should be noted that if Figure 1 As shown, the first bias adjustment signal can be provided by the first bias adjustment signal line 210, and the second bias adjustment signal can be provided by the second bias adjustment signal line 220. The first bias adjustment signal bus 201 is used to provide signals for the first bias adjustment signal line 210, and the second bias adjustment signal bus 202 is used to provide signals for the second bias adjustment signal line 220. The integrated chip 300 can be used to provide signals for the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202. The settings of the integrated chip and each signal line will be described in detail later.

[0030] Optional, reference Figure 2-Figure 5 , Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of the present application, Figure 3 is a schematic diagram of another pixel circuit provided in an embodiment of the present application, Figure 4 is a schematic diagram of another pixel circuit provided in an embodiment of the present application. Figure 5This is a schematic diagram of another pixel circuit provided in an embodiment of the present application, wherein the pixel circuit 10 includes a data writing module 11, a driving module 12, a compensation module 13 and a bias adjustment module 14; the driving module 12 includes a driving transistor T2, and the driving transistor T2 is used to provide a driving current for the light-emitting element 20 of the display panel 100; the data writing module 11 is connected to the first electrode (i.e., the N2 node) of the driving transistor T2, and is used to provide a data signal to the driving transistor T2; the bias adjustment module 14 is connected to the first electrode (i.e., the N2 node) or the second electrode (i.e., the N3 node) of the driving transistor T2, and is used to provide a bias adjustment signal V0 to the driving transistor T2; the compensation module 13 is connected between the gate (i.e., the N1 node) and the second electrode (i.e., the N3 node) of the driving transistor, and is used to compensate for the threshold voltage of the driving transistor T2.

[0031] In addition, the pixel circuit 10 may further include a reset module 15 for providing a reset signal Vref for the gate of the driving transistor T2; an initialization module 16 for providing an initialization signal Vini for the light-emitting element 20; and a light-emitting control module 17 for selectively allowing the light-emitting element 20 to enter the light-emitting stage. Optionally, the light-emitting control module 17 includes a first light-emitting control module 171 and a second light-emitting control module 172. The first light-emitting control module 171 is connected between the first power supply signal terminal and one pole of the driving transistor T2, and the second light-emitting control module 172 is connected between the other pole of the driving transistor T2 and the light-emitting element 20.

[0032] Optionally, in this embodiment, the control end of the data writing module 11 receives a first scanning signal S1, and the first scanning signal S1 controls the opening and closing of the data writing module 11; the control end of the compensation module 13 receives a second scanning signal S2, and the second scanning signal S2 controls the opening and closing of the compensation module 13; the control end of the bias adjustment module 14 receives a bias adjustment control signal SV, and the bias adjustment control signal SV controls the opening and closing of the bias adjustment module 14; the control end of the reset module 15 receives a third scanning signal S3, and the third scanning signal S3 controls the opening and closing of the reset module 15; the control end of the initialization module 16 receives a fourth scanning signal S4, and the fourth scanning signal S4 controls the opening and closing of the initialization module 16; the control end of the light-emitting control module 17 receives a light-emitting control signal EM, and the light-emitting control signal EM controls the opening and closing of the light-emitting control module 17.

[0033] In addition, optionally, in this embodiment, the data writing module 11 includes a data writing transistor T1, and the first scanning signal S1 controls the turning on and off of the data writing transistor T1; the compensation module 13 includes a compensation transistor T3, and the second scanning signal S2 controls the turning on and off of the compensation transistor T3; the bias adjustment module 14 includes a bias adjustment transistor T4, and the bias adjustment control signal SV controls the turning on and off of the bias adjustment transistor T4; the reset module 15 includes a reset transistor T5, and the third scanning signal S3 controls the turning on and off of the reset transistor T5; the initialization module 16 includes an initialization transistor T6, and the fourth scanning signal S4 controls the turning on and off of the initialization transistor T6; the first light-emitting control module 171 includes a first light-emitting control transistor T7, and the second light-emitting control module 172 includes a second light-emitting control transistor T8, and the light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T7 and the second light-emitting control transistor T8.

[0034] It should be noted that, when conditions permit, at least two of the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, the bias adjustment control signal SV, the light-emitting control signal EM and other signals can be the same signal. For example, when the bias adjustment transistor T4 and the initialization transistor T6 are transistors of the same type, the bias adjustment control signal SV and the fourth scan signal S4 can be the same signal.

[0035] It should be noted that if Figure 2 and Figure 3 As shown, the driving transistor T2 is a PMOS transistor, and the pixel circuit 10 further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the first power signal terminal, and a second electrode is connected to the gate of the driving transistor T2, for storing the signal transmitted to the gate of the driving transistor T2. Figure 2 As shown, the bias adjustment module 14 is connected to the first electrode of the driving transistor T2, that is, the N2 node, as shown in FIG. Figure 3 As shown, the bias adjustment module 14 is connected to the second electrode of the driving transistor T2, that is, the N3 node. Figure 4 and Figure 5 As shown, the driving transistor T2 is an NMOS transistor, and the pixel circuit 10 further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the light emitting element 20, and a second electrode is connected to the gate of the driving transistor T2, for storing the signal transmitted to the gate of the driving transistor T2. Figure 4 As shown, the bias adjustment module 14 is connected to the first electrode of the driving transistor T2, that is, the N2 node, as shown in FIG. Figure 5 As shown, the bias adjustment module 14 is connected to the second electrode of the driving transistor T2, that is, the N3 node.

[0036] In the above manner, a bias adjustment module 14 is provided in the pixel circuit 10, and the bias adjustment module 14 is used to provide a bias adjustment signal V0 for the driving transistor T2. Because the potential difference between the gate and the first or second electrode of the driving transistor T2 during the light emission process may cause a bias problem, that is, when the driving transistor T2 is a PMOS transistor, when the driving transistor T2 is turned on, but its gate voltage is greater than the voltage of the first or second electrode, a bias problem will occur; that is, when the driving transistor T2 is an NMOS transistor, when the driving transistor T2 is turned on, but its gate voltage is less than the voltage of the first or second electrode, a bias problem will occur. The bias problem often causes a reverse electric field to be generated inside the driving transistor T2, resulting in carrier polarization, thereby causing the threshold voltage of the driving transistor T2 to shift. The threshold voltage shift of the driving transistor T2 causes the driving current generated by the driving transistor T2 to be unstable, especially when the grayscale changes, resulting in flickering problems. In this embodiment, by providing a bias adjustment signal V0 to the first electrode or the second electrode of the driving transistor T2, the voltage difference between the gate of the driving transistor T2 and the first electrode or the second electrode is adjusted in time to offset the bias problem and avoid the threshold voltage of the driving transistor T2 from shifting, thereby helping to reduce the flicker phenomenon.

[0037] It should be noted that Figure 2-Figure 5 The following are only exemplary methods of setting the bias adjustment module 14 in several pixel circuits, but not all of them. A bias adjustment signal is provided for the pixel circuit to adjust the bias state of the driving transistor, and various other settings of the bias adjustment module that meet the limitations of the bias adjustment signal in this embodiment are within the scope of protection of the embodiments of the present application and will not be described in detail in this embodiment.

[0038] Optionally, in this embodiment, in some optional implementations, the working process of the pixel circuit 10 includes a data writing frame and a holding frame, the data writing frame includes a first bias adjustment stage, in the first bias adjustment stage, the voltage value of the first bias adjustment signal is V11, and the voltage value of the second bias adjustment signal is V12, wherein V11≠V12.

[0039] The data write frame includes a data write phase. During the data write phase, the data write module 11 and the compensation module 13 are turned on, and the data signal is written to the gate of the driving transistor T2. The hold frame generally does not include the data write phase. During the hold frame, the data signal is not written to the gate of the driving transistor T2. Therefore, generally speaking, a data signal refresh cycle of a pixel circuit includes one or more data write frames, and may also include a hold frame. Because the data write phase writes data to the gate of the driving transistor T2, which involves changes in the grayscale signal, the gate of the driving transistor T2 has high requirements for signal acquisition, and thus the stability of the driving transistor T2 has high requirements. Therefore, the data write frame is generally required to include a bias adjustment phase. The bias state in the driving transistor is fully adjusted through the bias adjustment signal to eliminate the offset of the threshold voltage, thereby avoiding flickering problems when the grayscale changes. Since the first display area 101 and the second display area 102 have different requirements for display functions, it is possible to select a first bias adjustment stage of the data writing frame in which the voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal, thereby independently adjusting the bias states of the first pixel circuit 110 and the second pixel circuit 120.

[0040] It should be noted that, in this embodiment, the first bias adjustment stage of the data writing frame is emphasized, and the voltage values ​​of the first bias adjustment signal and the second bias adjustment signal are different. At this time, the holding frame may include the bias adjustment stage or may not include the bias adjustment stage. If the holding frame includes the bias adjustment stage, then within the bias adjustment stage of the holding frame, the voltage values ​​of the first bias adjustment signal and the second bias adjustment signal may be the same or different.

[0041] Optionally, in this embodiment, in other optional implementations, the working process of the pixel circuit 10 includes a data writing frame and a holding frame, and the holding frame includes a second bias adjustment stage. In the second bias adjustment stage, the voltage value of the first bias adjustment signal is V21, and the voltage value of the second bias adjustment signal is V22, wherein V21≠V22.

[0042] As previously described, because the hold frame does not include a data write phase, the data signal is not written to the gate of the driving transistor T2. However, when the data refresh frequency of the display panel is low, that is, when a data refresh cycle includes a large number of hold frames, the bias phenomenon of the driving transistor in the hold phase for a long time will become increasingly serious. If the hold frame does not include a bias adjustment phase, the threshold voltage offset problem of the driving transistor T2 will be more serious. To avoid this phenomenon, a bias adjustment phase is generally provided in the hold frame. Since the first display area 101 and the second display area 102 have different display function requirements, the voltage value of the first bias adjustment signal can be different from the voltage value of the second bias adjustment signal in the second bias adjustment phase of the hold frame, thereby independently adjusting the bias states of the first pixel circuit 110 and the second pixel circuit 120.

[0043] It should be noted that, in this embodiment, emphasis is placed on maintaining the second bias adjustment stage of the frame, and the voltage values ​​of the first bias adjustment signal and the second bias adjustment signal are different. At this time, the data write frame may include a bias adjustment stage or may not include a bias adjustment stage. If the data write frame includes a bias adjustment stage, then within the bias adjustment stage of the data write frame, the voltage values ​​of the first bias adjustment signal and the second bias adjustment signal may be the same or different.

[0044] Optionally, in this embodiment, in some further optional implementations, the working process of the pixel circuit 10 includes a data writing frame and a holding frame, the data writing frame includes a first bias adjustment stage, the holding frame includes a second bias adjustment stage, in the first bias adjustment stage, the voltage value of the first bias adjustment signal is V11, and the voltage value of the second bias adjustment signal is V12, in the second bias adjustment stage, the voltage value of the first bias adjustment signal is V21, and the voltage value of the second bias adjustment signal is V22; wherein, |V11-V12|+|V21-V22|≠0.

[0045] When both the data writing frame and the hold frame include a bias adjustment phase, because the first display area 101 and the second display area 102 have different display function requirements, the first bias adjustment signal and the second bias adjustment signal can be set to be different in at least one of the data writing frame and the hold frame, that is, |V11-V12|+|V21-V22|≠0, thereby independently adjusting the bias states of the first pixel circuit 110 and the second pixel circuit 120. Furthermore, when |V11-V12|+|V21-V22|≠0, the following different situations can be included:

[0046] When |V11-V12|=0 and |V21-V22|≠0, that is, in the first bias adjustment phase of the data writing frame, the voltage value of the first bias adjustment signal is the same as the voltage value of the second bias adjustment signal, and in the second bias adjustment phase of the holding frame, the voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal. Therefore, the different display function requirements of the first display area 101 and the second display area 102 are matched mainly by adjusting the voltage value of the bias adjustment signal of the holding frame.

[0047] When |V11-V12|≠0 and |V21-V22|=0, that is, V11≠V12 and V21=V22, that is, in the first bias adjustment phase of the data writing frame, the voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal, and in the second bias adjustment phase of the holding frame, the voltage value of the first bias adjustment signal is the same as the voltage value of the second bias adjustment signal. Therefore, the different display function requirements of the first display area 101 and the second display area 102 are matched mainly by adjusting the voltage value of the bias adjustment signal of the data writing frame.

[0048] When |V11-V12|≠0 and |V21-V22|≠0, that is, V11=V12 and V21≠V22, that is, in the first bias adjustment phase of the data writing frame, the voltage value of the first bias adjustment signal is different from the voltage value of the second bias adjustment signal, and in the second bias adjustment phase of the holding frame, the voltage value of the first bias adjustment signal is also different from the voltage value of the second bias adjustment signal. Therefore, by adjusting the voltage values ​​of the bias adjustment signals of the data writing frame and the holding frame, the different display function requirements of the first display area 101 and the second display area 102 are matched. In this case, |V11-V12| can be |V21-V22|, or |V11-V12|≠|V21-V22|, that is, |V11-V12|<V21-V22|, or, |V11-V12|>|V21-V22|. When |V11-V12|=|V21-V22|, the change in the voltage value of the bias adjustment signal in the first bias adjustment stage of the data writing frame in the first display area 101 and the second display area 102 is equal to the change in the voltage value of the bias adjustment signal in the second bias adjustment stage of the holding frame in the first display area 101 and the second display area 102, that is, the change amplitude of the bias adjustment signal of the data writing frame is the same as the change amplitude of the bias adjustment signal of the holding frame, which is beneficial to reducing the complexity of signal adjustment. In some embodiments, |V11-V12|<|V21-V22|, in which case the amplitude of the bias adjustment signal change in the data write frame is smaller than the amplitude of the bias adjustment signal change in the hold frame. When the display panel refreshes data at a low frequency, the hold frame lasts for a long time. In this case, the bias adjustment stage in the hold frame plays a relatively important role in adjusting the bias state of the drive transistor. In this case, the amplitude of the bias adjustment signal change in the hold frame is set to be larger, and the display function requirements of the first display area 101 and the second display area 102 are matched primarily by the change of the bias adjustment signal in the hold frame. In other embodiments, |V11-V12|>|V21-V22|, in which case the amplitude of the bias adjustment signal change in the data write frame is larger than the amplitude of the bias adjustment signal change in the hold frame. When the display panel refreshes at a high frequency, there are fewer hold frames and more data write frames. In this case, the amplitude of the bias adjustment signal change in the data write frame is set to be larger, and the display function requirements of the first display area 101 and the second display area 102 are matched primarily by the change of the bias adjustment signal in the data write frame.

[0049] Optionally, in some embodiments, (V11-V12)×(V21-V22)>0, that is, V11>V12 and V21>V22, or, V11<V12 and V21<V22, that is, the change trend of the bias adjustment signal in the data writing frame is the same as the change trend of the bias adjustment signal in the holding frame. When the bias adjustment signal of the data writing frame becomes smaller, the bias adjustment signal of the holding frame also becomes smaller; when the bias adjustment signal of the data writing frame becomes larger, the bias adjustment signal of the holding frame also becomes larger. Generally speaking, after the display function requirements of the first display area 101 and the second display area 102 are determined, the bias state adjustment requirements for the pixel circuits therein are also determined. Therefore, generally, how the change trend of the bias adjustment signal in the data writing frame is set, the change trend of the bias adjustment signal in the holding frame can also be set to the same trend.

[0050] Optionally, in other embodiments, (V11-V12)×(V21-V22)<0, that is, V11>V12 and V21<V22, or, V11<V12 and V21>V22. In some special cases, there is a situation where the changing trend of the bias adjustment signal in the data writing frame is opposite to the changing trend of the bias adjustment signal in the maintaining frame. It can be flexibly adjusted depending on specific display requirements.

[0051] Optionally, in this embodiment, in the first pixel circuit 110, the first pixel circuit that provides a driving current for the light-emitting element with a light-emitting color of the first color includes a first driving transistor, and in the second pixel circuit 120, the second pixel circuit that provides a driving current for the light-emitting element with a light-emitting color of the first color includes a second driving transistor, the width-to-length ratio of the channel region of the first driving transistor is R11, and the width-to-length ratio of the channel region of the second driving transistor is R12, wherein R11≠R12.

[0052] In some implementations of this embodiment, the width-to-length ratios of the driving transistors in the first pixel circuit 110 and the second pixel circuit 120 are different, thereby achieving different display function requirements of the first display area 101 and the second display area 102. Generally, when the width-to-length ratio of the driving transistor is larger, the driving transistor has a greater driving capability. When other conditions are the same, a driving transistor with a larger width-to-length ratio can provide a larger driving current, which is beneficial for driving light-emitting elements with higher requirements for luminous brightness or larger luminous area. When the first display area 101 and the second display area 102 have different requirements for the luminous brightness and luminous area of ​​the light-emitting elements, it is often necessary to set driving transistors with different width-to-length ratios to meet the different display function requirements of the first display area 101 and the second display area 102.

[0053] Because the bias adjustment signal is used to adjust the bias state of the driver transistor, when the aspect ratio of the driver transistor is different, its bias state will be different when other conditions are the same. Therefore, different bias adjustment signals are needed to specifically adjust the bias state of the driver transistor with different aspect ratios. Therefore, when R11 ≠ R12, V1 ≠ V2 can be set.

[0054] Optionally, in some embodiments, R11 < R12 and V1 > V2 can be set. That is, the voltage value of the bias adjustment signal received by the pixel circuit with a smaller width-to-length ratio of the driving transistor is greater than the voltage value of the bias adjustment signal received by the pixel circuit with a larger width-to-length ratio of the driving transistor. Because when the width-to-length ratio of the driving transistor is small, it is generally used to provide driving current for a light-emitting element with a smaller driving current requirement. At this time, the data signal received by its gate is relatively large. Taking the case where the driving transistor is a PMOS transistor as an example, when the driving transistor is in the light-emitting stage, the higher the potential of its gate, the more likely it is to form a reverse electric field with either the source or the drain, thereby causing a bias phenomenon. That is, in this case, the bias phenomenon may be more likely to occur and may be more serious. Therefore, it is necessary to set a larger bias adjustment signal to offset the bias phenomenon of the driving transistor in a shorter time. Therefore, when R11 < R12, V1 > V2.

[0055] Optionally, in other embodiments, R11 is set to be less than R12, and V1 is set to be less than V2. That is, the voltage value of the bias adjustment signal received by the pixel circuit with a smaller width-to-length ratio of the driving transistor is less than the voltage value of the bias adjustment signal received by the pixel circuit with a larger width-to-length ratio of the driving transistor. In some special cases, when the width-to-length ratio of the driving transistor is large, its bias level is also large. For example, when the pixel circuit with a larger width-to-length ratio of the driving transistor is used to provide driving current for more than one light-emitting element, because it connects more light-emitting elements and the driving current is large, the threshold voltage stability requirements of the driving transistor are higher. It is also possible to set the pixel circuit with a larger width-to-length ratio of the driving transistor to receive a larger bias adjustment signal, so it is set that when R11 is less than R12, V1 is less than V2.

[0056] Furthermore, in this embodiment, R11 / R12 < V2 / V1, meaning the ratio of the drive transistor's aspect ratios is less than the ratio of V2 to V1. When R11 < R12 and V1 < V2, this equation holds true for the reasons described above and will not be repeated. When R11 < R12 and V1 > V2, this indicates that the magnitude of the bias adjustment signal's change is less than the magnitude of the drive transistor's aspect ratio change. As previously mentioned, changes in the drive transistor's aspect ratio affect its drive capability and ability to generate drive current. Small changes in the aspect ratio typically have little significant impact on these capabilities, while large changes in the aspect ratio can significantly alter these capabilities. The bias adjustment signal regulates the bias state of the drive transistor. In addition to being related to the aspect ratio of the drive transistor, the bias state is also significantly affected by the display panel's data refresh rate. Specifically, the longer the drive transistor remains on duty within a data cycle, the more severe the bias. Therefore, when the data refresh frequency is constant, the degree of change in the bias state of the driving transistor caused by the width-to-length ratio of the driving transistor is relatively limited. Therefore, in this application, R11 / R12 is set to be less than V2 / V1, thereby avoiding a large change in the bias adjustment signal and causing an increase in power consumption, and reducing the difficulty in the process.

[0057] In addition, optionally, in this embodiment, the operation process of the pixel circuit 10 includes a data writing frame and a holding frame, the data writing frame includes a first bias adjustment stage, and the holding frame includes a second bias adjustment stage. In the first bias adjustment stage, the voltage value of the bias adjustment signal is V11, and the voltage value of the second bias adjustment signal is V12. In the second bias adjustment stage, the voltage value of the first bias adjustment signal is V21, and the voltage value of the second bias adjustment signal is V22; wherein, R11 / R12<V12 / V11, and / or, R11 / R12<V22 / V21. When R11<R12 and V11<V12, and / or, R11<R12 and V21<V22, the above formula is naturally established and no further explanation is needed. When R11<R12 and V11>V12, and / or, R11<R12 and V21>V22, the reason is similar to the previous paragraph, because the change in the bias state of the driving transistor caused by the change in the aspect ratio of the driving transistor is relatively limited, therefore, in order to avoid increasing power consumption and process difficulty, the change amplitude of the bias adjustment signal in the data writing frame is limited to be smaller than the change amplitude of the aspect ratio of the driving transistor, and / or, the change amplitude of the bias adjustment signal in the frame is kept smaller than the change amplitude of the aspect ratio of the driving transistor, that is, R11 / R12<V12 / V11, and / or, R11 / R12<V22 / V21.

[0058] Optionally, in this embodiment, when the first pixel circuit 110 and the second pixel circuit 120 receive the same data signal, the first pixel circuit 110 generates a driving current I1 and the second pixel circuit 120 generates a driving current I2, where I1≠I2.

[0059] When the first display area 101 and the second display area 102 have different driving current requirements for the light-emitting elements, the bias states of the driving transistors are often different due to their different abilities to generate driving currents. Therefore, when I1≠I2, V1≠V2, and the bias states of the driving transistors of the pixel circuits of the first display area 101 and the second display area 102 are adjusted separately.

[0060] Optionally, in some embodiments, I1<I2, and V1>V2, when the driving transistor has a low ability to generate a driving current, in some cases, the bias level of the driving transistor is relatively large. In this case, a larger bias adjustment signal can be used to adjust its bias state. In some other embodiments, I1<I2, and V1<V2, when the driving transistor has a low ability to generate a driving current, in some cases, the bias level of the driving transistor is relatively small. In this case, a smaller bias adjustment signal can be used to adjust its bias state. Flexible adjustments can be made according to specific circumstances.

[0061] Optionally, in this embodiment, the distribution density of the light-emitting elements in at least part of the first display area 101 is ρ1, and the distribution density of the light-emitting elements in at least part of the second display area 102 is ρ2, where ρ1≠ρ2.

[0062] When the distribution density of the light-emitting elements in the first display area 101 and the second display area 102 is different, because the distribution density of the light-emitting elements is different, in order to ensure the uniformity of the display effect of each area of ​​the display panel, the luminous brightness of the light-emitting elements at different distribution densities may be different. The different luminous brightness requires different capabilities of the driving transistor to generate driving current. Therefore, the bias degree of the driving transistor may also be different. Therefore, when ρ1≠ρ2, V1≠V2, so that the bias states of the driving transistors of the pixel circuits in the first display area 101 and the second display area 102 are adjusted separately.

[0063] Optionally, in some embodiments, ρ1<ρ2, and V1<V2, when the distribution density of the light-emitting elements is large, in some cases, the bias level of the driving transistor is large. In this case, a larger bias adjustment signal can be used to adjust its bias state. In some other embodiments, ρ1<ρ2, and V1>V2, when the distribution density of the light-emitting elements is large, in some cases, the bias level of the driving transistor is small. In this case, a smaller bias adjustment signal can be used to adjust its bias state. Flexible adjustments can be made according to specific circumstances.

[0064] Optionally, in this embodiment, the light emitting area of ​​the light emitting element with the first color in the first display area 101 is S11, and the light emitting area of ​​the light emitting element with the first color in the second display area 102 is S12, where S11<S12.

[0065] In this embodiment, the light-emitting area of ​​the light-emitting elements in the first display area 101 can be smaller than the light-emitting area in the second display area 102. Optionally, as will be described later, the second display area 102 includes a transmissive area. The operation of the second display area includes a light-transmitting phase. At least during the light-transmitting phase, the transmissive area allows light to pass through the display panel. Because space must be reserved in the second display area for the transmissive area, the number of light-blocking structures such as pixel circuits needs to be minimized. As the number of pixel circuits is reduced, the number of light-emitting elements is also reduced accordingly. Therefore, the light-emitting area of ​​the light-emitting elements in the second display area 102 is set larger to fully ensure the light brightness and display effect of the second display area 102.

[0066] Optionally, in this embodiment, in the first display area 101, a first pixel circuit 110 provides driving current for m1 light-emitting elements, and in the second display area 102, a second pixel circuit 120 provides driving current for m2 light-emitting elements, where m1 ≥ 1, m2 ≥ 1, and m1 < m2. That is, the number of light-emitting elements driven by the second pixel circuit 120 is greater than the number of light-emitting elements driven by the first pixel circuit 110.

[0067] In this embodiment, when the first display area 101 and the second display area 102 need to perform different functions, for example, when the second display area 102 includes a transmissive area, in order to fully reduce the number of pixel circuits in the second display area 102, the second pixel circuit 120 is configured to drive a larger number of light-emitting elements. This ensures a larger area for the transmissive area while maintaining the display quality of the second display area 102. In this case, because the number of light-emitting elements driven by the first pixel circuit 110 differs from the number of light-emitting elements driven by the second pixel circuit 120, when uniform display brightness is required in the first and second display areas 101, 102, the second pixel circuit 120 requires a larger drive current to distribute to the larger number of light-emitting elements. This results in different drive current generation capabilities and bias levels for the first and second pixel circuits 110, 120, requiring different bias adjustment signals for adjustment. That is, when m1 < m2, V1 ≠ V2.

[0068] Optionally, in some embodiments, m1 < m2 and V1 < V2. As described above, the second pixel circuit 120 drives a larger number of light-emitting elements and generates a larger drive current. In some cases, the larger drive current may cause the bias of the drive transistor to be greater, thereby requiring a larger bias adjustment signal to adjust its bias state. Therefore, in this case, V1 < V2. In some other embodiments, m1 < m2 and V1 > V2 may also exist. In particular, when the larger drive current generated in the second pixel circuit 120 is achieved because the data signal it receives is smaller, in this case, the data signal received by the second pixel circuit 120 is smaller and the data signal received by the first pixel circuit 110 is larger. The drive transistor in the first pixel circuit 110 is more likely to have a bias problem, and the bias problem may be more serious. In this case, setting V1 > V2 can better adjust the bias states of the first pixel circuit 110 and the second pixel circuit 120.

[0069] In this embodiment, m1=1, m2=2, m2=3, or m2=4. That is, in the first display area 101, one first pixel circuit 110 provides a driving current for one light-emitting element, and in the second display area 102, one second pixel circuit 120 provides a driving current for two, three, or four light-emitting elements. In the first display area 101, because there is no need to consider the problem of the transparent area, one pixel circuit drives one light-emitting element, which is conducive to fully ensuring the driving capability of one pixel circuit for the light-emitting element. In the second display area 102, because the problem of the transparent area needs to be considered, one pixel circuit drives multiple light-emitting elements. However, the inventors found through experiments that when one pixel circuit drives more than four light-emitting elements, the driving capability requirements for the pixel circuit are higher, and the instability of the driving process increases, which is not conducive to ensuring the display effect of the display panel. Of course, in other embodiments, when the stability of the pixel circuit is fully overcome, m1 can also be an integer greater than 1, and m2 can also be an integer greater than 4.

[0070] Optionally, in this embodiment, if Figure 1 As shown, the display panel 100 includes a first bias adjustment signal line 210 and a first bias adjustment signal bus 201, as well as a second bias adjustment signal line 220 and a second bias adjustment signal bus 202. The first bias adjustment signal line 201 is connected between the first pixel circuit 110 and the first bias adjustment signal bus 201, and the second bias adjustment signal line 220 is connected between the second pixel circuit 120 and the second bias adjustment signal bus 202; the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 are located in at least one of the first side frame 401 and the second side frame 402 that are oppositely arranged of the display panel. Figure 1 In the embodiment, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 are arranged in both the first side frame 401 and the second side frame 402, providing signals to the first bias adjustment signal line 210 and the second bias adjustment signal line 220 from both sides. In other embodiments, the first bias adjustment signal bus 201 can be located in the first side frame 401 and the second bias adjustment signal bus 202 can be located in the second side frame 402, or the first bias adjustment signal bus 201 can be located in the second side frame 402 and the second bias adjustment signal bus 202 can be located in the first side frame 401. In other embodiments, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 can both be located in the first side frame 401 or both in the second side frame 402. It can be flexibly adjusted according to the specific situation.

[0071] Optionally, in this embodiment, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 are located in the same film layer, and the first bias adjustment signal line 210 and the second bias adjustment signal line 220 are located in different film layers; or, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 are located in different film layers, and the first bias adjustment signal line 201 and the second bias adjustment signal line 202 are located in the same film layer; or, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 are located in the same film layer, and the first bias adjustment signal line 201 and the second bias adjustment signal line 202 are located in the same film layer.

[0072] In this embodiment, the film layer relationship between the first bias adjustment signal line 210, the second bias adjustment signal line 220, the first bias adjustment signal bus 201, and the second bias adjustment signal bus 202 can be flexibly designed according to actual needs. When the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 are located in different film layers, the two can at least partially overlap with each other, thereby fully saving the frame area.

[0073] Optional, reference Figure 6 , Figure 6 This is a schematic diagram of a routing connection method provided in an embodiment of the present application, wherein the first bias adjustment signal bus 201 is connected to the first bias adjustment signal line 210 through a transition routing 211, and the transition routing 211 and at least one of the first bias adjustment signal bus 201 and the first bias adjustment signal line 210 are located in different film layers; and / or, the second bias adjustment signal bus 202 is connected to the second bias adjustment signal line 220 through a transition routing 222, and the transition routing 222 and at least one of the second bias adjustment signal bus 202 and the second bias adjustment signal line 220 are located in different film layers.

[0074] Because there are many traces with various functions in the display panel, in some cases, the bias adjustment signal bus connected to the bias adjustment signal line may need to cross other traces, such as the reset signal bus or the initialization signal bus also located in the frame area. In this case, a transition trace may need to be set to connect the bias adjustment signal bus with the bias adjustment signal line. In addition, because traces with different functions in the display panel may be located on the same layer, for example, in some cases, the reset signal bus and the initialization signal bus and the bias adjustment signal bus may be located on the same layer. Then, in order to use the transition trace for crossing the traces, the transition trace may need to be set on a different film layer from at least one of the bias adjustment signal bus and the bias adjustment signal line, so as to achieve electrical connection between the two.

[0075] Optionally, in this embodiment, in some implementations, such as Figure 1As shown, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 extend in the same direction, and the first bias adjustment signal line 210 and the second bias adjustment signal line 220 extend in the same direction.

[0076] In some cases, such as Figure 1 As shown, the first display area 101 and the second display area 102 are both arranged adjacent to the first side frame 401 or the second side frame 402. In this way, the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 can extend in the same direction, and the first bias adjustment signal line 210 and the second bias adjustment signal line 220 can extend in the same direction to achieve connection. The structure is simple and easy to implement.

[0077] Optional, reference Figure 7 , Figure 7 : This is a schematic diagram of another display panel provided by an embodiment of the present application, wherein the first bias adjustment signal bus 201 is located in at least one of the first side frame 401 and the second side frame 402 of the display panel; the second bias adjustment signal bus 202 is located at least in the first side frame 401 and the third side frame 403 of the display panel, and the third side frame 403 is arranged adjacent to the first side frame 401; wherein the first bias adjustment signal line 210 extends along the first direction X and is connected to the first bias adjustment signal bus 201, and the second bias adjustment signal line 220 extends along the second direction Y and is connected to the second bias adjustment signal bus 202; the first direction X intersects with the second direction Y.

[0078] In some cases, the second display area 102 only occupies a small part of the display area, the first display area 101 is adjacent to the first side frame 401 and the second side frame 402, but the second display area 102 is not adjacent to at least one of the first side frame 401 or the second side frame 402. In this case, the second bias adjustment signal bus 202 can be set on the third side frame 403, and the second bias adjustment signal line 220 is connected to the second bias adjustment signal bus 202 along the second direction Y, and the first bias adjustment signal line 210 is connected to the first bias adjustment signal bus 201 along the first direction X, so that the two signal buses avoid problems such as concentrated routing and the need to cross lines, thereby simplifying the process.

[0079] Optionally, in this embodiment, the width of the first bias adjustment signal line 210 is W1, and the width of the second bias adjustment signal line 220 is W2, wherein, in some embodiments, W1 may be W2, and in other embodiments, W1≠W2, because the number of light-emitting elements connected to the first bias adjustment signal line 210 is often different from the number of light-emitting elements connected to the second bias adjustment signal line 220. Therefore, the length of the first bias adjustment signal line 210 and the load borne thereon are different from the length of the second bias adjustment signal line 220 and the load borne thereon. Therefore, setting W1≠W2 is more conducive to independently adjusting the transmission process of the first bias adjustment signal and the second bias adjustment signal.

[0080] Generally speaking, if Figure 7 As shown, when the second display area 102 includes a transparent area, it is generally used to mount a camera on the display device. The area of ​​the second display area 102 generally does not need to be too large. That is, the area of ​​the first display area 101 is larger than that of the second display area 102. Within the second display area 102, the second pixel circuit 120 drives a relatively small number of light-emitting elements, and the second bias adjustment signal line 220 generally carries a relatively small number of light-emitting elements. Therefore, W1 is set greater than W2, so that the width of the bias adjustment signal line carrying more light-emitting elements is greater than the width of the bias adjustment signal line carrying fewer light-emitting elements. The larger the line width, the smaller the resistance, thereby reducing the load on the bias adjustment signal line carrying more light-emitting elements. Of course, in other cases, W1 can also be set less than W2, and this can be set according to the specific situation.

[0081] Optionally, in this embodiment, the width of the first bias adjustment signal bus 201 is W11, and the width of the second bias adjustment signal bus 202 is W22, wherein, in some embodiments, W11=W22, and in other embodiments, W11≠W22. Because the positions of the first display area 101 and the second display area 102 are often different, the lengths of the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 may also be different. Then, it is necessary to design the two bias adjustment signal buses separately to balance the load and resistance thereon. In some cases, W11>W22. For example, when the number of light-emitting elements loaded on the first bias adjustment signal bus 201 is large, in order to reduce the load thereon, its width is set to be wider to reduce the resistance and balance the load. In other cases, W11<W22 can also be set. For example, Figure 7 As shown, when the second bias adjustment signal bus 202 is wound around the third side frame 403, resulting in a longer length and increased resistance, it is necessary to set its width to be larger to reduce resistance and balance the load thereon. This can be set according to specific circumstances.

[0082] refer to Figure 8 , Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present application. Optionally, in this embodiment, the second display area 102 includes a transmission area 500, and the working process of the second display area 102 includes a light transmission stage. At least in the light transmission stage, the transmission area 500 allows light to pass through the display panel.

[0083] Currently, under-screen camera technology is one of the hot technologies in the display industry. By installing the camera device below the second display area 102 of the display panel, a transparent area 500 is set in the second display area 102. When the camera function needs to be turned on, the camera obtains external light through the transparent area 500. When the camera function is turned off, the second display area 102 can display normally, thereby realizing full-screen display.

[0084] In this embodiment, the first display area 101 is a normal display area and does not have a transparent area. The second display area 102 is an under-screen camera area and has a transparent area 500. Because the transparent area 500 needs to occupy a certain area, the distribution density of the light-emitting elements, the size of the light-emitting area, the number of light-emitting elements driven by the pixel circuit, the width-to-length ratio of the driving transistor in the pixel circuit, etc. in the first display area 101 and the second display area 102 are different. This can lead to the limitations of the various embodiments described above. Of course, in other embodiments, such as when the display functions of the first display area 101 and the second display area 102 differ in other aspects, the limitations of the various embodiments described above may also apply.

[0085] Optionally, in this embodiment, in at least one operation phase of the display panel 100 , the data refresh frequency in the first display area 101 is F1 , and the data refresh frequency in the second display area 102 is F2 , wherein F1 ≠ F2 .

[0086] As users demand increasingly advanced display panel functionality, in some cases, different areas of the panel may need to be refreshed at different frequencies. For example, some pages may be used for gaming or video playback and require high-frequency refreshes, while others may display static images for extended periods or require low-frequency refreshes for text reading, effectively saving panel power. In this case, F1 ≠ F2. When F1 ≠ F2, V1 ≠ V2 can be set. This is because when the display panel refreshes data at a higher frequency, the driver transistor receives data signals at a higher frequency, and the voltages between its gate, source, and drain remain in a constant state. However, when the display panel refreshes data at a lower frequency, the driver transistor receives data signals at a lower frequency, and the voltages between its gate, source, and drain may remain in a constant state for extended periods. Because the bias problem of the driver transistor is primarily caused by the reverse electric field that may appear between the gate, source, and drain of the driver transistor during the light-emitting phase, different data refresh frequencies may result in different bias levels for the driver transistor. Different bias adjustment signals are required for targeted adjustments to regions with different data refresh frequencies.

[0087] Further optionally, in this embodiment, as described above, when the display panel refreshes data at a higher frequency, the frequency at which the driving transistor receives the data signal is higher, and the voltage between its gate, source, and drain remains in a state of change. When the display panel refreshes data at a lower frequency, the frequency at which the driving transistor receives the data signal is lower, and the voltage between its gate, source, and drain may remain in a state for a long time. Therefore, when the display panel refreshes at a low frequency, the bias may be more serious. In order to offset the bias phenomenon as much as possible, a larger bias adjustment signal is required for adjustment. Therefore, when F1>F2, V1<V2, the bias states of the high refresh frequency region and the low refresh frequency region can be adjusted in a targeted manner. In addition, in some special cases, there are other factors that affect F1>F2 and V1>V2 to meet the requirements, and it can be flexibly adjusted according to the specific situation.

[0088] Optionally, in this embodiment, in at least one stage of operation of the display panel 100, the light-emitting elements in the first display area 101 operate in a first mode, and the light-emitting elements in the second display area 102 operate in a second mode, and the light-emitting brightness of the light-emitting elements in the first mode is greater than the light-emitting brightness of the light-emitting elements in the second mode.

[0089] Users may often have different requirements for the display brightness of different areas of the display panel. For example, the display brightness of the text reading area generally does not need to be high to meet the requirements, while the display brightness of the video playback part often needs to be higher to display more clearly. Therefore, this embodiment provides a display panel with different luminous brightness in different areas. Based on this, because the luminous brightness of the light-emitting elements in the first display area 101 and the second display area 102 is different, and the luminous brightness is often related to the size of the driving current generated by the driving transistor and the luminous duration of the light-emitting element within one frame time, and factors such as the size of the driving current and the luminous duration are factors that affect the bias degree of the driving transistor. Therefore, in this embodiment, different bias adjustment signals are provided for the first display area 101 and the second display area 102, and the two areas are adjusted separately, that is, V1≠V2.

[0090] Further optionally, V1>V2, because the luminous brightness of the first display area 101 is greater than the luminous brightness of the second display area 102. Therefore, in some cases, the luminous duration of the light-emitting element in the first display area 101 within one frame time is greater than the luminous duration of the light-emitting element in the second display area 102 within one frame time. As mentioned above, the longer the luminous duration of the light-emitting element in one frame time, the more serious its bias may be. Therefore, in this case, the display area with high luminous brightness receives a larger bias adjustment signal, and the display area with low luminous brightness receives a smaller bias adjustment signal, so that the areas with more serious bias problems and relatively mild bias problems are each better adjusted.

[0091] In addition, generally speaking, when the data signal is larger, the driving current may be smaller, and when the data signal is smaller, the driving current may be larger. When the change in luminous brightness is achieved by changing the data signal, for the NMOS type driving transistor, the smaller the data signal received by its gate, the more likely it is to have a bias problem during the light-emitting stage. Therefore, for areas with higher luminous brightness, a larger bias signal needs to be set for adjustment.

[0092] In some cases, optionally, V1 < V2 may exist. As mentioned above, for a PMOS type driving transistor, the larger the data signal received by its gate, the more likely it is to have a bias problem during the light-emitting stage. Therefore, for areas with lower light-emitting brightness, a larger bias signal needs to be set for adjustment.

[0093] The above methods can be flexibly selected and adjusted according to the specific display conditions and brightness change methods.

[0094] Another aspect of the present application provides an integrated chip for providing a bias adjustment signal for the display panel in any of the above embodiments, such as Figure 1As shown, the integrated chip 300 provides a first bias adjustment signal for the first pixel circuit 110, which is used to adjust the bias state of the first pixel circuit 110, and the integrated chip 300 provides a second bias adjustment signal for the second pixel circuit 120, which is used to adjust the bias state of the second pixel circuit 120; the voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, wherein V1≠V2.

[0095] In the present application, since two independent bias adjustment signals are required, which are transmitted to the display area through the first bias adjustment signal bus 201 and the second bias adjustment signal bus 202 respectively, two different output ports are set on the integrated chip, one of which is used to output the first bias adjustment signal and the other is used to output the second bias adjustment signal, thereby meeting the signal transmission requirements in any of the aforementioned embodiments.

[0096] Yet another aspect of the present application provides a display device, comprising the display panel according to any of the aforementioned embodiments.

[0097] refer to Figure 9 , Figure 9 This is a schematic diagram of a display device provided in an embodiment of the present application, wherein the display device 600 includes a display panel 100, and the display panel 100 is the display panel in any of the aforementioned embodiments. The display device can be a mobile phone, a television, a laptop computer, a flat-panel display device, a smart wearable display device, etc., and this application does not make any special limitations.

[0098] Optionally, when the display device provided herein is an under-screen camera display device, the second display area 102 includes a transmissive area 500. The operation of the second display area 102 includes a light-transmitting phase. At least during the light-transmitting phase, the transmissive area 500 allows light to pass through the display panel. The display device 600 includes a functional device, which is arranged corresponding to the transmissive area 500 of the second display area 102. During the light-transmitting phase, the functional device can transmit and receive light through the transmissive area. Optionally, the functional device is a camera. As previously described, by placing the camera below the display area with the transmissive area, a full-screen function can be achieved.

[0099] Through the above description, the display panel, integrated chip and display device provided by the present application, wherein the display panel 100 includes a first display area 101 and a second display area 102, a first pixel circuit 110 for providing a driving current for the light-emitting element of the first display area 101 receives a first bias adjustment signal, and a second pixel circuit 120 for providing a driving current for the light-emitting element of the second display area 102 receives a second bias adjustment signal, and a voltage value of the first bias adjustment signal is different from a voltage value of the second bias adjustment signal. Due to various factors such as the different width-to-length ratios of the driving transistors of the pixel circuits in the first display area 101 and the second display area 102, the different numbers of light-emitting elements driven by the pixel circuits, the different distribution densities, driving currents, and light-emitting areas of the light-emitting elements, the different data refresh frequencies of the pixel circuits, and the different luminous brightness of the light-emitting elements, there are differences in the bias states of the pixel circuits in the first display area 101 and the second display area 102. Therefore, in the present application, by setting the bias adjustment signals received by the first display area 101 and the second display area 102 to be different, the bias states of the first display area 101 and the second display area 102 are adjusted in a targeted manner, so that the first display area 101 and the second display area 102 can achieve better display effects while ensuring their respective display functions.

[0100] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: a first display area and a second display area; A pixel circuit, the pixel circuit comprising a data writing module, a driving module and a bias adjustment module, the driving module comprising a driving transistor, the data writing module being used to provide a data signal to the driving transistor, the pixel circuit comprising a first pixel circuit and a second pixel circuit, the driving module of the first pixel circuit being used to provide a driving current to the light-emitting element of the first display area, and the driving module of the second pixel circuit being used to provide a driving current to the light-emitting element of the second display area; The pixel circuit receives a bias adjustment signal, the bias adjustment module is used to provide the bias adjustment signal for the driving transistor, the bias adjustment signal includes a first bias adjustment signal and a second bias adjustment signal, the first pixel circuit receives the first bias adjustment signal to adjust the bias state of the first pixel circuit, and the second pixel circuit receives the second bias adjustment signal to adjust the bias state of the second pixel circuit; wherein, The voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, wherein V1≠V2.

2. The display panel according to claim 1, characterized in that: The pixel circuit also includes a compensation module; The data writing module is connected to the first electrode of the driving transistor; The bias adjustment module is connected to the first electrode or the second electrode of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor, and is used to compensate for the threshold voltage of the driving transistor.

3. The display panel according to claim 1, characterized in that: The working process of the pixel circuit includes a data writing frame and a holding frame, and the data writing frame includes a first bias adjustment stage. In the first bias adjustment stage, the voltage value of the first bias adjustment signal is V11, and the voltage value of the second bias adjustment signal is V12, wherein V11≠V12.

4. The display panel according to claim 1, characterized in that: The working process of the pixel circuit includes a data writing frame and a holding frame, and the holding frame includes a second bias adjustment stage. In the second bias adjustment stage, the voltage value of the first bias adjustment signal is V21, and the voltage value of the second bias adjustment signal is V22, wherein V21≠V22.

5. The display panel according to claim 1, characterized in that: The working process of the pixel circuit includes a data writing frame and a holding frame, the data writing frame includes a first bias adjustment stage, the holding frame includes a second bias adjustment stage, in the first bias adjustment stage, the voltage value of the first bias adjustment signal is V11, the voltage value of the second bias adjustment signal is V12, in the second bias adjustment stage, the voltage value of the first bias adjustment signal is V21, the voltage value of the second bias adjustment signal is V22; wherein, |V11-V12|+|V21-V22|≠0.

6. The display panel according to claim 5, characterized in that: V11≠V12, V21=V22; or, V11=V12, V21≠V22.

7. The display panel according to claim 5, characterized in that: |V11-V12|=|V21-V22|.

8. The display panel according to claim 5, characterized in that: |V11-V12|>|V21-V22|, or, |V11-V12|<|V21-V22|.

9. The display panel according to claim 5, characterized in that: (V11-V12)×(V21-V22)>0.

10. The display panel according to claim 5, characterized in that: (V11-V12)×(V21-V22)<0.

11. The display panel according to claim 1, characterized in that: In the first pixel circuit, the first pixel circuit providing a driving current for the light emitting element with a first light emitting color comprises a first driving transistor, and in the second pixel circuit, the second pixel circuit providing a driving current for the light emitting element with a first light emitting color comprises a second driving transistor; The width-to-length ratio of the channel region of the first driving transistor is R11, and the width-to-length ratio of the channel region of the second driving transistor is R12, wherein R11≠R12.

12. The display panel according to claim 11, characterized in that: R11<R12, and V1>V2.

13. The display panel according to claim 11, characterized in that: R11<R12, and V1<V2.

14. The display panel according to claim 11, characterized in that: R11 / R12<V2 / V1.

15. The display panel according to claim 11, characterized in that: The working process of the pixel circuit includes a data writing frame and a holding frame, the data writing frame includes a first bias adjustment stage, the holding frame includes a second bias adjustment stage, in the first bias adjustment stage, the voltage value of the first bias adjustment signal is V11, the voltage value of the second bias adjustment signal is V12, in the second bias adjustment stage, the voltage value of the first bias adjustment signal is V21, the voltage value of the second bias adjustment signal is V22; wherein, R11 / R12<V12 / V11, and / or, R11 / R12<V22 / V21.

16. The display panel according to claim 1, characterized in that: When the first pixel circuit and the second pixel circuit receive the same data signal, the driving current generated by the first pixel circuit is I1, and the driving current generated by the second pixel circuit is I2, wherein I1≠I2.

17. The display panel according to claim 16, characterized in that: I1<I2, and V1>V2.

18. The display panel according to claim 16, characterized in that: I1<I2, and V1<V2.

19. The display panel according to claim 1, characterized in that: The distribution density of the light emitting elements in at least a part of the first display area is ρ1, and the distribution density of the light emitting elements in at least a part of the second display area is ρ2, wherein ρ1≠ρ2.

20. The display panel according to claim 19, characterized in that: ρ1<ρ2, and V1<V2.

21. The display panel according to claim 19, characterized in that: ρ1<ρ2, and V1>V2.

22. The display panel according to claim 19, characterized in that: The light emitting area of ​​the light emitting element with the first color in the first display area is S11, and the light emitting area of ​​the light emitting element with the first color in the second display area is S12, wherein S11<S12.

23. The display panel according to claim 1, characterized in that: In the first display area, the first pixel circuit provides driving current for m1 light-emitting elements, and in the second display area, the second pixel circuit provides driving current for m2 light-emitting elements; wherein, m1≥1, m2≥1, and m1<m2.

24. The display panel according to claim 23, characterized in that: V1<V2, or, V1>V2.

25. The display panel according to claim 23, characterized in that: m1=1, m2=2 or m2=3 or m2=4.

26. The display panel according to claim 1, characterized in that: The display panel includes a first bias adjustment signal line and a first bias adjustment signal bus, and a second bias adjustment signal line and a second bias adjustment signal bus, the first bias adjustment signal line is connected between the first pixel circuit and the first bias adjustment signal bus, and the second bias adjustment signal line is connected between the second pixel circuit and the second bias adjustment signal bus; The first bias adjustment signal bus and the second bias adjustment signal bus are located in at least one of a first side frame and a second side frame that are oppositely disposed on the display panel.

27. The display panel according to claim 26, characterized in that: The first bias adjustment signal bus and the second bias adjustment signal bus are located in the same film layer, and the first bias adjustment signal line and the second bias adjustment signal line are located in different film layers; or, The first bias adjustment signal bus and the second bias adjustment signal bus are located in different film layers, and the first bias adjustment signal line and the second bias adjustment signal line are located in the same film layer; or, The first bias adjustment signal bus and the second bias adjustment signal bus are located in the same film layer, and the first bias adjustment signal line and the second bias adjustment signal line are located in the same film layer.

28. The display panel according to claim 26, characterized in that: The first bias adjustment signal bus is connected to the first bias adjustment signal line through a transition line, and the transition line and at least one of the first bias adjustment signal bus and the first bias adjustment signal line are located in a different film layer; and / or, The second bias adjustment signal bus is connected to the second bias adjustment signal line through a transition line, and the transition line and at least one of the second bias adjustment signal bus and the second bias adjustment signal line are located in different film layers.

29. The display panel according to claim 26, characterized in that: The first bias adjustment signal bus and the second bias adjustment signal bus extend in the same direction, and the first bias adjustment signal line and the second bias adjustment signal line extend in the same direction.

30. The display panel according to claim 26, characterized in that: The first bias adjustment signal bus is located in at least one of a first side frame and a second side frame of the display panel; The second bias adjustment signal bus is at least located at the first side frame and the third side frame of the display panel, and the third side frame is arranged adjacent to the first side frame; wherein, The first bias adjustment signal line is connected to the first bias adjustment signal bus after extending along a first direction, and the second bias adjustment signal line is connected to the second bias adjustment signal bus after extending along a second direction; The first direction intersects the second direction.

31. The display panel according to claim 26, characterized in that: The width of the first bias adjustment signal line is W1, and the width of the second bias adjustment signal line is W2, wherein W1≠W2.

32. The display panel according to claim 26, characterized in that: The width of the first bias adjustment signal bus is W11, and the width of the second bias adjustment signal bus is W22, wherein W11≠W22.

33. The display panel according to claim 1, characterized in that: The second display area includes a transmission area, and the operation process of the second display area includes a light transmission stage. At least in the light transmission stage, the transmission area allows light to pass through the display panel.

34. The display panel according to claim 1, characterized in that: In at least one stage of operation of the display panel, a data refresh frequency in the first display area is F1, and a data refresh frequency in the second display area is F2, wherein F1≠F2.

35. The display panel according to claim 1, characterized in that: F1>F2, and V1<V2.

36. The display panel according to claim 1, characterized in that: In at least one stage of operation of the display panel, the light-emitting elements in the first display area operate in a first mode, and the light-emitting elements in the second display area operate in a second mode, and the light-emitting brightness of the light-emitting elements in the first mode is greater than the light-emitting brightness of the light-emitting elements in the second mode.

37. An integrated chip for providing a bias adjustment signal for the display panel according to any one of claims 1 to 36, characterized in that: The integrated chip provides the first bias adjustment signal for the first pixel circuit to adjust the bias state of the first pixel circuit, and the integrated chip provides the second bias adjustment signal for the second pixel circuit to adjust the bias state of the second pixel circuit; wherein, The voltage value of the first bias adjustment signal is V1, and the voltage value of the second bias adjustment signal is V2, wherein V1≠V2.

38. A display device, characterized in that: A display panel comprising any one of claims 1-36.

39. The display device according to claim 38, characterized in that The second display area includes a transmission area, and the operation process of the second display area includes a light transmission stage. At least in the light transmission stage, the transmission area allows light to pass through the display panel; The display device comprises a functional device, and the functional device is arranged corresponding to the transmission area of ​​the second display area. In the light transmission stage, the functional device can emit and receive light through the transmission area.

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