SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving method and system for quantitatively inhibiting voltage overshoot peak

Abstract

The invention provides a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving method and system for quantitatively suppressing a voltage overshoot peak. The method comprises the following steps of: reducing drain-source voltage of a SiC MOSFET to a voltage range which can be detected by a post-stage circuit; the output of the degraded drain-source voltage is detected, and the overshoot peak value of the drain-source voltage is maintained and output; sampling the output drain-source voltage overshoot peak value; a pulse signal is output according to the current drop stage of the turn-off of the drain-source voltage identification device; operating the PI control module to obtain an output current value of the voltage-controlled current source, and outputting a voltage value corresponding to the output current of the voltage-controlled current source; a corresponding voltage value is used as input, a pulse signal triggers a voltage-controlled current source to output, extra driving current is injected into a grid electrode of the SiC MOSFET, and voltage overshoot peaks are regulated and controlled. According to the invention, the closed-loop control of the voltage overshoot peak value is realized, the voltage overshoot peak value is quantitatively suppressed, and the reliability and efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics and electric drive, and in particular to a SiC MOSFET driving method and system for quantitatively suppressing voltage overshoot spikes. Background Art

[0002] Wide bandgap power semiconductor devices represented by silicon carbide metal-oxide semiconductor field effect transistors (SiC MOSFETs) have excellent performance. Compared with traditional silicon-based devices, they have faster switching speeds, lower on-resistances, and higher operating temperatures. They have been widely used in electric vehicles, new energy generation, and aerospace. Their high switching speeds effectively reduce switching losses, but they also bring some negative effects. Since device packaging and printed circuit board (PCB) layouts inevitably introduce parasitic inductance into the power loop, severe voltage overshoots will occur when the SiC MOSFET is turned off, and the voltage overshoot peak is positively correlated with the load current. It is extremely serious under high load current conditions and may cause overvoltage damage to the device. This will seriously reduce the operating reliability of the SiC MOSFET.

[0003] There are two main methods to suppress the turn-off voltage overshoot spike of SiC MOSFET. One is to add a passive suppression method such as a buffer circuit or a damping circuit. The circuit structure of this method is relatively simple, but this method requires different buffer circuit parameters to be designed under different working conditions (such as input voltage, load current level, circuit parasitic parameters, etc.), which makes the suppression effect relatively limited under variable load current conditions. In addition, passive devices are often directly connected to the device drain source or both ends of the bridge arm, which faces frequent high voltage shocks, and high reliability design is also a challenge. The second method is to use an active gate drive circuit. This method can achieve flexible control of dv / dt, di / dt, current overshoot, voltage overshoot, etc. during the device switching process by dynamically adjusting the device drive parameters, which is an effective way to improve the performance of SiC MOSFET. However, in terms of the turn-off voltage overshoot suppression of SiC MOSFET, the existing active gate drive circuit often only has a fixed voltage overshoot suppression effect, and cannot achieve quantitative suppression of voltage overshoot spikes. In addition, most existing active gate drive circuits can only operate under specific input and output conditions, and are still insufficient under variable load conditions, causing additional switching losses under low load currents.

[0004] Nowadays, SiC MOSFET design and manufacturing technology are developing rapidly, and there is an urgent need for its high reliability and high efficiency application in converters. Therefore, it is of great significance to quantitatively suppress the SiC MOSFET turn-off voltage overshoot peak, optimize the switching loss under low load, suppress the voltage overshoot peak under high load, and improve the device application reliability and work efficiency under actual operating conditions. Summary of the invention

[0005] The purpose of the present invention is to provide a SiC MOSFET driving method and system with quantitative voltage overshoot spike suppression, which is used to achieve quantitative voltage overshoot spike suppression, reduce switching losses under low current load, improve system efficiency, and quantitatively suppress voltage overshoot spikes under high current load to improve device operation reliability.

[0006] A SiC MOSFET driving method for quantitatively suppressing voltage overshoot spikes, wherein the gate of the SiC MOSFET is connected to the output end of a voltage-controlled current source, and the specific steps of the method are as follows:

[0007] S1: Reduce the drain-source voltage of SiC MOSFET to a voltage range that can be detected by the subsequent circuit;

[0008] S2: Detect the output of the drain-source voltage after degradation, maintain the overshoot peak value of the drain-source voltage and output it;

[0009] S3: sampling the drain-source voltage overshoot peak value output in step S2;

[0010] S4: Identify the current drop phase of device shutdown according to the drain-source voltage and output a pulse signal;

[0011] S5: running the PI control module to obtain the output current value of the voltage-controlled current source, and outputting a voltage value corresponding to the output current of the voltage-controlled current source;

[0012] S6: Using the output voltage value in step S5 as input, trigger the voltage-controlled current source output with a pulse signal, inject additional drive current into the SiCMOSFET gate, and regulate the voltage overshoot spike.

[0013] Optionally, the specific steps of outputting the pulse signal in step S4 are:

[0014] S4.1: Compare the stepped-down drain-source voltage with the first reference voltage, output a pulse signal, latch the first rising edge of the pulse signal, and output a start signal;

[0015] S4.2: Input the drain-source voltage of the SiC MOSFET into the differential circuit to obtain a differential signal, compare the differential signal with the second reference voltage, output a pulse signal and invert it, latch the first rising edge of the signal, and output an end signal;

[0016] S4.3: Perform an XOR logic operation on the start signal and the end signal to generate a trigger signal.

[0017] Optionally, the specific steps in step S5 are:

[0018] S5.1: Taking the SiC MOSFET turn-off voltage overshoot peak value sampled in step S2 as the feedback input of the PI control module;

[0019] S5.2: Compare the feedback input of the PI control module with the preset upper limit value of the overshoot peak value of the PI control module, and perform a PI control algorithm operation once in each switching cycle;

[0020] S5.3: Output the calculated value of the PI control module in the form of voltage, and output the voltage-controlled reference voltage.

[0021] Optionally, the specific method for regulating the voltage overshoot peak in step S6 is:

[0022] When the drain current of the SiC MOSFET is turned off and decreases, the trigger signal controls the voltage-controlled reference voltage to be input into the voltage-controlled current source, and the output current of the voltage-controlled current source is injected into the gate of the SiC MOSFET to adjust the turn-off voltage overshoot peak value of the SiC MOSFET. Combined with step S5, the turn-off voltage overshoot peak value of the SiC MOSFET is closed-loop regulated.

[0023] A SiC MOSFET driving system with quantitative voltage overshoot spike suppression, comprising a voltage-controlled current source, an RC voltage divider circuit, a peak holding circuit, a phase identification circuit, a microcontroller and a SiC MOSFET;

[0024] The output end of the voltage-controlled current source is connected to the gate of the SiC MOSFET, the voltage-controlled current source is connected to the microcontroller through the multiplexer S1, the drain of the SiC MOSFET is connected to the input end of the RC voltage divider circuit, and the output end of the RC voltage divider circuit is connected to the peak holding circuit and the stage identification circuit;

[0025] The microcontroller is used to collect the output of the peak holding circuit and calculate the output voltage value. The voltage-controlled current source takes the output voltage value of the microcontroller as input and the pulse signal of the stage recognition circuit as a trigger signal and outputs, injects additional drive current into the SiCMOSFET gate, and regulates the voltage overshoot peak.

[0026] Optionally, the voltage-controlled current source further includes a reference current source, a current mirror circuit and a power supply V CC ;

[0027] One end of the reference current source is connected to the microcontroller through a multiplexer S1, and the reference current source is connected to a current mirror circuit, and the input end of the current mirror circuit is connected to a power supply V CC The output end of the current mirror circuit is connected to the gate of the SiC MOSFET.

[0028] Optionally, the first RC parallel module and the second RC parallel module are connected at one end;

[0029] The other end of the first RC parallel module is connected to the drain of the SiC MOSFET, the other end of the second RC parallel module is grounded, and the connection end of the first RC parallel module and the second RC parallel module is connected to the peak holding circuit and the stage identification circuit.

[0030] Optionally, the peak holding circuit includes a transconductance operational amplifier, a charging diode, a clamping diode, a reset MOS tube, a holding capacitor and a high-bandwidth operational amplifier;

[0031] The non-inverting input terminal of the transconductance operational amplifier is connected to the output terminal of the RC voltage divider circuit, the inverting input terminal of the transconductance operational amplifier is connected to the inverting input terminal of the high-bandwidth operational amplifier, and the output terminal of the transconductance operational amplifier is connected to the anode of the charging diode and the cathode of the clamping diode;

[0032] The cathode of the charging diode is connected to one end of the holding capacitor and the drain of the reset MOS tube, and then connected to the same-direction input end of the high-bandwidth operational amplifier. The source of the reset MOS tube, the other end of the holding capacitor and the anode of the clamping diode are all grounded. The output end of the high-bandwidth operational amplifier is connected to the microcontroller.

[0033] Optionally, the stage compensation circuit includes a differential resistor, a differential capacitor, a first comparator, a second comparator, an inverter, a first D flip-flop, a second D flip-flop and an XOR gate module;

[0034] The non-inverting input terminal of the first comparator is connected to the RC voltage divider network, the inverting input terminal of the first comparator is connected to the first reference voltage, the output terminal of the first comparator is connected to the CLK pin of the first D flip-flop, and the output terminal of the first D flip-flop is connected to the first input terminal of the XOR gate module;

[0035] The differential resistor is connected in series with the differential capacitor, the other end of the differential resistor is grounded, the other end of the differential capacitor is connected to the drain of the SiC MOSFET, the connection point of the differential resistor and the differential capacitor is connected to the non-inverting input of the second comparator, the inverting input of the second comparator is connected to the second reference voltage, the output of the second comparator is connected to the input of the inverter, the output of the inverter is connected to the CLK pin of the second D flip-flop, the output of the second D flip-flop is connected to the second input of the XOR gate module, and the CLR pins of the first D flip-flop and the second D flip-flop are connected to the drive signal.

[0036] Optionally, the microcontroller includes an ADC module, a PI control module and a DAC module;

[0037] The ADC module is used to sample the drain-source voltage overshoot peak value output by the peak holding circuit, the PI control module is used to calculate the output current value of the voltage-controlled current source, and the DAC module is used to output a voltage value corresponding to the output current of the voltage-controlled current source.

[0038] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0039] 1. The present application realizes closed-loop control of the voltage overshoot peak value and quantitatively suppresses the voltage overshoot peak value. Compared with the existing methods, the invention has high control flexibility, reduces switching loss under low load current conditions, quantitatively suppresses the voltage overshoot peak value under high load current, avoids SiC MOSFET overvoltage breakdown, and improves reliability and efficiency.

[0040] 2. The present application extracts the SiC MOSFET turn-off voltage overshoot peak value through a peak hold circuit in the current switching cycle; then samples it through the ADC module of the microcontroller; then uses the ADC module sampling value as the feedback input of the PI control algorithm running inside the microcontroller, and performs an operation with the voltage overshoot control target preset inside the microcontroller as the set value; then outputs the calculated output current value of the voltage-controlled current source injected into the SiC MOSFET gate in the next switching cycle through the DAC module of the microcontroller; then identifies the drain current falling phase of the SiC MOSFET through the phase identification circuit in the next switching cycle, triggers the voltage-controlled current mirror to work in this phase to inject the output current value of the voltage-controlled current source into the SiC MOSFET gate, and controls the voltage overshoot peak value.

[0041] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings of the present invention are as follows.

[0043] Figure 1 4 is a circuit framework diagram of the SiC MOSFET driving system of the present invention.

[0044] Figure 2 4 is a circuit structure diagram of the voltage divider circuit of the present invention.

[0045] Figure 3 4 is a circuit structure diagram of the peak holding circuit of the present invention.

[0046] Figure 4 This is a circuit diagram of the stage identification circuit of the present invention.

[0047] Figure 5 4 is a circuit structure diagram of the voltage-controlled current source of the present invention.

[0048] Figure 6 The current i of the present invention ctrl Simplified diagram of the circuit when injecting into the gate of a SiC MOSFET.

[0049] Figure 7 This is a diagram of key signals output by each circuit of the present invention.

[0050] Figure 8 Schematic diagram of delay time compensation of the present invention.

[0051] Fig. 9 This is a comparison chart of the turn-off losses of the present invention and the method of increasing the gate resistance.

[0052] Fig.10 This is a diagram of the quantitative suppression experiment of the turn-off voltage overshoot peak of SiC MOSFET of the present invention. DETAILED DESCRIPTION

[0053] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0054] Embodiment 1:

[0055] like Figure 1 A SiC MOSFET driving system for quantitatively suppressing voltage overshoot spikes shown includes a voltage-controlled current source, an RC voltage divider circuit, a peak holding circuit, a phase identification circuit, and a microcontroller;

[0056] The output end of the voltage-controlled current source is connected to the gate of the SiC MOSFET, the voltage-controlled current source is connected to the microcontroller through the multiplexer S1, the drain of the SiC MOSFET is connected to the input end of the RC voltage divider circuit, and the output end of the RC voltage divider circuit is connected to the peak holding circuit and the stage identification circuit;

[0057] The microcontroller is used to collect the output of the peak holding circuit and calculate the output voltage value. The voltage-controlled current source takes the output voltage value of the microcontroller as input and the pulse signal of the stage recognition circuit as a trigger signal and outputs, injects additional drive current into the SiCMOSFET gate, and regulates the voltage overshoot peak.

[0058] like Figure 5 As shown, the voltage-controlled current source includes an operational amplifier OP3, a multiplexer S1, a feedback resistor R f , N-type MOS tube Q2, P-type MOS tube Q3, P-type MOS tube Q4, P-type MOS tube Q5 and P-type MOS tube Q6; the feedback resistor R fOne end of the feedback resistor R is connected in series with the source of the N-type MOS tube Q2. f The other end of the operational amplifier OP3 is grounded, the output end of the operational amplifier OP3 is connected to the gate of the N-type MOS tube Q2, and the inverting input end of the operational amplifier OP3 is connected to the feedback resistor R f One end of the multiplexer S1 is connected to the in-phase input end of the operational amplifier OP3, and the other end of the multiplexer S1 is connected to the microcontroller;

[0059] The gate of the P-type MOS transistor Q3 is connected to the gate of the P-type MOS transistor Q4, and the drains of the P-type MOS transistor Q3 and the P-type MOS transistor Q4 are connected to the power supply V CC The gate of the P-type MOS tube Q5 is connected to the gate of the P-type MOS tube Q6, the source of the P-type MOS tube Q5 is connected to the drain of the N-type MOS tube Q2, the drain of the P-type MOS tube Q5 is connected to the source of the P-type MOS tube Q3, the drain of the P-type MOS tube Q6 is connected to the source of the P-type MOS tube Q4, and the source of the P-type MOS tube Q6 is connected to the gate of the SiC MOSFET.

[0060] In this embodiment, the operational amplifier OP3, the feedback resistor R f , N-type MOS tube Q2 constitute a reference current source, and P-type MOS tube Q3, P-type MOS tube Q4, P-type MOS tube Q5 and P-type MOS tube Q6 constitute a current mirror circuit.

[0061] like Figure 2 As shown, the first RC parallel module and the second RC parallel module are connected at one end; the first RC parallel module includes a voltage-dividing resistor R1 and a voltage-dividing capacitor C1, and the second RC parallel module includes a voltage-dividing resistor R2 and a voltage-dividing capacitor C2;

[0062] The other end of the first RC parallel module is connected to the drain of the SiC MOSFET, the other end of the second RC parallel module is grounded, and the connection end of the first RC parallel module and the second RC parallel module is connected to the peak holding circuit and the stage identification circuit.

[0063] like Figure 3 As shown, the peak holding circuit includes a transconductance operational amplifier OP1, a charging diode D1, a clamping diode D2, a reset MOS tube Q1, and a holding capacitor C P and high bandwidth operational amplifier OP2;

[0064] The non-inverting input terminal of the transconductance operational amplifier OP1 is connected to the connection terminal of the first parallel module and the second parallel module, the inverting input terminal of the transconductance operational amplifier OP1 is connected to the inverting input terminal of the high-bandwidth operational amplifier OP2, and the output terminal of the transconductance operational amplifier OP1 is connected to the anode of the charging diode D1 and the cathode of the clamping diode D2;

[0065] The cathode of the charging diode D1 is connected to the holding capacitor C P The drain of the reset MOS tube Q1 is connected to the same-direction input terminal of the high-bandwidth operational amplifier OP2, and the source of the reset MOS tube Q1 and the holding capacitor C P The other end of and the anode of the clamping diode D2 are grounded, and the output end of the high bandwidth operational amplifier OP2 is connected to the microcontroller.

[0066] like Figure 4 As shown, the phase identification circuit includes a differential resistor R3, a differential capacitor C3, a first comparator, a second comparator, an inverter INV1, a first D flip-flop, a second D flip-flop and an XOR gate module XOR1; the differential resistor R3 is connected in series with the differential capacitor C3, the other end of the differential resistor R3 is grounded, and the other end of the differential capacitor C3 is connected to the drain of the SiC MOSFET;

[0067] The non-inverting input terminal of the first comparator is connected to the RC voltage divider network, and the inverting input terminal of the first comparator is connected to the first reference voltage V ref1 The output end of the first comparator is connected to the CLK pin of the first D flip-flop, and the output end of the first D flip-flop is connected to the first input end of the XOR gate module XOR1; the connection point of the differential resistor R3 and the differential capacitor C3 is connected to the non-inverting input end of the second comparator, and the inverting input end of the second comparator is connected to the second reference voltage V ref2 The output end of the second comparator is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the CLK pin of the second D flip-flop, and the output end of the second D flip-flop is connected to the second input end of the XOR gate module XOR1; the data pins D of the first D flip-flop and the second D flip-flop are connected to +5V, and the CLR pins of the first D flip-flop and the second D flip-flop are connected to the drive signal.

[0068] like Figure 1 As shown, the microcontroller includes an ADC module, a PI control module and a DAC module. The ADC module is used to sample the drain-source voltage overshoot peak value output by the peak holding circuit, the PI control module is used to calculate the output current value of the voltage-controlled current source, and the DAC module is used to output a voltage value corresponding to the output current of the voltage-controlled current source.

[0069] In this embodiment, the ADC module is used to sample the peak voltage of the low-impedance output of the high-bandwidth operational amplifier OP2. The microcontroller (MCU) uses the STM32G474CET6 of ST Company, which integrates a 12-bit ADC module. When the peak holding circuit collects the current peak voltage v ds_peak The conversion starts immediately.

[0070] Embodiment 2:

[0071] A SiC MOSFET driving method with quantitative voltage overshoot spike suppression adopts the SiC MOSFET driving system with quantitative voltage overshoot spike suppression described in Example 1, and the specific steps are as follows:

[0072] S1: Reduce the drain-source voltage of SiC MOSFET to a voltage range that can be detected by the subsequent circuit;

[0073] In this embodiment, if Figure 2 As shown in the RC voltage divider circuit, since the bus voltage of SiC MOSFET is as high as several hundred volts, it is difficult for the phase detection circuit and the peak detection circuit to detect it directly. Therefore, an RC voltage divider network is used to divide the several hundred V ds Reduce to the voltage range that the subsequent circuit can detect. In addition, in order to reduce the influence of the circuit parasitic capacitance, the voltage divider capacitors C1 and C2 are used to improve the dynamic performance of the voltage divider network. Among them, the voltage divider ratio is determined by R2 / (R1+R2), and the values ​​of the voltage divider capacitors C1 and C2 satisfy the following relationship:

[0074]

[0075] S2: Detect the output of the drain-source voltage after degradation, maintain the overshoot peak value of the drain-source voltage and output it;

[0076] In this embodiment, if Figure 3 The peak hold circuit shown in the figure has a drain-source voltage v ds The change is very fast. If the peak value is detected directly, an ADC conversion chip with very fast sampling speed is required, and the sampled data needs to be processed, which is complex to implement and has low accuracy. The peak holding circuit can keep v ds The overshoot peak value can be converted using a conventional ADC converter. In this embodiment, when the input voltage v of the transconductance operational amplifier OP1 is ds_d Greater than the peak voltage v ds_peak When the transconductance operational amplifier OP1 outputs current to the holding capacitor C P Charging, input voltage v ds_d After reaching the maximum value, it starts to decrease. At this time, the charging diode D1 is cut off, and the capacitor C P The voltage remains unchanged, and the large input impedance of the high-bandwidth operational amplifier OP2 reduces the holding capacitor Cp Voltage drop rate. When the input voltage v ds_d Less than the peak voltage v ds_peak When the reverse recovery current of the charging diode D1 is too large, the clamping diode D2 provides a current path for the transconductance operational amplifier OP1, clamping the output of the transconductance operational amplifier OP1 to 0V. In addition, to prevent the excessive reverse recovery current of the charging diode D1 from causing the holding capacitor C p The voltage drops significantly, and the charging diode D1 uses a Schottky diode. After the ADC sampling is completed, the MOS tube Q1 is reset to hold the capacitor C p Discharge, so that the holding capacitor C p In the next cycle, the drain-source voltage v can be maintained normally ds_d peak value.

[0077] S3: sampling the drain-source voltage overshoot peak value output in step S2;

[0078] In this embodiment, the drain voltage v attenuated by the RC voltage divider circuit is used. ds As the input source, a slowly rising ramp signal is obtained through an RC low-pass filter circuit. After a hysteresis comparator, a reference voltage v is set. ds_peak_lim Compared with the slowly rising ramp signal, at v ds A rising edge is output after a fixed delay time after the start of the rise, triggering the ADC module to sample the peak hold circuit output.

[0079] S4: Identify the current drop phase of the device shutdown according to the drain-source voltage and output a pulse signal. The specific steps are as follows:

[0080] S4.1: The output of the RC voltage divider circuit is compared with the first reference voltage V through a high-speed hysteresis comparator. ref1 Compare and output a pulse signal, the first D flip-flop latches the first rising edge of the pulse signal and outputs a start signal;

[0081] In this embodiment, the current and voltage waveforms and key signals when the device is turned off are as follows: Figure 7 As shown, the drain-source voltage v ds First rise to the busbar flow i d Then it starts to decrease, and the first comparator is used to identify the bus current i d The reference voltage V of the first comparator starts to decrease at time t3. ref1 The theoretical value is V DC , when v ds_d Rising to V ref1 When the first comparator outputs a high level, to avoid v ds_d The oscillation causes the level of the first comparator to jump repeatedly, and the first rising edge of the output of the first comparator is synchronized by using the first D flip-flop, and finally a stable trigger signal is output.

[0082] S4.2: Set the SiC MOSFET drain-source voltage v ds The differential signal of the drain-source voltage is input into the differential circuit of the phase identification circuit, and the differential signal of the drain-source voltage is obtained. ref2 Compare and output a pulse signal; then, invert it through the inverter, and finally latch the first rising edge of the signal through the second D flip-flop, and output an end signal;

[0083] In this embodiment, a differential circuit composed of R3 and C3 is used to ds Differentiate, when the drain-source voltage v ds When it rises to its peak value, v ds_dif drops to zero, and the current i is no longer controlled. d Falling speed. V ref2 Set to 0.1V to configure the second comparator as a zero-crossing comparator. ds_dif When it drops to zero, it outputs a negative edge signal and then inverts through inverter INV1. ds_dif The oscillation causes the output of the inverter INV1 to jump repeatedly, and the second D flip-flop is used to synchronize the first rising edge of the inverter INV1. ds_dif for:

[0084]

[0085] S4.3: Use the XOR gate module to perform XOR logic operation on the start signal and the end signal, and finally generate the trigger signal v trig , indicating the drain current falling stage of SiC MOSFET, during which the trigger signal v trig As the control signal of the voltage-controlled current source, the current mirror circuit outputs a driving current to the gate of the SiC MOSFET.

[0086] In this embodiment, the trigger signal v trig Triggering the voltage-controlled current source to inject additional gate current during the SiC MOSFET drain current drop phase can reduce switching losses. Due to the delay in the actual circuit. Figure 8 As shown, when positioning the moment t3, the reference voltage V of the first comparator needs to be appropriately reduced. ref1 At t'3 trigger, V ref1 The value of can be calculated as follows:

[0087]

[0088] In addition, since there is a delay of about 10ns from the second comparator to the current mirror output when the drain-source voltage rises to its peak value, i ctrl The effective interval lasts exactly until i dThe decline phase ends even longer, and i d After the descent phase ends d is 0A, so i ctrl in i d Continuing output after the falling phase ends will not increase device loss. ref2 No special design required.

[0089] S5: running the PI control module to obtain the output current value of the voltage-controlled current source, and outputting a voltage value corresponding to the output current of the voltage-controlled current source;

[0090] S5.1: The SiC MOSFET turn-off voltage overshoot peak value sampled by the ADC module is used as the feedback input of the PI control module;

[0091] S5.2: The feedback input of the PI control module is compared with the preset upper limit value V of the overshoot peak value of the PI control module. ds_peak_lim For comparison, the PI control algorithm operation is performed once in each switching cycle;

[0092] S5.3: The calculated value of the PI control module is output in the form of voltage through the DAC module of the microcontroller, and the voltage control reference voltage v is output. ctrl .

[0093] In this embodiment, the DAC module of the microcontroller MCU updates v ctrl (i+1) value, controls the output current i of the current mirror circuit ctrl The size of the drain-source voltage is finally controlled by the overshoot peak value.

[0094] S6: Using the output voltage value in step S5 as input, trigger the voltage-controlled current source output with a pulse signal, inject additional drive current into the SiCMOSFET gate, and regulate the voltage overshoot spike.

[0095] In this embodiment, the DAC module of the microcontroller outputs the calculated value of the PI control algorithm in the form of voltage before the device is turned off. When the drain current of the SiC MOSFET is turned off and decreases, the trigger signal controls the voltage-controlled reference voltage to be input to the voltage-controlled current source, and the output current of the voltage-controlled current source is injected into the gate of the SiC MOSFET to adjust the overshoot peak value of the SiC MOSFET turn-off voltage, and the overshoot peak value of the SiC MOSFET turn-off voltage is closed-loop regulated in combination with step S5.

[0096] In this embodiment, if Figure 5 The voltage-controlled current source circuit shown, OP3, Q2 and R f The reference current source is formed, Q3~Q6 form a current mirror circuit, and the reference current i ref for:

[0097]

[0098] The cascode structure is used to increase the output impedance of the current mirror and provide a stable I when the gate-source voltage changes rapidly. ctrl , at this time i ctrl with i ref Approximately equal.

[0099] When in i d In the falling phase, the current i ctrl When the gate is injected, the SiC MOSFET and the proposed circuit can be simplified to Figure 6 The gate-source voltage of SiC MOSFET is v gs for:

[0100]

[0101] τ is the RC constant of the SiC MOSFET gate:

[0102] τ=R g C iss

[0103] This stage d It can be approximately calculated by the following formula:

[0104]

[0105] d d The expression of / dt can be further derived as:

[0106]

[0107] The SiC MOSFET turn-off voltage overshoot peak is calculated by the following formula:

[0108]

[0109] Therefore, the present invention controls i ctrl The overshoot peak value of the turn-off voltage of the SiC MOSFET is adjusted, and a closed-loop control system is formed in combination with step S5 to effectively control the overshoot peak value of the turn-off voltage of the SiC MOSFET.

[0110] S7: Experiment and simulation: Fig. 9 As shown in the figure, under the test of 600V / 40A, the peak value of SiC MOSFET turn-off voltage overshoot is suppressed from 868V to 764V. Compared with the traditional method of increasing gate resistance, the turn-off loss is reduced by 41.23%, and the turn-off delay time is greatly reduced. In addition, Fig.10The invention can quantitatively suppress the SiC MOSFET turn-off voltage overshoot peak under 800V voltage and variable load current conditions. Fig.10 (a) shows that under the traditional drive, as the load current increases, the voltage overshoot peak rises to 1060V. Fig.10 (b) shows that under the present invention, the voltage overshoot peak is quantitatively suppressed to 950V.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A SiC MOSFET driving method with quantitative voltage overshoot spike suppression, characterized in that: The gate of the SiC MOSFET is connected to the output terminal of the voltage-controlled current source. The specific steps of the method are as follows: S1: Reduce the drain-source voltage of SiC MOSFET to a voltage range that can be detected by the subsequent circuit; S2: Detect the output of the drain-source voltage after degradation, maintain the overshoot peak value of the drain-source voltage and output it; S3: sampling the drain-source voltage overshoot peak value output in step S2; S4: Identify the current drop phase of device shutdown according to the drain-source voltage and output a pulse signal; S5: running the PI control module to obtain the output current value of the voltage-controlled current source, and outputting a voltage value corresponding to the output current of the voltage-controlled current source; S6: Using the output voltage value in step S5 as input, trigger the voltage-controlled current source output with a pulse signal, inject additional drive current into the SiCMOSFET gate, and regulate the voltage overshoot spike.

2. The SiC MOSFET driving method for quantitatively suppressing voltage overshoot spikes according to claim 1, characterized in that: The specific steps of outputting the pulse signal in step S4 are: S4.1: Compare the stepped-down drain-source voltage with the first reference voltage, output a pulse signal, latch the first rising edge of the pulse signal, and output a start signal; S4.2: Input the drain-source voltage of the SiC MOSFET into the differential circuit to obtain a differential signal, compare the differential signal with the second reference voltage, output a pulse signal and invert it, latch the first rising edge of the signal, and output an end signal; S4.3: Perform an XOR logic operation on the start signal and the end signal to generate a trigger signal.

3. The SiC MOSFET driving method for quantitatively suppressing voltage overshoot spikes according to claim 1, characterized in that: The specific steps in step S5 are: S5.1: Taking the SiC MOSFET turn-off voltage overshoot peak value sampled in step S2 as the feedback input of the PI control module; S5.2: Compare the feedback input of the PI control module with the preset upper limit value of the overshoot peak value of the PI control module, and perform a PI control algorithm operation once in each switching cycle; S5.3: Output the calculated value of the PI control module in the form of voltage, and output the voltage-controlled reference voltage.

4. The SiC MOSFET driving method for quantitatively suppressing voltage overshoot spikes according to claim 3, characterized in that: The specific method for regulating the voltage overshoot peak in step S6 is: When the drain current of the SiC MOSFET is turned off and decreases, the trigger signal controls the voltage-controlled reference voltage to be input into the voltage-controlled current source, and the output current of the voltage-controlled current source is injected into the gate of the SiC MOSFET to adjust the turn-off voltage overshoot peak value of the SiC MOSFET. Combined with step S5, the turn-off voltage overshoot peak value of the SiC MOSFET is closed-loop regulated.

5. A SiC MOSFET drive system with quantitative voltage overshoot spike suppression, characterized in that: It includes a voltage-controlled current source, an RC voltage divider circuit, a peak holding circuit, a phase identification circuit, a microcontroller and a SiC MOSFET; The output end of the voltage-controlled current source is connected to the gate of the SiC MOSFET, the voltage-controlled current source is connected to the microcontroller through the multiplexer S1, the drain of the SiC MOSFET is connected to the input end of the RC voltage divider circuit, and the output end of the RC voltage divider circuit is connected to the peak holding circuit and the stage identification circuit; The microcontroller is used to collect the output of the peak holding circuit and calculate the output voltage value. The voltage-controlled current source takes the output voltage value of the microcontroller as input and the pulse signal of the stage recognition circuit as a trigger signal and outputs, injects additional drive current into the SiCMOSFET gate, and regulates the voltage overshoot peak.

6. The SiC MOSFET driving system with quantitative voltage overshoot spike suppression according to claim 5, characterized in that: The voltage-controlled current source also includes a reference current source, a current mirror circuit and a power supply V CC ; One end of the reference current source is connected to the microcontroller through a multiplexer S1, and the reference current source is connected to a current mirror circuit, and the input end of the current mirror circuit is connected to a power supply V CC The output end of the current mirror circuit is connected to the gate of the SiC MOSFET.

7. The SiC MOSFET driving system with quantitative voltage overshoot spike suppression according to claim 5, characterized in that: The method comprises a first RC parallel module and a second RC parallel module connected at one end; The other end of the first RC parallel module is connected to the drain of the SiC MOSFET, the other end of the second RC parallel module is grounded, and the connection end of the first RC parallel module and the second RC parallel module is connected to the peak holding circuit and the stage identification circuit.

8. The SiC MOSFET driving system with quantitative voltage overshoot spike suppression according to claim 7, characterized in that: The peak holding circuit includes a transconductance operational amplifier, a charging diode, a clamping diode, a reset MOS tube, a holding capacitor and a high-bandwidth operational amplifier; The non-inverting input terminal of the transconductance operational amplifier is connected to the output terminal of the RC voltage divider circuit, the inverting input terminal of the transconductance operational amplifier is connected to the inverting input terminal of the high-bandwidth operational amplifier, and the output terminal of the transconductance operational amplifier is connected to the anode of the charging diode and the cathode of the clamping diode; The cathode of the charging diode is connected to one end of the holding capacitor and the drain of the reset MOS tube, and then connected to the same-direction input end of the high-bandwidth operational amplifier. The source of the reset MOS tube, the other end of the holding capacitor and the anode of the clamping diode are all grounded. The output end of the high-bandwidth operational amplifier is connected to the microcontroller.

9. The SiC MOSFET driving system with quantitative voltage overshoot spike suppression according to claim 7, characterized in that: The phase compensation circuit includes a differential resistor, a differential capacitor, a first comparator, a second comparator, an inverter, a first D flip-flop, a second D flip-flop and an XOR gate module; The non-inverting input terminal of the first comparator is connected to the RC voltage divider network, the inverting input terminal of the first comparator is connected to the first reference voltage, the output terminal of the first comparator is connected to the CLK pin of the first D flip-flop, and the output terminal of the first D flip-flop is connected to the first input terminal of the XOR gate module; The differential resistor is connected in series with the differential capacitor, the other end of the differential resistor is grounded, the other end of the differential capacitor is connected to the drain of the SiC MOSFET, the connection point of the differential resistor and the differential capacitor is connected to the non-inverting input of the second comparator, the inverting input of the second comparator is connected to the second reference voltage, the output of the second comparator is connected to the input of the inverter, the output of the inverter is connected to the CLK pin of the second D flip-flop, the output of the second D flip-flop is connected to the second input of the XOR gate module, and the CLR pins of the first D flip-flop and the second D flip-flop are connected to the drive signal.

10. The SiC MOSFET driving system with quantitative voltage overshoot spike suppression according to claim 5, characterized in that: The microcontroller includes an ADC module, a PI control module and a DAC module; The ADC module is used to sample the drain-source voltage overshoot peak value output by the peak holding circuit, the PI control module is used to calculate the output current value of the voltage-controlled current source, and the DAC module is used to output a voltage value corresponding to the output current of the voltage-controlled current source.

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