Multi-face-gate silicon carbide mosfet and preparation method therefor, and chip

Abstract

The present invention relates to semiconductor technology, and in particular to a multi-face-gate silicon carbide MOSFET and a preparation method therefor, and a chip. A comb-tooth-shaped first gate structure is formed in a source region, a corresponding well region and a silicon carbide drift region of the multi-face-gate silicon carbide MOSFET. The comb-tooth-shaped first gate structure has three faces, i.e., a comb-tooth side wall face, a comb-tooth top face and a comb-tooth bottom face, and the three faces are in contact with a channel region, such that the width of the channel region is increased; and the comb-tooth side wall face is perpendicular to an existing substrate plane or forms a certain inclination angle with same, such that the channel mobility of the channel region corresponding to the comb-tooth side wall face is greater than the channel mobility of the channel region corresponding to the comb-tooth top face and the comb-tooth bottom face of the comb-tooth-shaped first gate structure, thereby improving the overall mobility of a device.

Description

Polyhedral gate silicon carbide MOSFET transistor and its preparation method and chip Technical Field

[0001] The present invention relates to a semiconductor method, and in particular to a multi-faceted gate silicon carbide MOSFET transistor, a preparation method thereof, and a chip. Background Art

[0002] Silicon carbide power devices are increasingly being used in new energy applications such as charging stations, electric vehicles, photovoltaic inverters, and energy storage. Existing silicon carbide MOSFET transistor structures primarily include planar gate and trench gate structures.

[0003] Existing silicon carbide MOSFET transistors, whether planar gate structure or trench gate structure, have their own shortcomings. For example, although the reliability of silicon carbide MOSFET transistors with planar gate structure is very good, the plane where the channel is located is perpendicular to the c-axis of 4H-SiC, and the channel mobility in this plane is low (generally less than 30cm 2 / V·s) brings additional conduction loss. The channel plane of the trench gate silicon carbide MOSFET transistor is parallel to the c-axis, and its channel mobility is high (up to 120cm 2 / V·s), but because silicon carbide is very difficult to etch, it is generally difficult to etch trenches deeper than 1.5um, making the yield of this process step a huge challenge in large-scale device production. At the same time, the high breakdown electric field of silicon carbide (>2.5MV / cm) also makes the protection of the gate oxide at the bottom of the trench a major difficulty in structural design and process implementation.

[0004] Summary of the Invention

[0005] To solve the problems mentioned in the background technology, an embodiment of the present invention provides a multi-faceted gate silicon carbide MOSFET transistor and its preparation method and chip, which are compatible with the existing planar gate silicon carbide MOSFET process, are conducive to maintaining a high yield and reliability at the application end during large-scale mass production, and also have a high channel mobility.

[0006] A polyhedral gate silicon carbide MOSFET transistor, comprising:

[0007] A semiconductor substrate, a silicon carbide drift region located on a first surface of the semiconductor substrate, and a drain electrode located on a second surface of the semiconductor substrate;

[0008] a well region located in the silicon carbide drift region, and a source region located in the well region, wherein the semiconductor substrate, the silicon carbide drift region and the source region are of a first doping type, and the well region is of a second doping type;

[0009] a source electrode located on a surface of the source region;

[0010] A gate structure located on the surface of the source region, the well region and the silicon carbide drift region, wherein the portion of the well region in contact with the gate structure serves as a channel region;

[0011] The gate structure includes a comb-tooth-shaped first gate structure, which is located in the source region, the corresponding well region and the silicon carbide drift region. The comb length direction of the comb-tooth-shaped first gate structure is consistent with the current direction of the channel region, and the channel mobility of the channel corresponding to the comb side wall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel corresponding to the comb top surface and the comb bottom surface of the comb-tooth-shaped first gate structure.

[0012] Optionally, the sidewall surface of the comb teeth is perpendicular to the substrate plane, or the sidewall surface of the comb teeth is inclined to form an angle with the substrate plane.

[0013] Optionally, the comb tooth sidewall surface is silicon carbide m-face, a-face or Bevel.

[0014] Optionally, when the side wall surface of the comb teeth is When the surface is inclined, the cross-section of the comb teeth is an inverted triangle or an inverted trapezoid.

[0015] Optionally, the number of the comb teeth is one or more.

[0016] Optionally, the depth of the comb teeth ranges from 0.1 micrometers to 1.5 micrometers, and the depth of the comb teeth is less than the depth of the well region.

[0017] Optionally, the method further includes a JFET current enhancement layer located in the silicon carbide drift region and adjacent to the well region, wherein the JFET current enhancement layer has a first doping type and a doping concentration greater than that of the silicon carbide drift region.

[0018] Optionally, a lightly doped channel of the first doping type is further included in the channel region.

[0019] An embodiment of the present invention further provides a method for preparing a polyhedral gate silicon carbide MOSFET transistor, comprising:

[0020] Providing a semiconductor substrate, forming a silicon carbide drift region on a first surface of the semiconductor substrate, wherein the semiconductor substrate and the silicon carbide drift region have a first doping concentration;

[0021] forming a drain electrode on the second surface of the semiconductor substrate;

[0022] forming a well region and a source region in the silicon carbide drift region, wherein the well region is located in the silicon carbide drift region, the source region is located in the well region, the source region is of a first doping type, and the well region is of a second doping type;

[0023] Etching the source region, the well region and the silicon carbide drift region to form comb-tooth-shaped grooves;

[0024] A gate structure is formed on the surface of the comb-tooth-shaped trench, and a portion of the well region contacted by the gate structure serves as a channel region. The gate structure includes a comb-tooth-shaped first gate structure located in the comb-tooth-shaped trench, wherein the length direction of the comb teeth of the comb-tooth-shaped first gate structure is consistent with the direction of current in the channel region, and the channel mobility of the channel region corresponding to the comb-tooth sidewall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure;

[0025] A source electrode is formed on the surface of the source region.

[0026] An embodiment of the present invention further provides a chip having the polyhedral gate silicon carbide MOSFET transistor.

[0027] In summary, this application has the following advantages:

[0028] Comb-tooth-shaped grooves are formed in the source region, the corresponding well region and the silicon carbide drift region of the polyhedral gate silicon carbide MOSFET transistor, and a comb-tooth-shaped first gate structure is formed accordingly. The comb-tooth-shaped first gate structure has three surfaces, namely, comb-tooth sidewalls, comb-tooth top surfaces and comb-tooth bottom surfaces, which are in contact with the channel region, thereby increasing the width of the channel region. The comb-tooth sidewalls are perpendicular to the existing substrate plane or form a certain inclination angle. By reasonably adjusting the crystal plane of the comb-tooth sidewalls, the channel mobility of the channel region corresponding to the comb-tooth sidewalls is greater than the channel mobility of the channel region corresponding to the comb-tooth top surfaces and comb-tooth bottom surfaces of the comb-tooth-shaped first gate structure, thereby improving the overall comprehensive mobility.

[0029] Furthermore, the multi-faceted gate silicon carbide MOSFET transistor is compatible with the process of existing planar gate silicon carbide MOSFET transistors and has low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the AA′ plane according to an embodiment of the present invention;

[0031] FIG2 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along plane BB′ according to an embodiment of the present invention;

[0032] FIG3 is a three-dimensional structural diagram of a polyhedral gate silicon carbide MOSFET transistor according to an embodiment of the present invention (excluding the gate structure);

[0033] 4 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the CC′ plane according to an embodiment of the present invention;

[0034] 5 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the DD′ plane according to an embodiment of the present invention;

[0035] 6 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the EE′ plane according to an embodiment of the present invention;

[0036] 7 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the FF′ plane according to another embodiment of the present invention;

[0037] 8 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the GG′ plane according to another embodiment of the present invention;

[0038] 9 is a schematic cross-sectional structure diagram along the HH′ plane of a polyhedral gate silicon carbide MOSFET transistor according to another embodiment of the present invention;

[0039] 10 is a schematic cross-sectional view of a polyhedral gate silicon carbide MOSFET transistor according to another embodiment of the present invention;

[0040] 11 is a schematic cross-sectional structure diagram along plane II′ of a polyhedral gate silicon carbide MOSFET transistor according to another embodiment of the present invention;

[0041] 12 is a schematic cross-sectional structure diagram of a polyhedral gate silicon carbide MOSFET transistor along the JJ′ plane according to another embodiment of the present invention;

[0042] FIG13 is a schematic diagram of a cross-sectional structure of a polyhedral gate silicon carbide MOSFET transistor along the KK′ plane according to another embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] Please refer to Figures 1 to 6, which are schematic structural diagrams of a multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention, wherein Figure 1 is a schematic structural diagram of a cross-section along the AA′ plane of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention, Figure 2 is a schematic structural diagram of a cross-section along the BB′ plane of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention, Figure 3 is a three-dimensional structural diagram of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention (excluding the gate structure), Figure 4 is a schematic structural diagram of a cross-section along the CC′ plane of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention, Figure 5 is a schematic structural diagram of a cross-section along the DD′ plane of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention, and Figure 6 is a schematic structural diagram of a cross-section along the EE′ plane of the multi-faceted gate silicon carbide MOSFET transistor according to an embodiment of the present invention.

[0045] The polyhedral gate silicon carbide MOSFET transistor of an embodiment of the present invention includes:

[0046] A semiconductor substrate 10, a silicon carbide drift region 20 located on a first surface of the semiconductor substrate 10, and a drain electrode 30 located on a second surface of the semiconductor substrate 10;

[0047] a well region 40 located in the silicon carbide drift region 20 and a source region 50 located in the well region 40 , wherein the semiconductor substrate 10 , the silicon carbide drift region 20 and the source region 50 are of a first doping type, and the well region 40 is of a second doping type;

[0048] a source electrode 70 located on the surface of the source region 50;

[0049] A gate structure 60 is located on the surface of the source region 50 , the well region 40 and the silicon carbide drift region 20 , wherein a portion of the well region contacted by the gate structure 60 serves as a channel region 55 ;

[0050] The gate structure 60 includes a comb-tooth-shaped first gate structure 65, which is located in the source region 50, the corresponding well region 40 and the silicon carbide drift region 20. The comb-tooth length direction of the comb-tooth-shaped first gate structure 65 is consistent with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth side wall surface 61 of the comb-tooth-shaped first gate structure 65 is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface 63 and the comb-tooth bottom surface 62 of the comb-tooth-shaped first gate structure, where the comb-tooth length direction is the direction aa′.

[0051] Since the channel mobility of SiC materials on different crystal planes varies greatly, the channel plane of existing planar gate SiC MOSFET transistors is perpendicular to the c-axis of 4H-SiC, and the channel mobility of this plane is low (generally less than 30 cm 2 / V·s), which will bring additional conduction loss. However, the channel of the silicon carbide MOSFET transistor with a trench gate structure is parallel to the c-axis, so its mobility is high, up to 120cm 2 / V·s, but due to the large trench depth of the trench gate structure, etching of silicon carbide material is very difficult. It is generally difficult to etch trenches deeper than 1.5um, which makes the yield of this process step a great challenge in large-scale device production.

[0052] In an embodiment of the present invention, a comb-tooth-shaped groove 21 is formed in the source region 50, the corresponding well region 40 and the silicon carbide drift region 20, and a comb-tooth-shaped first gate structure 65 is formed accordingly. The comb-tooth-shaped first gate structure has three surfaces, namely, a comb-tooth side wall surface 61, a comb-tooth top surface 63 and a comb-tooth bottom surface 62, which are in contact with the channel region. The comb-tooth top surface 63 and the comb-tooth bottom surface 62 are parallel to the existing substrate plane, and the comb-tooth side wall surface 61 is perpendicular to the existing substrate plane or forms a certain inclination angle. By reasonably adjusting the crystal orientation of the comb-tooth side wall surface 61, the channel mobility of the channel region corresponding to the comb-tooth side wall surface 61 is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface 63 and the comb-tooth bottom surface 62 of the comb-tooth-shaped first gate structure.

[0053] In this embodiment, the planes where the comb tooth top surface 63 and comb tooth bottom surface 62 of the polyhedral gate silicon carbide MOSFET transistor lie are perpendicular to the c-axis of 4H-SiC, and the planes where the comb tooth sidewall surface 61 lies are parallel to the c-axis of 4H-SiC.

[0054] Since the channel mobility of silicon carbide on the substrate plane is low (~25cm 2 / V·s), while the channel mobility of a-face and m-face in the vertical direction parallel to the c-axis of 4H-SiC is higher (50~120cm 2 / V·s), the comprehensive mobility obtained by the multi-faceted channels of the multi-faceted gate silicon carbide MOSFET transistor of the embodiment of the present invention is higher than that of the traditional planar gate structure.

[0055] Furthermore, since the comb-tooth-shaped first gate structure 65 of the present invention has three surfaces: the comb-tooth sidewall surface 61, the comb-tooth top surface 63, and the comb-tooth bottom surface 62, compared with the prior art that introduces a side MOS interface, the effective channel width-to-length ratio (W) of the multi-faceted gate silicon carbide MOSFET transistor of the present invention is ch / L ch ) has a higher channel width-to-length ratio than the conventional planar gate (if the trench 21 has a depth-to-width ratio of 1, the W ch / L ch The ratio is twice that of the traditional planar gate), which makes the channel resistance (its reciprocal 1 / R ch =μ n *W ch / Lch *C ox *(V G -V TH )) can be significantly reduced.

[0056] The embodiment of the present invention can improve the channel resistance by adjusting the ratio of the comb tooth side wall surface 61 to the comb tooth top surface 63 and the comb tooth bottom surface 62 by adjusting the depth-to-width ratio of the groove, and at the same time improve the comprehensive channel mobility of the multi-faceted gate silicon carbide MOSFET transistor of the present invention by adjusting the corresponding crystal plane of the comb tooth side wall surface 61.

[0057] And since the current direction of the channel region of the present invention is generally in the horizontal direction parallel to the substrate plane, it can still be regarded as a planar structure and is compatible with the traditional planar gate process (only before forming the gate structure, strip grooves perpendicular to the gate layout direction are etched inside the silicon carbide), and the cost is relatively low.

[0058] In an embodiment of the present invention, the height of the comb teeth of the comb-toothed first gate structure 65 (i.e., the height of the comb tooth sidewalls) is less than the depth of the well region 40 but greater than the depth of the source region 50. As an embodiment, the height of the comb teeth is 0.2 microns, the depth of the well region is 0.8 microns, and the depth of the source region is 0.3 microns or 0.15 microns.

[0059] In other embodiments, the height of the comb teeth ranges from 0.1 micrometers to 1.5 micrometers, preferably from 0.1 micrometers to 0.5 micrometers.

[0060] Compared to the traditional trench gate structure, the well region of the present invention is deeper than the bottom of the comb-tooth trench. The deeper PN junction formed at the bottom of the well region and the silicon carbide drift region can effectively protect the gate oxide, reduce the high electric field formed by the gate oxide under the high voltage bias of the drain, and improve the gate oxide life. From the perspective of process implementation, the trench etching depth of the traditional trench gate needs to be strictly controlled, generally around 1 to 1.5um, and the depth of the channel etching needs to be deeper than the outlet of the channel current in the well region, but shallower than the deep PN junction used for avalanche clamping. The process difficulties faced here include: the trench gate etching process is relatively difficult, and the process difficulty of the deep junction for clamping protection is also very great. Since the trench depth of the present invention can be controlled within 0.5 microns, as long as the aspect ratio of the trench structure is controlled to ensure sufficient side gate width, the present invention can even work at a depth of only 0.1 microns. The requirements for the silicon carbide etching process are relatively low, and the process difficulty of forming a high-quality gate oxide layer in a shallower trench is also relatively small. This greatly reduces the process difficulty, is conducive to the formation of a high-quality gate structure, and ensures a high yield of the product in mass production.

[0061] In high-voltage applications, the channel current direction of conventional trench-gate MOSFET structures is perpendicular to the substrate plane and parallel to the electric field direction of the drift region. As a result, in the off state, the channel region is affected by the drain-induced barrier lowering (DIBL) effect, resulting in high channel leakage current under high-voltage drain bias. The channel current direction of the present invention remains parallel to the substrate plane and perpendicular to the electric field of the drift region, making the channel less susceptible to the DIBL effect and significantly reducing leakage current in high-voltage applications.

[0062] In other embodiments, referring to Figures 7 to 9 , the height of the comb teeth of the comb-shaped first gate structure 65 is less than the depth of the well region 40 and less than the depth of the source region 50. Since it is not critical whether the trench depth is deeper than the source region, the present invention has a high process margin for the trench etching depth.

[0063] In this embodiment, the number of the comb teeth is one or more, and an appropriate number of comb teeth can be reasonably set according to the width of the channel.

[0064] In this embodiment, the gate structure 60 includes a comb-shaped first gate structure 65 located in the source region, the corresponding well region and the silicon carbide drift region, and a second gate structure located on the surface of the comb-shaped first gate structure.

[0065] 1 and 2 , in this embodiment, a cell structure includes two polyhedral gate SiC MOSFET transistors, wherein after carriers exit the channel, they need to pass through the JFET region formed by two adjacent well regions before reaching the SiC drift region.

[0066] In other embodiments, a cell structure may also include only one polyhedral gate silicon carbide MOSFET transistor, for example, as shown in FIG3 .

[0067] In this embodiment, the semiconductor substrate is a heavily doped silicon carbide substrate. In other embodiments, the semiconductor substrate may also be other suitable substrates, such as a silicon substrate, a diamond substrate, an aluminum nitride substrate, a gallium nitride substrate, etc.

[0068] In this embodiment, the polyhedral gate silicon carbide MOSFET transistor is an N-type channel MOSFET transistor, the first doping type is N-type, and the second doping type is P-type, wherein the semiconductor substrate 10 is an N-type heavily doped substrate, the silicon carbide drift region 20 is an N-type lightly doped drift region, the well region 40 is a P-type lightly doped well region, and the source region 50 is an N-type heavily doped source region.

[0069] In other embodiments, the polyhedral gate silicon carbide MOSFET transistor may also be a P-type channel MOSFET transistor, wherein the first doping type is P-type and the second doping type is N-type, wherein the semiconductor substrate 10 is a P-type heavily doped substrate, the silicon carbide drift region 20 is a P-type lightly doped drift region, the well region 40 is an N-type lightly doped well region, and the source region 50 is a P-type heavily doped source region.

[0070] Referring to Figure 10 , similar to a conventional planar gate structure, carriers exiting the channel region must pass through the JFET region formed by two adjacent well regions before reaching the drift region. To reduce the resistance of the JFET region, the SiC MOSFET can further introduce a higher doping level than the drift region into the JFET region, forming a JFET current enhancement layer 25.

[0071] Furthermore, the depth of the N-type doping of the JFET current enhancement layer 25 is greater than the depth of the well region, which is beneficial to the lateral diffusion of current in the drift region.

[0072] Referring to FIG. 11 , the channel region of the polyhedral gate silicon carbide MOSFET transistor can also be a lightly doped channel 45 of the first doping type. Because the comb-shaped first gate structure forms a three-sided ring-gate structure within the silicon carbide channel body, gate control capability is enhanced, enabling the lightly doped first-type channel doping to still allow the device to operate in enhancement mode (i.e., if the device is an N-channel enhancement-mode MOSFET, its threshold voltage Vth>0). Adjusting the threshold voltage can be achieved by selecting gate materials with different work functions and adjusting the concentration of the N-type doping within the channel.

[0073] Please refer to FIG12 and FIG13, which are schematic structural diagrams of polyhedral gate silicon carbide MOSFET transistors according to two other embodiments of the present invention, wherein the plane where the comb-tooth sidewall surface 61 is located is The inclined surface forms an angle of 54.7° with the substrate plane. The channel mobility corresponding to the inclined surface is higher, so the comprehensive mobility of the multi-faceted gate silicon carbide MOSFET transistor is higher.

[0074] Please refer to FIG12 , the cross-sectional shape of the comb teeth is an inverted triangle, and the two side walls of the inverted triangle are The comb teeth have an inclined surface and no bottom surface.

[0075] Please refer to FIG13 , the cross-sectional shape of the comb teeth is an inverted trapezoid, and the two side walls of the inverted trapezoid are The comb teeth have an inclined surface and a bottom surface 62 .

[0076] An embodiment of the present invention further provides a chip having the above-mentioned polyhedral gate silicon carbide MOSFET transistor.

[0077] An embodiment of the present invention further provides a method for preparing a polyhedral gate silicon carbide MOSFET transistor, comprising:

[0078] Providing a semiconductor substrate, forming a silicon carbide drift region on a first surface of the semiconductor substrate, wherein the semiconductor substrate and the silicon carbide drift region have a first doping concentration;

[0079] forming a well region and a source region in the silicon carbide drift region, wherein the well region is located in the silicon carbide drift region, the source region is located in the well region, the source region is of a first doping type, and the well region is of a second doping type;

[0080] Etching the source region, the well region and the silicon carbide drift region to form comb-tooth-shaped grooves;

[0081] A gate structure is formed on the surface of the comb-tooth-shaped trench, and a portion of the well region contacted by the gate structure serves as a channel region. The gate structure includes a comb-tooth-shaped first gate structure located in the comb-tooth-shaped trench, wherein the length direction of the comb teeth of the comb-tooth-shaped first gate structure is consistent with the direction of current in the channel region, and the channel mobility of the channel region corresponding to the comb-tooth sidewall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure;

[0082] forming a source electrode on the surface of the source region;

[0083] A drain electrode is formed on the second surface of the semiconductor substrate.

[0084] The multi-faceted gate silicon carbide MOSFET transistor of the embodiment of the present invention is compatible with the traditional planar gate process. It only requires etching comb-shaped grooves in the gate layout direction inside the silicon carbide before forming the gate structure, and filling to form the gate structure, so the process cost is low.

[0085] The etching process for forming the comb-shaped grooves can be prepared using the existing silicon carbide etching process, which will not be described in detail here.

[0086] Finally, it should be noted that any modification or equivalent replacement of part or all of the technical features based on the device structure of the present invention and the technical solutions of the embodiments, which does not deviate from the essence of the corresponding technical solutions of the present invention, falls within the patent scope of the device structure of the present invention and the implementation scheme.

Claims

1. A polyhedral gate silicon carbide MOSFET transistor, characterized in that: include: A semiconductor substrate, a silicon carbide drift region located on a first surface of the semiconductor substrate, and a drain electrode located on a second surface of the semiconductor substrate; A well region located in the silicon carbide drift region, a source region located in the well region, the semiconductor substrate, the silicon carbide drift region and the source region are of a first doping type, and the well region is of a second doping type; a source electrode located on the surface of the source region; A gate structure located on the surface of the source region, the well region and the silicon carbide drift region, wherein a portion of the well region in contact with the gate structure serves as a channel region; The gate structure includes a comb-tooth-shaped first gate structure, which is located in the source region, the corresponding well region and the silicon carbide drift region. The comb-tooth length direction of the comb-tooth-shaped first gate structure is consistent with the current direction of the channel region, and the channel mobility of the channel corresponding to the comb-tooth side wall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure.

2. The polyhedral gate silicon carbide MOSFET transistor according to claim 1, characterized in that: The side wall surface of the comb teeth is perpendicular to the substrate plane, or the side wall surface of the comb teeth is inclined to the substrate plane to form an angle.

3. The polyhedral gate silicon carbide MOSFET transistor according to claim 1, characterized in that: The comb tooth side wall surface is a silicon carbide m-face, a-face or Bevel.

4. The polyhedral gate silicon carbide MOSFET transistor according to claim 4, characterized in that: When the side wall surface of the comb teeth is When the surface is inclined, the cross-section of the comb teeth is an inverted triangle or an inverted trapezoid.

5. The polyhedral gate silicon carbide MOSFET transistor according to claim 1, characterized in that: The number of the comb teeth is one or more.

6. The polyhedral gate silicon carbide MOSFET transistor according to claim 1, characterized in that: The depth of the comb teeth ranges from 0.1 micrometers to 1.5 micrometers, and the depth of the comb teeth is less than the depth of the well region.

7. The polyhedral gate silicon carbide MOSFET transistor according to claim 1, characterized in that: The invention also includes a JFET current enhancement layer located in the silicon carbide drift region and adjacent to the well region, wherein the JFET current enhancement layer has a first doping type and a doping concentration greater than that of the silicon carbide drift region.

8. The polyhedral gate silicon carbide MOSFET transistor according to claim 1, characterized in that: Also included is a first doping type lightly doped channel located in the channel region.

9. A method for preparing a multi-faceted gate silicon carbide MOSFET transistor, characterized in that: include: Providing a semiconductor substrate, forming a silicon carbide drift region on a first surface of the semiconductor substrate, wherein the semiconductor substrate and the silicon carbide drift region have a first doping concentration; forming a well region and a source region in the silicon carbide drift region, wherein the well region is located in the silicon carbide drift region, the source region is located in the well region, the source region is of a first doping type, and the well region is of a second doping type; Etching the source region, the well region and the silicon carbide drift region to form comb-tooth-shaped grooves; A gate structure is formed on the surface of the comb-tooth-shaped groove, and a portion of the well region contacted by the gate structure is used as a channel region. The gate structure includes a comb-tooth-shaped first gate structure located in the comb-tooth-shaped groove, the comb-tooth length direction of the comb-tooth-shaped first gate structure is consistent with the current direction of the channel region, and the channel mobility of the channel region corresponding to the comb-tooth sidewall surface of the comb-tooth-shaped first gate structure is greater than the channel mobility of the channel region corresponding to the comb-tooth top surface and the comb-tooth bottom surface of the comb-tooth-shaped first gate structure; forming a source electrode on the surface of the source region; A drain electrode is formed on the second surface of the semiconductor substrate.

10. A chip having a multi-faceted gate silicon carbide MOSFET transistor according to any one of claims 1 to 8.

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