Zero-value memory compression

Abstract

A coherency management device receives a request to read data from an address in a main memory or to write data to the address. On a write, if the data comprises zero data, an entry corresponding to the memory address is created in a cache directory if the entry does not already exist, the entry is set to an invalid state and the entry indicates that the data comprises zero data. The zero data is not written to the main memory or cache. On a read, an entry corresponding to the memory address is checked in the cache directory. If the entry exists in the cache directory, is valid and comprises an indication that the data corresponding to the memory address comprises zero data, the coherency management device returns zero data in response to the request without fetching the data from the main memory or cache.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. nonprovisional patent application number 16 / 723,780, filed December 20, 2019, the contents of which are hereby incorporated by reference. Background Technology

[0003] The main memory of a computer system typically includes relatively inexpensive and high-density memory devices, such as Dynamic Random Access Memory (DRAM). However, access times for such devices are typically relatively long. Therefore, computer systems usually also include at least one cache memory to improve performance. Cache memory is a relatively high-speed memory device that is typically located relatively close to the processor. In a multiprocessor computer system, each processor (or processor core) typically has its own dedicated Level 1 (L1) cache, and in some cases shares other caches (e.g., Level 2 (L2) and Level 3 (L3) caches) with other processors or processor cores.

[0004] In multi-node computer systems where each node (e.g., processor, core, or core complex) has a dedicated cache, various techniques are implemented to maintain the consistency of data being used by different nodes. For example, if a processor attempts to access data stored at a certain memory address in main memory, the processor must first determine whether the data corresponding to that memory address is stored in another cache and whether it has been modified. Some such methods include a cache catalog that tracks cache lines currently in use by the system. In some cases, a cache catalog improves memory bandwidth by reducing the number of memory requests and probe requests required by the computer system. Cache catalogs are often excessively large (implemented through "guard bands"), for example, to address local "hot spots" that process certain datasets during application runtime. Therefore, applications often retain spare unused entries in the cache catalog.

[0005] In some applications, the processor writes zero data (i.e., data containing only zeros) to main memory. Such applications may include memory erasure (e.g., clearing memory for another purpose) or storing datasets with highly sparsity characteristics (e.g., machine learning data). Attached Figure Description

[0006] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings:

[0007] Figure 1 It is a block diagram of an example apparatus that can implement one or more features of this disclosure;

[0008] Figure 2 yes Figure 1 A block diagram of the device, which shows further details;

[0009] Figure 3 This is a block diagram illustrating a portion of the example computing system;

[0010] Figure 4 This is a block diagram illustrating a portion of an example multiprocessor computing system;

[0011] Figure 5 This is a block diagram illustrating an example implementation of a cache directory;

[0012] Figure 6 This is a flowchart illustrating an example method for zero-data compression by a consistency management device during write operations; and

[0013] Figure 7 This is a flowchart illustrating an example method for zero-data compression by a consistency management device during read operations. Detailed Implementation

[0014] Some implementations provide a consistency management apparatus. The consistency management apparatus includes circuitry for receiving a request to read data stored at an address in main memory. The consistency management apparatus further includes circuitry for determining whether a cache directory includes a cache directory entry corresponding to the address. The consistency management apparatus further includes circuitry for determining whether a cache directory entry is invalid if the cache directory includes the cache directory entry corresponding to the address. The consistency management apparatus further includes circuitry for determining whether the cache directory entry includes an indication that the data corresponding to the memory address includes zero data if the cache directory entry includes the indication. The consistency management apparatus further includes circuitry for returning zero data in response to the request if the cache directory entry includes the indication.

[0015] In some implementations of the consistency management device, the indication includes bits in the cache directory entry. In some implementations, the indication includes a standby state in the status field of the cache directory entry. In some implementations, the indication includes at least one bit in the status field of the cache directory entry. In some implementations, the indication includes bits in the shared vector field of the cache directory entry. In some implementations, if the cache directory entry is invalid and includes the indication, the consistency management device returns the zero data in response to the request without reading the main memory. In some implementations, the consistency management device includes a consistency slave device, a probe filter device, and / or a sniffer filter device. In some implementations, the consistency management device receives the request from a consistency master device. In some implementations, the request includes a non-temporary read operation.

[0016] Some implementations provide a method for managing cache coherency in a computer system, implemented in a coherency management apparatus. The method includes: receiving a request to read data at an address stored in main memory; and determining whether a cache directory includes a cache directory entry corresponding to the address. The method further includes: if the cache directory includes the cache directory entry corresponding to the address, determining whether the cache directory entry is invalid. The method further includes: if the cache entry is invalid, determining whether the cache directory entry includes an indication that the data corresponding to the memory address includes zero data. The method further includes: if the cache directory entry includes the indication, returning zero data in response to the request.

[0017] In some implementations of the method, the indication includes bits in the cache directory entry. In some implementations, the indication includes a standby state in the status field of the cache directory entry. In some implementations, the indication includes at least one bit in the status field of the cache directory entry. In some implementations, the indication includes bits in the shared vector field of the cache directory entry. In some implementations, if the cache directory entry is invalid and includes the indication, the consistency management device does not allocate a cache entry in the system corresponding to the request. In some implementations, if the cache directory entry is invalid and includes the indication, the consistency management device returns the zero data in response to the request without reading the main memory. In some implementations, the consistency management device includes a consistency slave device, a probe filter device, and / or a snoop filter device. In some implementations, the consistency management device receives the request from a consistency master device. In some implementations, the request includes a non-temporary read operation.

[0018] Some implementations provide a consistency management apparatus. The consistency management apparatus includes circuitry for receiving a request to write data to an address in main memory. The consistency management apparatus further includes circuitry for determining whether the data includes zero data. The consistency management apparatus further includes circuitry for determining whether a cache directory includes a cache directory entry corresponding to the address. The consistency management apparatus further includes circuitry for setting the state of the cache directory entry to invalid and setting an indication in the cache directory entry that the data corresponding to the memory address includes zero data if the data includes zero data and the cache directory includes the cache directory entry. The consistency management apparatus further includes circuitry for creating the cache directory entry, setting the state of the cache directory entry to invalid, and setting the indication in the cache directory entry that the data corresponding to the memory address includes zero data if the cache directory does not include the cache directory entry.

[0019] In some implementations, determining whether the data includes zero data by the consistency management device includes determining whether the data includes only zero data. In some implementations, determining whether the data includes zero data by the consistency management device includes determining whether the request includes an instruction containing an opcode indicating that zeros should be written to the address. In some implementations, the indication includes at least one bit in the status field of the cache directory entry. In some implementations, the indication includes a bit in the shared vector field of the cache directory entry. In some implementations, if the data includes zero data, the consistency management device sets the indication in response to the request without writing to the main memory. In some implementations, the consistency management device includes a consistency slave device, a probe filter device, and / or a snoop filter device. In some implementations, the consistency management device receives the request from a consistency master device. In some implementations, the request includes a non-temporary write operation.

[0020] Some implementations provide a method for managing cache coherency in a computer system, implemented in a coherency management apparatus. The method includes: receiving a request to write data to an address in main memory; determining whether the data includes zero data; and determining whether a cache directory includes a cache directory entry corresponding to the address. The method further includes: if the data includes zero data and the cache directory includes the cache directory entry, then setting the state of the cache directory entry to invalid and setting an indication in the cache directory entry that the data corresponding to the memory address includes zero data. The method further includes: if the cache directory does not include the cache directory entry, then creating the cache directory entry, setting the state of the cache directory entry to invalid, and setting the indication in the cache directory entry that the data corresponding to the memory address includes zero data.

[0021] In some implementations of the method, determining whether the data includes zero data by the consistency management device includes determining whether the data includes only zero data. In some implementations, determining whether the data includes zero data by the consistency management device includes determining whether the request includes an instruction containing an opcode indicating that zeros should be written to the address. In some implementations, the indication includes at least one bit in the status field of the cache directory entry. In some implementations, the indication includes a bit in the shared vector field of the cache directory entry. In some implementations, if the data includes zero data, the consistency management device sets the indication in response to the request without writing to the main memory. In some implementations, the consistency management device includes a consistency slave device, a probe filter device, and / or a snoop filter device. In some implementations, the consistency management device receives the request from a consistency master device. In some implementations, the request includes a non-temporary write operation.

[0022] Figure 1 This is a block diagram of an example device 100 that can implement one or more features of the present disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include... Figure 1 Additional components not shown.

[0023] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core may be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0024] Storage device 106 includes fixed or removable storage devices, such as hard disk drives, solid-state drives, optical disk drives, or flash drives. Input device 108 includes, but is not limited to: keyboards, keypads, touchscreens, touchpads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes, but is not limited to: displays, speakers, printers, haptic feedback devices, one or more lights, antennas, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals).

[0025] Input driver 112 communicates with processor 102 and input device 108, and permits processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110, and permits processor 102 to send output to output device 110. It should be noted that input driver 112 and output driver 114 are optional components, and device 100 will operate in the same manner in the absence of input driver 112 and output driver 114. Output driver 116 includes an accelerated processing unit (“APD”) 116 coupled to display device 118. The APD receives computation commands and graphics rendering commands from processor 102, processes those commands, and provides pixel output to display device 118 for display. As described in further detail below, APD 116 includes one or more parallel processing units to perform computations according to the Single Instruction Multiple Data (“SIMD”) paradigm. Therefore, although various functions are described herein as being performed by or in combination with APD 116, in various alternatives, the functions described as being performed by APD 116 may additionally or alternatively be performed by other computing devices with similar capabilities, which are not driven by a host processor (e.g., processor 102) and provide graphics output to display device 118. For example, it is conceivable that any processing system performing processing tasks according to the SIMD paradigm can perform the functions described herein. Alternatively, it is conceivable that a computing system not performing processing tasks according to the SIMD paradigm can perform the functions described herein.

[0026] Figure 2This is a block diagram of device 100, illustrating additional details related to performing processing tasks on APD 116. Processor 102 maintains one or more control logic modules in system memory 104 for execution by processor 102. The control logic modules include operating system 120, kernel-mode driver 122, and application program 126. These control logic modules control various features of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with the hardware and provides an interface to the hardware for other software executing on processor 102. Kernel-mode driver 122 controls the operation of APD 116 by providing, for example, an application programming interface (“API”) to software executing on processor 102 (e.g., application program 126) to access various functions of APD 116. Kernel-mode driver 122 also includes a just-in-time (JIT) compiler that compiles programs for execution by processing units of APD 116, such as SIMD unit 138, which is discussed in further detail below.

[0027] APD 116 executes commands and procedures related to selected functions, such as graphics and non-graphics operations suitable for parallel processing. APD 116 can be used to perform graphics pipeline operations based on commands received from processor 102, such as pixel manipulation, geometric calculations, and rendering images to display device 118. APD 116 can also perform computational processing operations not directly related to graphics operations based on commands received from processor 102, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks.

[0028] APD 116 includes a computation unit 132 comprising one or more SIMD units 138 that perform operations in parallel upon request from processor 102 according to a SIMD paradigm. A SIMD paradigm is one in which multiple processing elements share a single program control flow unit and program counter, and thus execute the same program, but can execute that program using different data. In one example, each SIMD unit 138 includes sixteen channels, where each channel executes the same instruction simultaneously with other channels in the SIMD unit 138, but can execute that instruction using different data. If not all channels need to execute a given instruction, an assertion can be used to shut down a channel. Assertions can also be used to execute programs with divergent control flow. More specifically, for programs with conditional branches or other instructions, where control flow is based on computation performed by a single channel, assertions corresponding to channels with currently unexecuted control flow paths and the serial execution of different control flow paths allow for arbitrary control flow.

[0029] The basic unit of execution in computing unit 132 is a work item. Each work item represents a single instantiation of a program that will be executed in parallel on a specific channel. Work items can be executed simultaneously as “wavefronts” on a single SIMD processing unit 138. One or more wavefronts are included in a “workgroup,” which comprises a set of work items designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that make up the workgroup. Alternatively, wavefronts are executed sequentially on a single SIMD unit 138, or partially or completely in parallel on different SIMD units 138. A wavefront can be considered as the largest set of work items that can be executed simultaneously on a single SIMD unit 138. Therefore, if a command received from processor 102 indicates that a particular program will be parallelized to the extent that the program cannot be executed simultaneously on a single SIMD unit 138, the program is decomposed into wavefronts that are parallelized on two or more SIMD units 138 or serialized on the same SIMD unit 138 (or parallelized and serialized as needed). Scheduler 136 performs various wavefront-related operations on different computing units 132 and SIMD units 138.

[0030] The parallelism provided by the computing unit 132 is suitable for graphics-related operations, such as pixel value calculation, vertex transformation, and other graphics operations. Therefore, in some instances, the graphics pipeline 134, which receives graphics processing commands from the processor 102, provides computing tasks to the computing unit 132 for parallel execution.

[0031] The computing unit 132 is also used to perform computational tasks that are unrelated to graphics or are not part of the "normal" operation of the graphics pipeline 134 (e.g., performing custom operations to supplement the processing performed for the operation of the graphics pipeline 134). The application program 126 or other software executing on the processor 102 transfers programs defining such computational tasks to the APD 116 for execution.

[0032] Figure 3 This is a block diagram illustrating a portion of the example computing system 300. In some instances, such as relative to... Figure 1 and Figure 2 As shown and described, computing system 300 is implemented using some or all of device 100. Computing system 300 includes one or more core complexes 310A to 310N, input / output (I / O) interfaces 320, interconnects 330, one or more memory controllers 340, and network interfaces 350. In other instances, computing system 300 includes additional components, different components, and / or is arranged in a different manner.

[0033] In some implementations, each of the core complexes 310A to 310N includes at least one processing device. In this example, at least one of the core complexes 310A to 310N includes one or more general-purpose processing devices, such as a CPU. It should be noted that "core complex" is also referred to as a "processing node" in some cases. In some implementations, such processors use... Figure 1 The processor 102 shown and described is used for implementation. In this example, at least one of the core complexes 310A to 310N includes one or more data-parallel processors. Examples of data-parallel processors include GPUs, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc. In some implementations, such processors use methods such as those described above. Figure 1 The APD 116 shown and described is used for implementation.

[0034] In some implementations, each processor core within the core complex 310A to 310N includes a cache subsystem with one or more levels of cache. In some implementations, each core complex 310A to 310N includes a cache (e.g., a Level 3 (L3) cache) shared among multiple processor cores.

[0035] Memory controller 340 includes at least one memory controller accessible, for example, via interconnect 330, from core complexes 310A to 310N. Memory controller 340 includes one or more of any suitable type of memory controller. Each of the memory controllers is coupled to (or otherwise communicates with) any number and type of memory device (not shown) and controls access to the memory device. In some implementations, such memory devices include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and / or any other suitable memory device. Interconnect 330 includes components suitable for… Figure 3 Any computer communication medium, such as a bus, data structure, etc., for communication between the devices shown.

[0036] I / O interface 320 includes one or more I / O interfaces (e.g., Peripheral Component Interconnect (PCI) bus, PCI Expansion (PCI-X), PCIe (PCI Express) bus, Gigabit Ethernet (GBE) bus, Universal Serial Bus (USB), etc.). In some implementations, I / O interface 320 uses, for example, relative to Figure 1The input driver 112 and / or output driver 114 shown and described are used for implementation. Various types of peripheral devices can be coupled to the I / O interface 320. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc. In some implementations, such peripheral devices use methods such as those described above. Figure 1 This is achieved through the input device 108 and / or output device 118 shown and described.

[0037] Figure 4 This is a block diagram illustrating a portion of an example multiprocessor computing system 400. System 400 includes one or more core complexes 410A to 410N and one or more memory controllers 440A to 440N communicating with the core complexes 410A to 410N via interconnects 430 (e.g., via other components). In some instances, the core complexes 410A to 410N are coupled to interconnects 430 via coherent master devices 415A to 415N, and the memory controllers 440A to 440N are coupled to interconnects 430 via coherent slave devices 445A to 445N. Interconnect 430 includes components suitable for… Figure 4 Any computer communication medium, such as a bus, data structure, etc., for communication between the devices shown. It should be noted that, for illustrative purposes, the processor system 400 is described relative to a core complex; however, in other implementations, the processing node may include a single processor, a processor core not implemented in the core complex, or any other suitable processing node.

[0038] Each of the core complexes 410A to 410N includes one or more processor cores 412A to 412N. It should be noted that in some implementations, the processing device is not organized as a core complex. In some cases, such processors are referred to as such (e.g., as a processing device) rather than as a core complex. Each core complex 410A to 410N also includes a corresponding cache subsystem 414A to 414N. Each cache subsystem 414A to 414N includes any suitable number of cache levels and any suitable cache hierarchy that can be used to support the caches of the core complexes 410A to 410N.

[0039] Each core complex 410A to 410N communicates with its corresponding consistency master 415A to 415N. In some implementations, the consistency master is an agent that handles traffic flowing on the interconnect (e.g., interconnect 430) and manages the consistency of connected CPUs or core complexes. In some implementations, to manage consistency, the consistency master receives and processes consistency-related messages and probes, and generates and transmits consistency-related requests and probes.

[0040] Each core complex 410A to 410N communicates with one or more consistency slave devices 445A to 445N via its corresponding consistency master device 415A to 415N and interconnect 430. The consistency slave device is a proxy device that manages the consistency of a memory controller (e.g., a memory controller connected to the consistency slave device). In some implementations, to manage consistency, the consistency slave device receives and processes requests and probes targeting the corresponding memory controller.

[0041] exist Figure 4 In this example, the core complex 410A communicates with the coherent slave 445A via a coherent master 415A and an interconnect 430. The coherent slave (CS) 445A communicates with a memory controller (MC) 440A, which controls memory devices (e.g., main memory DRAM devices).

[0042] Each of the coherent slave devices 445A to 445N communicates with (or includes) a corresponding cache directory (CD) 450A to 450N. In some cases, the cache directory is referred to as a "probe filter". The cache directory 450A includes, for example, entries for memory addresses or regions of memory accessible through the memory controller 440A, which are cached in the cache lines of system 400 (e.g., cache subsystems 414A to 414N). In some implementations, each core complex 410A to 410N communicates with any suitable number of memory controllers 440A to 440N via a corresponding coherent master device 415A to 415N and a corresponding coherent slave device 445A to 445N.

[0043] Probes include messages passed from a consistency point (e.g., a consistency slave device) to one or more caches in a computer system, requesting a response indicating whether the cache has a copy of a data block, and in some implementations, instructing the cache to place the data block in a cache state. In some implementations, if a consistency slave device receives a memory request targeting its corresponding memory controller (e.g., a memory request for data stored at an address or address region in memory controlled by a memory controller that manages the consistency of the consistency slave device), the consistency slave device performs a lookup (e.g., a tag-based lookup) on its corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of either of the cache subsystems.

[0044] In some implementations, the cache catalog tracks cache regions, where a region comprises multiple cache lines. The size of the tracked region may vary depending on the implementation. It should be noted that "region" may also be referred to as "page" herein. In some such implementations, if a consistency slave receives a cache request, it determines the region to which the request is targeted and performs a lookup in the cache catalog for that region. If the lookup results in a hit, the consistency slave sends probes to one or more CPUs identified in the hit entry. The type of probe generated by the consistency slave depends on the consistency state specified by the hit entry. It should be noted that the instances of line-based tracing discussed herein can also be implemented using region-based tracing.

[0045] In some implementations, the interconnect 430 is connected to a component that is not explicitly shown for ease of description. Figure 4 Other components shown and / or communicating with said other components. For example, in some implementations, interconnect 430 includes connections to one or more I / O interfaces and / or one or more I / O devices (e.g., corresponding to, as relative to, other components shown). Figure 3 The connection of the I / O interface 320 and the network interface 350 shown and described.

[0046] Figure 5 It is shown as relative to Figure 4 A block diagram illustrating an example implementation of the cache directory 450A shown and described. The cache directory 450A includes a control unit 500 and an array 510. The array 510 includes any suitable number of directory entries 520 for storing the state of memory addresses or regions. The number of directory entries 520 is set to achieve a suitable level of jitter, and thus, a number of spare directory entries 520 (e.g., in an invalid state) are generally available for other purposes as appropriate (i.e., if available), such as zero-tracking as discussed herein.

[0047] In some implementations, each of the directory entries 520 includes a status field 550, a shared vector field 540, and a tag field 530. In some implementations, the directory entry 520 includes other fields, different fields, and / or is arranged in another suitable manner. The tag field 530 includes multiple address bits that specify a subset of the bits of the memory address. In some implementations, the tag field 530 includes all bits of the memory address. In some such cases, the field may be referred to as an address field. The bits of the tag field 530 identify the memory location or set of memory locations in memory mapped to the directory entry. In this example, the tag field 530 indicates the location of the entry relative to the memory address. Figure 4 A subset of address bits of memory locations in a memory (e.g., DRAM) controlled by the memory controller 440A shown and described.

[0048] Shared vector 540 includes multiple bits indicating which caches in the system (if any) have a copy of the cache line mapped to directory entry 520. In this example, shared vector 540 indicates which cache subsystems 414A to 414N (if any) have a cache copy corresponding to the cache line of directory entry 520. Status field 550 includes one or more status bits specifying the status of directory entry 520. In some implementations, status field 550 may indicate that a particular directory entry 520 is in a particular state. An appropriate number of bits are provided to indicate the various states. For example, in some implementations, two bits are used when status field 550 represents three states. Note that this arrangement provides additional unused bit values ​​for status field 550. Similarly, in some implementations, three bits are used when status field 550 represents six states. Note that this arrangement provides two additional unused bit values ​​for status field 550.

[0049] Figure 6 This is a flowchart illustrating an example method 600 for zero data compression during write operations by a consistency management device, such as a consistency slave device or other suitable consistency management device as discussed herein.

[0050] In step 610, the consistency management device receives a request to write data to an address in main memory and determines whether the request will write zero data. In some implementations, the request includes a non-temporary write operation. Non-temporary write operations bypass the cache structure but can be observed by the consistency management device. In some implementations, the consistency management device determines whether the request will write zero data based on the payload of the request (e.g., whether the payload contains only zeros). It should be noted that in other implementations, other types of data can be detected for compression in this manner, such as payloads consisting entirely of 1s or payloads with a predetermined pattern. In some implementations, the consistency management device determines whether the request will write zero data based on the opcode of the request (e.g., whether the opcode indicates a specific type of write instruction that writes zero data).

[0051] If condition 620 requests the writing of data other than zero data, the consistency management device processes the data write in step 630 based on typical operations (e.g., performing a cache directory lookup, cache invalidation, and writing to memory where appropriate). Otherwise, if the request requests the writing of zero data, the consistency management device determines whether the entry in the cache directory associated with the request includes an entry corresponding to a memory address. In some implementations, the consistency management device makes this determination by comparing the memory address with a tag field in the cache directory entry (or by passing the request to the cache directory, which will perform the comparison), the tag field including the memory address or a portion of the memory address.

[0052] If condition 640 is that the cache directory includes an entry corresponding to the address, in step 660, the state of the cache directory entry is set to invalid to indicate that the cached copy of the data (e.g., in cache subsystems 414A to 414N) is not valid, and a zero indicator is set in the cache directory entry. In some implementations, a spare state is set in the cache directory entry to indicate both invalidity and zero data. If condition 640 is that the cache directory does not include an entry corresponding to the address, and if a spare, unused, or invalid entry is available in the cache directory, then in step 650, an entry corresponding to the address is created in the cache directory, and then in step 660, the state of the cache directory entry is set to invalid, and a zero indicator is set in the cache directory entry (or a spare state is set to indicate both). If a spare, unused, or invalid entry is not available in the cache directory, then, as in step 630, the consistency management device handles data writes based on typical operations (e.g., performing a cache directory lookup, cache invalidation, and writing to memory where appropriate).

[0053] The operations in step 660 are performed in any suitable order, or simultaneously or in parallel. In some implementations, the zero data indicator is a bit in the cache directory entry. The bit used for zero data indication in this manner may be referred to as a "zero-detection" or "ZD" bit. In some implementations, the ZD bit is a repurposed bit of the shared vector of the cache directory entry. For example, an invalid entry implicitly indicates that none of the cache subsystems 414A to 414N has a valid copy of the data corresponding to the address in main memory. Therefore, the shared vector does not necessarily indicate which caches contain valid copies and can be repurposed for other indications, such as indicating zero data.

[0054] In some implementations, the zero indicator is a standby state set in the status field of a cache directory entry. For example, if the status field includes two bits to represent three states (e.g., cached, invalid, exclusive), then a standby state exists because two bits can be used to represent four states using binary encoding. Therefore, the standby state can be specified as a zero-detection or ZD state. In some such implementations, the ZD state is used as an invalid state and also indicates that the data corresponding to the address in main memory is zero data.

[0055] In some implementations, zero data is not written to main memory, or is not written to main memory at this time. In some cases, this can have the advantage of saving memory bandwidth. In some implementations, it is not necessary to write data to main memory when a zero data indicator is set in the corresponding cache directory, because the corresponding read operation will return zero data based on the indicator in the cache directory entry (e.g., ZD bit or ZD state). Some implementations that do not write zero data to main memory when a zero data indicator is set in the corresponding cache directory entry include logic that writes zero data to main memory when the cache directory entry is evicted.

[0056] Similarly, in some implementations, zero data is not cached (e.g., the zero data is not allocated in any of the cache subsystems 414A to 414N). In such implementations, zero data is not cached because cache entries are set to an invalid and / or ZD state, so that zero data can be returned without fetching data from any cache or main memory. This can have the advantage of saving bus bandwidth because no probe request to the cache is required to fetch the data before returning data about the read request in response to the read request.

[0057] Figure 7 This is a flowchart illustrating an example method 700 for zero data compression during a read operation by a consistency management device, such as a consistency slave device or other suitable consistency management device.

[0058] In step 710, the consistency management device receives a request to read data from an address in main memory, and determines whether an entry in the cache directory associated with the request includes an entry corresponding to the memory address. In some implementations, the consistency management device makes this determination by comparing the memory address with a tag field in the cache directory entry (or by passing the request to the cache directory, which performs the comparison), the tag field including the memory address or a portion of the memory address. In some implementations, the request includes a non-temporary read operation. Non-temporary read operations bypass the cache structure but can be observed by the consistency management device.

[0059] If condition 720 is that the cache directory does not contain an entry corresponding to the address, the consistency management device processes the data read in step 730 based on typical operations (e.g., performing a cache directory lookup and reading from the cache or main memory where appropriate). Otherwise, if condition 720 is that the cache directory does contain an entry corresponding to the address, the consistency management device determines whether the entry is invalid (e.g., whether it has a status field indicating an invalid or ZD state).

[0060] If condition 740 indicates that the cache entry is not invalid, the consistency management device processes the data read in step 730 based on typical operation. Otherwise, if condition 740 indicates that the cache entry is invalid, the consistency management device determines whether the directory entry includes an indication that the data to be read from the address in main memory includes zero data (e.g., including a ZD bit or ZD state).

[0061] If condition 750 indicates that the cache entry does not include an indication that the data to be read includes zero data, the consistency management device processes the data read in step 730 based on typical operation. Otherwise, if condition 750 indicates that the cache entry includes an indication that the data to be read from an address in main memory includes zero data, the consistency management device returns zero data in response to the request to read the data (step 760).

[0062] In some implementations, zero data is not read from main memory or cache; instead, a consistency management device (e.g., a consistency slave device) returns zero data in response to a read request based on an indication in a cache directory entry (e.g., a ZD bit or ZD state). In some cases, this can have the advantage of saving memory bandwidth.

[0063] Similarly, in some implementations, zero data is not cached (e.g., the zero data is not allocated in any of the cache subsystems 414A to 414N). In such implementations, zero data is not cached because cache entries are invalid and / or in a ZD state, allowing the coherence management device (e.g., a coherence slave device) to return zero data without fetching it from any cache or main memory. This can have the advantage of saving bus bandwidth because no probe request to the cache is required to fetch the data before it is returned in response to a read request.

[0064] It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in specific combinations, each feature or element may be used alone without other features and elements, or in various combinations with or without other features and elements.

[0065] The various functional units shown in the figures and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, accelerated processing device 116, scheduler 136, graphics processing pipeline 134, computing unit 132, SIMD unit 138) may be implemented as a general-purpose computer, processor, or processor core, or implemented as a program, software, or firmware, stored on a non-transitory computer-readable medium or another medium, executable by a general-purpose computer, processor, or processor core. The provided methods can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such instructions can be stored on a computer-readable medium). The result of this processing can be a mask, which is then used in a semiconductor manufacturing process to manufacture a processor that implements the features of this disclosure.

[0066] The methods or flowcharts provided herein can be implemented in a computer program, software, or firmware incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media such as CD-ROMs and digital versatile optical discs (DVDs).

Claims

1. A consistency management device, the consistency management device comprising: A circuit configured to receive a request for a non-temporary read of data stored at an address in main memory; The circuitry is configured to respond to requests for the non-transitory reads and to cache directories that include spare, unused, or invalid directory entries: Create cache directory entries for the address using the reserved, unused, or invalid directory entries. Set the status of the cache directory entry to invalid, wherein the invalid status indicates that no cache data copy corresponding to the address is valid, and The cache directory entry is set to include an indication that the data corresponding to the address includes zero data.

2. The consistency management apparatus of claim 1, wherein the indication includes bits in the cache directory entry, a standby state in the status field of the cache directory entry, bits in the status field of the cache directory entry, and / or bits in the shared vector field of the cache directory entry.

3. The consistency management apparatus of claim 1, wherein the consistency management apparatus is configured to return the zero data in response to the request without reading the main memory if the cache directory entry is invalid and includes the indication.

4. The consistency management device as claimed in claim 1, wherein the consistency management device includes a consistency slave device, a probe filter device, and / or a snooping filter device.

5. The consistency management device as claimed in claim 1, wherein the consistency management device receives the request from the consistency master device.

6. A method for managing cache coherency in a computer system, the method comprising: The consistency management unit receives requests for non-temporary reads of data stored at an address in main memory; In response to the request for the non-temporary read, and in response to the cache directory including spare, unused, or invalid directory entries: Create cache directory entries for the address using the spare, unused, or invalid directory entries; Set the status of the cache directory entry to invalid, wherein the invalid status indicates that no cache data copy corresponding to the address is valid, and The cache directory entry is set to include an indication that the data corresponding to the address includes zero data.

7. The method of claim 6, wherein the indication includes bits in the cache directory entry, a standby state in the status field of the cache directory entry, bits in the status field of the cache directory entry, and / or bits in the shared vector field of the cache directory entry.

8. The method of claim 6, wherein if the cache directory entry is invalid and includes the indication, the consistency management device returns the zero data in response to the request without reading the main memory.

9. The method of claim 6, wherein the consistency management device receives the request from the consistency master device.

10. A consistency management device, the consistency management device comprising: A circuit configured to receive requests for non-transitory writes to addresses in main memory; The circuitry is configured to respond to requests for the non-temporary writes, and to cache directories including spare, unused, or invalid directory entries. Create cache directory entries for the address using the reserved, unused, or invalid directory entries. The status of the cache directory entry is set to invalid, wherein the invalid status indicates that no cache data copy corresponding to the address is valid, and The cache directory entry is set to include an indication that the data corresponding to the address includes zero data.

11. The consistency management apparatus of claim 10, wherein the data includes zero data, wherein the data includes only zero and / or the request includes an instruction containing an opcode indicating that zeros are written to the address.

12. The consistency management apparatus of claim 10, wherein the indication includes at least one bit in the status field of the cache directory entry, a standby status in the status field of the cache directory entry, a bit in the status field of the cache directory entry, and / or a bit in the shared vector field of the cache directory entry.

13. The consistency management apparatus of claim 10, wherein the consistency management apparatus is configured to set the instruction in response to the request without writing to the main memory if the data includes zero data.

14. The consistency management device of claim 10, wherein the consistency management device includes a consistency slave device, a probe filter device, and / or a snoop filter device.

15. The consistency management device of claim 10, wherein the consistency management device receives the request from the consistency master device.

16. A method for managing cache coherency in a computer system, the method comprising: The consistency management device receives requests to write non-temporary data to addresses in main memory. as well as In response to the request for the non-temporary write, and in response to the cache directory including spare, unused, or invalid directory entries: Create cache directory entries for the address using the reserved, unused, or invalid directory entries. Set the status of the cache directory entry to invalid, wherein the invalid status indicates that no cache data copy corresponding to the address is valid, and The cache directory entry is set to include an indication that the data corresponding to the address includes zero data.

17. The method of claim 16, wherein the data includes zero data, wherein the data includes only zero and / or the request includes an instruction containing an opcode indicating that zeros are written to the address.

18. The method of claim 16, wherein the indication includes at least one bit in the status field of the cache directory entry, a standby status in the status field of the cache directory entry, a bit in the status field of the cache directory entry, and / or a bit in the shared vector field of the cache directory entry.

19. The method of claim 16, wherein if the data includes zero data, the consistency management device sets the instruction in response to the request without writing to the main memory.

20. The method of claim 16, wherein the consistency management device includes a consistency slave device, a probe filter device, and / or a snoop filter device.

21. The method of claim 16, wherein the consistency management device receives the request from the consistency master device.

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