A method and device for measuring the delay performance of RapidIO switch chips

Abstract

The present invention provides a method and apparatus for measuring the delay performance of a RapidIO switch chip. The method uses the RapidIO switch chip RTL code as the DUT (object under test). The DUT includes digital circuit code and analog circuit code. The analog circuit code includes a SerDes model, which is used to generate RapidIO protocol data packets as test stimuli and reflects the actual timing behavior of the physical analog circuit. The digital circuit code is transmitted within the DUT under the clock ticks corresponding to the analog circuit code. The method records the time value T1 corresponding to the rising edge of the first beat of the data packet at the switch chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat of the data at S1_I. The time difference between T2 and T1 represents the delay of the entire transmission path of the RapidIO switch chip. The method and apparatus for measuring the delay performance of a RapidIO switch chip described herein replace the object under test with the RTL design code, resolving the problem that existing testers cannot support delay testing of RapidIO switch chips at frequencies above 6.25Gbps.

Description

Technical Field

[0001] The present invention belongs to the technical field of delay performance testing of switch chips, and in particular to a method and device for measuring delay performance of a RapidIO switch chip. Background Art

[0002] The RapidIO protocol is an interconnect technology for high-performance embedded systems. It primarily serves as an internal system interconnect, supporting chip-to-chip and board-to-board communication. It boasts high bandwidth, low latency, and high reliability, and is widely used in aerospace, aviation, and military fields.

[0003] To test the transmission delay performance of a RapidIO switch chip in actual applications, a tester needs to send a data packet to the device under test and record the transmission delay of the data packet in the device.

[0004] Currently, the switching delay of the RapidIO protocol at frequencies of 6.25 Gbps and below is tested using the timestamp function of the RapidIO protocol tester. The tester can timestamp sent and received messages and calculate the difference between the timestamp values of the tester's received and sent timestamps for the same message to obtain the message delay time on the device under test and the transmission line.

[0005] With the development of RapidIO interconnect technology, the system bandwidth of RapidIO switch chips has been greatly improved, supporting performance levels from 1Gbps to 60Gbps, which has brought limitations to the use of RapidIO protocol delay testers.

[0006] Currently, there are no switch chip latency testers on the market that support RapidIO protocol version 3.0 or higher. This means that current RapidIO switch chip testers only support latency testing at frequencies of 6.25 Gbps and below. Therefore, it's impossible to use standard RapidIO protocol testers to perform switch latency testing at frequencies above 6.25 Gbps. Summary of the Invention

[0007] In view of this, the present invention aims to propose a method and apparatus for measuring the delay performance of a RapidIO switch chip, so as to solve the problem that existing methods and apparatuses cannot perform switch delay testing at frequencies above 6.25 Gbps.

[0008] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0009] On one hand, the present invention provides a method for measuring the delay performance of a RapidIO switch chip, using the RapidIO switch chip RTL code as the DUT;

[0010] The DUT includes digital circuit code and analog circuit code. The analog circuit code includes a SerDes model for generating RapidIO protocol data packets as test stimuli and reflecting the actual timing behavior of the physical analog circuit. The digital circuit code is transmitted in the DUT under the clock beat corresponding to the analog circuit code.

[0011] Record the time value T1 corresponding to the rising edge of the first beat data message at the switching chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat data at S1_I of the digital circuit code. The time difference between T2 and T1 is the delay time of the entire transmission path of the RapidIO switching chip.

[0012] Furthermore, the digital circuit code and the analog circuit code are both written in Verilog HDL language.

[0013] Furthermore, the testing method performs testing in an EDA simulation environment.

[0014] Furthermore, the DTU includes two ports, namely port0 and port1. The port0 port is connected to the Serdes model through a Serdes high-speed channel line. The output end of the port0 port is connected to the switching chip input port S0_I, and the input end is connected to the output end of the switching chip output port S0_O. The output end of the switching chip input port S0_I is connected to the input end of the switching chip output port S1_O, and the output end of the switching chip output port S1_O is connected to the input end of the port1 port. The input end of the switching chip output port S0_O is connected to the output end of the switching chip input port S1_I, and the input end of the switching chip input port S1_I is connected to the output end of the port1 port.

[0015] Furthermore, the other output end and the input end of the port1 are loop-back connected via a Serdes high-speed channel line.

[0016] Another aspect of the present invention provides a device for measuring the delay performance of a RapidIO switch chip, comprising:

[0017] The simulation circuit code module is used to generate RapidIO protocol data packets as test stimuli and reflect the actual timing behavior of the physical simulation circuit;

[0018] The digital circuit code module is transmitted in the DUT under the drive of the corresponding clock beat of the analog circuit code module;

[0019] A time recording module is used to record the time value T1 corresponding to the rising edge of the first beat data message of the digital circuit code at the switching chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat data of S1_I;

[0020] The delay calculation module is used to calculate the time difference between T2 and T1.

[0021] Furthermore, the analog circuit code module includes a traffic model platform, and the traffic model platform is connected to the DUT via a Serdes high-speed channel line.

[0022] Further, the DTU includes two ports, namely port0 and port1. The port0 port is connected to the Serdes model through a Serdes high-speed channel line. The output end of the port0 port is connected to the switching chip input port S0_I, and the input end is connected to the output end of the switching chip output port S0_O. The output end of the switching chip input port S0_I is connected to the input end of the switching chip output port S1_O, and the output end of the switching chip output port S1_O is connected to the input end of the port1 port. The input end of the switching chip output port S0_O is connected to the output end of the switching chip input port S1_I, and the input end of the switching chip input port S1_I is connected to the output end of the port1 port.

[0023] Furthermore, the other output end and input end of the port1 are loop-back connected via a Serdes high-speed channel line.

[0024] Compared with the prior art, the method and apparatus for measuring the latency performance of a RapidIO switch chip according to the present invention have the following advantages:

[0025] (1) The object to be tested in the method and apparatus for measuring the delay performance of a RapidIO switch chip of the present invention is replaced by the RTL design code, thereby solving the problem that existing testers cannot support delay testing of RapidIO switch chips at frequencies above 6.25 Gbps.

[0026] (2) The data packet format sent in the method and device for measuring the delay performance of the RapidIO switch chip described in the present invention is more flexible. The RapidIO frequency points supported by Serdes are configured mainly through code in the test platform, and the message stimulus for the delay test can be flexibly generated through the traffic model.

[0027] (3) The method and apparatus for measuring the delay performance of a RapidIO switch chip of the present invention can be used to track the code in the simulation waveform for local positioning and make corresponding analysis when the delay test result does not conform to the design theoretical index value; multiple data packets can be sent, and the maximum and minimum values can be removed, so that the average value is closer to the actual delay result. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which constitute part of the present invention, are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0029] Figure 1 This is a schematic diagram illustrating the principle of the method and device for measuring the delay performance of a RapidIO switch chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0031] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0032] like Figure 1 As shown, a method for measuring the delay performance of a RapidIO switch chip is provided, wherein the RTL code of the RapidIO switch chip is used as the DUT;

[0033] The DUT includes digital circuit code and analog circuit code. The analog circuit code includes a SerDes model for generating RapidIO protocol data packets as test stimuli and reflecting the actual timing behavior of the physical analog circuit. The digital circuit code is transmitted in the DUT under the clock beat corresponding to the analog circuit code.

[0034] The Serdes model is extracted from the actual analog circuit and can accurately reflect the timing behavior in the Serdes analog circuit.

[0035] Record the time value T1 corresponding to the rising edge of the first beat data message at the switching chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat data at S1_I of the digital circuit code. The time difference between T2 and T1 is the delay time of the entire transmission path of the RapidIO switching chip.

[0036] The digital circuit code and the analog circuit code are both written in Verilog HDL language.

[0037] This test method is performed in an EDA simulation environment. The delay performance of the RapidIO design code is simulated using EDA simulation tools, and the delay results obtained are close to the delay results of the actual physical device.

[0038] The DTU includes two ports, namely port0 and port1. The port0 port is connected to the Serdes model through a Serdes high-speed channel line. The output end of the port0 port is connected to the switching chip input port S0_I, and the input end is connected to the output end of the switching chip output port S0_O. The output end of the switching chip input port S0_I is connected to the input end of the switching chip output port S1_O, and the output end of the switching chip output port S1_O is connected to the input end of the port1 port. The input end of the switching chip output port S0_O is connected to the output end of the switching chip input port S1_I, and the input end of the switching chip input port S1_I is connected to the output end of the port1 port.

[0039] The other output end and input end of the port 1 are looped back and connected via a Serdes high-speed channel line.

[0040] A device for measuring the delay performance of a RapidIO switch chip, comprising:

[0041] The simulation circuit code module is used to generate RapidIO protocol data packets as test stimuli and reflect the actual timing behavior of the physical simulation circuit;

[0042] The digital circuit code module is transmitted in the DUT under the drive of the corresponding clock beat of the analog circuit code module;

[0043] A time recording module is used to record the time value T1 corresponding to the rising edge of the first beat data message of the digital circuit code at the switching chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat data of S1_I;

[0044] The delay calculation module is used to calculate the time difference between T2 and T1.

[0045] The simulation circuit code module includes a traffic model platform, which is connected to the DUT via a Serdes high-speed channel line. The traffic model can flexibly send various types of RapidIO protocol messages.

[0046] The DTU includes two ports, namely port0 and port1. The port0 port is connected to the Serdes model through a Serdes high-speed channel line. The output end of the port0 port is connected to the switching chip input port S0_I, and the input end is connected to the output end of the switching chip output port S0_O. The output end of the switching chip input port S0_I is connected to the input end of the switching chip output port S1_O, and the output end of the switching chip output port S1_O is connected to the input end of the port1 port. The input end of the switching chip output port S0_O is connected to the output end of the switching chip input port S1_I, and the input end of the switching chip input port S1_I is connected to the output end of the port1 port.

[0047] The other output end and input end of the port 1 are looped back and connected via a Serdes high-speed channel line.

[0048] The present invention provides a delay testing method for RapidIO switch chips based on EDA simulation tools. The measured object is the RapidIO switch chip RTL code, or the design under test (DUT). The DUT consists of digital and analog circuit code written in Verilog HDL. The analog code refers to the SerDes (Serdes) simulation portion, which is replaced by a SerDes model and accurately reflects the actual timing behavior of the physical analog circuit. The remaining digital circuit code is transmitted within the DUT according to protocol data packets and driven by the corresponding clock ticks. The time delay of this transmission path matches the delay results of the actual chip.

[0049] Here’s how it works:

[0050] like Figure 1 As shown in the figure, the traffic model platform (pkt_gen) connects to the device under test (DUT) via a SerDes (SerDes) high-speed channel. In the EDA simulation environment, the traffic model platform generates RapidIO protocol data packets as test stimulus and drives them to port 0 of the DUT. Based on the time values T1 corresponding to the rising edge of the first beat of the data packet at the core switch input port S0_I and T2 corresponding to the rising edge of the first beat of the data packet at S1_I, as recorded in the simulation waveform, the time difference between T2 and T1 is calculated to determine the delay of the packet throughout the entire transmission path of the RapidIO switch chip under test.

[0051] In the test method for the delay of the RapidIO switch chip, a Serdes high-speed channel line loopback mode is configured for port 1, that is, Figure 1 In Figure 7, the data packet is sent out from the Serdes1 high-speed channel line TX and looped back to the high-speed channel line RX, which ensures that the data packet transmits the complete path of the entire switch.

[0052] The traffic model platform sends a data packet to port 0 of the DUT, configures unicast routing to forward it to port 1, and records the timestamp value T1 corresponding to the rising edge of the first beat data message of the core switch input port S0_I in the simulation waveform. The data packet is looped back from port 1 through the Serdes1 high-speed channel and transmitted back to port 1. Configures unicast routing to forward it to port 0, records the timestamp value T2 corresponding to the rising edge of the first beat data of the core switch input port S1_I in the simulation waveform, and the data packet is transmitted to the traffic model through port 0.

[0053] By subtracting T2 and T1 from the above test, we can calculate the delay time T of the entire path of the RapidIO switch chip.

[0054] The transmission path of the T1 test is: traffic model → Serdes0 → Port0 of the design under test → core switch S0_I port, which is ①②③ in the figure;

[0055] The transmission path of the T2 test is: traffic model → Serdes0 → Port0 of the design under test → core switch S0_I port → core switch S1_O port → Port1 of the design under test → Serdes1 → Serdes1 high-speed channel self-loopback → Port1 of the design under test → core switch S1_I port, which is ①②③④⑤⑥⑦⑧⑨ in the figure;

[0056] Then, the complete transmission path of the RapidIO switch chip corresponding to the delay time T is: ④⑤⑥⑦⑧⑨.

[0057] Those skilled in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0058] In the several embodiments provided in this application, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the division of the units described above is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The above-mentioned units may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for measuring the latency performance of a RapidIO switch chip, characterized by: The RapidIO switch chip RTL code is used as the DUT; The DUT includes digital circuit code and analog circuit code. The analog circuit code includes a SerDes model, which is used to generate RapidIO protocol data packets as test stimuli and reflect the actual timing behavior of the physical analog circuit. The digital circuit code is transmitted in the DUT under the drive of the clock beat corresponding to the analog circuit code; Record the time value T1 corresponding to the rising edge of the first beat of the data message at the input port S0_I of the switching chip and the time value T2 corresponding to the rising edge of the first beat of the data at S1_I of the digital circuit code. The time difference between T2 and T1 is the delay time of the entire transmission path of the RapidIO switching chip. The DUT includes two ports, namely port0 and port1. The port0 port is connected to the Serdes model through a Serdes high-speed channel line. The output end of the port0 port is connected to the switching chip input port S0_I, and the input end is connected to the output end of the switching chip output port S0_O. The output end of the switching chip input port S0_I is connected to the input end of the switching chip output port S1_O, and the output end of the switching chip output port S1_O is connected to the input end of the port1 port. The input end of the switching chip output port S0_O is connected to the output end of the switching chip input port S1_I, and the input end of the switching chip input port S1_I is connected to the output end of the port1 port.

2. The method for measuring the delay performance of a RapidIO switch chip according to claim 1, wherein: The digital circuit code and the analog circuit code are both written in Verilog HDL language.

3. The method for measuring the delay performance of a RapidIO switch chip according to claim 1, wherein: This test method performs testing in an EDA simulation environment.

4. The method for measuring the delay performance of a RapidIO switch chip according to claim 1, wherein: The other output end and input end of the port 1 are looped back and connected via a Serdes high-speed channel line.

5. A device for measuring the delay performance of a RapidIO switch chip, characterized in that: include: The simulation circuit code module is used to generate RapidIO protocol data packets as test stimuli and reflect the actual timing behavior of the physical simulation circuit; The digital circuit code module is transmitted in the DUT under the drive of the corresponding clock beat of the analog circuit code module; A time recording module is used to record the time value T1 corresponding to the rising edge of the first beat data message of the digital circuit code at the switching chip input port S0_I and the time value T2 corresponding to the rising edge of the first beat data of S1_I; Delay calculation module, used to calculate the time difference between T2 and T1; The DUT includes two ports, namely port0 and port1. The port0 port is connected to the Serdes model through a Serdes high-speed channel line. The output end of the port0 port is connected to the switching chip input port S0_I, and the input end is connected to the output end of the switching chip output port S0_O. The output end of the switching chip input port S0_I is connected to the input end of the switching chip output port S1_O, and the output end of the switching chip output port S1_O is connected to the input end of the port1 port. The input end of the switching chip output port S0_O is connected to the output end of the switching chip input port S1_I, and the input end of the switching chip input port S1_I is connected to the output end of the port1 port.

6. The device for measuring delay performance of a RapidIO switch chip according to claim 5, characterized in that: The analog circuit code module includes a traffic model platform, and the traffic model platform is connected to the DUT via a Serdes high-speed channel line.

7. The device for measuring delay performance of a RapidIO switch chip according to claim 5, characterized in that: The other output end and input end of the port 1 are looped back and connected via a Serdes high-speed channel line.

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