Computational circuit, computing chip and method for manufacturing the same

Abstract

The present disclosure relates to an operation circuit, a computing chip and an operation circuit manufacturing method. An operation circuit is provided, comprising a plurality of operation stages, the plurality of operation stages being arranged in a pipeline structure, so that a data signal received by the operation circuit is sequentially transmitted along each of the plurality of operation stages, wherein each operation stage comprises a plurality of combinational logic stages and a first register arranged along a first direction parallel to the pipeline direction, the first register comprises a plurality of bit storage units arranged along a second direction perpendicular to the pipeline direction in a first bit order, each combinational logic stage comprises a plurality of bit operation units arranged along the second direction, and wherein a plurality of bit operation units in a first combinational logic stage of the plurality of combinational logic stages of each operation stage that receives data stored in a first register of a previous operation stage are arranged along the second direction in a second bit order different from the first bit order.

Description

Technical Field

[0001] The present disclosure generally relates to an operation circuit for performing a hash operation, a computing chip including the operation circuit, and a method of manufacturing the operation circuit. Background Art

[0002] A hash algorithm is an algorithm that takes variable-length data as input and generates a fixed-length hash value as output. Its essence is to refine information. Since 1993, the U.S. National Institute of Standards and Technology has designed and released several versions of the secure hash algorithm SHA (Secure Hash Algorithm), and SHA-256 is one of the secure hash algorithms with a hash length of 256 bits. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided an operation circuit, which includes a plurality of operation stages, which are arranged in a pipeline structure so that a data signal received by the operation circuit is transmitted in sequence along each of the plurality of operation stages, wherein each operation stage includes a plurality of combinational logic stages and a first register arranged along a first direction parallel to the pipeline direction, the first register includes a plurality of bit storage units arranged along a second direction perpendicular to the pipeline direction according to a first bit order, each combinational logic level includes a plurality of bit operation units arranged along the second direction, and wherein a plurality of bit operation units in a first combinational logic level of the plurality of combinational logic levels of each operation level that receives data stored in the first register of a previous operation level are arranged along the second direction according to a second bit order different from the first bit order.

[0004] According to a second aspect of the present disclosure, a computing chip is provided, which includes the operation circuit as described in the first aspect of the present disclosure.

[0005] According to a third aspect of the present disclosure, a method for manufacturing the operation circuit as described in the first aspect of the present disclosure is provided.

[0006] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0008] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0009] Figure 1A schematic diagram showing an exemplary pipeline structure for executing the SHA-256 algorithm;

[0010] Figure 2 and Figure 3 schematically depicts the connections between operational stages in which registers and combinatorial logic stages are arranged in sequential bit order;

[0011] Figure 4 A configuration diagram showing an example of an operation circuit according to some embodiments of the present disclosure;

[0012] Figure 5 Shows Figure 4 A configuration diagram of a comparative example of an arithmetic circuit of;

[0013] Figure 6 A configuration diagram showing an example of an operation circuit according to some embodiments of the present disclosure;

[0014] Figure 7 Shows Figure 6 A configuration diagram of a comparative example of an arithmetic circuit of;

[0015] Figure 8 and Fig. 9 The effect of the position of the bit operation units with cross-bit connections of a combinatorial logic level arranged in the second bit sequence within the combinatorial logic level on the wire length is schematically depicted.

[0016] Fig.10 A configuration diagram showing an example of an operation circuit according to other embodiments of the present disclosure;

[0017] Fig.11 Shows Fig.10 A configuration diagram of a comparative example of an arithmetic circuit of;

[0018] Fig.12 Schematically depicting the influence of the position of the bit operation unit with cross-bit connection of the combinatorial logic level arranged in the second bit order within the combinatorial logic level on the connection length;

[0019] Fig.13 A configuration diagram showing an example of an arithmetic circuit according to other embodiments of the present disclosure; and

[0020] Fig.14 A configuration diagram showing an example of an arithmetic circuit according to still other embodiments of the present disclosure.

[0021] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0022] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0024] The following description of at least one exemplary embodiment is merely illustrative in nature and is not intended to limit the present disclosure and its application or use. It will be appreciated by those skilled in the art that they are merely illustrative of exemplary ways that may be used to implement the present invention, rather than an exhaustive approach.

[0025] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0026] In order to present the inventive concept of the present disclosure more clearly and intuitively, the SHA-256 algorithm will be briefly introduced below and used as a representative example of a hash algorithm to describe the operation circuit according to the embodiment of the present disclosure. Those skilled in the art will understand that the operation circuit according to the embodiment of the present disclosure is applicable to any hash algorithm, and can even be further applied to any other suitable algorithm, and is not limited to implementing the SHA-256 algorithm.

[0027] Figure 1 A schematic diagram of an exemplary pipeline structure for executing the SHA-256 algorithm is shown. The input of SHA-256 is a maximum length less than 2 64 The output is a 256-bit data summary, i.e., a hash value. The input data is processed in 512-bit blocks. In order to implement the SHA-256 algorithm, 64 rounds of repeated operations are required for each 512-bit data block. Therefore, a pipeline structure including 64 operation stages can be used to parallelize 64 sets of data. Figure 1As shown, the pipeline structure includes the 0th operation stage to the 63rd operation stage, each operation stage includes 8 32-bit compression registers A to H for storing intermediate values ​​and 16 32-bit extension registers R0 to R1 for storing extended data. 15 The 0th operation stage can receive the input data block, then process it and provide it to the 1st operation stage. After that, each operation stage operates on the operation result received by the previous operation stage and provides its own operation result to the next operation stage. Finally, after 64 operation stages, the operation circuit can output the hash operation result of the SHA-256 algorithm executed once on the input data.

[0028] The following is a detailed discussion of the internal logic of a round of operations performed by SHA-256 at each operation level. The tth round of operations performed at the tth operation level is defined by the following operation formula (t is an integer and satisfies 0≤t≤63):

[0029] T1=H+∑1(E)+Ch(E,F,G)+K t +W t ;

[0030] T2=∑0(A)+Maj(A, B, C);

[0031] H = G;

[0032] G = F;

[0033] F = E;

[0034] E=D+T1;

[0035] D = C;

[0036] C = B;

[0037] B = A;

[0038] A=T1+T2;(Calculation formula 1)

[0039] in:

[0040]

[0041] Among them, ROTR n (x) means cyclically shifting the 32-bit variable x right by n bits; W t is a 32-bit word derived from the current 256-bit input data block; K t A 32-bit additional constant; + is modulo 2 32 Add; AND is a 32-bit bitwise AND operation; NOT is a negation operation; It is an XOR operation.

[0042] Next, we describe the 32-bit word W.t How is it derived from a 512-bit block of data? t It can be obtained according to the following calculation formula:

[0043] For 0 ≤ t ≤ 15: W t Data blocks taken directly from the input;

[0044] For 16 ≤ t ≤ 63:

[0045] W t =σ1(W t-2 )+W t-7 +σ0(W t-15 )+W t-16 (Equation 2)

[0046] in:

[0047]

[0048] Among them, ROTRn(x) means circularly shifting the 32-bit variable x right by n bits; SHRn(x) means shifting the 32-bit variable x right by n bits and filling the left side with 0; XOR operation; + is modulo 2 32 add.

[0049] Note that the formulas of the above ∑0(x), ∑1(x), σ0(x), and σ1(x) functions are specific forms for processing 32-bit data given with SHA-256 as an example. Those skilled in the art know that these functions can be adaptively adopted in other corresponding forms for processing data of other sizes (e.g., 64-bit data, etc.) in other SHA algorithms (e.g., SHA-512, etc.) or even other hash algorithms.

[0050] Therefore, as described above, the operation circuit for executing the hash algorithm can adopt a pipeline structure, including multiple operation stages according to the algorithm, and each operation stage can have a similar functional design and operation structure. Each operation stage in the pipeline structure is mainly composed of registers and combinational logic parts. For example, Figure 2 The schematic diagram shows an exemplary physical layout of a part of the operation stage, each of which may include combinational logic stages I to IV, a multi-bit adder ADD, and registers A to D, which are arranged along the pipeline direction D1 (i.e., the data signal transmission direction). It should be understood that Figure 2The arrangement order of the registers, combinational logic stages, and multi-bit adders is only exemplary and is not particularly limited in the present disclosure. Those skilled in the art can reasonably design and optimize their arrangement order as needed. For example, they can also be arranged as I, II, III, IV, ADD, D, A, B, C or A, B, C, D, ADD, I, II, III, IV, etc. In addition, although not shown, each operation stage can also include registers E to H, R0 to R1, and R2. 15 And additional combinational logic parts, etc.

[0051] As described above, each register may have 32 bit storage units for storing a 32-bit value, and each bit storage unit may store one bit of the 32-bit value. Generally, in each register, the 32 bit storage units may be arranged in a bit order from a low-order bit to a high-order bit (referred to herein as a sequential bit order) along a direction D2 perpendicular to the pipeline direction D1. The "bit order" described herein may be an order relative to the number of bits. Figure 2 As shown, the 0th to 31st bit storage units of each register A to D are arranged in the order from 0-31 bits along the direction D2.

[0052] For combinatorial logic levels I to IV for performing operations on the values ​​stored in the register according to the above algorithm (for example, combinatorial logic level I can be configured to perform ∑0 operations, combinatorial logic level II can act as a full adder, etc.), each combinatorial logic level can include 32 bit operation units, and these 32 bit operation units can each receive bit data from the corresponding bit storage unit of the register of the previous operation level or the processed bit data from the corresponding bit operation unit of the previous combinatorial logic level for processing, and work together to realize the operation function of the present combinatorial logic level. The bit operation unit can be composed of conventional logic units such as XOR gates, and each bit operation unit is not necessarily the same. Generally, the 32 bit operation units of the combinatorial logic level are arranged in the direction D2 according to the bit data storage position of the register and in the bit order from the low bit to the high bit, such as Figure 2 As shown, the 0th to 31st bit operation units of each combinational logic level I to IV are arranged in the order from 0-31 bits along the direction D2.

[0053] Depending on the specific algorithm, in some cases, the input / output between the combinatorial logic stage and the register of the previous operation stage and the next combinatorial logic stage occurs between the same bits (bit-by-bit connection), or the combinatorial logic stage and the previous combinatorial logic stage and the next combinatorial logic stage are bit-by-bit connected. Figure 2As shown, the bit data stored in the yth (y=0, 1, ..., 31)th bit storage unit of register A of operation level (t-1) is input to the yth bit operation unit of combinational logic level I of operation level t via a connection, and then the output of the yth bit operation unit of combinational logic level I of operation level t is further input to the yth bit operation unit of combinational logic level II of operation level t, and so on. In this case, the bit storage units in the register and the bit operation units in the combinational logic level are arranged in sequential bit order, and the total length of the connection is the shortest at this time.

[0054] However, depending on the specific algorithm, in other cases, the input / output between the combinatorial logic level and the register of the previous operation level and / or the next combinatorial logic level occurs between different bits (cross-bit connection), or the combinatorial logic level and the previous combinatorial logic level and / or the next combinatorial logic level are cross-bit connected. Figure 3 As shown, the bit data stored in the 28th bit storage unit of register A of operation level (t-1) is input to the 1st bit operation unit of combinational logic level I of operation level t via a connection, and then the output of the 1st bit operation unit of combinational logic level I of operation level t is further input to the 28th bit operation unit of combinational logic level II of operation level t. In this case, the bit storage units in the register and the bit operation units in the combinational logic level are arranged in sequential bit order, and the total length of the connection is obviously not the shortest at this time. Note that the inclined arrows in the figure are mainly to indicate the connection relationship and usually do not represent the actual connection. In actual manufacturing, the connection is often wired in two directions D1 and D2. For example, the connection from the 28th bit storage unit of register A of operation level (t-1) to the 1st bit operation unit of combinational logic level I of operation level t and the connection from the 1st bit operation unit of combinational logic level I of operation level t to the 28th bit operation unit of combinational logic level II of operation level t are more likely to be represented by the dotted lines in the figure in practice. However, it can be understood that the total length of the dotted line in the figure is positively correlated with the total length of the inclined arrows, that is, the length of the inclined arrows can also be used to represent the actual connection length.

[0055] When the combinatorial logic level has cross-bit connections, arranging the bit operation units in the combinatorial logic level in sequential bit order may not achieve a reduction in the length of the connection. When the connection in the operation circuit is long, it not only consumes too much wiring space when manufacturing the operation circuit in the chip, but also causes a significant increase in chip power consumption.

[0056] In the operation circuit according to the embodiment of the present disclosure, the arrangement order of the bit operation units of the combinational logic level is different from the arrangement order of the bit storage units of the register, which facilitates the realization of a shorter connection length as a whole, not only saving wiring space, but also significantly reducing chip power consumption. In some cases, even if such a different arrangement order does not lead to a shorter connection length, it can provide new connection options, thereby facilitating the optimization of the overall connection layout. Figure 4 The operation circuit 100A according to the embodiment of the present disclosure is described in detail. It should be understood that in order to highlight the main points of the present disclosure, Figure 4 Only some registers and combinational logic stages of the operation stage are shown, but the actual operation circuit may also include additional components, and in order to avoid obscuring the main points of the present disclosure, these additional components are not shown in the drawings and are not discussed in the present disclosure.

[0057] The operation circuit 100A may include a plurality of operation stages 110-0 to 110-63, which are arranged in a pipeline structure so that the data signal received by the operation circuit 100A is sequentially transmitted along each operation stage (i.e., along D1). Each operation stage 110-0 to 110-63 may include a plurality of combinational logic stages 121, 122 (as shown in the white box) and a first register 111 (as shown in the shaded box) arranged along a first direction D1 parallel to the pipeline direction. The first register 111 may include a plurality of bit storage units arranged D2 along a second direction perpendicular to the pipeline direction according to a first bit order. Each combinational logic stage may include a plurality of bit operation units arranged along the second direction D2. The plurality of bit operation units in the first combinational logic stage 121 of each operation stage that receives the data stored in the first register 111 of the previous operation stage are arranged along the second direction D2 according to a second bit order different from the first bit order.

[0058] It should be understood that although 64 operation stages are depicted in the drawings and each register in each operation stage includes 32-bit storage units and each combinational logic stage includes 32-bit operation units, as mentioned above, this article only uses the circuit for executing the SHA-256 algorithm as a non-limiting example, and the operation circuit according to the present disclosure can actually be applied to execute any hash algorithm known now or developed later (not limited to the SHA series algorithm), and can include any suitable number of operation stages, and each register and combinational logic stage can include any suitable number of units. It should also be understood that the arrangement order of the combinational logic stages and registers in each operation stage in the drawings in the first direction D1 is only exemplary and is not particularly limited in the present disclosure. Those skilled in the art can specifically design their arrangement order as needed.

[0059] In some embodiments, the first bit order may generally be a bit order from low-order bits to high-order bits. However, in other embodiments, the first bit order may also be a bit order from high-order bits to low-order bits, or may be any other suitable order. However, in the present disclosure, no particular limitation is made to the first bit order. For ease of description, in the accompanying drawings and the following text, the first bit order is described as an example. The second bit order will be described in detail hereinafter.

[0060] In some embodiments, multiple operation levels 110-0 to 110-63 may include a first operation level 110-a and a second operation level 110-b immediately following the first operation level 110-a, data stored in a first register 111 of the first operation level 110-a is input to a first combinational logic level 121 of the second operation level 110-b via a connection, and an output of the first combinational logic level 121 of the second operation level 110-b is input to a second combinational logic level 122 of the second operation level via a connection. For example, the second bit order may be configured such that the total length of the connection between the first combinatorial logic stage 121 of the second operation stage 110-b and the first register 111 of the first operation stage 110-a (which may be referred to as the input-side connection of the first combinatorial logic stage 121) and the connection with the second combinatorial logic stage 122 of the second operation stage 110-b (which may be referred to as the output-side connection of the first combinatorial logic stage 121) is less than or equal to the total length when the plurality of bit operation units in the first combinatorial logic stage 121 of the second operation stage 110-b are arranged according to the first bit order. In some embodiments, the second bit order may be configured such that the total length of the connection between the first combinatorial logic stage 121 of the second operation stage 110-b and the first register 111 of the first operation stage 110-a and the connection with the second combinatorial logic stage 122 of the second operation stage 110-b is minimized.

[0061] Specifically, the bit data stored in each bit storage unit in the first register 111 of the first operation level 110-a can be input to the corresponding bit operation unit in the first combinational logic level 121 of the second operation level 110-b via the corresponding connection, and the output of each bit operation unit in the first combinational logic level 121 of the second operation level 110-b can be input to the corresponding bit operation unit in the second combinational logic level 122 of the second operation level 110-b via the corresponding connection. Therefore, the connection between the first combinational logic level 121 of the second operation level 110-b and the first register 111 of the first operation level 110-a may, for example, include the connection between each bit operation unit in the first combinational logic level 121 of the second operation level 110-b and the corresponding bit storage unit in the first register 111 of the first operation level 110-a, and the connection between the first combinational logic level 121 of the second operation level 110-b and the second combinational logic level 122 of the second operation level 110-b may, for example, include the connection between each bit operation unit in the first combinational logic level 121 of the second operation level 110-b and the corresponding bit operation unit in the second combinational logic level 122 of the second operation level 110-b.

[0062] exist Figure 4 In the example of , the 32-bit storage units in the first register 111 of each operation stage are arranged along D2 in the order of bits 0-31, but the 32-bit operation units in the first combinational logic stage 121 are not arranged along D2 in the order of bits 0-31, but the positions of the 10th bit operation unit and the 25th bit operation unit are swapped. Figure 4 As shown, the 25th bit operation unit of the first combinatorial logic stage 121 of the operation stage 110-b receives input from the 10th bit storage unit of the first register 111 of the operation stage 110-a and provides output to the 10th bit operation unit of the second combinatorial logic stage 122 of the operation stage 110-b, and the 10th bit operation unit of the first combinatorial logic stage 121 of the operation stage 110-b receives input from the 25th bit storage unit of the first register 111 of the operation stage 110-a and provides output to the 25th bit operation unit of the second combinatorial logic stage 122 of the operation stage 110-b. In addition, the yth (y=0, 1, ..., 31 and y is not equal to 10 and 25) bit operation unit of the first combinatorial logic stage 121 of the operation stage 110-b receives input from the yth bit storage unit of the first register 111 of the operation stage 110-a and provides output to the yth bit operation unit of the second combinatorial logic stage 122 of the operation stage 110-b. Thus, Figure 5Compared with the comparative example 100A′ in which the 32-bit operation units in the first combinational logic level 121′ are arranged along D2 in the order of 0-31 bits, the total length of the input side connection and the output side connection of the second operation level 110-b is significantly shortened and minimized.

[0063] Figure 6 Another example 100B according to an embodiment of the present disclosure is schematically shown. Figure 6 In the example, the 32-bit storage units in the first register 111 of each operation stage are arranged along D2 in the order of bits 0-31. However, the 32-bit operation units in the first combinational logic stage 121″ are not arranged along D2 in the order of bits 0-31. Instead, the 5th, 10th, and 25th bit operation units are placed at the 25th, 5th, and 10th positions in the combinational logic stage 121″, respectively. Figure 6 As shown, the 25th bit operation unit of the first combinational logic level 121″ of the operation level 110-b receives input from the 10th bit storage unit of the first register 111 of the operation level 110-a and provides output to the 10th bit operation unit of the second combinational logic level 122 of the operation level 110-b, the 10th bit operation unit of the first combinational logic level 121″ of the operation level 110-b receives input from the 5th bit storage unit of the first register 111 of the operation level 110-a and provides output to the 5th bit operation unit of the second combinational logic level 122 of the operation level 110-b, the 5th bit operation unit of the first combinational logic level 121″ of the operation level 110-b receives input from the 25th bit storage unit of the first register 111 of the operation level 110-a and provides output to the 25th bit operation unit of the second combinational logic level 122 of the operation level 110-b. Thus, Figure 7 Compared with the comparative example 100B′ in the embodiment (in which the 32-bit operation units in the first combinational logic level 121′ are arranged along D2 in the order of 0-31 bits), the total length of the input-side connection and the output-side connection of the first combinational logic level 121″ of the second operation level 110-b is significantly shortened and minimized.

[0064] As a non-limiting example, the following Figure 8 and Fig. 9 Specifically analyze how to select the position of the bit operation unit with cross-bit connection in the first combinatorial logic level in the first combinatorial logic level so as to determine the second bit order. Figure 8 and Fig. 9In the figure, for the sake of clarity, only two adjacent operation stages 110-a and 110-b are shown, but it can be understood that any two adjacent operation stages of the multiple operation stages of the operation circuit can be the operation stages 110-a and 110-b shown in the figure. The dashed boxes 201′ and 202′ illustrate the situation where the first combinational logic stage for comparison is arranged in the first bit order, while the dashed boxes 201 and 202 illustrate the situation where the first combinational logic stage is arranged in the second bit order.

[0065] Assume that the first register of the first operation stage includes the 0th to mth bit storage units, and the first combinational logic stage and the second combinational logic stage of the second operation stage each include the 0th to mth bit operation units, where (m+1) is the number of bit storage units and is the number of bit operation units. Figure 8 As shown, the bit data stored in the i-th bit storage unit of the first register of the first operation stage 110-a is input to the j-th bit operation unit of the first combinational logic level of the second operation stage 110-b via a connection, and the output of the j-th bit operation unit of the first combinational logic level of the second operation stage 110-b is input to the k-th bit operation unit of the second combinational logic level of the second operation stage 110-b via a connection, where 1≤i≤m, 1≤j≤m, 1≤k≤m, and i, j, k are integers. In some embodiments, the i-th bit storage unit of the first register of the first operation level 110-a can be arranged as the i-th in the second direction D2 in the first register, the k-th bit operation unit of the second combinatorial logic level of the second operation level 110-b can be arranged as the k-th in the second direction D2 in the second combinatorial logic level, and the j-th bit operation unit of the first combinatorial logic level of the second operation level 110-b can be arranged as the x-th in the second direction D2 in the first combinatorial logic level (as shown in the dotted box 201, the j-th bit operation unit arranged as the x-th is represented as j×), where 1≤x≤m and x is an integer, and x is set so that |(xi)|+|(xk)|≤|(ji)|+|(jk)|.

[0066] from Figure 8It can be clearly seen that when the arrangement of the bit operation units of the first combinatorial logic level changes from 201′ to 201, the length of the actual connection line (indicated by the dotted line) in the D1 direction does not actually change, which can be determined by the distance between the first combinatorial logic level of the operation level 110-b and the first register of the operation level 110-a and the distance between the first combinatorial logic level and the second combinatorial logic level of the operation level 110-b. The change of the bit operation units of the first combinatorial logic level from the first bit order to the second bit order mainly causes the length of the actual connection line in the D2 direction to change (corresponding to the change in the value of (|(xi)|+|(xk)|) when x deviates from j). Therefore, the second bit order can, for example, at least partially depend on which bit storage unit of the first register the bit operation unit of the first combinatorial logic level is coupled to on the input side and which bit operation unit of the second combinatorial logic level it is coupled to on the output side.

[0067] Therefore, for the j-th bit operation unit with cross-bit connection in the first combinatorial logic level, its position x in the second bit order can be set to make |(xi)|+|(xk)|≤|(ji)|+|(jk)|, so that changing its position at least does not cause the total length of the connection to increase. The operations described above and below for the j-th bit operation unit can be performed on each bit operation unit with cross-bit connection in the first combinatorial logic level, thereby achieving overall optimization of the total length of the connection. In addition, for the bit operation unit with bit connection in the first combinatorial logic level, its position in the second bit order may not be changed relative to its position in the first bit order.

[0068] The following specifically describes how to select the position of the j-th bit operation unit in the second bit order. In some embodiments, when j is an integer between i and k, x can be set to an integer between i and k (including i and k) (optionally, x can be unequal to j). At this time, the change of x between i and k will not cause the change of the wire length, that is, |(x - i)| + |(x - k)| is always equal to |(j - i)| + |(j - k)|. This can make the position of the j-th bit operation unit have a relatively large margin range (x ∈ [i, k]). When it is necessary to adjust the position of the j-th bit operation unit in the overall optimization in consideration of the positions of other bit operation units, the rearrangement of the j-th bit operation unit within this margin range will not cause the deterioration of the total wire length. In some other embodiments, when j is an integer not falling between i and k, x can be set to an integer between i and k (including i and k), and at this time, the wire length can be significantly reduced. For illustration, assume that k < i < j and assume that the spacing between each bit storage unit on D2 and the spacing between each bit operation unit on D2 are equal to each other. As schematically shown in curve 210, when x changes from j to m, both |(x - i)| and |(x - k)| increase, resulting in an increase in the wire length; when x changes from j to i, both |(x - i)| and |(x - k)| decrease, resulting in a decrease in the wire length; when x changes between i and k, |(x - i)| increases while |(x - k)| decreases, resulting in an unchanged wire length; when x changes from k to 0, both |(x - i)| and |(x - k)| increase, resulting in an increase in the wire length. Therefore, the preferred range of x can be between i and k, as shown by the dashed box 201, and the wire length is the smallest. In this case, as shown in curve 210, the margin range of x can actually be between p and j (the wire length corresponding to p is equal to the wire length corresponding to j). When x changes within this margin range, the total length of the input side wire and the output side wire of the j-th bit operation unit in the first combinational logic stage will not deteriorate. Generally speaking, for the case where j is an integer between i and k, the original position of the j-th bit operation unit in the first bit order is relatively beneficial for wiring, but it is also allowed to arrange the j-th bit operation unit between the i-th and the k-th in the second bit order; for the case where j is an integer not falling between i and k, the j-th bit operation unit can be arranged between the p-th and the j-th in the second bit order, preferably between the i-th and the k-th, and at this time, the wire length can be significantly shortened.

[0069] Fig. 9 It is further described how to determine the second bit order when there are two bit operation units with cross-bit connections in the first combinational logic stage. As Fig. 9As shown, the bit data stored in the i′-th bit storage unit of the first register of the first operation stage 110-a is input to the j′-th bit operation unit of the first combinatorial logic level of the second operation stage 110-b via a connection, and the output of the j′-th bit operation unit of the first combinatorial logic level of the second operation stage 110-b is input to the k′-th bit operation unit of the second combinatorial logic level of the second operation stage 110-b via a connection, where 1≤i′≠i≤m, 1≤j′≠j≤m, 1≤k′≠k≤m, and i′, j′, k′ are integers. In some embodiments, the i′-th bit storage unit of the first register of the first operation stage 110-a is arranged as the i′-th in the second direction D2 in the first register, the k′-th bit operation unit of the second combinatorial logic level of the second operation stage 110-b is arranged as the k′-th in the second direction D2 in the second combinatorial logic level, and the j′-th bit operation unit of the first combinatorial logic level of the second operation stage 110-b is arranged as the x′-th in the second direction D2 in the first combinatorial logic level (as shown in the dotted box 202, the j′-th bit operation unit arranged as the x′-th is represented as j′x′), where 1≤x′≤m and x′ is an integer, and x and x′ are set so that |(xi)|+|(xk)|+|(x′-i′)|+|(x′-k′)|≤|(ji)|+|(jk)|+|(j′-i′)|+|(j′-k′)|. That is, when determining the second bit order, changes in the connection lengths of the j-th and j′-th bit operation units of the first combinatorial logic level are comprehensively considered.

[0070] In some embodiments, when j is an integer between i′ and k′ and j′ is an integer between i and k, x′ can be set to an integer between i′ and k′ (including i′ and k′) and x can be set to an integer between i and k (including i and k), for example, x=j′ and x′=j (equivalent to swapping the positions of the j-th and j′-th bit operation units in the first combinatorial logic level). In fact, the j-th and j′-th bit operation units of the first combinatorial logic level can be respectively subjected to the above-mentioned Figure 8 The described analysis finds the preferred range and margin range of x and x' respectively, and selects non-conflicting x and x' according to the margin ranges of x and x' to determine the second bit order that can optimize the total length of the connection as a whole.

[0071] In the case where there are more bit operation units with cross-bit connections in the first combinatorial logic level, the second bit order that can optimize the total length of the wiring as a whole can be determined in a similar manner as described above.

[0072] Furthermore, in some embodiments, the output of the first combinatorial logic level of the second operation level may also be input to a third combinatorial logic level among the multiple combinatorial logic levels of the second operation level via a connection, and wherein the second bit order may be configured such that the total length of the connection between the first combinatorial logic level of the second operation level and the first register of the first operation level (input side connection), the connection between the first combinatorial logic level of the second operation level and the second combinatorial logic level of the second operation level (output side connection), and the connection between the first combinatorial logic level of the second operation level and the third combinatorial logic level of the second operation level (output side connection) is less than or equal to the total length when the multiple bit operation units in the first combinatorial logic level of the second operation level are arranged in the first bit order.

[0073] like Fig.10 As shown, in the operation circuit 100C according to another embodiment of the present disclosure, a third combinational logic stage 123 of each operation stage is also shown. Fig.10 In the example of , the 32-bit storage units in the first register 111 of each operation stage are arranged along D2 in the order of bits 0-31, but the 32-bit operation units in the first combinational logic stage 121 are not arranged along D2 in the order of bits 0-31, but the positions of the 10th bit operation unit and the 25th bit operation unit are swapped. Fig.10 As shown, the 25th bit operation unit of the first combinatorial logic stage 121 of the operation stage 110-b receives the input from the 5th bit storage unit of the first register 111 of the operation stage 110-a and provides output to the 25th bit operation unit of the second combinatorial logic stage 122 of the operation stage 110-b and the 5th bit operation unit of the third combinatorial logic stage 123, and the 10th bit operation unit of the first combinatorial logic stage 121 of the operation stage 110-b receives the input from the 25th bit storage unit of the first register 111 of the operation stage 110-a and provides output to the 10th bit operation unit of the second combinatorial logic stage 122 of the operation stage 110-b and the 25th bit operation unit of the third combinatorial logic stage 123. Thus, Fig.11 Compared with the comparative example 100C′ in which the 32-bit operation units in the first combinational logic level 121′ are arranged along D2 in the order of 0-31 bits, the total length of the input side connection and the output side connection of the first combinational logic level 121 of the second operation level 110-b is significantly shortened.

[0074] As a non-limiting example, the following Fig.12 Specifically analyze how to select the position of the bit operation unit with cross-bit connection in the first combinational logic level in this case to determine the second bit order. Fig.12 In the figure, the dashed box 203' illustrates the case where the first combinatorial logic level used for comparison is arranged in a first bit order, while the dashed box 203 illustrates the case where the first combinatorial logic level is arranged in a second bit order.

[0075] like Fig.12 As shown, the bit data stored in the i-th bit storage unit of the first register of the first operation stage 110-a is input to the j-th bit operation unit of the first combinatorial logic level of the second operation stage 110-b via a connection, and the output of the j-th bit operation unit of the first combinatorial logic level of the second operation stage 110-b is input to the k-th bit operation unit of the second combinatorial logic level of the second operation stage 110-b and the h-th bit operation unit of the third combinatorial logic level of the second operation stage 110-b via a connection, where 1≤i≤m, 1≤j≤m, 1≤k≤m, 1≤h≤m, and i, j, k, h are integers. In some embodiments, the i-th bit storage unit of the first register of the first operation level 110-a can be arranged as the i-th in the second direction D2 in the first register, the k-th bit operation unit of the second combinatorial logic level of the second operation level 110-b can be arranged as the k-th in the second direction D2 in the second combinatorial logic level, the h-th bit operation unit of the third combinatorial logic level of the second operation level 110-b can be arranged as the h-th in the second direction D2 in the third combinatorial logic level, and the j-th bit operation unit of the first combinatorial logic level of the second operation level 110-b can be arranged as the x-th in the second direction D2 in the first combinatorial logic level, where 1≤x≤m and x is an integer, and x is set so that |(xi)|+|(xk)|+|(xh)|≤|(ji)|+|(jk)|+|(jh)|. In some embodiments, when j is greater than an intermediate value among i, k, and h, x can be set to be less than j but not less than the intermediate value, or when j is less than an intermediate value among i, k, and h, x can be set to be greater than j but not greater than the intermediate value.

[0076] For example, Fig.12In the example, it is assumed that k < i < j < h. As shown by curve 230, when x changes from j to h, both |(x - i)| and |(x - k)| increase while |(x - h)| decreases, generally causing the connection line length to increase; when x changes from h to m, |(x - i)|, |(x - k)|, and |(x - h)| all increase, generally causing the connection line length to increase; when x changes from j to i, both |(x - i)| and |(x - k)| decrease while |(x - h)| increases, generally causing the connection line length to decrease; when x changes from i to k, both |(x - i)| and |(x - h)| increase while |(x - k)| decreases, generally causing the connection line length to increase; when x changes from k to 0, |(x - i)|, |(x - k)|, and |(x - h)| all increase, causing the connection line length to increase. The dashed box 203 shows the situation where the j-th bit operation unit is located between the i-th and j-th positions in the second bit order. Compared with the situation of the dashed box 203', the connection line length is significantly reduced. In this case, as shown by curve 230, the margin range of x can actually be between p and j (the connection line length corresponding to p is equal to the connection line length corresponding to j). When x changes within this margin range, the total length of the input-side connection line and the output-side connection line of the j-th bit operation unit of the first combinational logic stage will not deteriorate. The situation when j is less than the median value among i, k, and h (for example, k < j < i < h) is similar and will not be elaborated here. The situation when j is greater than or less than all of i, k, and h is also similar. Preferably, x can be set to be close to or equal to the median value among i, k, and h, and there is also a corresponding margin range for facilitating selection during overall layout optimization.

[0077] In addition, in this case, for the situation where there are more bit operation units with cross-bit connections in the first combinational logic stage, the second bit order that can overall optimize the total connection line length can also be determined in a similar manner as described above (for example, determine the margin range of x for each bit operation unit with cross-bit connections respectively, and select non-conflicting x from the margin ranges of each x to determine the second bit order).

[0078] Thus, this article regarding Figure 8 describes the situation when the total number of the input-side connection line and the output-side connection line of the bit operation unit of the first combinational logic stage is a complex number (for example, 2). Regarding Fig.12The description describes the situation when the total number of input-side connections and output-side connections of the bit operation unit of the first combinatorial logic level is odd (for example, 3). Based on these descriptions, the situation when the total number of input-side connections and output-side connections of the bit operation unit of the first combinatorial logic level is 4, 5 or more (for example, receiving inputs from additional registers and / or combinatorial logic levels and / or providing outputs to additional combinatorial logic levels and / or registers) can be similarly considered, and no further details are given here.

[0079] In some other embodiments, the output of the second combinatorial logic level of the second operation level can be input to a third combinatorial logic level of the plurality of combinatorial logic levels of the second operation level via corresponding connections, wherein the plurality of bit operation units in the second combinatorial logic level of the second operation level can be arranged along the second direction according to a third bit order different from the first bit order, so that the total length of the connection between the second combinatorial logic level of the second operation level and the first combinatorial logic level of the second operation level (input side connection) and the connection between the second combinatorial logic level of the second operation level and the third combinatorial logic level of the second operation level (output side connection) is less than or equal to the total length when the plurality of bit operation units in the second combinatorial logic level of the second operation level are arranged according to the first bit order. For example, Fig.13 As shown, in the operation circuit 100D according to another embodiment of the present disclosure, the third combinational logic stage 123 of each operation stage is also shown, wherein the second combinational logic stage 122D provides input to the third combinational logic stage 123. In this example, the positions of the 10th and 25th bit operation units of the second combinational logic stage 122D are also swapped, thereby reducing the total length of the connection. In fact, the arrangement order of the bit operation units of other combinational logic stages can be similarly optimized according to the method described above for the first combinational logic stage, so that the total length of the connection of the operation circuit as a whole is reduced or even minimized.

[0080] In some other embodiments, for example, Fig.14In the example 300 shown, the above-mentioned multiple combinational logic levels of each operation level 310-0, ..., 310-a, 310-b, ..., 310-63 can be the first multiple combinational logic levels, and the first multiple combinational logic levels 321, 322, 323 and the first register 311 can be arranged in a first row along the first direction D1, wherein each operation level can also include a second multiple combinational logic levels 325, 326, 327 and a second register 312 arranged in a second row along the first direction, and the second row can be offset from the first row in the second direction D2 and aligned with the first row. The second register 312 can include a plurality of bit storage units arranged along the second direction D2 according to the first bit order. Each combinational logic level in the second multiple combinational logic levels can include a plurality of bit operation units arranged along the second direction. The multiple bit operation units in the fifth combinational logic level 325 of the second multiple combinational logic levels of each operation level that receives the data stored in the second register 312 of the previous operation level can be arranged along the second direction D2 according to a third bit order different from the first bit order.

[0081] In some examples, data stored in the second register 312 of the first operation stage 310-a can be input to the fifth combinational logic stage 325 of the second operation stage 310-b via a connection, and the output of the fifth combinational logic stage 325 of the second operation stage 310-b can be input to the sixth combinational logic stage 326 of the second operation stage 310-b via a connection, and wherein the third bit order can be configured such that the total length of the connection between the fifth combinational logic stage 325 of the second operation stage 310-b and the second register 312 of the first operation stage 310-a (input side connection) and the connection between the fifth combinational logic stage 325 of the second operation stage 310-b and the sixth combinational logic stage 326 of the second operation stage 310-b (output side connection) is less than or equal to the total length when the multiple bit operation units in the fifth combinational logic stage 325 of the second operation stage 310-b are arranged in the first bit order. In some examples, the output of the fifth combinatorial logic stage 325 of the second operation stage 310-b may also be input to the seventh combinatorial logic stage 327 of the second operation stage 310-b via a connection, and wherein the third bit order may be configured such that the total length of the connection (input side connection) between the fifth combinatorial logic stage 325 of the second operation stage 310-b and the second register 312 of the first operation stage 310-a, the connection (output side connection) between the fifth combinatorial logic stage 325 of the second operation stage 310-b and the sixth combinatorial logic stage 326 of the second operation stage 310-b, and the connection (output side connection) between the fifth combinatorial logic stage 325 of the second operation stage 310-b and the seventh combinatorial logic stage 327 of the second operation stage 310-b is less than or equal to the total length when the plurality of bit operation units in the fifth combinatorial logic stage 325 of the second operation stage 310-b are arranged in the first bit order. For example, as Fig.14As shown, the positions of the 10th and 25th bit operation units in the fifth combinatorial logic stage 325 are swapped compared to the first bit order.

[0082] In some examples, registers A to D may be arranged in the first row, and registers E to H may be arranged in the second row, wherein the first register 311 may be register A, and the second register 312 may be register E. The previous descriptions of the first register 111 and the plurality of combinational logic stages 121, 122, 123 are applicable to the first register 311 and the first plurality of combinational logic stages 321, 322, 323 and the second register 312 and the second plurality of combinational logic stages 325, 326, 327 herein, and are not repeated here.

[0083] The present disclosure may also provide a computing chip including an operation circuit as described in any of the above embodiments. The present disclosure may also provide a method for manufacturing an operation circuit as described in any of the above embodiments. In such a method, in particular, the step of arranging the bit operation units in the combinational logic level according to the second bit order and / or the third bit order as described above is included, which will not be repeated here. The operation circuit according to the present disclosure and the computing chip including the operation circuit can achieve a lower power consumption and computing power ratio.

[0084] The words "left", "right", "front", "back", "top", "bottom", "upper", "lower", "high", "lower", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe unchanged relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features previously described as being "above" other features may now be described as being "below" the other features. The device may also be otherwise oriented (rotated 90 degrees or at other orientations), and the relative spatial relationships will be interpreted accordingly.

[0085] In the specification and claims, when an element is said to be "on", "attached", "connected", "coupled", or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting another element, or one or more intermediate elements may be present. In contrast, when an element is said to be "directly" "on", "directly attached", "directly connected", "directly coupled", or "directly contacting" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0086] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any stated or implied theory given in the technical field, background, summary or detailed description. As used herein, the word "substantially" is meant to include any minor variations caused by design or manufacturing defects, device or component tolerances, environmental effects and / or other factors. The word "substantially" also allows for deviations from the perfect or ideal situation caused by parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0087] In addition, for reference purposes only, similar terms such as "first", "second", etc. may also be used herein, and thus are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words "first", "second", and other such numerical terms referring to structures or elements do not imply an order or sequence. It should also be understood that when the term "includes / comprising" is used herein, it indicates the presence of the indicated features, wholes, steps, operations, units, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or combinations thereof. In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" an object, etc.

[0088] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0089] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, which can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are equally possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0090] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A computing circuit, characterized in that: The operation circuit includes a plurality of operation stages, and the plurality of operation stages are arranged in a pipeline structure so that a data signal received by the operation circuit is sequentially transmitted along each of the plurality of operation stages. Each operation stage includes a plurality of combinational logic stages and a first register arranged along a first direction parallel to the pipeline direction, the first register includes a plurality of bit storage units arranged along a second direction perpendicular to the pipeline direction according to a first bit order, and each combinational logic stage includes a plurality of bit operation units arranged along the second direction. wherein the plurality of bit operation units in the first combinational logic level receiving the data stored in the first register of the preceding operation level in the plurality of combinational logic levels of each operation level are arranged along the second direction according to a second bit order different from the first bit order, wherein the plurality of operation stages include a first operation stage and a second operation stage immediately following the first operation stage, wherein the data stored in the first register of the first operation stage is input to the first combinational logic stage of the second operation stage via a connection, and the output of the first combinational logic stage of the second operation stage is input to the second combinational logic stage of the plurality of combinational logic stages of the second operation stage via a connection, and In which, the second bit order is configured so that the total length of the connection between the first combinatorial logic level of the second operation level and the first register of the first operation level and the second combinatorial logic level of the second operation level is less than or equal to the total length when the multiple bit operation units in the first combinatorial logic level of the second operation level are arranged according to the first bit order.

2. The operation circuit according to claim 1, characterized in that: The second bit order is configured such that a total length of a connection between the first combinatorial logic stage of the second operation stage and the first register of the first operation stage and a connection between the first combinatorial logic stage of the second operation stage and the second combinatorial logic stage of the second operation stage is minimized.

3. The operation circuit according to claim 1, characterized in that: The bit data stored in each bit storage unit in the first register of the first operation stage is input to the corresponding bit operation unit in the first combinatorial logic stage of the second operation stage via the corresponding connection line, and the output of each bit operation unit in the first combinatorial logic stage of the second operation stage is input to the corresponding bit operation unit in the second combinatorial logic stage of the second operation stage via the corresponding connection line, Among them, the connection between the first combinatorial logic level of the second operation level and the first register of the first operation level includes the connection between each bit operation unit in the first combinatorial logic level of the second operation level and the corresponding bit storage unit in the first register of the first operation level, and the connection between the first combinatorial logic level of the second operation level and the second combinatorial logic level of the second operation level includes the connection between each bit operation unit in the first combinatorial logic level of the second operation level and the corresponding bit operation unit in the second combinatorial logic level of the second operation level.

4. The operation circuit according to claim 1, characterized in that: The first register of the first operation stage includes 0th to mth bit storage units, the first combinational logic stage and the second combinational logic stage of the second operation stage each include 0th to mth bit operation units, wherein m+1 is the number of the plurality of bit storage units and is the number of the plurality of bit operation units, The bit data stored in the i-th bit storage unit of the first register of the first operation level is input to the j-th bit operation unit of the -th combinational logic level of the second operation level via a connection, and the output of the j-th bit operation unit of the first combinational logic level of the second operation level is input to the k-th bit operation unit of the second combinational logic level of the second operation level via a connection, wherein 1≤i≤m, 1≤j≤m, 1≤k≤m, and i, j, k are integers, and Among them, the i-th bit storage unit of the first register of the first operation level is arranged the i-th in the second direction in the first register, the k-th bit operation unit of the second combinatorial logic level of the second operation level is arranged the k-th in the second direction in the second combinatorial logic level, and the j-th bit operation unit of the first combinatorial logic level of the second operation level is arranged the x-th in the second direction in the first combinatorial logic level, wherein 1≤x≤m and x is an integer, and x is set so that |(xi)|+|(xk)|≤|(ji)|+|(jk)|.

5. The operation circuit according to claim 4, characterized in that: When j is an integer not falling between i and k, x is set to an integer between i and k.

6. The operation circuit according to claim 4, characterized in that: The bit data stored in the i′th bit storage unit of the first register of the first operation level is input to the j′th bit operation unit of the first combinatorial logic level of the second operation level via a connection, and the output of the j′th bit operation unit of the first combinatorial logic level of the second operation level is input to the k′th bit operation unit of the second combinatorial logic level of the second operation level via a connection, wherein 1≤i′≠i≤m, 1≤j′≠j≤m, 1≤k′≠k≤m, and i′, j′, k′ are integers, and wherein the i′th bit storage unit of the first register of the first operation level is arranged in the second register in the first register. The i′-th bit operation unit of the second combinatorial logic level of the second operation level is arranged in the k′-th direction in the second combinatorial logic level, and the j′-th bit operation unit of the first combinatorial logic level of the second operation level is arranged in the x′-th direction in the first combinatorial logic level, where 1≤x′≤m and x′ is an integer, and x and x′ are set to make |(xi)|+|(xk)|+|(x′-i′)|+|(x′-k′)|≤|(ji)|+|(jk)|+|(j′-i′)|+|(j′-k′)|.

7. The operation circuit according to claim 6, characterized in that: When j is an integer between i′ and k′ and j′ is an integer between i and k, x′ is set to an integer between i′ and k′ and x is set to an integer between i and k.

8. The operation circuit according to claim 7, characterized in that: x=j′ and x′=j.

9. The operation circuit according to claim 1, characterized in that: The output of the first combinatorial logic level of the second operation level is also input to the third combinatorial logic level of the multiple combinatorial logic levels of the second operation level via a connection, and wherein the second bit order is configured so that the total length of the connection between the first combinatorial logic level of the second operation level and the first register of the first operation level, the connection between the first combinatorial logic level of the second operation level and the second combinatorial logic level of the second operation level, and the connection between the first combinatorial logic level of the second operation level and the third combinatorial logic level of the second operation level is less than or equal to the total length when the multiple bit operation units in the first combinatorial logic level of the second operation level are arranged according to the first bit order.

10. The operation circuit according to claim 9, characterized in that: The first register of the first operation stage includes 0th to mth bit storage units, and the first combinational logic stage to the third combinational logic stage of the second operation stage each include 0th to mth bit operation units, wherein m+1 is the number of the plurality of bit storage units and is the number of the plurality of bit operation units, Wherein, the bit data stored in the i-th bit storage unit of the first register of the first operation level is input to the j-th bit operation unit of the first combinatorial logic level of the second operation level via a connection, and the output of the j-th bit operation unit of the first combinatorial logic level of the second operation level is input to the k-th bit operation unit of the second combinatorial logic level of the second operation level and the h-th bit operation unit of the third combinatorial logic level of the second operation level via a connection, wherein 1≤i≤m, 1≤j≤m, 1≤k≤m, 1≤h≤m, and i, j, k, h are integers, and Among them, the i-th bit storage unit of the first register of the first operation level is arranged the i-th in the second direction in the first register, the k-th bit operation unit of the second combinatorial logic level of the second operation level is arranged the k-th in the second direction in the second combinatorial logic level, the h-th bit operation unit of the third combinatorial logic level of the second operation level is arranged the h-th in the second direction in the third combinatorial logic level, and the j-th bit operation unit of the first combinatorial logic level of the second operation level is arranged the x-th in the second direction in the first combinatorial logic level, wherein 1≤x≤m and x is an integer, and x is set so that |(xi)|+|(xk)|+|(xh)|≤|(ji)|+|(jk)|+|(jh)|.

11. The operation circuit according to claim 10, characterized in that: When j is greater than an intermediate value among i, k, and h, x is set to be less than j and not less than the intermediate value, or When j is smaller than an intermediate value among i, k, and h, x is set to be larger than j and not larger than the intermediate value.

12. The operation circuit according to claim 1, characterized in that: The output of the second combinatorial logic level of the second operation level is input to the third combinatorial logic level of the multiple combinatorial logic levels of the second operation level via corresponding connections, wherein the multiple bit operation units in the second combinatorial logic level of the second operation level are arranged along the second direction according to a third bit order different from the first bit order, and the third bit order is configured so that the total length of the connection between the second combinatorial logic level of the second operation level and the first combinatorial logic level of the second operation level and the third combinatorial logic level of the second operation level is less than or equal to the total length when the multiple bit operation units in the second combinatorial logic level of the second operation level are arranged according to the first bit order.

13. The operation circuit according to claim 1, characterized in that: The plurality of combinatorial logic stages of each operation stage is a first plurality of combinatorial logic stages, the first plurality of combinatorial logic stages and the first register being arranged in a first row along the first direction, Each operation stage further comprises a second plurality of combinational logic stages and a second register arranged in a second row along the first direction, the second row being offset from the first row in the second direction and aligned with the first row, The second register includes a plurality of bit storage units arranged along the second direction according to the first bit order, each of the second plurality of combinatorial logic levels includes a plurality of bit operation units arranged along the second direction, wherein the plurality of bit operation units in the fifth combinatorial logic level of the second plurality of combinatorial logic levels of each operation level that receives the data stored in the second register of the previous operation level are arranged along the second direction according to a third bit order different from the first bit order, wherein the data stored in the second register of the first operation stage is input to the fifth combinational logic stage of the second operation stage via a connection, and the output of the fifth combinational logic stage of the second operation stage is input to the sixth combinational logic stage of the second plurality of combinational logic stages of the second operation stage via a connection, and In which, the third bit order is configured so that the total length of the connection between the fifth combinatorial logic level of the second operation level and the second register of the first operation level and the connection between the fifth combinatorial logic level of the second operation level and the sixth combinatorial logic level of the second operation level is less than or equal to the total length when the multiple bit operation units in the fifth combinatorial logic level of the second operation level are arranged according to the first bit order.

14. The operation circuit according to claim 13, characterized in that: The output of the fifth combinatorial logic stage of the second operation stage is also input to the seventh combinatorial logic stage of the second plurality of combinatorial logic stages of the second operation stage via a connection, and In which, the third bit order is configured so that the total length of the connection between the fifth combinatorial logic level of the second operation level and the second register of the first operation level, the connection between the fifth combinatorial logic level of the second operation level and the sixth combinatorial logic level of the second operation level, and the connection between the fifth combinatorial logic level of the second operation level and the seventh combinatorial logic level of the second operation level is less than or equal to the total length when the multiple bit operation units in the fifth combinatorial logic level of the second operation level are arranged according to the first bit order.

15. The operation circuit according to any one of claims 1 to 14, characterized in that: The first bit order is a bit order from low-order bits to high-order bits.

16. A computing chip, characterized in that: The computing chip comprises an operating circuit according to any one of claims 1-15.

17. A method for manufacturing an operational circuit according to any one of claims 1 to 15.

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