Pixel driving circuit and driving method thereof, and display panel

Abstract

The present invention provides a pixel driving circuit and a driving method thereof, and a display panel, wherein the pixel driving circuit comprises a first transistor, a second transistor, a fifth transistor, a first capacitor, a second capacitor, and a light-emitting device. The second transistor is made to store the threshold voltage of the first transistor in the first capacitor according to a second scanning signal, so as to compensate for the influence of the threshold voltage on the driving current when the first transistor drives the light-emitting device to emit light; the fifth transistor is made to make the voltage difference between the first node and the second node unrelated to the second voltage signal according to a fourth scanning signal, so as to realize the compensation of the second voltage signal, thereby improving the current attenuation problem caused by the voltage drop occurring during the signal transmission process.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] Although the display panel using active matrix driving mode in combination with row scanning technology can improve the problem of transient large current, the transistor that drives the light-emitting device to emit light will have a threshold voltage offset under long-term bias, causing the current flowing through the light-emitting device to attenuate; in addition, since there will be losses in the signal transmission process (such as voltage drop during signal transmission), the current driving the light-emitting devices in various locations in the panel will also be different, resulting in uneven display of the display panel. Summary of the invention

[0003] The embodiments of the present invention provide a pixel driving circuit and a driving method thereof, and a display panel, which can compensate for current attenuation caused by threshold voltage shift and voltage drop during signal transmission, and improve the problem of uneven display on the display panel.

[0004] An embodiment of the present invention provides a pixel driving circuit, wherein the pixel driving circuit includes a first transistor, a second transistor, a fifth transistor, a first capacitor, a second capacitor, and a light emitting device.

[0005] The gate of the first transistor is electrically connected to the first node, one of the source or the drain of the first transistor is electrically connected to the second node, and the other of the source or the drain of the first transistor is electrically connected to the third node.

[0006] The source and drain of the second transistor are electrically connected between the first node and the third node, the gate of the second transistor is electrically connected to a second scan line, and the second transistor is used to detect a threshold voltage of the first transistor according to a second scan signal.

[0007] The first capacitor is connected in series between the first node and the second node; the second capacitor is connected in series between the first node and the first voltage terminal; and the light emitting device is electrically connected between the first voltage terminal and the third node.

[0008] The source and drain of the fifth transistor are electrically connected between the second voltage terminal and the second node, the gate of the fifth transistor is electrically connected to the fourth scan line, and the fifth transistor is used to compensate the second voltage signal according to the fourth scan signal.

[0009] Optionally, in some embodiments of the present invention, the pixel driving circuit also includes a third transistor, the source and drain of the third transistor are electrically connected between the data line and the second node, and the gate of the third transistor is electrically connected to the first scan line, for transmitting a data signal to the second node according to the first scan signal.

[0010] Optionally, in some embodiments of the present invention, the pixel driving circuit also includes: a fourth transistor, the source and drain of the fourth transistor are electrically connected between the second capacitor and the first voltage terminal, and the gate of the fourth transistor is electrically connected to the first scanning line, for disconnecting the electrical connection between the first voltage terminal and the second capacitor when the fifth transistor compensates for the second voltage signal.

[0011] Optionally, in some embodiments of the present invention, the pixel driving circuit also includes: a sixth transistor, the source and drain of the sixth transistor are electrically connected between the first voltage terminal and the first node, and the gate of the sixth transistor is electrically connected to a third scan line, for initializing the potential of the first node according to a third scan signal.

[0012] Optionally, in some embodiments of the present invention, the pixel driving circuit further includes: a seventh transistor, a source and a drain of the seventh transistor being electrically connected between the light-emitting device and the third node, and a gate of the seventh transistor being electrically connected to an emission line.

[0013] Optionally, in some embodiments of the present invention, the pixel driving circuit further includes: an eighth transistor, a source and a drain of the eighth transistor being electrically connected between the second voltage terminal and the second node, and a gate of the eighth transistor being electrically connected to the emission line.

[0014] Optionally, in some embodiments of the present invention, the capacitance of the first capacitor is less than or equal to the capacitance of the second capacitor.

[0015] Optionally, in some embodiments of the present invention, the light-emitting device includes an organic light-emitting diode, a sub-millimeter light-emitting diode or a micro light-emitting diode.

[0016] An embodiment of the present invention further provides a driving method of a pixel driving circuit, which is used to drive any of the above-mentioned pixel driving circuits. The driving method includes:

[0017] Threshold voltage detection and data writing stage: the second transistor is turned on in response to the second scanning signal, so that the first transistor is connected in a diode manner.

[0018] Power supply voltage writing stage: the fifth transistor is turned on in response to the fourth scanning signal, and the second voltage signal provided by the second voltage terminal is transmitted to the second node.

[0019] An embodiment of the present invention further provides a display panel, comprising any one of the above-mentioned pixel driving circuits and a power supply, wherein the power supply is electrically connected to the first voltage terminal of the pixel driving circuit.

[0020] The embodiment of the present invention provides a pixel driving circuit and a driving method thereof, and a display panel. The pixel driving circuit includes a first transistor, a second transistor, a fifth transistor, a first capacitor, a second capacitor, and a light-emitting device. The first capacitor is connected in series between the gate and one of the source or drain of the first transistor, the second capacitor is connected in series between the gate and the first voltage terminal of the first transistor, the second transistor is electrically connected between the gate and the other of the source or drain of the first transistor, the fifth transistor is electrically connected between the second voltage terminal and one of the source or drain of the first transistor that is electrically connected to the first capacitor, and the light-emitting device is connected in series between the first voltage terminal and the other of the source or drain of the first transistor. By making the second transistor store the threshold voltage of the first transistor to the first capacitor according to the second scanning signal, the influence of the threshold voltage on the driving current is compensated when the first transistor drives the light-emitting device to emit light, and by making the fifth transistor make the voltage difference between the first node and the second node unrelated to the second voltage signal according to the fourth scanning signal, the compensation of the second voltage signal is realized, thereby improving the current attenuation problem caused by the voltage drop in the signal transmission process, and improving the display unevenness problem of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1A to Figure 1B is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0023] Figure 2A The embodiment of the present invention provides a corresponding Figure 1A A timing diagram of the pixel driving circuit shown;

[0024] Figure 2B The embodiment of the present invention provides a corresponding Figure 1B A timing diagram of the pixel driving circuit shown;

[0025] Figure 3is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0026] Figure 4A to Figure 4B Schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0028] Specifically, Figure 1A to Figure 1B Schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present invention. An embodiment of the present invention provides a pixel driving circuit, the pixel driving circuit comprising at least one light emitting device D, a first transistor T1, a second transistor T2, a first capacitor C1 and a second capacitor C2.

[0029] Optionally, the light emitting device D includes at least one of an organic light emitting diode, a sub-millimeter light emitting diode or a micro light emitting diode.

[0030] Optionally, the pixel driving circuit may include one light emitting device D, or may include a plurality of light emitting devices D. Optionally, when the pixel driving circuit includes a plurality of light emitting devices D, the plurality of light emitting devices D may be connected in series, or may be connected in parallel.

[0031] The first transistor T1 and the light emitting device D are electrically connected between a first voltage terminal VDD and a second voltage terminal VSS. The first transistor T1 is used to generate a driving current Ids for driving the light emitting device D to emit light.

[0032] Optionally, the light emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1; or, the light emitting device D is connected in series between the second voltage terminal VSS and the other of the source or drain of the first transistor T1. In the present invention, the light emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1 as an example for description.

[0033] Specifically, the gate of the first transistor T1 is electrically connected to the first node A, one of the source or the drain of the first transistor T1 is electrically connected to the second node B, the other of the source or the drain of the first transistor T1 is electrically connected to the third node C, the anode of the light emitting device D is electrically connected to the first voltage terminal VDD, and the cathode of the light emitting device D is electrically connected to the third node C. The light emitting device D is closer to the first voltage terminal VDD, which is beneficial to reducing the voltage amplitude corresponding to each transistor in the pixel driving circuit, and is more beneficial to reducing power consumption.

[0034] The first capacitor C1 is connected in series between the first node A and the second node B.

[0035] The second capacitor C2 is connected in series between the first node A and the first voltage terminal VDD.

[0036] Optionally, the capacitance of the first capacitor C1 is less than or equal to the capacitance of the second capacitor C2, so that the second capacitor C2 can achieve a better voltage stabilization effect on the gate potential of the first transistor T1.

[0037] The source and drain of the second transistor T2 are electrically connected between the first node A and the third node C, the gate of the second transistor T2 is electrically connected to the second scan line SL2, and the second transistor T2 is used to detect the threshold voltage of the first transistor T1 according to the second scan signal Scan2 transmitted by the second scan line SL2. Specifically, one of the source or drain of the second transistor T2 is electrically connected to the gate of the first transistor T1, and the other of the source or drain of the second transistor T2 is electrically connected to one of the source or drain of the first transistor T1 that is electrically connected to the light-emitting device D. The second transistor T2 makes the first transistor T1 diode-connected according to the second scan signal Scan2 transmitted by the second scan line SL2, so as to store the threshold voltage of the first transistor T1 in the first capacitor C1, and store the data signal Data in the second capacitor C2, so as to compensate for the influence of the threshold voltage on the driving current Ids when the first transistor T1 drives the light-emitting device D to emit light, thereby improving the problem of attenuation of the driving current Ids flowing through the light-emitting device D due to the threshold voltage offset of the first transistor T1.

[0038] Please continue reading Figure 1A to Figure 1BThe pixel driving circuit further includes a third transistor T3, a source and a drain of the third transistor T3 are electrically connected between the data line DL and the second node B, a gate of the third transistor T3 is electrically connected to the first scan line SL1, and the third transistor T3 is used to transmit the data signal Data to the second node B according to the first scan signal Scan1 transmitted by the first scan line SL1. Specifically, one of the source or the drain of the third transistor T3 is electrically connected to the data line DL, and the other of the source or the drain of the third transistor T3 is electrically connected to one of the source or the drain of the first transistor T1 that is electrically connected to the second voltage terminal VSS. The third transistor T3 transmits the data signal Data transmitted by the data line DL to the second node B according to the first scan signal Scan1 transmitted by the first scan line SL1.

[0039] Please continue reading Figure 1A to Figure 1B The pixel driving circuit further includes a fourth transistor T4, a source and a drain of the fourth transistor T4 are electrically connected between the second capacitor C2 and the first voltage terminal VDD, and a gate of the fourth transistor T4 is electrically connected to the first scan line SL1. Specifically, one of the source or the drain of the fourth transistor T4 is electrically connected to the second capacitor C2, and the other of the source or the drain of the fourth transistor T4 is electrically connected to the first voltage terminal VDD. The fourth transistor T4 is electrically connected to the first voltage terminal VDD and the second capacitor C2 according to the first scan signal Scan1 transmitted by the first scan line SL1.

[0040] Since the signal may have different degrees of loss during the transmission process (such as voltage drop during signal transmission), which affects the driving current Ids, in order to compensate for the attenuation of the driving current Ids caused by the voltage drop, the pixel driving circuit further includes a fifth transistor T5, the source and drain of the fifth transistor T5 are electrically connected between the second voltage terminal VSS and the second node B, the gate of the fifth transistor T5 is electrically connected to the fourth scan line SL4, and the fifth transistor T5 is used to compensate the second voltage signal according to the fourth scan signal Scan4 transmitted by the fourth scan line SL4. For details, please continue to refer to Figure 1A to Figure 1B, one of the source or the drain of the fifth transistor T5 is electrically connected to the second voltage terminal VSS, and the other of the source or the drain of the fifth transistor T5 is electrically connected to one of the source or the drain of the first transistor T1 and the first capacitor C1. The fifth transistor T5 transmits the second voltage signal provided by the second voltage terminal VSS to the second node B according to the fourth scan signal Scan4 transmitted by the fourth scan line SL4, so that the potential at the first node A changes due to capacitive coupling, so that the voltage difference between the first node A and the second node B is unrelated to the second voltage signal, thereby compensating for the second voltage signal, and then compensating for the influence of the voltage drop on the driving current Ids.

[0041] Optionally, the fourth transistor T4 can also be used to disconnect the electrical connection between the first voltage terminal VDD and the second capacitor C2 when the fifth transistor T5 compensates the second voltage signal. That is, the fourth transistor T4 is turned off when the fifth transistor T5 compensates the second voltage signal, so that the second voltage signal provided by the second voltage terminal VSS can be directly compensated through the fifth transistor T5, thereby reducing the complexity of the pixel driving circuit.

[0042] Please continue reading Figure 1A to Figure 1B , the pixel driving circuit further includes a sixth transistor T6. The source and drain of the sixth transistor T6 are electrically connected between the first voltage terminal VDD and the first node A, and the gate of the sixth transistor T6 is electrically connected to the third scan line SL3. Specifically, one of the source or the drain of the sixth transistor T6 is electrically connected to the first voltage terminal VDD, and the other of the source or the drain of the sixth transistor T6 is electrically connected to the gate of the first transistor T1. The sixth transistor T6 is used to transmit the first voltage signal provided by the first voltage terminal VDD to the first node A according to the third scan signal Scan3 transmitted by the third scan line SL3, so as to initialize the gate voltage of the first transistor T1 through the sixth transistor T6 and the first voltage signal.

[0043] Please continue reading Figure 1A to Figure 1BThe pixel driving circuit further includes a seventh transistor T7, a source and a drain of the seventh transistor T7 being electrically connected between the light emitting device D and the third node C, and a gate of the seventh transistor T7 being electrically connected to an emission line EML. Specifically, one of the source or the drain of the seventh transistor T7 is electrically connected to a cathode of the light emitting device D, and the other of the source or the drain of the seventh transistor T7 is electrically connected to one of the source or the drain of the first transistor T1, and the seventh transistor T7 switches between a conducting state and a cutting-off state according to an emission control signal EM transmitted by the emission line EML, and the seventh transistor T7 is turned on so that the first transistor T1 generates a driving current Ids for driving the light emitting device D to emit light under the action of the first voltage terminal VDD, the second voltage terminal VSS, and the data signal Data.

[0044] Optionally, see Figure 1B , the pixel circuit further includes an eighth transistor T8, the source and drain of the eighth transistor T8 are electrically connected between the second voltage terminal VSS and the second node B, and the gate of the eighth transistor T8 is electrically connected to the emission line EML. Specifically, one of the source or drain of the eighth transistor T8 is electrically connected to the other of the source or drain of the first transistor T1, and the other of the source or drain of the eighth transistor T8 is electrically connected to the second voltage terminal VSS. The eighth transistor T8 and the seventh transistor T7 are used to switch between the on state and the off state according to the emission control signal EM transmitted by the emission line EML. The seventh transistor T7 and the eighth transistor T8 are turned on so that the first transistor T1 generates a driving current for driving the light-emitting device D to emit light under the action of the first voltage terminal VDD, the second voltage terminal VSS, and the data signal Data.

[0045] It can be understood that the first transistor T1 to the eighth transistor T8 may include at least one of a P-type transistor or an N-type transistor; the active layer of the first transistor T1 to the eighth transistor T8 may include at least one of a silicon semiconductor layer or an oxide semiconductor layer. Optionally, the silicon semiconductor layer includes materials such as single crystal silicon, polycrystalline silicon, and amorphous silicon, and the oxide semiconductor layer includes at least one of materials such as zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide, and indium zinc tin oxide.

[0046] The present invention also provides a driving method of a pixel driving circuit, which is used to drive any of the above-mentioned pixel driving circuits. Specifically, Figure 2A The embodiment of the present invention provides a corresponding Figure 1A The timing diagram of the pixel driving circuit shown in FIG. Figure 2B The embodiment of the present invention provides a corresponding Figure 1B The timing diagram of the pixel driving circuit shown in FIG. 4 is taken as an example that the first transistor T1 to the eighth transistor T8 are all N-type transistors to illustrate the driving method of the pixel driving circuit.

[0047] The driving method of the pixel driving circuit includes an initialization phase t1, a threshold voltage detection and data writing phase t2, a transition phase t3, a power voltage writing phase t4 and a light emitting phase t5.

[0048] Initialization stage t1: the emission control signal EM transmitted by the emission line EML is at a low level, the data signal Data transmitted by the data line DL is Data_L, the first scan signal Scan1 transmitted by the first scan line SL1 is at a high level, the second scan signal Scan2 transmitted by the second scan line SL2 is at a low level, the third scan signal Scan3 transmitted by the third scan line SL3 is at a high level, and the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is at a low level. The second transistor T2 is turned off in response to the second scan signal Scan2, the fifth transistor T5 is turned off in response to the fourth scan signal Scan4, and the seventh transistor T7 (as Figure 1A and Figure 2A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 1B and Figure 2B The third transistor T3 and the fourth transistor T4 are turned on in response to the first scan signal Scan1, and the sixth transistor T6 is turned on in response to the third scan signal Scan3. The third transistor T3 and the fourth transistor T4 are turned on so that the data signal Data_L is transmitted to the second node B, and the potential at the second node B becomes Data_L; the sixth transistor T6 is turned on so that the first voltage signal provided by the first voltage terminal VDD is transmitted to the first node A, and the potential at the first node A becomes the voltage value Vdd corresponding to the first voltage signal; that is, the gate potential of the first transistor T1 is initialized by the first voltage signal provided by the first voltage terminal VDD through the sixth transistor T6. The voltage difference across the first capacitor C1 is Vdd-Data_L; because the sixth transistor T6 is turned on, the two ends of the second capacitor C2 are short-circuited, and the voltage difference across the second capacitor C2 is zero.

[0049] Threshold voltage detection and data writing stage t2: the emission control signal EM transmitted by the emission line EML is at a low level, the data signal Data transmitted by the data line DL is Data_H, the first scan signal Scan1 transmitted by the first scan line SL1 is at a high level, the second scan signal Scan2 transmitted by the second scan line SL2 is at a high level, the third scan signal Scan3 transmitted by the third scan line SL3 is at a low level, and the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is at a low level. The fifth transistor T5 is turned off in response to the fourth scan signal Scan4, the sixth transistor T6 is turned off in response to the third scan signal Scan3, and the seventh transistor T7 (as Figure 1A and Figure 2A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 1B and Figure 2B The second transistor T2 is turned on in response to the second scan signal Scan2, and the third transistor T3 and the fourth transistor T4 are turned on in response to the first scan signal Scan1. The third transistor T3 and the fourth transistor T4 are turned on so that the data signal Data_H is transmitted to the second node B, and the potential Data_L at the second node B changes from Data_H; the second transistor T2 is turned on so that the first transistor T1 is diode-connected, and the potential at the first node A changes from Vdd to Data_H+Vth, that is, the gate potential of the first transistor T1 changes from Vdd to Data_H+Vth. The voltage difference across the first capacitor C1 is Data_H-Data_H+Vth=Vth, and the voltage difference across the second capacitor C2 is Vdd-Data_H-Vth; that is, the threshold voltage of the first transistor T1 is stored in the first capacitor C1, and the data signal Data_H is stored in the second capacitor C2. Wherein, Vth represents the threshold voltage of the first transistor T1.

[0050] Transition stage t3: the emission control signal EM transmitted by the emission line EML is at a low level, the data signal Data transmitted by the data line DL is Data_L, the first scan signal Scan1 transmitted by the first scan line SL1 is at a high level, the second scan signal Scan2 transmitted by the second scan line SL2 is at a low level, the third scan signal Scan3 transmitted by the third scan line SL3 is at a low level, and the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is at a low level. The second transistor T2 is turned off in response to the second scan signal Scan2, the fifth transistor T5 is turned off in response to the fourth scan signal Scan4, the sixth transistor T6 is turned off in response to the third scan signal Scan3, and the seventh transistor T7 (as Figure 1A and Figure 2A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 1B and Figure 2B The third transistor T3 and the fourth transistor T4 are turned on in response to the first scan signal Scan1, and the third transistor T3 and the fourth transistor T4 are turned on so that the data signal Data_L is transmitted to the second node B, and the potential at the second node B changes from Data_H to Data_L. Due to the existence of the first capacitor C1, the potential at the first node A changes from Data_H+Vth to Data_H+Vth+V0 due to capacitive coupling; that is, the gate potential of the first transistor T1 changes from Data_H+Vth to Data_H+Vth+V0. The voltage difference across the first capacitor C1 is Data_H+Vth+V0-Data_L, and the voltage difference across the second capacitor C2 is Vdd-Data_H-Vth-V0. Wherein, V0=(Data_H-Data_L)*C1 / (C1+C2).

[0051] Power supply voltage writing stage t4: the emission control signal EM transmitted by the emission line EML is at a low level, the data signal Data transmitted by the data line DL is Data_L, the first scan signal Scan1 transmitted by the first scan line SL1 is at a low level, the second scan signal Scan2 transmitted by the second scan line SL2 is at a low level, the third scan signal Scan3 transmitted by the third scan line SL3 is at a low level, and the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is at a high level. The second transistor T2 is turned off in response to the second scan signal Scan2, the third transistor T3 and the fourth transistor T4 are turned off in response to the first scan signal Scan1, the sixth transistor T6 is turned off in response to the third scan signal Scan3, and the seventh transistor T7 (as Figure 1A and Figure 2A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 1B and Figure 2B The fifth transistor T5 is turned on in response to the fourth scan signal Scan4, and the second voltage signal provided by the second voltage terminal VSS is transmitted to the second node B, and the potential at the second node B changes from Data_L to the voltage value Vss corresponding to the second voltage signal. Due to the existence of the first capacitor C1, the potential at the first node A changes from Data_H+Vth+V0 to Data_H+Vth+V0+Vss-Data_L due to capacitive coupling; that is, the gate potential of the first transistor T1 changes from Data_H+Vth+V0 to Data_H+Vth+V0+Vss-Data_L, and the voltage difference across the first capacitor C1 is Data_H+Vth+V0+Vss-Data_L-Vss=Data_H+Vth+V0-Data_L, and the voltage difference between the first node A and the second node B is not related to the second voltage signal.

[0052] Light-emitting stage t5: the emission control signal EM transmitted by the emission line EML is at a high level, the data signal Data transmitted by the data line DL is Data_L, the first scan signal Scan1 transmitted by the first scan line SL1 is at a low level, the second scan signal Scan2 transmitted by the second scan line SL2 is at a low level, the third scan signal Scan3 transmitted by the third scan line SL3 is at a low level, the second transistor T2 is turned off in response to the second scan signal Scan2, the third transistor T3 and the fourth transistor T4 are turned off in response to the first scan signal Scan1, and the sixth transistor T6 is turned off in response to the third scan signal Scan3. When the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is at a high level (e.g. Figure 1A and Figure 2A As shown), the fifth transistor T5 is turned on in response to the fourth scan signal Scan4, the seventh transistor T7 is turned on in response to the emission control signal EM, and the first transistor T1 generates the driving current Ids for driving the light emitting device D to emit light. When the fourth scan signal Scan4 transmitted by the fourth scan line SL4 is at a low level (as shown Figure 1B and Figure 2B As shown), the fifth transistor T5 is turned off in response to the fourth scan signal Scan4, the seventh transistor T7 and the eighth transistor T8 are turned on in response to the emission control signal EM, and the first transistor T1 generates the driving current Ids for driving the light emitting device D to emit light.

[0053] Since Vgs=Data_H+Vth+V0+Vss-Data_L-Vss=Data_H+Vth+V0-Data_L, the driving current Ids=(C ox μ m W / L)*(Vgs-Vth) 2 / 2; where C ox , μ m , W, L are the unit area channel capacitance, channel mobility, channel width and channel length of the transistor respectively; then the driving current Ids=(C ox μ m W / L)*(Vgs-Vth) 2 / 2=(C ox μ m W / L)*(Data_H+V0-Data_L) 2 Therefore, the driving current Ids is not affected by the change of the threshold voltage of the first transistor T1 and the second voltage signal transmitted by the second voltage terminal VSS, thereby ensuring the stability of the light emission of the light emitting device D.

[0054] Compared to Figure 1B The pixel driving circuit shown in FIG. Figure 1A The pixel driving circuit shown uses fewer transistors, which is beneficial to saving layout space and manufacturing costs.

[0055] An embodiment of the present invention further provides a display panel, wherein the display panel includes any of the above-mentioned pixel driving circuits.

[0056] like Figure 3 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. An embodiment of the present invention further provides a display panel, wherein the display panel includes a driving circuit. Optionally, the display panel includes a passive light-emitting display panel and a self-luminous display panel; the driving circuit includes a backlight driving circuit and a pixel driving circuit. In the present invention, the driving circuit is a pixel driving circuit as an example for description.

[0057] The display panel includes a display area 100a and a non-display area 100b. The display panel implements a display function in the display area 100a. Optionally, the non-display area 100b is located outside the display area 100a. Optionally, the display panel may further include a sensing area, which may be located in the display area 100a or in the non-display area 100b. The display panel includes a sensing element arranged corresponding to the sensing area. Optionally, the sensing element includes a camera, a fingerprint sensor, a distance sensor, etc.

[0058] The display panel includes a plurality of scan lines SL, a plurality of data lines DL, a plurality of emission lines EML, and a plurality of pixel driving circuits.

[0059] The plurality of data lines DL transmit a plurality of data signals. Optionally, the plurality of data lines DL are arranged along a first direction x and extend along a second direction y in the display area 100a. The first direction x and the second direction y intersect.

[0060] The plurality of scan lines SL transmit a plurality of scan signals. Optionally, the plurality of scan lines SL are arranged along the second direction y in the display area 100a and extend along the first direction x.

[0061] The plurality of emission lines EML transmit a plurality of emission control signals. Optionally, the plurality of emission lines EML are arranged along the second direction y in the display area 100a and extend along the first direction x.

[0062] The plurality of pixel driving circuits are electrically connected to the plurality of scan lines SL, the plurality of data lines DL and the plurality of emission lines EML, so as to enable the display panel to display according to the corresponding scan signals, the data signals and the emission control signals. Optionally, the plurality of pixel driving circuits are located in the display area 100a.

[0063] The display panel further includes a driving module, and the driving module is electrically connected to the pixel driving circuit. Optionally, the driving module includes a power supply electrically connected to the first voltage terminal VDD of the pixel driving circuit. Optionally, the driving module further includes a gate driving chip and a source driving chip, the gate driving chip is electrically connected to the plurality of scanning lines SL so as to provide scanning signals for the plurality of scanning lines SL; the source driving chip is electrically connected to the plurality of data lines DL so as to transmit data signals for the plurality of data lines DL. Optionally, the driving module further includes an emission control chip, the emission control chip is electrically connected to the plurality of emission lines EML so as to provide emission control signals for the plurality of emission lines EML.

[0064] like Figure 4A to Figure 4B is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present invention. To realize the display function of the display panel, each pixel driving circuit at least includes a first transistor T1 and a light emitting device D. The first transistor T1 is used to generate a driving current for driving the light emitting device D to emit light according to the data signal, so that the light emitting device D emits light.

[0065] Optionally, the light emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1; or, the light emitting device D is connected in series between the second voltage terminal VSS and the other of the source or drain of the first transistor T1.

[0066] Optionally, in order to reduce the power consumption of the display panel, the light-emitting device D is connected in series between the first voltage terminal VDD and one of the source or drain of the first transistor T1, so that the light-emitting device D is closer to the first voltage terminal VDD, which is beneficial to reducing the voltage amplitude corresponding to each transistor in the pixel driving circuit.

[0067] Optionally, the light emitting device D includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc. Optionally, the light emitting layer of the light emitting device may include a perovskite material, a fluorescent material, a quantum dot material, etc.

[0068] Please continue reading Figure 4A to Figure 4B The pixel driving circuit further includes a second transistor T2, a first capacitor C1 and a second capacitor C2.

[0069] The first capacitor C1 is connected in series between the gate of the first transistor T1 and one of the source or drain of the first transistor T1 electrically connected to the second voltage terminal VSS; the second capacitor C2 is connected in series between the gate of the first transistor T1 and the first voltage terminal VDD.

[0070] The source and drain of the second transistor T2 are electrically connected between the gate of the first transistor T1 and one of the source or drain of the first transistor T1 electrically connected to the light emitting device D, and the gate of the second transistor T2 is electrically connected to the corresponding scan line SL. Specifically, the gate of the second transistor T2 is electrically connected to the second scan line SL2, one of the source or drain of the second transistor T2 is electrically connected to the gate of the first transistor T1, and the other of the source or drain of the second transistor T2 is electrically connected to one of the source or drain of the first transistor T1 electrically connected to the light emitting device D. The second transistor T2 is used to store the threshold voltage of the first transistor T1 to the first capacitor C1 and the data signal to the second capacitor C2 according to the second scan signal transmitted by the second scan line SL2, so as to compensate for the influence of the threshold voltage on the driving current when the first transistor T1 drives the light emitting device D to emit light, thereby improving the attenuation of the driving current flowing through the light emitting device D caused by the threshold voltage offset of the first transistor T1, and improving the display effect of the display panel.

[0071] To achieve the writing of the data signal, the pixel driving circuit further includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the corresponding scan line SL, and the source and drain of the third transistor T3 are electrically connected between the corresponding data line DL and one of the source or drain of the first transistor T1 electrically connected to the first capacitor C1. Specifically, the gate of the third transistor T3 is electrically connected to the first scan line SL1. One of the source or drain of the third transistor T3 is electrically connected to the corresponding data line DL, and the other of the source or drain of the third transistor is electrically connected to one of the source or drain of the first transistor T1 electrically connected to the first capacitor C1. The third transistor T3 is used to transmit the data signal Data transmitted by the data line DL to one of the source or drain of the first transistor T1 electrically connected to the first capacitor C1 according to the first scan signal transmitted by the first scan line SL1.

[0072] Optionally, in order to realize the controllable electrical connection between the second capacitor C2 and the first voltage terminal VDD, the pixel driving circuit further includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the corresponding scan line SL, and the source and drain of the fourth transistor T4 are electrically connected between the second capacitor C2 and the first voltage terminal VDD. Optionally, the gates of the third transistor T3 and the fourth transistor T4 are electrically connected to the same scan line SL, and the third transistor T3 and the fourth transistor T4 are both P-type transistors or both N-type transistors, so that when the third transistor T3 is turned on, the fourth transistor T4 is also turned on, ensuring the effective writing of the data signal and the effective detection of the threshold voltage of the first transistor T1. Specifically, the gate of the fourth transistor T4 is electrically connected to the first scan line SL1, one of the source or drain of the fourth transistor T4 is electrically connected to the second capacitor C2, and the other of the source or drain of the fourth transistor T4 is electrically connected to the first voltage terminal VDD.

[0073] Since the signal may be lost during transmission (such as voltage drop during signal transmission), the driving current for driving the light-emitting devices D at various locations in the display panel to emit light may be different, resulting in uneven display of the display panel. The pixel driving circuit further includes a fifth transistor T5, wherein the gate of the fifth transistor T5 is electrically connected to the corresponding scan line SL, and the source and drain of the fifth transistor T5 are electrically connected between the second voltage terminal VSS and one of the source or the drain of the first transistor T1 that is electrically connected to the first capacitor C1. Specifically, the gate of the fifth transistor T5 is electrically connected to the fourth scan line SL4, one of the source or the drain of the fifth transistor T5 is electrically connected to the second voltage terminal VSS, and the other of the source or the drain of the fifth transistor T5 is electrically connected to one of the source or the drain of the first transistor T1 and the first capacitor C1, and the fifth transistor T5 is used to transmit the second voltage signal provided by the second voltage terminal VSS to one of the source or the drain of the first transistor T1 and the first capacitor C1 according to the fourth scan signal transmitted by the fourth scan line SL4, so as to compensate for the influence of the voltage drop on the driving current through the second voltage signal.

[0074] In order to ensure that the first transistor T1 can generate accurate driving current every time the light-emitting device D emits light, the pixel driving circuit further includes a sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the corresponding scan line SL, and the source and drain of the sixth transistor T6 are electrically connected between the first voltage terminal VDD and the gate of the first transistor T1. Specifically, the gate of the sixth transistor T6 is electrically connected to the third scan line SL3, one of the source or drain of the sixth transistor T6 is electrically connected to the first voltage terminal VDD, and the other of the source or drain of the sixth transistor T6 is electrically connected to the gate of the first transistor T1, and the sixth transistor T6 is used to transmit the first voltage signal provided by the first voltage terminal VDD to the gate of the first transistor T1 according to the third scan signal transmitted by the third scan line SL3, so as to initialize the gate voltage of the first transistor T1 through the first voltage signal.

[0075] In order to realize the controllable light-emitting stage of the light-emitting device D, the pixel driving circuit further includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the corresponding emission line EML, and the source and drain of the seventh transistor T7 are electrically connected between the light-emitting device D and one of the source or the drain of the first transistor T1. Specifically, one of the source or the drain of the seventh transistor T7 is electrically connected to the cathode of the light-emitting device D, and the other of the source or the drain of the seventh transistor T7 is electrically connected to one of the source or the drain of the first transistor T1, and the seventh transistor T7 is used to make the first transistor T1 generate a driving current for driving the light-emitting device D to emit light according to the emission control signal transmitted by the emission line EML.

[0076] Optionally, the fifth transistor T5 may be turned on when the seventh transistor T7 responds to the emission control signal, so that the first transistor T1 generates a driving current between the first voltage terminal VDD and the second voltage terminal VSS to drive the light emitting device D to emit light.

[0077] Optionally, the pixel driving circuit further includes an eighth transistor T8, the gate of the eighth transistor T8 is electrically connected to the emission line EML, and the source and drain of the eighth transistor are electrically connected between the second voltage terminal VSS and the other of the source or the drain of the first transistor T1. Specifically, one of the source or the drain of the eighth transistor T8 is electrically connected to the other of the source or the drain of the first transistor T1, and the other of the source or the drain of the eighth transistor T8 is electrically connected to the second voltage terminal VSS, and the eighth transistor T8 and the seventh transistor T7 are used to enable the first transistor T1 to generate a driving current between the first voltage terminal VDD and the second voltage terminal VSS to drive the light-emitting device D to emit light according to the emission control signal transmitted by the emission line EML.

[0078] In the Nth frame period, the driving method of the pixel driving circuit includes: an initialization phase, a threshold voltage detection and data writing phase, a transition phase, a power supply voltage writing phase and a light emitting phase.

[0079] In the initialization stage, the emission control signal transmitted by the emission line EML is at a low level, the data signal Data transmitted by the data line DL is Data_L, the first scanning signal transmitted by the first scanning line SL1 is at a high level, the second scanning signal transmitted by the second scanning line SL2 is at a low level, the third scanning signal transmitted by the third scanning line SL3 is at a high level, and the fourth scanning signal transmitted by the fourth scanning line SL4 is at a low level. The second transistor T2, the fifth transistor T5, and the seventh transistor T7 (as Figure 4A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 4B The third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned on. The data signal Data_L is transmitted to one of the source or the drain of the first transistor T1 which is electrically connected to the first capacitor C1, and the first voltage signal provided by the first voltage terminal VDD is transmitted to the gate of the first transistor T1 to initialize the gate potential of the first transistor T1.

[0080] In the threshold voltage detection and data writing stage, the data signal Data transmitted by the data line DL is Data_H, the first scan signal and the second scan signal are high level, and the third scan signal, the fourth scan signal and the emission control signal are low level. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 (as Figure 4A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 4B The second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on. The data signal Data_H is transmitted to one of the source or drain of the first transistor T1 which is electrically connected to the first capacitor C1; the second transistor T2 is turned on so that the first transistor T1 is diode-connected, the gate potential of the first transistor T1 changes from Vdd to Data_H+Vth, the threshold voltage of the first transistor T1 is stored in the first capacitor C1, and the data signal Data_H is stored in the second capacitor C2. Wherein, Vth represents the threshold voltage of the first transistor T1.

[0081] In the transition phase, the data signal Data transmitted by the data line DL is Data_L, the first scanning signal is at a high level, and the second scanning signal, the third scanning signal, the fourth scanning signal and the emission control signal are at a low level. The second transistor, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 (as Figure 4A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 4B The third transistor T3 and the fourth transistor T4 are turned on, and the data signal Data_L is transmitted to one of the source or drain of the first transistor T1 that is electrically connected to the first capacitor C1. The gate potential of the first transistor T1 changes from Data_H+Vth to Data_H+Vth+V0 due to capacitive coupling. Wherein, V0=(Data_H-Data_L)*C1 / (C1+C2).

[0082] In the power supply voltage writing stage, the data signal Data transmitted by the data line DL is Data_L, the first scanning signal, the second scanning signal, the third scanning signal and the emission control signal are at a low level, and the fourth scanning signal is at a high level. The second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 (as Figure 4A As shown) or the seventh transistor T7 and the eighth transistor T8 (as shown Figure 4B The fifth transistor T5 is turned on, and the second voltage signal provided by the second voltage terminal VSS is transmitted to one of the source or the drain of the first transistor T1 which is electrically connected to the first capacitor C1, and the gate potential of the first transistor T1 changes from Data_H+Vth+V0 to Data_H+Vth+V0+Vss-Data_L due to capacitive coupling.

[0083] In the light-emitting stage, the data signal Data transmitted by the data line DL is Data_L, the emission control signal is at a high level, the first scanning signal, the second scanning signal, and the third scanning signal are at a low level; the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off. If the fourth scanning signal is at a high level (such as Figure 4A ), the fifth transistor T5 is turned on, the seventh transistor T7 is turned on in response to the emission control signal, and the first transistor T1 generates the driving current for driving the light emitting device D to emit light. If the fourth scanning signal is at a low level (as shown in FIG. Figure 4B As shown), the fifth transistor T5 is turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first transistor T1 generates the driving current for driving the light emitting device D to emit light.

[0084] The present invention further provides a display device, comprising any one of the above-mentioned driving circuits or any one of the above-mentioned display panels.

[0085] It can be understood that the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

[0086] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: a first transistor, wherein a gate of the first transistor is electrically connected to a first node, one of a source or a drain of the first transistor is electrically connected to a second node, and the other of the source or the drain of the first transistor is electrically connected to a third node; a second transistor, wherein a source and a drain of the second transistor are electrically connected between the first node and the third node, and a gate of the second transistor is electrically connected to a second scan line, and is used to detect a threshold voltage of the first transistor according to a second scan signal; A first capacitor connected in series between the first node and the second node; A second capacitor is connected in series between the first node and the first voltage terminal; a light emitting device, electrically connected between the first voltage terminal and the third node; as well as a fifth transistor, wherein a source and a drain of the fifth transistor are electrically connected between the second voltage terminal and the second node, a gate of the fifth transistor is electrically connected to a fourth scan line, and is used to compensate the second voltage signal according to a fourth scan signal, and the fifth transistor is used to transmit the second voltage signal provided by the second voltage terminal to the second node according to the fourth scan signal, so that the potential at the first node changes due to the coupling effect of the first capacitor; a third transistor, wherein a source and a drain of the third transistor are electrically connected between the data line and the second node, and a gate of the third transistor is electrically connected to the first scan line, and is used to transmit a data signal to the second node according to a first scan signal; a fourth transistor, wherein the source and the drain of the fourth transistor are electrically connected between the second capacitor and the first voltage terminal, and the gate of the fourth transistor is electrically connected to the first scan line, and is used for disconnecting the electrical connection between the first voltage terminal and the second capacitor when the fifth transistor compensates for the second voltage signal.

2. The pixel driving circuit according to claim 1, characterized in that: Also includes: A sixth transistor, wherein the source and the drain of the sixth transistor are electrically connected between the first voltage terminal and the first node, and the gate of the sixth transistor is electrically connected to the third scan line, for initializing the potential of the first node according to a third scan signal.

3. The pixel driving circuit according to claim 1, characterized in that: Also includes: A seventh transistor, wherein a source and a drain of the seventh transistor are electrically connected between the light emitting device and the third node, and a gate of the seventh transistor is electrically connected to the emission line.

4. The pixel driving circuit according to claim 3, characterized in that: Also includes: An eighth transistor, wherein a source and a drain of the eighth transistor are electrically connected between the second voltage terminal and the second node, and a gate of the eighth transistor is electrically connected to the emission line.

5. The pixel driving circuit according to claim 1, characterized in that: The capacitance of the first capacitor is less than or equal to the capacitance of the second capacitor.

6. The pixel driving circuit according to claim 1, characterized in that: The light emitting device includes an organic light emitting diode, a sub-millimeter light emitting diode or a micro light emitting diode.

7. A driving method for a pixel driving circuit, characterized in that: Used to drive the pixel driving circuit according to any one of claims 1 to 6, the driving method comprising: Threshold voltage detection and data writing stage: the second transistor is turned on in response to the second scanning signal, so that the first transistor is connected in a diode manner; Power supply voltage writing stage: the fifth transistor is turned on in response to the fourth scanning signal, and the second voltage signal provided by the second voltage terminal is transmitted to the second node.

8. A display panel, characterized in that: It comprises a power supply and the pixel driving circuit according to any one of claims 1 to 6, wherein the power supply is electrically connected to the first voltage terminal of the pixel driving circuit.

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