Semiconductor packaging structure

Abstract

This invention discloses a semiconductor packaging structure, comprising: a semiconductor die; a first molding compound layer surrounding the semiconductor die; a first redistribution layer structure formed on the non-active surface of the semiconductor die and the first molding compound layer; a second molding compound layer formed on the first redistribution layer structure; an insulating capping layer covering the second molding compound layer; and a first antenna electrically coupled to the semiconductor die, comprising: a first antenna element formed in the first redistribution layer structure; and a second antenna element formed between the second molding compound layer and the insulating capping layer. This allows the insulating capping layer to protect the second antenna element, preventing antenna oxidation and surface damage during testing, and also reinforces the second antenna element, reducing the possibility of it detaching.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor packaging structure. Background Technology

[0002] To ensure the continued miniaturization and versatility of electronic products and communication devices, semiconductor packages must be small in size, support multi-pin connections, operate at high speeds, and possess high functionality. Furthermore, in high-frequency applications such as radio frequency (RF) system-in-package (SiP) components, antennas are typically used to enable wireless communication.

[0003] When constructing wireless communication packages with antennas, the package design needs to provide good antenna characteristics (e.g., high efficiency, wide bandwidth) while offering a reliable and low-cost packaging solution. In this traditional SiP structure, discrete antenna elements are individually packaged or mounted on a printed circuit board (PCB) or package. Because the PCB needs to provide additional area for the antenna components mounted on it, it is difficult to reduce device size. Furthermore, antennas mounted on the package can cause problems such as antenna oxidation, delamination between the antenna and the underlying package, and / or surface damage during testing. These issues reduce the reliability, yield, and throughput of the semiconductor package structure.

[0004] Therefore, a novel semiconductor packaging structure is desired. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor packaging structure that can avoid antenna oxidation and damage to the antenna surface, thereby solving the above problems.

[0006] According to a first aspect of the present invention, a semiconductor package structure is disclosed, comprising:

[0007] Semiconductor grains;

[0008] A first molding compound layer surrounds the semiconductor die;

[0009] A first redistribution layer structure is formed on the non-active surface of the semiconductor grain and the first molding compound layer;

[0010] A second molding compound layer is formed on the first redistribution layer structure;

[0011] An insulating cover layer covering the second molding compound layer; and

[0012] The first antenna, electrically coupled to the semiconductor die, includes:

[0013] A first antenna element is formed in the first redistribution layer structure; and

[0014] A second antenna element is formed between the second molding compound layer and the insulating cover layer.

[0015] The semiconductor package provided by this invention includes: a semiconductor die; a first molding compound layer surrounding the semiconductor die; a first redistribution layer structure formed on the non-active surface of the semiconductor die and the first molding compound layer; a second molding compound layer formed on the first redistribution layer structure; an insulating capping layer covering the second molding compound layer; and a first antenna electrically coupled to the semiconductor die, including: a first antenna element formed in the first redistribution layer structure; and a second antenna element formed between the second molding compound layer and the insulating capping layer. This allows the insulating capping layer to protect the second antenna element, preventing antenna oxidation and surface damage during testing, and also reinforces the second antenna element, reducing the possibility of it detaching. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0017] Figure 2 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0018] Figure 3 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0019] Figure 4 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0020] Figure 5 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments.

[0021] Figure 6 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments. Detailed Implementation

[0022] The following description illustrates preferred embodiments of the present invention. These embodiments are merely illustrative of the technical features of the invention and are not intended to limit the scope of the invention. The scope of the invention should be determined with reference to the appended claims.

[0023] The invention will now be described with reference to specific embodiments and certain accompanying drawings, but the invention is not limited thereto and is limited only by the claims. The described drawings are illustrative only and not restrictive. In the drawings, for illustrative purposes, the dimensions of some elements may be exaggerated rather than drawn to scale. In practice, dimensions and relative dimensions do not correspond to actual dimensions.

[0024] Figure 1 This is a cross-sectional view of an exemplary semiconductor package structure 10 according to some embodiments. In some embodiments, the semiconductor package structure 10 is a wafer-level semiconductor package structure and a flip-chip semiconductor package structure. Figure 1 As shown, according to some embodiments, the semiconductor package structure 10 is mounted on a substrate (not shown). For example, the semiconductor package structure may be a system-on-chip (SOC) package structure. Furthermore, the substrate may include a printed circuit board (PCB) and may be formed of polypropylene (PP). Alternatively, the substrate is a package substrate. The semiconductor package structure 10 is mounted to the substrate via a bonding process. For example, the semiconductor package structure 10 includes a conductive structure 150, which is mounted on the substrate via a bonding process and electrically connected to the substrate. In some embodiments, such as Figure 1 As shown, each conductive structure 150 includes a conductive bump structure, such as a copper bump or a solder bump structure. Alternatively, each conductive structure 150 includes a conductive post structure, a conductive wire structure, or a conductive paste structure.

[0025] In some embodiments, the semiconductor package structure 10 further includes a semiconductor die 100, such as a system-on-chip (SOC) die. For example, the SOC die may include a microcontroller (MCU), a microprocessor (MPU), a power management integrated circuit (PMIC), a global positioning system (GPS) device, or a radio frequency (RF) device, or any combination thereof. It should be noted that the number of semiconductor dies integrated in the semiconductor package structure 10 is not limited to the number disclosed in the embodiments.

[0026] In some embodiments, the semiconductor die 100 has two opposing sides. More specifically, the semiconductor die 100 has a non-active surface 100a (also referred to as the back surface, or passive surface) and an active surface 100b (also referred to as the front surface, or active surface) opposite the non-active surface 100a. Pads 101 of the semiconductor die 100 are disposed on the active surface 100b and electrically connected to the circuitry of the semiconductor die 100 (not shown). In some embodiments, the pads 101 of the semiconductor die 100 belong to the uppermost metal layer. It should be noted that the number of semiconductor dies integrated in the semiconductor package structure 10 is not limited to the number disclosed in this embodiment, and may be, for example, one, two, three, or more.

[0027] In some embodiments, the semiconductor package structure 10 further includes a molding compound layer 108 surrounding the semiconductor die 100. In some embodiments, the molding compound layer 108 may be formed of epoxy resin, resin, moldable polymer, or similar materials. The molding compound layer 108 may be applied while substantially liquid and then cured by a chemical reaction, such as in an epoxy resin or resin. In some other embodiments, the molding compound layer 108 may be an ultraviolet (UV) or thermosetting polymer that can be applied as a gel or stretchable solid capable of being disposed around the semiconductor die 100 and then cured by a UV or thermosetting process. The molding compound layer 108 may be cured using a mold (not shown).

[0028] In some embodiments, the semiconductor package structure 10 further includes a redistribution layer (RDL) structure 106 formed beneath the semiconductor die 100 and the molding compound layer 108. The RDL structure 106 is also referred to as a fan-out structure. The RDL structure 106 is disposed on the active surface 100b of the semiconductor die 100 and electrically connected to the semiconductor die 100 via pads 101. Furthermore, a conductive structure 150 is mounted on and electrically coupled to the RDL structure 106, such that the conductive structure 150 is separated from the molding compound layer 108 and the semiconductor die 100 by the RDL structure 106. In other words, the conductive structure 150 does not contact the molding compound layer 108 and the semiconductor die 100.

[0029] In some embodiments, the RDL structure 106 includes one or more conductive traces (e.g., conductive trace 103, etc.) disposed in an inter-metal dielectric (IMD) layer 102. The conductive trace 103 is disposed at a first level of the IMD layer 102, and at least one conductive trace 103 is electrically coupled to a semiconductor die 100. Furthermore, conductive trace 105 is disposed at a second level different from the first level of the IMD layer 102. Additionally, at least one conductive trace 105 is electrically coupled to one or more conductive structures 150, such that the conductive structures 150 are electrically coupled to the semiconductor die 100 via the RDL structure 106.

[0030] In some embodiments, the IMD layer 102 includes a first sub-dielectric layer 102a and a second sub-dielectric layer 102b continuously stacked from the active surface 100b of the semiconductor die 100, such that conductive traces 103 are formed in the semiconductor die 100. The first sub-dielectric layer 102a and conductive traces 105 are formed in the second sub-dielectric layer 102b. It should be noted that... Figure 1 The number of conductive traces and sub-dielectric layers in the RDL structure 106 shown is merely an example and not a limitation of the invention. The number of conductive traces and sub-dielectric layers in this embodiment can be set as needed.

[0031] In some embodiments, the IMD layer 102 is formed of an organic material, including a polymer substrate material, or an organic material, including silicon nitride (SiNX), silicon oxide (SiOX), graphene, etc. For example, the first sub-dielectric layer 102a and the second sub-dielectric layer 102b are made of a polymer substrate. In some other embodiments, the IMD layer 102 is a high-k dielectric layer (k is the dielectric constant of the dielectric layer). In some other embodiments, the IMD layer 102 may be formed of a photosensitive material, including a dry film photoresist or an adhesive tape.

[0032] In some embodiments, the semiconductor package structure 10 further includes one or more via structures 110 formed in and through the molding compound layer 108. The via structures 110 are electrically coupled to conductive traces 103 of the RDL structure 106. The via structure 110 may be referred to as a through-insulator via (TIV) and is formed of copper. Therefore, the via structure 110 may also be referred to as a conductive via.

[0033] In some embodiments, the semiconductor package structure 10 further includes an RDL structure 120 formed over the semiconductor die 100 and the molding compound layer 108. The RDL structure 120 may have a structure similar to that of the RDL structure 106 and is also referred to as a fan-out structure. In some embodiments, the non-active surface 100a of the semiconductor die 100 is adhered to the RDL structure 120 via an adhesion layer 114, such that the semiconductor die 100 and the molding compound layer 108 are interposed between the RDL structure 106 and the RDL structure 120.

[0034] In some embodiments, an RDL structure 120 is disposed on a molding compound layer 108 and a semiconductor die 100, and the RDL structure 120 includes an IMD layer 121 and conductive traces (not shown) within the IMD layer 121. The IMD layer 121 may be a single-layer or multi-layer structure. The methods and materials used to form the IMD layer 121 may be the same as or similar to those used to form the IMD layer 102. Similarly, the methods and materials used to form the conductive traces of the RDL structure 120 may be the same as or similar to those used to form the conductive traces 103 and 105 of the RDL structure 106. In other words, the process used to form the RDL structure 106 can be used to form the RDL structure 120.

[0035] In some embodiments, the semiconductor package structure 10 further includes a molding compound layer 122 formed on an RDL structure 120 above the non-active surface 100a of the semiconductor die 100 and the molding compound layer 108. Therefore, the RDL structure 120 separates the semiconductor die 100 from the molding compound layer 122. In some embodiments, the method and materials used to form the molding compound layer 122 may be the same as or similar to the method and materials used to form the molding compound layer 108.

[0036] In some embodiments, the semiconductor package structure 10 further includes one or more antennas 112 and one or more antennas 130 within the semiconductor package structure 100, and both antennas 112 and 130 are electrically coupled to the semiconductor die 100. More specifically, in some embodiments, the antenna 112 is formed in a molding compound layer 108, and a via structure 110 located in the molding compound layer 108 is disposed between the semiconductor die 100 and the antenna 112. The antenna 112 is electrically connected to the semiconductor die 100 via at least one of the conductive traces 103 of the RDL structure 106. In some embodiments, the antenna 112 is a dipole antenna. In some embodiments, the methods and materials used to form the antenna 112 may be the same as or similar to the methods and materials used to form the via structure 110.

[0037] In some embodiments, unlike antenna 112, antenna 130 includes a first antenna element 130a and a second antenna element 130b separated from the first antenna element 130a. More specifically, in some embodiments, the first antenna element 130a is embedded in the IMD layer 121 of the RDL structure 120, such that the first antenna element 130a is formed between molding compound layer 108 and molding compound layer 122. The second antenna element 130b is formed on and in direct contact with molding compound layer 122, such that the first antenna element 130a is separated from the second antenna element 130b by molding compound layer 122. In some embodiments, a via structure 110 formed in molding compound layer 122 electrically couples at least one of the first antenna element 130a and the conductive trace 103 of RDL structure 106, such that semiconductor die 100 is electrically coupled to antenna 130 (first antenna element 130a). Alternatively, the second antenna element 130b may not be electrically coupled to semiconductor die 100. In some embodiments, the antenna 130 (including a first antenna element 130a and a second antenna element 130b) is a patch antenna that uses a molding compound layer 122 as a resonator. That is, the first antenna element 130a and the second antenna element 130b are spaced apart by the molding compound layer 122, and the molding compound layer 122 serves as the resonator or resonant cavity. Therefore, the thickness of the molding compound layer 122 depends on the desired dielectric constant (Dk) and desired dissipation factor (Df, also known as the loss tangent) of the antenna 130. In some embodiments, the first antenna element 130a may be formed from at least one conductive trace of the RDL structure 120. In these cases, the method and materials used to form the first antenna element 130a may be the same as or similar to those used to form conductive traces 103 and 105 in the IMD layer 102 of the RDL structure 106. In this embodiment, the first antenna element 130a and the second antenna element 130b are vertically aligned, or their vertical positions coincide, or the first antenna element 130a is directly above the second antenna element 130b (the second antenna element 130b is directly below the first antenna element 130a) or above it, and both can be the same size and shape. Here, "directly above" or "directly below" can be understood as meaning that, viewed from a top-down angle (perspective), the projections of the two elements (e.g., their horizontal projections) at least partially overlap, and preferably, most of their areas overlap, or more specifically, at least their center positions overlap; or it can also be understood as excluding the case where the projections of the two elements do not overlap at all (or, viewed from a top-down angle, they do not overlap at all).

[0038] In some embodiments, the semiconductor package structure 10 further includes an insulating capping layer 140 that covers and directly contacts the top surface 122a of the molding compound layer 122 and the top surface and sidewall surfaces of the second antenna element 130b, such that the second antenna element 130b is formed between the molding compound layer 122 and a portion thereof. A portion of the insulating capping layer 140 may be spaced apart from the molding compound layer 122 by the second antenna element 130b, and another portion of the insulating capping layer 140 may be in direct contact with the molding compound layer 122.

[0039] In some embodiments, the insulating capping layer 140 serves as a protective layer to prevent oxidation or damage to the second antenna element 130b of the antenna 130. The insulating capping layer 140 has a substantially flat top surface 140a and a thickness T1 measured from the top surface 122a of the molding compound layer 122 to the top surface 140a. In some embodiments, the thickness T1 is in the range of about 10 μm to about 100 μm. In some embodiments, the insulating capping layer 140 is made of polyimide, silicon nitride, silicon oxynitride, Ajinomoto™ reinforcement film (ABF, Ajinomoto...). TM Made of build-up film or other suitable organic materials. In some embodiments, the insulating cover layer 140 is formed by a lamination process, in which case, such as Figure 1As shown, the insulating cover layer 140 has a substantially flat top surface 140a. In this embodiment, the first antenna element 130a and the second antenna element 130b are spaced apart by a molding compound layer 122. Therefore, the molding compound layer 122 can be used as a resonator, and it can protect the antenna element, improve the mechanical strength of the semiconductor package, and provide stable support for the antenna element. In this embodiment, the first antenna element 130a is disposed in the RDL structure 120, which facilitates the electrical connection between the first antenna element 130a and the semiconductor die 100. Furthermore, embedding it in the RDL structure 120 not only facilitates manufacturing but also better protects the first antenna element 130a, preventing antenna oxidation and surface damage during testing. The second antenna element 130b is mounted on the molding compound layer 122 and covered by the insulating cover layer 140. The first antenna element 130a and the second antenna element 130b are arranged vertically, reducing space occupation and thus the (lateral) size of the package. The insulating cover layer 140 and the molding compound layer 122 protect the second antenna element 130b from oxidation and surface damage during testing. The insulating cover layer 140 also reinforces the second antenna element 130b, reducing the possibility of it detaching. Furthermore, in this embodiment, an antenna 112 can be provided and mounted in the molding compound layer 108, further increasing antenna density to meet broader needs, improve design flexibility, and further reduce space occupation, thereby reducing the package size. The first antenna element 130a and the second antenna element 130b are used to transmit signals upwards, while the antenna 112 is used to transmit signals laterally, thus allowing the semiconductor package structure to have more signal transmission directions to meet a wider range of needs. Meanwhile, the antenna 112, mounted within the molding compound layer 108, allows for easier connection to the semiconductor die 100 using shorter lines, reducing wiring complexity and improving signal transmission efficiency. The above-described solution in this embodiment also ensures stable mounting of the first antenna element 130a and the second antenna element 130b, reducing the possibility of antenna detachment and increasing the reliability, yield, and production volume of the semiconductor packaging structure.

[0040] Figure 2 This is a cross-sectional view of an exemplary semiconductor package structure 20 according to some embodiments of the present invention. For the sake of brevity, references to previous documents may be omitted below. Figure 1 Description of elements in those identical or similar embodiments. In this embodiment, the semiconductor package structure 20 is similar to... Figure 1The semiconductor package structure 10 shown includes, in addition to the semiconductor package structure 20, an adhesive layer 124 formed between the molding compound layer 122 and the insulating cover layer 140. The adhesive layer 124 between the molding compound layer 122 and the second antenna element 130b of the antenna 130 can improve the adhesion between the molding compound layer 122 and the second antenna element 130b, for example, by increasing the adhesive strength to prevent detachment, thus ensuring the stability of the package structure. At this time, the second antenna element 130b is also located between the molding compound layer 122 and the insulating cover layer 140. The second antenna element 130b is surrounded by and in direct contact with the insulating cover layer 140. The second antenna element 130b may not be in direct contact with the molding compound layer 122 (e.g., separated by the adhesive layer 124).

[0041] In some embodiments, the adhesive layer 124 is formed of a material selected from polyimide, silicon nitride, silicon oxynitride, or ABF. In some embodiments, the adhesive layer 124 is formed of a material different from that of the insulating cover layer 140. By using different materials, the adhesive layer 124 and the insulating cover layer 140 can have different Dk and Df values, thus allowing the thickness of the insulating cover layer 140 to be adjusted according to the antenna requirements to achieve the desired thickness, thereby increasing design flexibility. For example, if the insulating cover layer 140 is formed of polyimide, then the adhesive layer 124 is formed of a material other than polyimide (e.g., silicon nitride, silicon oxynitride, ABF). In this embodiment, forming the adhesive layer 124 between the molding compound layer 122 and the insulating cover layer 140 can further improve the stability of the semiconductor package structure and further reduce the possibility of the antenna (second antenna element 130b) falling off or detaching, ensuring the secure mounting of the antenna element. Furthermore, in addition to the molding compound layer 122, an adhesive layer 124 is provided between the first antenna element 130a and the second antenna element 130b. (The material of the adhesive layer 124 can be different from that of the molding compound layer 122, thus having different Dk and Df values.) This allows the Dk and Df values ​​of the resonator (including the molding compound layer 122 and the adhesive layer 124) between the first antenna element 130a and the second antenna element 130b to be freely adjusted (compared to only having the molding compound layer 122), thereby increasing design flexibility to adapt to different needs. It also allows for a reduction in the thickness of the molding compound layer 122 (the thickness of the molding compound layer 122 is reduced and then supplemented by the adhesive layer 124, which is thinner than the reduced portion of the molding compound layer 122, thus reducing the thickness or distance between the first antenna element 130a and the second antenna element 130b), thereby reducing the overall thickness of the semiconductor package structure and consequently reducing the size or height of the semiconductor package structure. This also allows for greater flexibility in material selection for the first antenna element 130a and the second antenna element 130b, reducing antenna loss. In this embodiment, the molding compound layer 122, adhesive layer 124, and insulating cover layer 140 can be made of different materials, each with different Dk and Df values. Therefore, the thickness of each layer in the molding compound layer 122, adhesive layer 124, and insulating cover layer 140 can be flexibly adjusted according to antenna requirements to meet different thickness and antenna requirements (e.g., the Dk and Df values ​​of the adhesive layer 124 are larger or smaller than those of the molding compound layer 122, the insulating cover layer 140 are larger or smaller than those of the molding compound layer 122, and the adhesive layer 124 are larger or smaller than those of the insulating cover layer 140), further increasing design flexibility.

[0042] Figure 3This is a cross-sectional view of an exemplary semiconductor package structure 30 according to some embodiments of the present invention. For the sake of brevity, references to previous documents may be omitted below. Figure 1 Description of elements in those identical or similar embodiments. In this embodiment, the semiconductor package structure 30 is similar to... Figure 1 The semiconductor package structure 10 shown is shown. The insulating cover layer 140 in the semiconductor package structure 10 (and...) Figure 1 Unlike the example shown, the insulating capping layer 140' in the semiconductor package structure 30 has a substantially uniform thickness T2, and the top surface and sidewall surface of the second antenna element 130b of the antenna 130 are conformally covered by the insulating capping layer 140'. Conformal coverage can mean that it is formed simultaneously on the top surface and sidewall surface, and structurally, the insulating capping layer 140' has equal thickness and is uniformly distributed at both locations. In this embodiment, the insulating capping layer 140' can be formed by a coating process, thus the thickness of the entire insulating capping layer 140' is relatively uniform. In addition to the above-mentioned features, this embodiment also includes... Figure 1 In addition to the advantages of the semiconductor packaging structure 10 shown, it is also easier to manufacture.

[0043] In some embodiments, the insulating cover layer 140' has a thickness measured from the top surface 122a of the molding layer 122 to the top surface 141 of the insulating cover layer 140' that directly contacts a portion of the molding layer 122. In some embodiments, this thickness may be substantially equal to the thickness T2. Furthermore, the thickness from the top surface of the second antenna element 130b to the top surface 143 of the insulating cover layer 140' may also be equal to T2. And the thickness from the side surface of the second antenna element 130b to the side surface between the top surfaces 141 and 143 of the insulating cover layer 140' may also be equal to T2. In some embodiments, the insulating cover layer 140' has a height H measured from the top surface 122a of the molding layer 122 to the top surface 143 of the insulating cover layer 140' located above the second antenna element 130b of the antenna 130. In some embodiments, the height H is in the range of about 10 μm to about 100 μm. In some embodiments, the insulating cover layer 140' is formed by a deposition process (e.g., chemical vapor deposition (CVD)) or a coating process.

[0044] Figure 4 This is a cross-sectional view of an exemplary semiconductor package structure 40 according to some embodiments of the present invention. The descriptions of elements in the following embodiments are the same as or similar to those previously described with reference to Figures 1, 2, and 3, and may be omitted for brevity. In this embodiment, the semiconductor package structure 40 is similar to... Figure 3The semiconductor package structure 30 shown differs in that the semiconductor package structure 40 further includes an adhesive layer 124 formed between the molding compound layer 122 and the insulating cover layer. The adhesive layer 124 between the molding compound layer 122 and the second antenna element 130b of the antenna 130 can improve the adhesion between the molding compound layer 122 and the second antenna element 130b, for example, by increasing the adhesive strength to prevent detachment, thus ensuring the stability of the package structure. The semiconductor package structure 40 in this embodiment combines... Figure 2 The advantages of the semiconductor package structure 20 shown (adhesive layer 124) and Figure 3 The advantages of the semiconductor package structure 30 shown (uniform thickness insulating cover layer 140').

[0045] Figure 5 This is a cross-sectional view of an exemplary semiconductor package structure 50 according to some embodiments of the present invention. For the sake of brevity, references to previous documents may be omitted below. Figure 1 Description of elements in those identical or similar embodiments. In this embodiment, the semiconductor package structure 50 is similar to... Figure 1 The semiconductor package structure 10 is shown. Unlike the semiconductor package structure 10, the second antenna element 130b of the antenna 130 in the semiconductor package structure 50 is formed in the molding compound layer 122. More specifically, the second antenna element 130b is formed on the bottom surface 140b of the insulating cover layer 140, having a uniform thickness T3, which can be substantially equal to... Figure 1 The thickness T1 is shown in the figure. At this time, the second antenna element 130b is also located between the molding layer 122 and the insulating cover layer 140, except that it is surrounded by the molding layer 122. The insulating cover layer 140 can also be in direct contact with the second antenna element 130b, for example, in direct contact with the top surface of the second antenna element 130b.

[0046] Furthermore, the molding compound layer 122 extends on the sidewall of the second antenna element 130b, such that the second antenna element 130b of the antenna 130 is surrounded by the molding compound layer 122 and separated from the first antenna element 130a of the antenna 130. In this case, the bottom surface and sidewall surface of the second antenna element 130b are covered by the molding compound layer 122, and the top surface of the molding compound layer 122 is substantially flush with the top surface of the second antenna element 130b of the antenna 130. In this embodiment, the second antenna element 130b is disposed in the molding compound layer 122, which can protect the second antenna element 130b, and the top surface of the second antenna element 130b can also be protected by the insulating cover layer 140; thereby better protecting the second antenna element 130b, and this structure can prevent the second antenna element 130b from detaching or falling off, making the second antenna element 130b more securely installed. Furthermore, this embodiment differs from the embodiment shown in Figures 1-4 in terms of process. In the embodiments shown in Figures 1-4, the molding compound layer 122 is formed first, and then the second antenna element 130b is formed on the molding compound layer 122. In this embodiment, the second antenna element 130b can be formed first, and then the molding compound layer 122 can be formed around the second antenna element 130b. Therefore, this embodiment also provides another process method to adapt to different manufacturing needs.

[0047] Figure 6 This is a cross-sectional view of an exemplary semiconductor package structure 60 according to some embodiments of the present invention. For the sake of brevity, descriptions of elements in the embodiments described below, which are the same as or similar to those previously described with reference to Figures 1, 2, and 5, may be omitted. In this embodiment, the semiconductor package structure 60 is similar to... Figure 5 The semiconductor package structure 50 is shown. Unlike semiconductor package structure 50, semiconductor package structure 20 also includes an adhesive layer 124 formed between the molding compound layer 122 and the insulating layer. Furthermore, a second antenna element 130b of the antenna 130 in semiconductor package structure 60 is formed in the adhesive layer 124. In this case, the second antenna element 130b is also located between the molding compound layer 122 and the insulating cover layer 140. The second antenna element 130b may not be in direct contact with the molding compound layer 122 (e.g., separated by the adhesive layer 124), but it may be in direct contact with the insulating cover layer 140, for example, the insulating cover layer 140 may be in direct contact with the top surface of the second antenna element 130b.

[0048] More specifically, the second antenna element 130b is formed on the bottom surface 140b of the insulating cover layer 140. Furthermore, the adhesive layer 124 extends on the sidewalls of the second antenna element 130b, such that the second antenna element 130b of the antenna 130 is surrounded by the adhesive layer 124. In this configuration, the bottom surface and sidewall surfaces of the second antenna element 130b are covered by the adhesive layer 124, and the top surface of the second antenna element 130b is substantially flush with the top surface of the adhesive layer 124.

[0049] In some embodiments, the insulating cover layer 140 has a uniform thickness T3, which may be substantially equal to... Figure 1 The thickness T1 shown is given. In some embodiments, the adhesive layer 124 has a thickness T4 measured from the top surface 122a of the molding compound layer 122 to the top surface of the adhesive layer 124. In some embodiments, the thickness T4 is in the range of about 10 μm to about 100 μm. In this embodiment, the second antenna element 130b is disposed in the adhesive layer 124, which can further improve the stability of the semiconductor package structure and further reduce the possibility of the antenna (second antenna element 130b) falling off or detaching, ensuring the antenna element is securely mounted; the insulating cover layer 140 protects the top surface of the second antenna element 130b, thereby better protecting the second antenna element 130b. In addition, this embodiment differs from the embodiments shown in Figures 2 and 4 in terms of process. In the embodiments shown in Figures 2 and 4, the adhesive layer 124 is formed first and then the second antenna element 130b is formed on the adhesive layer 124; while in this embodiment, the second antenna element 130b can be formed first and then the adhesive layer 124 is formed around the second antenna element 130b. Therefore, this embodiment also provides another process method to adapt to different manufacturing requirements. And, with Figure 2Similar to the semiconductor packaging structure 20 in this embodiment, the resonator between the first antenna element 130a and the second antenna element 130b includes a molding compound layer 122 and an adhesive layer 124. Therefore, the Dk and Df of the resonator can be freely adjusted (compared to only the molding compound layer 122), thereby increasing the design flexibility. The thickness of the resonator (including the molding compound layer 122 and the adhesive layer 124) can be freely adjusted to adapt to different needs, such as different thickness requirements and antenna requirements (e.g., the Dk and Df of the adhesive layer 124 are larger or smaller than those of the molding compound layer 122). Furthermore, since the resonator includes a molding compound layer 122 and an adhesive layer 124 (e.g., the Dk and Df of the adhesive layer 124 are smaller than those of the molding compound layer 122), the molding compound layer 122 is thinner, and the newly added adhesive layer 124 is thinner than the reduced portion of the molding compound layer 122. Therefore, the thickness or distance between the first antenna element 130a and the second antenna element 130b will be reduced, thereby reducing the overall thickness of the semiconductor package structure and thus reducing the size or height of the semiconductor package structure. This also allows for greater flexibility in the selection of materials for the first antenna element 130a and the second antenna element 130b, reducing antenna losses.

[0050] According to the foregoing embodiments, the semiconductor package structure is designed to manufacture an insulating capping / protective layer and integrate an antenna into the semiconductor package structure. The insulating capping / protective layer prevents the antenna element on the molding compound layer from being oxidized, prevents the antenna element from delaminating from the underlying molding compound layer, and / or prevents damage to the antenna element during testing. Therefore, the reliability, yield, and production volume of the semiconductor package structure can be improved. This increases the reliability, yield, and production volume of the semiconductor package structure and reduces the manufacturing cost. Furthermore, the integrated insulating capping / protective layer provides design flexibility in the selection of materials for the patch antenna integrated into the semiconductor package structure, thereby minimizing antenna losses.

[0051] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that, include: Semiconductor grains; A first molding compound layer surrounds the semiconductor die; A first redistribution layer structure is formed on the non-active surface of the semiconductor grain and the first molding compound layer; A second molding compound layer is formed on the first redistribution layer structure; An insulating covering layer that covers the second molding compound layer; as well as The first antenna includes: A first antenna element, electrically coupled to the semiconductor die, is formed in the first redistribution layer structure; and A second antenna element is formed between the second molding compound layer and the insulating cover layer; The insulating cover layer has a uniform thickness, and the top surface and sidewall surfaces of the second antenna element are conformally covered by the insulating cover layer. The first antenna element and the second antenna element are the same size and shape and are positioned vertically overlapping, and neither of them overlaps with the semiconductor die.

2. The semiconductor packaging structure as described in claim 1, characterized in that, Also includes: A second redistribution layer structure is formed on the active surface of the semiconductor grain and electrically coupled to the active surface of the semiconductor grain; A second antenna is formed in the first molding compound layer and electrically coupled to the semiconductor die through the second redistribution layer structure; A via structure is formed in the first molding compound layer and electrically coupled between the first antenna element and the second redistribution layer structure, such that the semiconductor die is electrically coupled to the first antenna element.

3. The semiconductor packaging structure as described in claim 2, characterized in that, The first antenna is a patch antenna, and the second antenna is a dipole antenna.

4. The semiconductor packaging structure as described in claim 2, characterized in that, It also includes a conductive structure electrically coupled to the semiconductor grain through the second redistribution layer structure.

5. The semiconductor packaging structure as described in claim 1, characterized in that, It also includes an adhesive layer formed between the second molding compound layer and the insulating cover layer.

6. The semiconductor packaging structure as described in claim 5, characterized in that, The insulating covering layer is formed of a material different from that of the adhesive layer.

7. The semiconductor packaging structure according to any one of claims 1-6, characterized in that, The insulating cover layer has a first top surface above the second antenna element and a second top surface below the first top surface, wherein the thickness from the top surface of the second antenna element to the first top surface is equal to the thickness from the bottom surface of the insulating cover layer to the second top surface.

8. The semiconductor packaging structure as described in claim 7, characterized in that, The thickness of the sidewall surface from the second antenna element to the side surface between the first and second top surfaces of the insulating cover is equal to the thickness from the bottom surface of the insulating cover to the second top surface.

9. A semiconductor packaging structure, characterized in that, include: Semiconductor grains; A first molding compound layer surrounds the semiconductor die; A second molding compound layer is formed on the first surface of the semiconductor die and the first molding compound layer; A through-hole structure is formed in the first molding compound layer; An insulating covering layer that covers the second molding compound layer; A patch antenna includes: a first antenna element formed between a first molding compound layer and a second molding compound layer, and electrically coupled to a semiconductor die through a through-hole structure; and a second antenna element, the top surface and sidewall surfaces of the second antenna element being covered by the insulating capping layer; and A dipole antenna is formed in the first molding compound layer; The insulating cover layer has a uniform thickness, and the top surface and sidewall surfaces of the second antenna element are conformally covered by the insulating cover layer. The first antenna element and the second antenna element are the same size and shape and are positioned vertically overlapping, and neither of them overlaps with the semiconductor die.

10. A semiconductor package structure, comprising: Semiconductor grains; A first molding compound layer surrounds the semiconductor die; A second molding compound layer is formed on the semiconductor die and the first molding compound layer; A through-hole structure is formed in the first molding compound layer; An insulating covering layer that covers the second molding compound layer; A patch antenna, comprising: A patch antenna includes: a first antenna element formed between a first molding compound layer and a second molding compound layer, and electrically coupled to a semiconductor die through a via structure; and a second antenna element formed on the bottom surface of the insulating cover layer, and spaced apart from the first antenna element by the second molding compound layer; and A dipole antenna is formed in the first molding compound layer; The insulating cover layer has a uniform thickness, and the top surface and sidewall surfaces of the second antenna element are conformally covered by the insulating cover layer. The first antenna element and the second antenna element are the same size and shape and are positioned vertically overlapping, and neither of them overlaps with the semiconductor die.

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