Multi-core soc chip and inter-core time synchronization method and system thereof, automobile

Abstract

The application provides a multi-core SoC chip, a method and system for inter-core time synchronization of the multi-core SoC chip, and an automobile. A global register (for example, a global time base counter) that can be accessed by a first core and each second core is arranged in the multi-core SoC chip. The first core sets time information into the global register after synchronizing time with a master clock device outside the chip through an Ethernet communication protocol. The second core periodically reads the time information in the global register and synchronizes the time information to a slave clock device hung below the chip through another communication protocol (for example, a CAN communication protocol). Thus, the inter-core time synchronization of the multi-core SoC chip can be realized through only simple periodic register read and write operations, without considering the clock deviation problem of the inter-core time synchronization of the multi-core SoC chip, improving the precision of the inter-core time synchronization of the multi-core SoC chip, and avoiding the difficulty and development workload of realizing the inter-core time synchronization of the multi-core SoC chip through other protocol modes.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a multi-core SoC chip and an inter-core time synchronization method, system, and automobile thereof. Background Art

[0002] With the development of intelligent vehicles, a car now often has dozens or even hundreds of ECUs (electronic control units). The number of ECUs has increased dramatically. Under the complex distributed electronic and electrical architecture, the computing power of ECUs cannot be coordinated and is redundant with each other, resulting in huge waste. It is also difficult to carry the complex functions of the car. Therefore, the evolution trend of electronic and electrical architecture (EEA) is from distribution to domain controllers, then to cross-domain integration, and finally to central integration.

[0003] Among them, current cross-domain integration is usually implemented based on a multi-core SoC (System on Chip) solution. In this solution, the master clock device (Clock Master) outside the SoC synchronizes time with an Ethernet-capable core (Clock Slave) inside the SoC through an Ethernet communication protocol (such as 802.1AS). Then, another core without Ethernet capability needs to synchronize to this time and synchronize the time information to the CAN node connected to it.

[0004] Because conventional multi-core SoC chips interact through inter-core communication based on shared memory (or other solutions), they are prone to long time delays (e.g., more than 100us). For systems requiring high time accuracy, this can result in significant time synchronization errors. Therefore, it is necessary to address the synchronization accuracy issues brought about by cross-core time synchronization in multi-core SoC chips.

[0005] In addition, the inter-core communication solution of multi-core SoC chips based on shared memory (or other solutions) does not have hardware timestamps like time-sensitive network switches (TSN switches). When using non-real-time operating systems (such as Linux systems, etc.), it is difficult to obtain relatively accurate timestamps for sending and receiving time synchronization data due to the uncertainty of system scheduling. Therefore, even if a general time synchronization protocol is used as a cross-core time synchronization solution, it cannot be guaranteed to meet the system's time synchronization accuracy requirements. Summary of the Invention

[0006] The purpose of the present invention is to provide a multi-core SoC chip and its inter-core time synchronization method, system, and vehicle, which can improve the accuracy of inter-core time synchronization of the multi-core SoC chip and reduce the difficulty.

[0007] To achieve the above object, the present invention provides a multi-core SoC chip, which includes a first core, a global register and at least one second core integrated in the same chip; wherein,

[0008] The first core is used to synchronize time with an off-chip master clock device through an Ethernet communication protocol, and after synchronizing to the time information, set the time information into the global register;

[0009] The second core is used to communicate with the corresponding slave clock device hanging off the chip through a communication protocol other than the Ethernet communication protocol, and periodically obtain the time information in the global register, and further synchronize the obtained time information to the corresponding slave clock device hanging off the chip.

[0010] Optionally, the multi-core SoC chip further includes a crystal oscillator, and the first core, each of the second cores and the global register all provide clocks based on the crystal oscillator.

[0011] Optionally, the first core is used to periodically synchronize time information of the off-chip master clock device through an Ethernet communication protocol and perform a write operation on the global register.

[0012] Optionally, the first core has a slave clock module, which has a built-in time-sensitive network switching unit. The time-sensitive network switching unit is used to generate an interrupt handler when detecting a time synchronization message, and use the interrupt handler to complete clock synchronization with the master clock device outside the chip. At the same time, the slave clock module writes the time information of the synchronized master clock device into the global register.

[0013] Optionally, the location where the first core writes the global register is deployed in the system bottom layer code.

[0014] Optionally, the second core has a master clock module, which has a built-in time correction unit. The time correction unit is used to perform static delay compensation on the time information after the master clock module periodically reads the time information of the global register, and synchronize the compensated time information to the slave clock device outside the chip through the other communication protocol.

[0015] Optionally, the slave clock device is a CAN node device, and the other communication protocol is a CAN communication protocol.

[0016] Optionally, the global register is a global time base counter; the first core is also used to set the synchronized time information into the global time base counter after the first core synchronizes time with the master clock device; the global time base counter is used to continuously count at the corresponding time base to generate a corresponding global time base count value, so that the second core periodically obtains the global time base count value to obtain time information.

[0017] Based on the same inventive concept, the present invention also provides a method for inter-core time synchronization of a multi-core SoC chip, wherein the multi-core SoC chip includes a first core, a global register, and at least one second core integrated in the same chip, and the inter-core time synchronization method includes:

[0018] The first core establishes a communication connection with a master clock device outside the multi-core SoC chip via an Ethernet communication protocol, and the second core establishes a communication connection with a slave clock device outside the multi-core SoC chip via a communication protocol other than the Ethernet communication protocol;

[0019] The first core synchronizes time with the master clock device, and after the first core is synchronized to the time information of the master clock device, performs a write operation on the global register;

[0020] The second core periodically reads the time information in the global register and synchronizes the time information to the slave clock device through the other communication protocol.

[0021] Optionally, the step of synchronizing time between the first core and the master clock device includes: the first core detects the time synchronization message based on the built-in time-sensitive network switching unit, and generates a corresponding interrupt handler when the time synchronization message is detected, and further uses the interrupt handler to complete the clock synchronization with the master clock device.

[0022] Optionally, the global register is a global time base counter;

[0023] The step of the first core performing a write operation on the global register includes: after the first core synchronizes time with the master clock device, the first core sets the synchronized time information into the global time base counter; the global time base counter continuously counts at a corresponding time base to generate a corresponding global time base count value;

[0024] The step of the second core periodically reading the time information in the global register includes: the second core periodically acquiring the global time base count value to obtain corresponding time information.

[0025] Optionally, after the second core periodically reads the time information in the global register, it first performs static delay compensation on the read time information, and then synchronizes the compensated time information to the slave clock device through the other communication protocol.

[0026] Based on the same inventive concept, the present invention also provides a multi-core SoC chip system, which includes the multi-core SoC chip described in the present invention, a master clock device and at least one slave clock device, the master clock device is communicatively connected to the first core of the multi-core SoC chip via an Ethernet communication protocol, and the slave clock device is communicatively connected to the corresponding second core in the multi-core SoC chip via a communication protocol other than the Ethernet communication protocol.

[0027] Based on the same inventive concept, the present invention also provides a car, which includes the multi-core SoC chip system described in the present invention.

[0028] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0029] 1. A global register (e.g., a global time base counter) is set inside the multi-core SoC chip that can be accessed by the first core and each second core. The first core can set the time information to the global register after synchronizing the time with the master clock device outside the multi-core SoC chip through the Ethernet communication protocol. The second core can periodically read the time information in the global register and then synchronize it to the slave clock device outside the multi-core SoC chip through a communication protocol other than the Ethernet communication protocol (e.g., the CAN communication protocol). In this way, inter-core time synchronization of the multi-core SoC chip can be achieved only through simple periodic register read and write operations. There is no need to consider the clock deviation problem of inter-core time synchronization of the multi-core SoC chip, which improves the accuracy of inter-core time synchronization of the multi-core SoC chip. At the same time, it can avoid the difficulty and development workload of implementing inter-core time synchronization of the multi-core SoC chip through other protocols.

[0030] 2. The second core performs static compensation on the read time information, which can further improve the accuracy of time synchronization between cores of the multi-core SoC chip.

[0031] 3. The static compensation performed by the second core on the time information read (ie, the time compensation for the read and write operations of the global register) can be achieved through relatively easy software or program calibration, thereby simplifying the system development process and improving synchronization accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the system architecture design of a multi-core SoC chip according to an embodiment of the present invention.

[0033] Figure 2 1 is a timing diagram of a method for synchronizing time between cores of a multi-core SoC chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, certain technical features known in the art have not been described to avoid obscuring the present invention. It should be understood that the present invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. Throughout, like reference numerals denote like elements. As used herein, the singular forms "a," "an," and "said" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items. The terms "core" and "core" may refer solely to the core device or to the core device and its peripheral components.

[0035] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0036] Please refer to Figure 1 An embodiment of the present invention provides a multi-core SoC chip 1, which includes a first core 11, at least one second core 12, a global time base counter 13 and a crystal oscillator 14 integrated in the same chip.

[0037] Among them, the first core 11 and each second core 12 can access the global time base counter 13, and the first core 11, each second core 12 and the global time base counter 13 are all based on the same crystal oscillator 14 to provide clocks, so there is no need to consider the clock deviation problem of inter-core time synchronization of the multi-core SoC chip 1.

[0038] In this embodiment, the first core 11 is the only core in the multi-core SoC chip 1 that can communicate with the outside world via Ethernet, while each second core 12 can only obtain time information from the first core 11 through the internal mechanism of the multi-core SoC chip 1 (i.e., by reading the global time base counter 13). Each second core 12 can connect to and control a clock slave device 3 external to the multi-core SoC chip 1 (referred to as off-chip) on a one-to-one basis. The second core 12 communicates with the clock slave device 3 via a communication protocol other than the Ethernet communication protocol (such as the CAN communication protocol, which may also be referred to as the CAN time synchronization protocol).

[0039] Therefore, in this embodiment, the first core 11 is used to synchronize time with a clock grand master (e.g., a car's TBOX) 2 external to the multi-core SoC chip 1 (referred to as an off-chip) via an Ethernet communication protocol (also referred to as an Ethernet time synchronization protocol). After synchronizing to the time information, the first core 11 sets the time information into the global time base counter 13. As an example, the first core 11 may be an automotive MPU (Microprocessor Unit) core, which, in addition to supporting instructions for basic arithmetic and logical operations, also supports DSP (digital signal processor) instructions and floating-point instructions.

[0040] The second core 12 is used to communicate with the corresponding slave clock device 3 hanging off the chip through a communication protocol other than Ethernet, and periodically obtain the time information in the global time base counter 13, and further synchronize the obtained time information to the corresponding slave clock device 3 hanging off the chip. As an example, the second core 12 can be an MCU (MicroControl Unit) core of an automobile, which can only support instructions for basic arithmetic and logical operations. Of course, it can also support not only instructions for basic arithmetic and logical operations, but also instructions such as floating-point operations and DSP operations.

[0041] Optionally, the first core 11 has a clock slave module (Clock Slave) 110, which can periodically synchronize to the time of the master clock device 2 through the 802.1AS protocol (i.e., an Ethernet precision time synchronization protocol), and after periodically synchronizing to the time information of the master clock device 2 (i.e., obtaining absolute time), the synchronized time information is set to the global time base counter 13 by performing a write operation on the global time base counter 13.

[0042] Further optionally, the slave clock module 110 has a built-in TSN (Time Sensitive Network) switch unit (TSNSwitch) 111. The TSN switch unit 111 can detect time synchronization messages and generate an interrupt handler when the time synchronization message is detected. Then, according to the interrupt handler, the clock is periodically synchronized with the master clock device 2 and the synchronized time information is written into the global time base counter 13.

[0043] Optionally, the location where the first core writes the global time base counter 13 is deployed in the system bottom layer code (such as in the kernel of the Linux system).

[0044] In the entire synchronization link, some time errors (i.e., delays) will be generated when the subsystem on the first core 11 side writes to the global time base counter 13 and when the global time base counter 13 is read on the second core 12 side, thereby affecting the time synchronization accuracy. Therefore, optionally, the second core 12 may have a master clock module (Clock Master) 120. The master clock module 120 can periodically read the global time base count value in the global time base counter 13 and determine the corresponding time information through the global time base count value. The master clock module 120 has a built-in time correction unit (not shown). The time correction unit is used to perform static delay compensation on the read time information after the master clock module 120 periodically reads the time information of the global time base counter 13, and synchronize the compensated time information to the off-chip slave clock device 3. The static delay compensation can be calibrated by a preset program to meet the time accuracy requirements. The compensated time information T mcu =T mpu +T 静态延迟补偿 , T 静态延迟补偿 =T 写入延迟补偿 +T 读取延迟补偿 , T mpu is the time information synchronized by the first core 11, T 写入延迟补偿 The time information T to which the first core 11 will be synchronized mpu The time compensation for the delay generated during writing to the global time base counter 13 is done, T 读取延迟补偿 This is time compensation for the delay generated when the second core 12 reads time information from the global time base counter 13.

[0045] The global time base counter 13 refers to a hardware module with a software-settable time base and continuous counting capability. It can be triggered after the first core 11 is synchronized to the time information of the master clock device 2 to continuously count at the corresponding time base and generate a corresponding global time base count value, so that the second core 12 obtains the corresponding time information by periodically obtaining the global time base count value.

[0046] Please refer to Figure 1 and Figure 2 This embodiment also provides a method for synchronizing time between cores of a multi-core SoC chip 1, comprising the following steps:

[0047] First, the first core (e.g., MPU) 11 of the multi-core SoC chip 1 establishes a communication connection with a master clock device (Grand Master) 2 outside the multi-core SoC chip 1 via the Ethernet protocol, and the second core (e.g., MCU) 12 of the multi-core SoC chip 1 establishes a communication connection with a slave clock device 3 outside the multi-core SoC chip 1 via a communication protocol other than the Ethernet communication protocol.

[0048] Next, the TSN interaction unit (i.e., TSNSwitch) 111 inside the first core 11 synchronizes time with the master clock device (Grand Master) 2 through an Ethernet communication protocol (e.g., 802.1AS synchronization protocol). During this period, the TSN interaction unit detects the time synchronization message and generates an interrupt handler when the time synchronization message is detected. Then, according to the interrupt handler, the clock synchronization with the master clock device 2 is periodically completed. After synchronizing to the time information of the master clock device (TBOX GrandMaster) 2, the slave clock module (Clock Slave) 110 performs a write operation on the global time base counter 13 (i.e., the global time base counter 13 starts to continuously count based on the corresponding time base to obtain the corresponding global time base count value);

[0049] Then, the master clock module (Clock Master) 120 of the second core 12 periodically reads the global time base count value in the global time base counter 13, that is, obtains the corresponding time information, and performs static delay compensation (that is, time correction) on the obtained time information, and then synchronizes the compensated time information to the slave clock device 3 under it through corresponding other communication protocols.

[0050] In the above-mentioned synchronization timing, the inter-core time synchronization of the multi-core SoC chip 1 only corresponds to the range from the first core 11 (MPU) to the second core 12 (MCU). The first core 11 (MPU) and the second core 12 (MCU) can achieve time synchronization only through simple periodic register operations (that is, periodic reading and writing operations of the global time base counter 13). In addition, the later static delay compensation calibration of the program (or software, algorithm) can adjust and determine the static delay caused by the reading and writing operations of the global time base counter 13, and obtain satisfactory time synchronization accuracy.

[0051] The multi-core SoC chip 1 and its inter-core time synchronization method of this embodiment utilize the existing global timebase counter 13 within the multi-core SoC chip 1, avoiding the difficulty and development workload associated with implementing inter-core time synchronization through other protocols. Furthermore, internal time compensation for read and write operations on the global timebase counter 13 can be calibrated using a relatively simple program (or software, algorithm), resulting in ideal time synchronization error compensation. This simplifies the development process of the inter-core time synchronization system and improves synchronization accuracy.

[0052] Please refer to Figure 1 This embodiment also provides a multi-core SoC chip system, which includes the multi-core SoC chip 1 described in this embodiment, a master clock device 2 and at least one slave clock device 3. The master clock device 2 is communicatively connected to the first core 11 of the multi-core SoC chip 1 via an Ethernet communication protocol, and the slave clock device 3 is communicatively connected to the corresponding second core 12 in the multi-core SoC chip 1 via a communication protocol other than the Ethernet communication protocol.

[0053] Among them, the main clock device 2 is, for example, the TBOX of a car. TBOX is a box on the car, which is an Android operating system with Ethernet communication function. It contains a SIM card and supporting hardware such as GPS antenna and 4G antenna. It is a necessary device for realizing vehicle-computer networking.

[0054] The slave clock device 3 is, for example, a corresponding CAN node device of a car. The CAN node devices of a car are, for example, doors, lights, air conditioners, seats, engines, gearboxes, steering systems, anti-lock braking systems, and the like.

[0055] Please refer to Figure 1 , this embodiment also provides a car, which includes the multi-core SoC chip system described in this embodiment.

[0056] It should be understood that the current cross-domain automotive integration solution, with its electrical / electronic architecture (EEA), can divide the overall EEA architecture into the vehicle control domain, the intelligent driving domain, and the intelligent cockpit domain. The first core 11 and each second core 12 of the multi-core SoC chip 1 can be different cores in the same domain controller or in controllers of different domains. The EEA is the overall layout of the automotive EEA system, integrating the various sensors, central processing units, wiring topology, EEA distribution systems, and hardware and software within the vehicle to achieve the configuration and functionality of the entire vehicle, as well as the distribution of computing, power, and energy. The EEA is the brain and nerves of the vehicle, the foundation and key to automotive intelligence, connecting, driving, and controlling nearly all of the vehicle's functions. Furthermore, with the advancement of automotive intelligence, a single vehicle often has dozens or even hundreds of ECUs, a significant increase in the number of ECUs. In a cross-domain integrated EEA, a single domain controller can integrate multiple ECUs.

[0057] Moreover, the first core 11 and the second core 12 can be any suitable processor cores, such as R series processor cores, A series processor cores or M series processor cores, etc., and the technical solution of the present invention does not make specific limitations on this.

[0058] In addition, it should be noted that the above embodiments are merely examples of the technical solutions of the present invention and do not limit the scope of protection of the technical solutions of the present invention. Those skilled in the art may make appropriate modifications to obtain other embodiments of the present invention. For example, the "global time base counter" mentioned above refers to a hardware module with a software-settable time base and continuous counting capabilities, which can represent time information through count values. In another embodiment of the present invention, the global time base counter can be replaced with a global register that can store time information and allows both the first core and the second core to access it, or any other suitable hardware module. For another example, Figure 1 The “TSN (Time Sensitive Network) switching unit 111” shown is embedded in the clock slave module (Clock Slave) 110 of the first core 11, but in other embodiments of the present invention, the “TSN (Time Sensitive Network) switching unit 111” can also be separated from the clock module 110, such as Figure 2 shown.

[0059] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of the technical solution of the present invention.

Claims

1. A multi-core SoC chip, characterized in that: It includes a first core, a global register and at least one second core integrated in the same chip; wherein, The first core is used to synchronize time with an off-chip master clock device through an Ethernet communication protocol, and after synchronizing to the time information, set the time information into the global register; The second core is used to communicate with the corresponding slave clock device hanging off the chip through a communication protocol other than the Ethernet communication protocol, and periodically obtain the time information in the global register, and further synchronize the obtained time information to the corresponding slave clock device hanging off the chip.

2. The multi-core SoC chip according to claim 1, wherein: A crystal oscillator is also included, and the first core, each of the second cores, and the global register all provide clocks based on the crystal oscillator.

3. The multi-core SoC chip according to claim 1, wherein: The first core is used to periodically synchronize time information of the off-chip master clock device through an Ethernet communication protocol and perform a write operation on the global register.

4. The multi-core SoC chip according to claim 1, wherein: The first core has a slave clock module, which has a built-in time-sensitive network switching unit. The time-sensitive network switching unit is used to generate an interrupt handler when a time synchronization message is detected, and use the interrupt handler to complete clock synchronization with the master clock device outside the chip. At the same time, the slave clock module writes the time information of the synchronized master clock device into the global register.

5. The multi-core SoC chip according to claim 1, wherein: The location where the first core writes into the global register is deployed in the system bottom layer code.

6. The multi-core SoC chip according to claim 1, wherein: The second core has a master clock module, which has a built-in time correction unit. The time correction unit is used to perform static delay compensation on the time information after the master clock module periodically reads the time information of the global register, and synchronize the compensated time information to the slave clock device outside the chip through the other communication protocol.

7. The multi-core SoC chip according to claim 1, wherein: The slave clock device is a CAN node device, and the other communication protocol is a CAN communication protocol.

8. The multi-core SoC chip according to any one of claims 1 to 7, wherein: The global register is a global time base counter; the first core is also used to set the synchronized time information into the global time base counter after the first core synchronizes time with the master clock device; the global time base counter is used to continuously count at the corresponding time base and generate a corresponding global time base count value, so that the second core periodically obtains the global time base count value to obtain time information.

9. A method for inter-core time synchronization of a multi-core SoC chip, characterized in that: The multi-core SoC chip includes a first core, a global register, and at least one second core integrated in the same chip, and the inter-core time synchronization method includes: The first core establishes a communication connection with a master clock device outside the multi-core SoC chip via an Ethernet communication protocol, and the second core establishes a communication connection with a slave clock device outside the multi-core SoC chip via a communication protocol other than the Ethernet communication protocol; The first core synchronizes time with the master clock device, and after the first core is synchronized to the time information of the master clock device, performs a write operation on the global register; The second core periodically reads the time information in the global register and synchronizes the time information to the slave clock device through the other communication protocol.

10. The inter-core time synchronization method according to claim 9, wherein: The step of synchronizing time between the first core and the master clock device includes: the first core detects the time synchronization message based on the built-in time-sensitive network switching unit, and generates a corresponding interrupt handler when the time synchronization message is detected, and further uses the interrupt handler to complete clock synchronization with the master clock device.

11. The inter-core time synchronization method according to claim 9, wherein: The global register is a global time base counter; The step of the first core performing a write operation on the global register includes: after the first core synchronizes time with the master clock device, the first core sets the synchronized time information into the global time base counter; the global time base counter continuously counts at a corresponding time base to generate a corresponding global time base count value; The step of the second core periodically reading the time information in the global register includes: the second core periodically acquiring the global time base count value to obtain corresponding time information.

12. The inter-core time synchronization method according to any one of claims 9 to 11, characterized in that: After the second core periodically reads the time information in the global register, it first performs static delay compensation on the read time information, and then synchronizes the compensated time information to the slave clock device through the other communication protocol.

13. A multi-core SoC chip system, characterized in that: It comprises a multi-core SoC chip according to any one of claims 1 to 8, a master clock device, and at least one slave clock device, wherein the master clock device is communicatively connected to the first core of the multi-core SoC chip via an Ethernet communication protocol, and the slave clock device is communicatively connected to the corresponding second core in the multi-core SoC chip via a communication protocol other than the Ethernet communication protocol.

14. An automobile, characterized in that: Including the multi-core SoC chip system described in claim 13.

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