Data processing method, system and computer equipment for improving the efficiency of issuing digital currency

Through intelligent prediction technology and parallel computing, data processing process is optimized, combined with CPU level three cache and thread pool, the problem of inefficient issuance of digital currency is solved, efficient issuance and cost reduction are achieved, and the needs of massive users are supported.

CN114881621BActive Publication Date: 2025-08-22BEIJING ANYU DAOHE TECH CO LTD
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Patent Information

Application Number
CN202110624847.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-06-04
Publication Date
2025-08-22
Estimated Expiration
2041-06-04

AI Technical Summary

Technical Problem

The prior art has problems such as inefficiency and long-term server resource utilization in the issuance of digital currency, especially when a large number of users or equipment issuance, resulting in increased costs.

Method used

Intelligent prediction technology, CPU level three cache, thread pool and parallel computing technology are adopted, combined with snowflake algorithm and Bloom filter, the data processing process is optimized, parallel computing and cache management is realized, and the number of server interactions is reduced.

Benefits of technology

It has improved the efficiency of issuance of digital currency, reduced system costs, met the needs of massive users, supported GP and digital RMB standards, and increased the issuance efficiency by 15 times.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present invention belongs to the technical field of digital currency issuance, IC card issuance and industry card issuance, and discloses a data processing method, system and computer equipment for improving the efficiency of digital currency issuance. The data processing method for improving the efficiency of digital currency issuance includes: using intelligent prediction technology to predict the security measures for subsequent issuance according to the current equipment status and complete the calculation in advance; using the CPU three-level cache principle, combined with parallel computing technology, and applying it to the software system; based on the optimization of the ideas of first-in-first-out, least recently used, and least frequently used, when the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU; using the thread pool to execute and schedule tasks; initializing the thread pool and starting it in the product; and applying the snowflake algorithm and the distribution algorithm in big data to the device issuance design. The present invention innovatively applies the snowflake algorithm and the distribution algorithm to the device issuance design, which can effectively improve efficiency.
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Description

Technical Field

[0001] The present invention belongs to the technical field of digital currency issuance, IC card issuance and industry card issuance, and in particular relates to a data processing method, system and computer equipment for improving the efficiency of digital currency issuance. Background Art

[0002] The existing technology issuance model all adopts a parallel mode, that is, issuing a digital wallet requires 147 instructions, and the background must generate an instruction, then send it to the terminal device, the terminal device executes an instruction, and then returns the result to the background. The background judges the return value of the terminal device and generates the next instruction. Figure 6 shown.

[0003] Generating the next batch of instructions requires the counter and card challenge generated by the terminal device. In the traditional issuance model, a single interaction with the terminal is required to obtain the counter and card challenge. This model not only consumes a lot of server resources but also has very low execution efficiency.

[0004] In order to meet the issuance efficiency of massive users or massive devices, it is necessary to innovate a feasible solution and implementation method to solve the above problems under the new scenarios and new businesses of digital currency.

[0005] The above analysis reveals the following problems and drawbacks of existing technologies: The traditional issuance model not only occupies server resources for a long time but also has very low execution efficiency. With the vigorous promotion of the digital RMB and the massive increase in users, the number of simultaneous issuances is currently the system's biggest bottleneck. To address this bottleneck, system builders have continuously increased server resources, resulting in a sharp increase in costs.

[0006] The difficulty of solving the above problems and defects is:

[0007] It must comply with GP standards, PBOC standards and digital RMB standards.

[0008] Meet the requirements of massive users to issue digital RMB wallets at the same time.

[0009] Innovate the issuance model for new business scenarios and realize the dynamic calculation of the environmental security authentication code of the wallet hardware medium.

[0010] Refer to the CPU three-level cache technology to implement data cache, instruction cache, and request information cache.

[0011] The significance of solving the above problems and defects is:

[0012] Under the premise of complying with the GP specification requirements and the digital RMB specification requirements, improve the efficiency of system issuance; meet the needs of massive users, reduce enterprise operating costs, and accelerate the promotion of digital RMB. Summary of the Invention

[0013] In response to the problems existing in the prior art, the present invention provides a data processing method, system and computer equipment for improving the efficiency of issuing digital currency.

[0014] The present invention is implemented as follows: a data processing method for improving the efficiency of issuing digital currency, comprising:

[0015] Step 1: Utilize intelligent pre-processing technology to predict subsequent security measures based on current device conditions and complete calculations in advance. This utilizes the principle of CPU three-level cache, combined with parallel computing technology, and applies it to the software system.

[0016] Step 2: Based on the idea of ​​first-in-first-out, least recently used, and least frequently used, when the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU;

[0017] Step three: Use the thread pool to execute and schedule tasks; initialize the thread pool and start it in the product; and apply the snowflake algorithm and deployment algorithm in big data to the device distribution design.

[0018] Furthermore, in step 1, the intelligent prediction technology is used to predict the security measures to be issued subsequently based on the current equipment status and complete the calculation in advance; wherein, the algorithm design concept of the intelligent prediction technology is:

[0019] Given the conditions SKUMAC and SKUENC session key, the input condition is the security domain AID, the algorithm is DES+final3DES, the key uses SKUMAC, calculates STRUCTURED, takes the left 6B, and inputs the card challenge.

[0020] Using the SKUENC session key, the algorithm uses 3DES-CBC, inputs the ICV, terminal random number, counter, card challenge, and supplements 80 to calculate the card CRYPTOGRAM, which is compared with the CRYPTOGRAM returned by the security chip. If the comparison is successful, it means that it can be predicted, and all instructions can be generated in advance.

[0021] After the intelligent prediction technology was launched, the issuance mode was changed from the original serial mode to the parallel mode.

[0022] Furthermore, in step 1, the process of the intelligent prediction technology includes:

[0023] (1) The terminal device is initialized and a request is made to request the first batch of instructions. After receiving the request, the TSM generates the first batch of instructions and returns them to the terminal device. At the same time, a task is created and a thread is used to perform asynchronous startup intelligent prediction and calculate the authentication code.

[0024] (2) After the intelligent prediction calculation completes the authentication code, it calculates the next batch of instructions, generates the ID of the next batch according to the snowflake algorithm, and saves it in the cache;

[0025] (3) The terminal device requests the second batch of instructions and returns the execution results of the first batch of instructions. The results of the first batch of instructions include an authentication code. The authentication code returned by the terminal is compared with the intelligent prediction. If they are the same, it means the prediction is successful. The second batch of instructions is directly obtained from the cache according to the Bloom algorithm. The same applies to other batches of instructions.

[0026] (4) The background does not calculate the next batch of instructions in time, but instead calculates the instruction set and the next batch and obtains it through the cache.

[0027] Furthermore, in step 1, the CPU three-level cache technology includes:

[0028] The principle of CPU three-level cache is applied to the software system and combined with parallel computing technology to improve the issuance efficiency; it is optimized based on the ideas of first-in-first-out, least recently used, and least frequently used. When the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU.

[0029] Furthermore, in step 1, the CPU three-level cache technology further includes:

[0030] (1) FIFO: First in, first out. In this elimination algorithm, the first item that enters the cache will be eliminated first.

[0031] (2) LRU: Least Recently Used algorithm, each time data is accessed, it is placed at the end of the queue. If data needs to be eliminated, only the head of the queue needs to be eliminated;

[0032] (3) LFU: Least Recently Used, uses extra space to record the usage frequency of each data, and then selects the one with the lowest frequency for elimination.

[0033] Furthermore, in step 1, the CPU three-level cache technology further includes:

[0034] (1) The first-level cache uses memory; the goal of L1 is to reduce the number of reads from L2, using expiration mechanisms and manual cache recycling;

[0035] (2) The second-level cache uses Redis. Because a large number of cache reads can cause the L2 network to become a bottleneck for the entire system, an expiration mechanism and manual cache mechanism are used for recycling.

[0036] (3) The third-level cache uses a database mechanism. When L1 and L2 reach their maximum limits, the L3 cache is directly accessed.

[0037] Furthermore, in step three, the thread pool technology includes:

[0038] Creating a new thread each time to execute a task will consume a lot of system resources, so the thread pool is used to schedule tasks, and the thread pool is initialized when the product starts.

[0039] For the issuance equipment business, since batch instruction sets can be intelligently predicted, the subtasks are actually parallel, so these parallel tasks are placed in different queues, and the large task is decomposed into four subtasks: subtask 1, subtask 2, subtask 3, and subtask 4. That is, four task queues are created, and then three working threads are created to correspond to the queues one by one.

[0040] There is a basic idea in the field of algorithms called "divide and conquer". The so-called "divide and conquer" is to split large problems that are difficult to solve directly into smaller sub-problems. Based on the "divide and conquer" idea, a large task is divided into multiple small tasks to be executed, and the results of each small task are combined into the required return value.

[0041] Another object of the present invention is to provide a data processing system for improving the efficiency of issuing digital currency, which is applied with the data processing method for improving the efficiency of issuing digital currency. The data processing system for improving the efficiency of issuing digital currency comprises:

[0042] The intelligent prediction module is used to use intelligent prediction technology to predict the subsequent security measures based on the current equipment status and complete the calculation in advance;

[0043] The three-level cache module is used to apply the principle of CPU three-level cache to the software system in combination with parallel computing technology. It is optimized based on the ideas of first-in-first-out, least recently used, and least recently frequently used. When the cache data exceeds the maximum value, the LRU algorithm is used to replace it. The cache elimination algorithm uses FIFO and LFU.

[0044] The thread pool scheduling module is used to use the thread pool to execute and schedule tasks; initialize the thread pool and start it in the product; and apply the snowflake algorithm and distribution algorithm in big data to device distribution design.

[0045] Another object of the present invention is to provide a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the following steps:

[0046] Utilize intelligent pre-processing technology to predict subsequent security measures based on current device status and complete calculations in advance; use the principle of CPU three-level cache, combined with parallel computing technology, and apply it to the software system; optimize based on the ideas of first-in-first-out, least recently used, and least frequently used. When the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU; use the thread pool to execute and schedule tasks; initialize the thread pool and start it in the product; and apply the snowflake algorithm and the deployment algorithm in big data to the device issuance design.

[0047] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the data processing method for improving the efficiency of issuing digital currency.

[0048] In combination with all the above technical solutions, the advantages and positive effects of the present invention are as follows: the data processing method for improving the efficiency of issuing digital currency provided by the present invention involves digital currency issuance, IC card issuance and industry card issuance, especially for massive users or massive terminal devices, and is an algorithm implementation for improving issuance efficiency under the premise of complying with GP specifications.

[0049] The present invention uses intelligent prediction technology to predict the security measures for subsequent issuance based on the current device status and complete the calculation in advance; it uses the principle of CPU three-level cache to apply to the software system and combines it with parallel computing technology to improve issuance efficiency; it is optimized based on the ideas of first-in-first-out, least recently used, and least frequently used. When the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU. The present invention uses a thread pool to execute tasks to improve the utilization of system resources; creating a new thread to execute a task each time will greatly consume system resources, so the thread pool is used to schedule tasks; the thread pool is initialized when the product is started to reduce additional resource consumption during system operation. The present invention innovatively applies the snowflake algorithm and the distribution algorithm in big data to the device issuance design to improve efficiency.

[0050] By using this method, the following goals can be achieved in terms of security and performance:

[0051] (1) Fully supports SCP02 in the GP specification and can be expanded to SCP10. Fully supports the digital RMB specification and can be expanded to support PBOC and other industry specifications

[0052] (2) Results of improved distribution efficiency: Concurrency performance increased 15 times, that is, the online distribution time for 100,000 devices was reduced from 5,000 seconds to 200 seconds.

[0053] (3) High availability architecture: layered architecture design, centralized storage, atomic computing, and unified scheduling. It supports multiple protocols and can quickly adapt to different access requirements.

[0054] (4) High availability of services: information caching, dynamic adjustment of service groups, automatic isolation of abnormal services, service load balancing, support for simplex and duplex secure communication, and support for online horizontal and vertical expansion of its own services.

[0055] (5) High data availability: Reasonable data structure design, sufficient cache computing and processing to ensure high data availability, database cluster mechanism, read-write separation, and reasonable resource allocation

[0056] (6) Superior system performance optimization: Targeted at the transaction characteristics of TSM, we have implemented specialized optimizations, including algorithm optimization, structural optimization, data processing flow optimization, and algorithm enhancements: the time taken by the general library has been improved from 640 milliseconds to 0.176 milliseconds by the proprietary library. We innovatively apply the principle of the CPU's three-level cache to the software system and combine it with parallel computing technology. We also create unique intelligent pre-processing technology that predicts the security measures for subsequent issuance based on the current device status and completes calculations in advance. We innovatively apply the snowflake algorithm and the distribution algorithm from big data to the device issuance design to improve efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0058] Figure 1 This is a flow chart of a data processing method for improving the efficiency of issuing digital currency provided by an embodiment of the present invention.

[0059] Figure 2 This is a structural block diagram of a data processing system for improving the efficiency of issuing digital currency, provided by an embodiment of the present invention;

[0060] In the figure: 1. Intelligent prediction module; 2. Three-level cache module; 3. Thread pool scheduling module.

[0061] Figure 3 This is a schematic diagram of the design principle of the intelligent pre-technology algorithm provided by an embodiment of the present invention.

[0062] Figure 4 It is a schematic diagram showing that the distribution mode provided by an embodiment of the present invention is changed from the original serial mode to the parallel mode.

[0063] Figure 5 This is a schematic diagram of the thread pool technology provided by an embodiment of the present invention.

[0064] Figure 6 It is a schematic diagram of a traditional distribution model provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0066] In response to the problems existing in the prior art, the present invention provides a data processing method and system for improving the efficiency of issuing digital currency. The present invention is described in detail below with reference to the accompanying drawings.

[0067] like Figure 1 As shown, the data processing method for improving the efficiency of issuing digital currency provided by the embodiment of the present invention includes the following steps:

[0068] S101 uses intelligent pre-processing technology to predict the security measures to be issued in the future based on the current equipment status and complete the calculation in advance; it uses the principle of CPU three-level cache and combines parallel computing technology to apply it to the software system;

[0069] S102 is optimized based on the idea of ​​first-in-first-out, least recently used, and least frequently used. When the cached data exceeds the maximum value, the LRU algorithm is used to replace it. The cache elimination algorithm uses FIFO and LFU.

[0070] S103, use the thread pool to execute and schedule tasks; initialize the thread pool and start it in the product; at the same time, apply the snowflake algorithm and the deployment algorithm in big data to the device distribution design.

[0071] like Figure 2 As shown, the data processing system for improving the efficiency of issuing digital currency provided by an embodiment of the present invention includes:

[0072] Intelligent prediction module 1 is used to use intelligent prediction technology to predict the safety measures to be issued later based on the current equipment status and complete the calculation in advance;

[0073] The third-level cache module 2 is used to apply the principle of the CPU's third-level cache to the software system in combination with parallel computing technology. It is optimized based on the ideas of first-in-first-out, least recently used, and least recently frequently used. When the cached data exceeds the maximum value, the LRU algorithm is used to replace it. The cache elimination algorithm uses FIFO and LFU.

[0074] The thread pool scheduling module 3 is used to use the thread pool to execute and schedule tasks; initialize the thread pool and start it in the product; and apply the snowflake algorithm and the distribution algorithm in big data to the device distribution design.

[0075] The technical solution of the present invention is further described below in conjunction with the explanation of terms.

[0076] Snowflake is Twitter's open-source distributed ID generation algorithm. Its core concept is to use a 64-bit long number as a globally unique ID. It is widely used in distributed systems, and the ID incorporates a timestamp, making it essentially auto-incremental. Detailed comments are included in the code below.

[0077] Bloom Filter: Proposed by Bloom in 1970, it is essentially a long binary vector and a series of random mapping functions. Bloom filters can be used to determine whether an element is in a set. Its advantages are space efficiency and query time far exceeding those of conventional algorithms. However, its disadvantages include a certain false positive rate and difficulty in deletion.

[0078] The technical solution of the present invention is further described below in conjunction with embodiments.

[0079] In response to the problems existing in the prior art, the present invention provides an implementation method based on three-level cache, intelligent prediction, thread pool and algorithm library.

[0080] By using this method, the following goals can be achieved in terms of security and performance:

[0081] (1) Fully supports SCP02 in the GP specification and can be expanded to SCP10. Fully supports the digital RMB specification and can be expanded to support PBOC and other industry specifications.

[0082] (2) Results of improved distribution efficiency: Concurrency performance increased 15 times, that is, the online distribution time for 100,000 devices was reduced from 5,000 seconds to 200 seconds.

[0083] (3) High availability architecture: layered architecture design, centralized storage, atomic computing, and unified scheduling. It supports multiple protocols and can quickly adapt to different access requirements.

[0084] (4) High availability of services: information caching, dynamic adjustment of service groups, automatic isolation of abnormal services, service load balancing, support for simplex and duplex secure communication, and support for online horizontal and vertical expansion of its own services.

[0085] (5) High data availability: Reasonable data structure design, sufficient cache computing and processing to ensure high data availability, database cluster mechanism, read-write separation, and reasonable resource allocation.

[0086] (6) Superior system performance optimization: Targeted at the transaction characteristics of TSM, we have implemented specialized optimizations, including algorithm optimization, structural optimization, data processing flow optimization, and algorithm enhancements: the time taken by the general library has been improved from 640 milliseconds to 0.176 milliseconds by the proprietary library. We innovatively apply the principle of the CPU's three-level cache to the software system and combine it with parallel computing technology. We also create unique intelligent pre-processing technology that predicts the security measures for subsequent issuance based on the current device status and completes calculations in advance. We innovatively apply the snowflake algorithm and the distribution algorithm from big data to the device issuance design to improve efficiency.

[0087] The core technologies of the present invention are as follows:

[0088] (1) Intelligent prediction technology predicts the subsequent security measures based on the current equipment status and completes the calculation in advance.

[0089] Intelligent prediction technology algorithm design idea: given the conditions SKUMAC and SKUENC session key, the input condition is the security domain AID, the algorithm is DES+final 3DES, the key is SKUMAC, calculate STRUCTURED, take the left 6B, and input the card challenge. Figure 3 shown.

[0090] Using the SKUENC session key, the algorithm uses 3DES-CBC, inputs the ICV, terminal random number, counter, card challenge, and supplements 80 to calculate the card CRYPTOGRAM, which is compared with the CRYPTOGRAM returned by the security chip. If the comparison is successful, it means that it can be predicted, and all instructions can be generated in advance.

[0091] After the intelligent prediction technology is launched, the issuance mode is changed from the original serial mode to the parallel mode, such as Figure 4 shown.

[0092] Process Description:

[0093] The terminal device initializes and initiates a request for the first batch of instructions. After receiving the request, the TSM generates the first batch of instructions and returns them to the terminal device. Simultaneously, a task is created and threads are used to asynchronously initiate intelligent prediction and calculate the authentication code.

[0094] After the intelligent prediction calculation completes the authentication code, it calculates the next batch of instructions, generates the ID of the next batch according to the snowflake algorithm, and saves it in the cache.

[0095] The terminal device requests the second batch of instructions and returns the results of the first batch of instructions. The results of the first batch of instructions include an authentication code. The authentication code returned by the terminal is compared with the intelligent prediction. If they are the same, the prediction is successful. The second batch of instructions is directly retrieved from the cache according to the Bloom algorithm. The same process is repeated for other batches of instructions.

[0096] The background no longer calculates the next batch of instructions in time, but instead calculates the instruction set and the next batch and obtains it through the cache.

[0097] (2)CPU three-level cache technology

[0098] The present invention applies the principle of CPU three-level cache to the software system and combines it with parallel computing technology to improve the issuance efficiency; based on the optimization ideas of first-in-first-out, least recently used, and least frequently used, when the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU.

[0099] FIFO: First In, First Out. In this elimination algorithm, the first items that enter the cache will be eliminated first, resulting in a very low hit rate.

[0100] LRU: Least Recently Used algorithm. Each time a piece of data is accessed, it is placed at the end of the queue. If data needs to be removed, it is removed from the head of the queue. However, there is still a problem. If a piece of data is accessed 1000 times in 1 minute, and then not accessed again in the next minute, but other data is accessed, this hot data will be removed.

[0101] LFU: Least Recently Used uses extra space to record the frequency of use of each data item, and then selects the item with the lowest frequency for elimination. This avoids the problem of LRU being unable to handle the time period.

[0102] The first-level cache uses memory. The goal of L1 is to reduce the number of reads from L2. It uses an expiration mechanism and manual cache recycling.

[0103] The second-level cache uses Redis. Due to the large number of cache reads, the L2 network becomes a bottleneck for the entire system. Expiration and manual cache recycling are used.

[0104] The third-level cache uses a database mechanism to achieve high availability of the program, but when L1 and L2 reach their maximum limits, the L3 cache is directly accessed.

[0105] (3)Thread pool technology

[0106] Creating a new thread each time to execute a task would consume a lot of system resources, so a thread pool is used to schedule tasks. The thread pool is initialized when the product is started.

[0107] The general thread pool has only one task queue, but for the issuance equipment business, since the batch instruction set can be intelligently predicted, the subtasks are actually parallel. In order to improve efficiency and reduce thread competition, these parallel tasks are placed in different queues, such as Figure 5In the example, the large task is decomposed into four subtasks: subtask 1, subtask 2, subtask 3, and subtask 4. Then four task queues are created, and then three worker threads are created corresponding to the queues one by one.

[0108] There is a basic idea in the field of algorithms called "divide and conquer". The so-called "divide and conquer" is to divide a large problem that is difficult to solve directly into several smaller sub-problems so that they can be solved one by one.

[0109] Based on the above ideas, we can split a large task into multiple small tasks for execution, and then merge the results of each small task into the return value we need.

[0110] Proof section (specific examples / experiments / simulations / pharmacological analysis / positive experimental data that can prove the inventiveness of the invention, etc.)

[0111] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented in whole or in part in the form of a computer program product, the computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL) or wireless (e.g., infrared, wireless, microwave, etc.)) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0112] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A data processing method for improving the efficiency of issuing digital currency, characterized in that: Applied to computer equipment, the data processing method for improving the efficiency of issuing digital currency includes the following steps: Step 1, using intelligent prediction technology to predict the security measures for subsequent issuance based on the current equipment status and perform calculations in advance; using the CPU three-level cache principle, combined with parallel computing technology, and applying it to the software system; Step 2, based on the first-in-first-out, least recently used, and least recently used principles, when the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU; Step 3, using the thread pool to execute and schedule tasks; initializing the thread pool and starting it in the product; and applying the snowflake algorithm and Bloom algorithm in big data to the device issuance design; Step 4 In the first, the intelligent prediction technology specifically includes: (1) the terminal device is initialized, a request is initiated, and the first batch of instructions is requested. After receiving the request, the TSM generates the first batch of instructions and returns them to the terminal device; at the same time, a task is created, and the thread pool is used to execute the asynchronous start of the intelligent prediction and calculate the authentication code; (2) after the intelligent prediction calculates the authentication code, the next batch of instructions is calculated, and the ID of the next batch is generated according to the snowflake algorithm and saved in the cache; (3) the terminal device requests the second batch of instructions and returns the execution result of the first batch of instructions. The result of the first batch of instructions includes the authentication code. The authentication code returned by the terminal is compared with the intelligent prediction. If they are the same, it means that the prediction is successful. The ID is directly obtained from the cache according to the Bloom algorithm. Get the second batch of instruction sets; other batches of instructions are deduced in the same way; (4) The background no longer calculates the next batch of instructions, but calculates the next batch of instruction sets and obtains them through the cache; in step 1, the use of intelligent prediction technology to calculate in advance includes: known conditions SKUMAC and SKUENC session key, input conditions are security domain AID, algorithm is DES+final3DES, key uses SKUMAC, calculates STRUCTURED, takes left 6B, inputs card challenge; uses SKUENC session key, algorithm uses 3DES-CBC, inputs ICV, terminal random number, counter, card challenge, supplement 80, calculates card CRYPTOG RAM is compared with the CRYPTOGRAM returned by the security chip. If the comparison is successful, it means that it can be predicted, and all instructions are generated in advance. After the intelligent prediction technology is started, the issuance mode is changed from the original serial mode to the parallel mode. In step 1, the CPU three-level cache technology includes: (1) FIFO: First-in-first-out. In this elimination algorithm, the first data to enter the cache will be eliminated first; (2) LRU: Least Recently Used Algorithm. Each time data is accessed, it will be placed at the end of the queue. If data needs to be eliminated, only the head of the queue needs to be eliminated; (3) LFU: Least Frequently Used. Extra space is used to record the frequency of use of each data, and then the lowest frequency data is selected for elimination.

2. The data processing method for improving the efficiency of issuing digital currency according to claim 1, characterized in that: In step 1, the CPU three-level cache technology includes: (1) the first-level cache uses memory; the goal of L1 is to reduce the number of reads to L2, and an expiration mechanism and a manual cache mechanism are used for recycling; (2) the second-level cache uses Redis; since a large number of cache reads will cause the L2 network to become a bottleneck of the entire system, an expiration mechanism and a manual cache mechanism are used for recycling; (3) the third-level cache uses a database mechanism, and when L1 and L2 reach the maximum limit, the L3 cache is directly accessed.

3. The data processing method for improving the efficiency of issuing digital currency according to claim 1, characterized in that: In step three, the thread pool technology includes: creating a new thread each time to execute a task, which will consume a lot of system resources, so the thread pool is used to schedule tasks, and the thread pool is initialized when the product is started; for the issuance equipment business, each batch of instruction sets can be intelligently predicted, and each subtask is actually a parallel relationship, so these parallel tasks are placed in different queues, and the large task is decomposed into four subtasks: subtask 1, subtask 2, subtask 3, and subtask 4, that is, four task queues are created, and then three working threads are created to correspond to the queues one by one.

4. A data processing system for improving the efficiency of issuing digital currency using the data processing method for improving the efficiency of issuing digital currency according to any one of claims 1 to 3, characterized in that: The data processing system for improving the efficiency of issuing digital currency includes: an intelligent prediction module, which is used to use intelligent prediction technology to predict the security measures for subsequent issuance based on the current device status and complete the calculation in advance; a three-level cache module, which is used to use the CPU three-level cache principle, combined with parallel computing technology, and applied to the software system; based on the optimization of the ideas of first-in-first-out, least recently used, and least frequently used, when the cached data exceeds the maximum value, the LRU algorithm is used to replace it, and the cache elimination algorithm uses FIFO and LFU; a thread pool scheduling module, which is used to use the thread pool to execute and schedule tasks; initialize the thread pool and start it in the product; and at the same time, apply the snowflake algorithm and Bloom algorithm in big data to the device issuance design.

5. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the data processing method for improving the efficiency of issuing digital currency as described in any one of claims 1 to 3.

6. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the data processing method for improving the efficiency of issuing digital currency as described in any one of claims 1 to 3.

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