Shift register, display driver, and display panel

Abstract

The present invention discloses a shift register, a display driver, and a display panel. The shift register includes: a trigger writing module configured to write a trigger signal into a first node according to a first clock signal; a power supply introducing module configured to write a first power supply signal into a second node according to the first clock signal; a first output adjusting module configured to adjust a first output signal of a first output terminal of the shift register according to the trigger signal of the first node and the first power supply signal of the second node; and a second output adjusting module configured to generate a second output signal of a second output terminal of the shift register, which is opposite to the first output signal, according to the trigger signal of the first node and the first output signal. The technical solution of the embodiment of the present invention realizes that two scanning signals can be output by using one shift register, thereby reducing the border of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular, to a shift register, a display driver, and a display panel. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more extensive, and the corresponding requirements for display panels are also getting higher and higher. In a display panel, various scanning signals required for pixel display need to be provided by a shift register. When different scanning signals are required for pixel circuits, different shift registers are needed to implement, which is not conducive to the narrow border design of the display panel. Summary of the Invention

[0003] The present invention provides a shift register, a display driver, and a display panel, so that one shift register can output two scanning signals, thereby reducing the border of the display panel.

[0004] According to an aspect of the present invention, a shift register is provided, which includes:

[0005] A trigger writing module, configured to write a trigger signal to a first node according to a first clock signal;

[0006] A power supply introducing module, configured to write a first power supply signal to a second node according to the first clock signal;

[0007] A first output adjusting module, configured to adjust a first output signal of a first output end of the shift register according to the trigger signal of the first node and the first power supply signal of the second node;

[0008] A second output adjusting module, configured to generate a second output signal of a second output end of the shift register, which is opposite to the first output signal, according to the trigger signal of the first node and the first output signal.

[0009] Optionally, the second output adjusting module includes:

[0010] A first pull-up sub-module, a first end of the first pull-up sub-module is connected to a second power supply signal, a second end of the first pull-up sub-module is electrically connected to the second output end, and a control end of the first pull-up sub-module is electrically connected to the first output end;

[0011] A first pull-down sub-module, a first end of the first pull-down sub-module is connected to the first power supply signal, a second end of the first pull-down sub-module is electrically connected to the second output end, and a control end of the first pull-down sub-module is electrically connected to the first node;

[0012] The on-control signal of the first pull-up sub-module is opposite to the on-control signal of the first pull-down sub-module.

[0013] Optionally, the second output adjustment module includes:

[0014] A first pull-up sub-module, a first end of the first pull-up sub-module is connected to a second power signal, a second end of the first pull-up sub-module is electrically connected to the second output end, and a control end of the first pull-up sub-module is electrically connected to the first node;

[0015] A first pull-down sub-module, a first end of the first pull-down sub-module is connected to the first power signal, a second end of the first pull-down sub-module is electrically connected to the second output end, and a control end of the first pull-down sub-module is electrically connected to the first output end;

[0016] The conduction control signal of the first pull-up sub-module is opposite to the conduction control signal of the first pull-down sub-module.

[0017] Optionally, the first pull-up sub-module includes a first transistor, a first end of the first transistor is the first end of the first pull-up sub-module, a second end of the first transistor is the second end of the first pull-up sub-module, and a control end of the first transistor is the control end of the first pull-up sub-module;

[0018] The first pull-down sub-module includes a second transistor, a first end of the second transistor is the first end of the first pull-down sub-module, a second end of the second transistor is the second end of the first pull-down sub-module, and a control end of the second transistor is the control end of the first pull-down sub-module;

[0019] The conduction control signal of the first transistor is opposite to the conduction control signal of the second transistor.

[0020] Optionally, the shift register further includes a third transistor;

[0021] A first end of the third transistor is electrically connected to the first node, a second end of the third transistor is electrically connected to the trigger write module, and a control end of the third transistor is connected to the first power signal; or,

[0022] A first end of the third transistor is electrically connected to the first output adjustment module, a second end of the third transistor is electrically connected to the first node, and a control end of the third transistor is connected to the first power signal.

[0023] Optionally, the shift register further includes:

[0024] A first feedback sub-module, the first feedback sub-module is configured to write the first clock signal to the second node according to the trigger signal of the first node;

[0025] A second feedback sub-module, which is configured to write a second power signal into the first node according to the first power signal and the second clock signal of the second node.

[0026] Optionally, the first output adjustment module includes:

[0027] A second pull-up sub-module, the first end of the second pull-up sub-module is connected to a second power signal, the second end of the second pull-up sub-module is electrically connected to the first output end, and the control end of the second pull-up sub-module is electrically connected to the second node;

[0028] A second pull-down sub-module, the first end of the second pull-down sub-module is connected to a second clock signal, the second end of the second pull-down sub-module is electrically connected to the first output end, and the control end of the second pull-down sub-module is electrically connected to the first node.

[0029] Optionally, the first output adjustment module further includes a first capacitor and a second capacitor;

[0030] The first end of the first capacitor is connected to a second power signal, and the second end of the first capacitor is electrically connected to the second node;

[0031] The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the first output end.

[0032] According to another aspect of the present invention, a display driver is provided, which includes a plurality of cascaded shift registers as described in any implementation manner of the present invention;

[0033] Wherein, the trigger signal of the nth stage shift register is provided by the output signal of the first output end of the (n - 1)th stage shift register, and n is an integer greater than or equal to 2.

[0034] According to another aspect of the present invention, a display panel is provided, which includes the display driver as described in any implementation manner of the present invention and a plurality of pixel circuits;

[0035] The first output end and the second output end of the shift register are used to provide scan signals to corresponding pixel circuits.

[0036] Optionally, the pixel circuit includes: a driving module, a light-emitting module, a threshold compensation module, a first initialization module and a storage module;

[0037] The driving module is configured to generate a driving current, and the light-emitting module is configured to respond to the driving current;

[0038] The storage module is configured to maintain the potential of the control end of the driving module;

[0039] The threshold compensation module is configured to capture the threshold voltage of the driving module to the control end of the driving module;

[0040] The first initialization module is configured to initialize the potential of the control end of the driving module;

[0041] Wherein, the control end of the first initialization module is electrically connected to the second output end of the corresponding shift register, the first end of the first initialization module receives an initialization signal, and the second end of the first initialization module is electrically connected to the control end of the driving module; the first end of the threshold compensation module is electrically connected to the control end of the driving module, the second end of the threshold compensation module is electrically connected to the first end of the driving module, and the control end of the threshold compensation module is electrically connected to the second output end of the corresponding shift register.

[0042] In the technical solution of the embodiment of the present invention, the shift register includes a first output adjustment module for adjusting a first output signal of the first output end of the shift register according to the potentials of a first node and a second node; a trigger writing module for writing a trigger signal into the first node according to a first clock signal; a power supply introduction module for writing a first power supply signal into the second node according to the first clock signal; and a second output adjustment module for generating a second output signal with a polarity opposite to that of the first output signal according to the potential of the first node and the first output signal, so that the shift register can provide two scanning signals with opposite polarities to meet the requirements of the pixel circuit, reduce the number of shift registers, and is beneficial to the narrow border design of the display panel. The technical solution of the embodiment of the present invention solves the problem that when different scanning signals are required for the pixel circuit, different shift registers are needed to implement, which is not beneficial to the narrow border design of the display panel, and realizes that two scanning signals can be output by using one shift register, thereby reducing the border of the display panel.

[0043] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0045] Figure 1 is a schematic circuit structure diagram of a shift register provided by an embodiment of the present invention;

[0046] Figure 2 It is a timing diagram of a shift register provided by an embodiment of the present invention;

[0047] Figure 3 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention;

[0048] Figure 4 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention;

[0049] Figure 5 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention;

[0050] Figure 6 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention;

[0051] Figure 7 It is a timing diagram of another shift register provided by an embodiment of the present invention;

[0052] Figure 8 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention;

[0053] Figure 9 It is a schematic circuit diagram of a display driver provided by an embodiment of the present invention;

[0054] Figure 10 It is a schematic circuit diagram of a display panel provided by an embodiment of the present invention;

[0055] Figure 11 It is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present invention. Detailed implementation manners

[0056] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0057] It should be noted that the terms "first", "second", etc. in the specification, claims and the above drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0058] Figure 1 is a schematic circuit structure diagram of a shift register provided by an embodiment of the present invention. Refer to Figure 1 , the shift register includes: a trigger writing module 102 for writing a trigger signal SIN into a first node N1 according to a first clock signal SCK1; a power supply introducing module 103 for writing a first power supply signal VGL into a second node N2 according to the first clock signal SCK1; a first output adjusting module 101 for adjusting a first output signal Gout1 at a first output end of the shift register according to the trigger signal SIN at the first node N1 and the first power supply signal VGL at the second node N2; and a second output adjusting module 104 for generating a second output signal Gout2 at a second output end of the shift register, which is opposite to the first output signal Gout1, according to the trigger signal SIN at the first node N1 and the first output signal Gout1.

[0059] Specifically, the trigger writing module 102 can write the trigger signal SIN input at the trigger signal input terminal into the first node N1 according to the first clock signal SCK1. The shift register can shift the trigger signal SIN and output it through its first output terminal. That is, the output signal Gout1 at the first output terminal of the shift register is the shifted signal of the trigger signal SIN. The first output adjustment module 101 can output a second power supply signal VGH or a second clock signal SCK2. For example, when the potential of the first node N1 enables the first output adjustment module 101, the second clock signal SCK2 is output at the first output terminal of the shift register; when the potential on the second node N2 enables the first output adjustment module 101, the second power supply signal VGH is output at the first output terminal of the shift register; and the potential of the first node N1 is controlled by the trigger writing module 102, that is, under the control of the first clock signal SCK1, the trigger signal SIN is written into the first node N1; the first clock signal SCK1 and the second clock signal SCK2 can be anti-phase signals, that is, when the first clock signal SCK1 is at a low level during operation, the second clock signal SCK2 is at a high level, and when the first clock signal SCK1 is at a high level, the second clock signal SCK2 is at a low level; the second node N2 is controlled by the power supply introduction module 103. The power supply introduction module 103 writes the first power supply signal VGL into the second node N2 under the control of the first clock signal SCK1. The first power supply signal VGL and the second power supply signal VGH are opposite signals. For example, the first power supply signal VGL is at a low level and the second power supply signal VGH is at a high level; through the cooperative control of the first clock signal SCK1 and the second clock signal SCK2, the first output signal Gout1 at the first output terminal of the shift register is shifted relative to the trigger signal SIN; the first output signal Gout1 at the first output terminal of the shift register can be used as the scan signal of the pixel in the display panel. The potential of the first node N1 and the first output signal Gout1 can also be used to control the second output adjustment module 104, so that the second output adjustment module 104 can output the first power supply signal VGL or the second power supply signal VGH; for example, when the potential of the first node N1 enables the second output adjustment module 104, the second output adjustment module 104 outputs the first power supply signal VGL, that is, the second output signal Gout2 output at the second output terminal of the shift register is the first power supply signal VGL; when the first output signal Gout1 enables the second output adjustment module 104, the second output adjustment module 104 outputs the second power supply signal VGH, that is, the second output signal Gout2 output at the second output terminal of the shift register is the second power supply signal VGH; the second output signal Gout2 at the second output terminal of the shift register can be used as the scan signal of the pixel in the display panel.

[0060] In this embodiment, the second output signal Gout2 of the shift register can be adjusted according to the first output signal Gout1. When the first output signal Gout1 is at a high level, the second output signal Gout2 of the second output terminal of the shift register is at a low level; when the first output signal Gout1 is at a low level, the second output signal Gout2 of the second output terminal of the shift register is at a high level. That is, the second output signal Gout2 of the second output terminal of the shift register has a polarity opposite to that of the first output signal Gout1, so that the shift register can provide two scanning signals with opposite polarities to meet the requirements of the pixel circuit, reduce the number of shift registers, and is beneficial to the narrow bezel design of the display panel.

[0061] In addition, by using the first node N1 and the first output signal Gout1 to control the second output adjustment module 104, the load of the first output terminal can be reduced, and the distortion of the first output signal Gout1 can be avoided, thereby ensuring the accuracy of the first output signal Gout1.

[0062] Figure 2 It is a timing diagram of a shift register provided by an embodiment of the present invention, which can correspond to Figure 1 the shift register shown in Figure 1 and Figure 2 . In this embodiment, exemplarily, the first output adjustment module 101, the trigger writing module 102, and the power supply introduction module 103 are turned on at a low level and turned off at a high level; the second output adjustment module 104 can output different signals according to high and low levels; the working process of the shift register can include six stages from t1 to t6:

[0063] In the t1 stage, the trigger signal SIN is at a low level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the trigger writing module 102 is turned on, and the trigger signal SIN is written into the first node N1. The potential of the first node N1 is at a low level, and the potential of the first node N1 enables the first output adjustment module 101 to output the second clock signal SCK2; the power supply introduction module 103 is turned on, and the first power supply signal VGL is written into the second node N2. The potential of the second node N2 is at a low level, and the potential of the second node N2 enables the first output adjustment module 101 to output the second power supply signal VGH, that is, the first output signal Gout1 is at a high level; the first output signal Gout1 or the potential of the first node N1 enables the second output adjustment module 104 to output the first power supply signal VGL, that is, the second output signal Gout2 is at a low level;

[0064] At stage t2, the trigger signal SIN is at high level, the first clock signal SCK1 is at high level, and the second clock signal SCK2 is at low level; the trigger writing module 102 and the power supply introducing module 103 are turned off, the first node N1 maintains a low level, and the potential of the first node N1 enables the first output regulating module 101 to output the second clock signal SCK2, that is, the first output signal Gout1 is at low level; the first output signal Gout1 or the potential of the first node N1 enables the second output regulating module 104 to output the second power supply signal VGH, that is, the second output signal Gout2 is at high level;

[0065] At stage t3, the trigger signal SIN is at high level, the first clock signal SCK1 is at low level, and the second clock signal SCK2 is at high level; the power supply introducing module 103 is turned on, and the first power supply signal VGL is written into the second node N2. The potential of the second node N2 is at low level, and the potential of the second node N2 enables the first output regulating module 101 to output the second power supply signal VGH, that is, the first output signal Gout1 is at high level; the trigger writing module 102 is turned on, and the trigger signal SIN is written into the first node N1. The potential of the first node N1 is at high level, and the potential of the first node N1 or the first output signal Gout1 enables the second output regulating module 104 to output the first power supply signal VGL, that is, the second output signal Gout2 is at low level;

[0066] At stage t4, the trigger signal SIN is at high level, the first clock signal SCK1 is at high level, and the second clock signal SCK2 is at low level; the trigger writing module 102 and the power supply introducing module 103 are turned off, the first node N1 maintains a high level, the second node N2 maintains a low level, and the potential of the second node N2 enables the first output regulating module 101 to output the second power supply signal VGH, that is, the first output signal Gout1 is at high level; the potential of the first node N1 or the first output signal Gout1 enables the second output regulating module 104 to output the first power supply signal VGL, that is, the second output signal Gout2 is at low level;

[0067] At stage t5, the trigger signal SIN is at high level, the first clock signal SCK1 is at low level, and the second clock signal SCK2 is at high level; the power supply introducing module 103 is turned on, and the first power supply signal VGL is written into the second node N2. The potential of the second node N2 is at low level, and the potential of the second node N2 enables the first output regulating module 101 to output the second power supply signal VGH, that is, the first output signal Gout1 is at high level; the trigger writing module 102 is turned on, and the trigger signal SIN is written into the first node N1. The potential of the first node N1 is at high level, and the potential of the first node N1 or the first output signal Gout1 enables the second output regulating module 104 to output the first power supply signal VGL, that is, the second output signal Gout2 is at low level;

[0068] At stage t6, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the trigger write module 102 and the power supply introduction module 103 are turned off, the first node N1 maintains a high level, the second node N2 maintains a low level, and the potential of the second node N2 enables the first output adjustment module 101 to output the second power signal VGH, that is, the first output signal Gout1 is at a high level; the potential of the first node N1 or the first output signal Gout1 enables the second output adjustment module 104 to output the first power signal VGL, that is, the second output signal Gout2 is at a low level.

[0069] Therefore, the polarities of the first output signal Gout1 and the second output signal Gout2 are opposite, that is, the shift register can output two different scan signals, which can meet the requirements of the pixel circuits in the display panel for different scan signals, can reduce the number of shift registers, and is beneficial to reducing the border of the display panel.

[0070] In the technical solution of this embodiment, the shift register includes a first output adjustment module for adjusting the first output signal of the first output end of the shift register according to the potentials of the first node and the second node; a trigger write module for writing the trigger signal into the first node according to the first clock signal; a power supply introduction module for writing the first power signal into the second node according to the first clock signal; a second output adjustment module for generating a second output signal with a polarity opposite to that of the first output signal according to the potential of the first node and the first output signal, so that the shift register can provide two scan signals with opposite polarities to meet the requirements of the pixel circuit, reduce the number of shift registers, and is beneficial to the narrow border design of the display panel. The technical solution of this embodiment solves the problem that when different scan signals are required by the pixel circuit, different shift registers are needed to implement, which is not conducive to the narrow border design of the display panel, and realizes that two scan signals can be output by using one shift register, thereby reducing the border of the display panel.

[0071] Figure 3 It is a schematic circuit diagram of another shift register provided by an embodiment of the present invention. Optionally, refer to Figure 3, the second output adjustment module 104 includes: a first pull-up sub-module 1041, a first end of the first pull-up sub-module 1041 is connected to a second power signal VGH, a second end of the first pull-up sub-module 1041 is electrically connected to a second output end, and a control end of the first pull-up sub-module 1041 is electrically connected to a first output end; a first pull-down sub-module 1042, a first end of the first pull-down sub-module 1042 is connected to a first power signal VGL, a second end of the first pull-down sub-module 1042 is electrically connected to the second output end, and a control end of the first pull-down sub-module 1042 is electrically connected to a first node N1; a conduction control signal of the first pull-up sub-module 1041 is opposite to a conduction control signal of the first pull-down sub-module 1042.

[0072] Specifically, the first pull-up sub-module 1041 and the first pull-down sub-module 1042 are turned on in response to control signals of different polarities, that is, when the first pull-up sub-module 1041 is turned on, the first pull-down sub-module 1042 is turned off; when the first pull-up sub-module 1041 is turned off, the first pull-down sub-module 1042 is turned on; for example, when a first output signal Gout1 is at a low level, the first pull-up sub-module 1041 is turned on, and the first pull-up sub-module 1041 outputs the second power signal VGH, that is, a second output signal Gout2 is at a high level; when a potential of the first node N1 is at a high level, the first pull-down sub-module 1042 is turned on, and the first pull-down sub-module 1042 outputs the first power signal VGL, that is, the second output signal Gout2 is at a low level.

[0073] Or, Figure 4 is a schematic circuit diagram of another shift register provided by an embodiment of the present invention. Optionally, refer to Figure 4 , the second output adjustment module 104 includes: a first pull-up sub-module 1041, a first end of the first pull-up sub-module 1041 is connected to a second power signal VGH, a second end of the first pull-up sub-module 1041 is electrically connected to a second output end, and a control end of the first pull-up sub-module 1041 is electrically connected to a first node N1; a first pull-down sub-module 1042, a first end of the first pull-down sub-module 1042 is connected to a first power signal VGL, a second end of the first pull-down sub-module 1042 is electrically connected to the second output end, and a control end of the first pull-down sub-module 1042 is electrically connected to a first output end; a conduction control signal of the first pull-up sub-module 1041 is opposite to a conduction control signal of the first pull-down sub-module 1042.

[0074] Specifically, the first pull-up sub-module 1041 and the first pull-down sub-module 1042 are turned on in response to control signals of different polarities. That is, when the first pull-up sub-module 1041 is turned on, the first pull-down sub-module 1042 is turned off; when the first pull-up sub-module 1041 is turned off, the first pull-down sub-module 1042 is turned on. For example, when the first output signal Gout1 is at a high level, the first pull-down sub-module 1042 is turned on, and the first pull-down sub-module 1042 outputs the first power supply signal VGL, that is, the second output signal Gout2 is at a low level; when the potential of the first node N1 is at a low level, the first pull-up sub-module 1041 is turned on, and the first pull-up sub-module 1041 outputs the second power supply signal VGH, that is, the second output signal Gout2 is at a high level.

[0075] Figure 5 is a schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention. Optionally, referring to Figure 5 , the first pull-up sub-module 1041 includes a first transistor M1. The first end of the first transistor M1 is the first end of the first pull-up sub-module 1041, the second end of the first transistor M1 is the second end of the first pull-up sub-module 1041, and the control end of the first transistor M1 is the control end of the first pull-up sub-module 1041; the first pull-down sub-module 1042 includes a second transistor M2. The first end of the second transistor M2 is the first end of the first pull-down sub-module 1042, the second end of the second transistor M2 is the second end of the first pull-down sub-module 1042, and the control end of the second transistor M2 is the control end of the first pull-down sub-module 1042; the turn-on control signal of the first transistor M1 is opposite to the turn-on control signal of the second transistor M2.

[0076] Specifically, the types of the first transistor M1 and the second transistor M2 are different. For example, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor. When the potential of the first node N1 is at a high level, the second transistor M2 is turned on, and the second transistor M2 outputs the first power supply signal VGL, that is, the second output signal Gout2 at the second output end is at a low level; when the first output signal Gout1 is at a low level, the first transistor M1 is turned on, and the first transistor M1 outputs the second power supply signal VGH, that is, the second output signal Gout2 at the second output end is at a high level, so that the polarities of the first output signal Gout1 and the second output signal Gout2 are opposite.

[0077] Optionally, the shift register further includes a third transistor M3; a first end N11 of the third transistor M3 is electrically connected to the first node N1, a second end N12 of the third transistor M3 is electrically connected to the trigger writing module 102, and a control end of the third transistor M3 is connected to a first power supply signal VGL; or, the first end N11 of the third transistor M3 is electrically connected to the first output adjustment module 101, the second end N12 of the third transistor M3 is electrically connected to the first node N1, and the control end of the third transistor M3 is connected to the first power supply signal VGL.

[0078] Specifically, with continued reference to Figure 5 , the second output adjustment module 104 is electrically connected to the first end N11 of the third transistor M3. The third transistor M3 is, for example, a P-type transistor, and the control end of the third transistor M3 is connected to the first power supply signal VGL. Therefore, the third transistor M3 is always in a conducting state. For example, when the trigger writing module 102 is conducting, a trigger signal SIN is written to the second end N12 of the third transistor M3. When the trigger signal SIN is at a low level, the second end N12 of the third transistor M3 is at a low level, and the first end N11 of the third transistor M3 is also at a low level. The second transistor M2 is not conducting, and the second output adjustment module 104 maintains the signal output of the previous frame; when the trigger signal SIN is at a high level, the second end N12 of the third transistor M3 is at a high level, the first end N11 of the third transistor M3 is at a high level, the second transistor M2 is conducting, and the second output adjustment module 104 outputs the first power supply signal VGL, that is, the second output signal Gout2 at the second output end of the shift register is at a low level, thereby adjusting the second output signal Gout2 at the second output end of the shift register.

[0079] Or, Figure 6 is a schematic circuit diagram of another shift register provided by an embodiment of the present invention. Referring to Figure 6 , the second output adjustment module 104 is electrically connected to the second end N12 of the third transistor M3. The third transistor M3 is, for example, a P-type transistor, and the control end of the third transistor M3 is connected to the first power supply signal VGL. Therefore, the third transistor M3 is always in a conducting state. For example, when the trigger writing module 102 is conducting, a trigger signal SIN is written to the second end N12 of the third transistor M3. When the trigger signal SIN is at a low level, the second end N12 of the third transistor M3 is at a low level, the second transistor M2 is not conducting, and the second output adjustment module 104 maintains the signal output of the previous frame; when the trigger signal SIN is at a high level, the second end N12 of the third transistor M3 is at a high level, the second transistor M2 is conducting, and the second output adjustment module 104 outputs the first power supply signal VGL, that is, the second output signal Gout2 at the second output end of the shift register is at a low level, thereby adjusting the second output signal Gout2 at the second output end of the shift register.

[0080] Optionally, continuing to refer to Figure 5 , the shift register further includes: a first feedback sub-module for writing the first clock signal SCK1 to the second node N2 according to the trigger signal SIN of the first node N1; a second feedback sub-module for writing the second power supply signal VGH to the first node N1 according to the first power supply signal VGL and the second clock signal SCK2 of the second node N2.

[0081] Exemplarily, the first feedback sub-module includes a fourth transistor M4. The first end of the fourth transistor M4 is connected to the first clock signal SCK1, the second end of the fourth transistor M4 is electrically connected to the second node N2, and the control end of the fourth transistor M4 is electrically connected to the first node N1. The second feedback sub-module includes a fifth transistor M5 and a sixth transistor M6. The first end of the fifth transistor M5 is connected to the second power supply signal VGH, the second end of the fifth transistor M5 is electrically connected to the first end of the sixth transistor M6, and the control end of the fifth transistor M5 is electrically connected to the second node N2. The second end of the sixth transistor M6 is electrically connected to the first node N1, and the control end of the sixth transistor M6 is connected to the second clock signal SCK2. The first feedback module can feedback-control the second node N2 according to the potential of the first node N1, so that when the second clock signal SCK2 is at a low level and the second pull-down sub-module of the first output adjustment module 101 is turned on, the second pull-up sub-module of the first output adjustment module 101 is in an off state, preventing the first output end of the shift register from outputting high and low levels simultaneously, that is, preventing the occurrence of instability of Gout1; the second feedback module can feedback-control the potential of the first node N1 according to the potential of the second node N2, so that when the second clock signal SCK2 is at a low level and the second node N2 is at a low level, the first node N1 is controlled to be at a high level, preventing the first output end of the shift register from outputting high and low levels simultaneously, that is, preventing the occurrence of instability of Gout1.

[0082] Optionally, continuing to refer to Figure 5 , the first output adjustment module 101 includes: a second pull-up sub-module, the first end of the second pull-up sub-module is connected to the second power supply signal, the second end of the second pull-up sub-module is electrically connected to the first output end, and the control end of the second pull-up sub-module is electrically connected to the second node; a second pull-down sub-module, the first end of the second pull-down sub-module is connected to the second clock signal, the second end of the second pull-down sub-module is electrically connected to the first output end, and the control end of the second pull-down sub-module is electrically connected to the first node.

[0083] Exemplarily, the second pull-up sub-module includes a seventh transistor M7. The first end of the seventh transistor M7 is the first end of the second pull-up sub-module, the second end of the seventh transistor M7 is the second end of the second pull-up sub-module, and the control end of the seventh transistor M7 is the control end of the second pull-up sub-module. The second pull-down sub-module includes an eighth transistor M8. The first end of the eighth transistor M8 is the first end of the second pull-down sub-module, the second end of the eighth transistor M8 is the second end of the second pull-down sub-module, and the control end of the eighth transistor M8 is the control end of the second pull-down sub-module. The seventh transistor M7 and the eighth transistor M8 are, for example, P-type transistors. In some other embodiments, the seventh transistor M7 and the eighth transistor M8 can also be transistors of other types, which are not limited herein.

[0084] Specifically, when the trigger writing module 102 is turned on, the trigger signal SIN is written to the first node N1. When the trigger signal SIN is at a low level, the potential of the first node N1 is at a low level, and the eighth transistor M8 is turned on. The eighth transistor M8 outputs the second clock signal SCK2, that is, the second clock signal SCK2 is output at the first output terminal. When the power supply introduction module 103 is turned on, the first power signal VGL is written to the second node N2, causing the seventh transistor M7 to be turned on. The seventh transistor M7 outputs the second power signal VGH, that is, the first output signal Gout1 output at the first output terminal is at a high level, thereby realizing the adjustment of the first output signal Gout1 at the first output terminal of the shift register.

[0085] Optionally, continue to refer to Figure 5 , the first output adjustment module 101 further includes a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1 is connected to the second power signal VGH, and the second end of the first capacitor C1 is electrically connected to the second node N2; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first output terminal.

[0086] Specifically, the first capacitor C1 has an energy storage function and can maintain the potential of the second node N2; the second capacitor C2 has an energy storage function and can maintain the potential of the first node N1; and the second capacitor C2 has a bootstrap function. For example, in the previous stage, the potential of the second end of the second capacitor C2 is VGH, and the potential of the first end of the second capacitor C2 is VGL + Vth; in the current stage, the second end of the second capacitor C2 is at a low level and the voltage decreases. Due to the bootstrap function of the second capacitor C2, the second capacitor C2 will keep the voltage difference between the two ends unchanged, so the first end N11 of the second capacitor C2 is at an ultra-low level, making the node N11 at an ultra-low level.

[0087] Optionally, continue to refer to Figure 5, the trigger write module 102 includes a ninth transistor M9. The first end of the ninth transistor M9 is the first end of the trigger write module 102, the second end of the ninth transistor M9 is the second end of the trigger write module 102, and the control end of the ninth transistor M9 is the control end of the trigger write module 102. The power supply introduction module 103 includes a tenth transistor M10. The first end of the tenth transistor M10 is the first end of the power supply introduction module 103, the second end of the tenth transistor M10 is the second end of the power supply introduction module 103, and the control end of the tenth transistor M10 is the control end of the power supply introduction module 103.

[0088] Figure 7 is the timing diagram of another shift register provided by the embodiment of the present invention. Refer to Figure 5 and Figure 7 , the second transistor M2 is, for example, an N-type transistor, which conducts when the level is high and turns off when the level is low; the remaining transistors in the shift register are, for example, all P-type transistors, which conduct when the level is low and turn off when the level is high; the working process of the shift register may include six stages from t1 to t6:

[0089] In the t1 stage, the trigger signal SIN is at a low level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the ninth transistor M9 and the tenth transistor M10 are turned on. The ninth transistor M9 writes the trigger signal SIN to the second end N12 of the third transistor M3. The second end N12 of the third transistor M3 is at a low level of VGL+Vth, where Vth is the threshold voltage of the ninth transistor M9; the third transistor M3 is turned on, and the first end N11 of the third transistor M3 is at a low level of VGL+Vth; the potential of the node N11 causes the eighth transistor M8 to be turned on, and the eighth transistor M8 outputs the second clock signal SCK2, that is, the first output signal Gout1 at the first output end = VGH. The tenth transistor M10 writes the first power supply signal VGL to the second node N2. The potential of the second node N2 is VGL+Vth, where Vth is the threshold voltage of the tenth transistor M10; the potential of the second node N2 causes the seventh transistor M7 to be turned on, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 at the first output end = VGH. The potential of the node N11 cannot turn on the second transistor M2, and the first output signal Gout1 cannot turn on the first transistor M1, so the second output signal Gout2 maintains the second output signal of the previous frame.

[0090] In stage t2, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the ninth transistor M9 and the tenth transistor M10 are turned off, and the second terminal N12 of the third transistor M3 maintains a low level of VGL + Vth; the third transistor M3 is turned on, so the first terminal N11 of the third transistor M3 is at a low level, and the potential of node N11 causes the eighth transistor M8 to turn on. The eighth transistor M8 outputs the second clock signal SCK2, that is, the first output signal Gout1 = VGL; in the previous stage, the potential of the second terminal of the second capacitor C2 is VGH, and the potential of the first terminal of the second capacitor C2 is VGL + Vth. In this stage, the second terminal of the second capacitor C2 is at a low level, and the voltage decreases. Due to the bootstrap effect of the second capacitor C2, the second capacitor C2 will maintain the voltage difference across its two ends unchanged, so the first terminal N11 of the second capacitor C2 is at an ultra-low level, that is, node N11 is at an ultra-low level; the potential of node N12 causes the fourth transistor M4 to turn on, and the fourth transistor M4 writes the first clock signal SCK1 to the second node N2, making the second node N2 at a high level VGH, and the seventh transistor is turned off. The potential of node N11 causes the first transistor M1 to turn off; the first output signal Gout1 causes the first transistor M1 to turn on, and the first transistor M1 outputs the second power supply signal VGH, that is, the second output signal Gout2 = VGH; thus, the second output signal Gout2 and the first output signal Gout1 have opposite polarities.

[0091] Or, Figure 8 is a schematic circuit diagram of another shift register provided by an embodiment of the present invention. Refer to Figure 8 , the control terminal of the first pull-up sub-module 1041 in the second output adjustment module 104 is electrically connected to the first terminal N11 of the third transistor M3, that is, the control terminal of the first transistor M1 is electrically connected to the first terminal N11 of the third transistor M3. When the first terminal N11 of the third transistor M3 is at an ultra-low potential, the first transistor M1 can be turned on more fully, so that the second output signal Gout2 output by the first transistor M1 better meets the requirements for the scan signal.

[0092] At stage t3, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the tenth transistor M10 is turned on, and the tenth transistor M10 writes the first power supply signal VGL to the second node N2. The potential of the second node N2 is at a low level VGL + Vth. The potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 = VGH; the ninth transistor M9 is turned on, and the trigger signal SIN is written to the second terminal N12 of the third transistor M3. The second terminal N12 of the third transistor M3 is at a high level VGH, and the third transistor M3 is turned on, so the first terminal N11 of the third transistor M3 is at a high level VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power supply signal VGL, that is, the second output signal Gout2 = VGL; thus, the second output signal Gout2 and the first output signal Gout1 have opposite polarities.

[0093] At stage t4, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the ninth transistor M9 and the tenth transistor M10 are turned off, the potentials of the node N11 and the node N12 are maintained at a high level VGH, and the potential of the second node N2 is maintained at a low level VGL + Vth; the potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 = VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power supply signal VGL, that is, the second output signal Gout2 = VGL; thus, the second output signal Gout2 and the first output signal Gout1 have opposite polarities.

[0094] At stage t5, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the tenth transistor M10 is turned on, and the tenth transistor M10 writes the first power supply signal VGL to the second node N2. The potential of the second node N2 is at a low level VGL + Vth. The potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 = VGH; the ninth transistor M9 is turned on, and the trigger signal SIN is written to the second terminal N12 of the third transistor M3. The second terminal N12 of the third transistor M3 is at a high level VGH, and the third transistor M3 is turned on, so the first terminal N11 of the third transistor M3 is at a high level VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power supply signal VGL, that is, the second output signal Gout2 = VGL; thus, the second output signal Gout2 and the first output signal Gout1 have opposite polarities.

[0095] At stage t6, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the ninth transistor M9 and the tenth transistor M10 are turned off, the potentials of node N11 and node N12 are maintained at a high level VGH, and the potential of the second node N2 is maintained at a low level VGL + Vth; the potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power signal VGH, that is, the first output signal Gout1 = VGH; the potential of node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power signal VGL, that is, the second output signal Gout2 = VGL; thus, the second output signal Gout2 has a polarity opposite to that of the first output signal Gout1.

[0096] In addition, referring to Figure 6 , connecting the control terminal of the second transistor M2 to the second terminal N12 of the third transistor M3 can prevent the gate-source voltage difference of the second transistor M2 from being too large when the first terminal N11 of the third transistor M3 is at an ultra-low level, thereby damaging the second transistor M2.

[0097] Figure 9 is a schematic circuit diagram of a display driver provided by an embodiment of the present invention. Referring to Figure 9 , the display driver 201 includes a plurality of cascaded shift registers 2011, and the shift register 2011 is the shift register provided by any embodiment of the present invention; wherein, the trigger signal SIN of the nth-stage shift register is provided by the output signal SCK1 of the first output terminal of the (n - 1)th-stage shift register, and n is greater than or equal to 2.

[0098] Specifically, the display driver 201 can be applied to a display panel to provide a scan signal for a pixel circuit in the display panel. Since it includes the shift register provided by any embodiment of the present invention, it also has the same beneficial effects and will not be elaborated herein. The display driver 201 can be disposed at the border position of the display panel. Preferably, two display drivers 201 can be disposed on both sides of the display panel respectively, thereby reducing the voltage drop on the data line in the display area of the display panel and improving the display uniformity.

[0099] Exemplarily, the first clock signal of the mth row pixel circuit is connected to the first clock signal input terminal of the mth-stage shift register, and the second clock signal of the mth row pixel circuit is connected to the second clock signal input terminal of the mth-stage shift register; the first clock signal of the (m + 1)th row pixel circuit is connected to the second clock signal input terminal of the (m + 1)th-stage shift register, and the second clock signal of the (m + 1)th row pixel circuit is connected to the first clock signal input terminal of the (m - 1)th-stage shift register; this facilitates the shift register to perform shift output on the trigger signal. Wherein, m is a positive integer greater than or equal to 1 and m is an odd number.

[0100] Figure 10 is a schematic circuit diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 10 , the display panel includes the display driver 201 provided by any embodiment of the present invention and a plurality of pixel circuits PX; the first output terminal and the second output terminal of the shift register 2011 are used to provide scan signals to the corresponding pixel circuits.

[0101] Specifically, the display panel may include a display area and a non-display area. The display area may include a plurality of data lines and scan lines that intersect horizontally and vertically to define the area of the pixel circuit; the display panel may be, for example, a display panel on a mobile phone, a tablet, an MP3, an MP4, a smart watch, a smart helmet, or other wearable devices, etc. Since it includes the display driver provided by any embodiment of the present invention, it also has the same beneficial effects and will not be elaborated here.

[0102] Exemplarily, the pixel circuit includes: a driving module, a light-emitting module, a threshold compensation module, a first initialization module, and a storage module; the driving module is used to generate a driving current, and the light-emitting module is used to emit light in response to the driving current; the storage module is used to maintain the potential of the control terminal of the driving module; the threshold compensation module is used to capture the threshold voltage of the driving module to the control terminal of the driving module; the first initialization module is used to initialize the potential of the control terminal of the driving module; wherein, the control terminal of the first initialization module is electrically connected to the second output terminal of the corresponding shift register, the first terminal of the first initialization module accesses the initialization signal Vref, and the second terminal of the first initialization module is electrically connected to the control terminal of the driving module; the first terminal of the threshold compensation module is electrically connected to the control terminal of the driving module, the second terminal of the threshold compensation module is electrically connected to the first terminal of the driving module, and the control terminal of the threshold compensation module is electrically connected to the second output terminal of the corresponding shift register.

[0103] Specifically, Figure 11 is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present invention, as Figure 11As shown, the driving module includes an eleventh transistor M11; the pixel circuit further includes a data writing module, the data writing module includes a twelfth transistor M12, the threshold compensation module includes a thirteenth transistor M13; the pixel circuit further includes a first light emission control module and a second light emission control module, wherein the first light emission control module includes a fourteenth transistor M14, the second light emission control module includes a fifteenth transistor M15, the pixel circuit further includes a second initialization module, the second initialization module includes a sixteenth transistor M16, the first initialization module includes a seventeenth transistor M17; the storage module includes a third capacitor C3; the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17 and the third capacitor C3 are connected to form Figure 11The structure shown; wherein, the control terminal of the twelfth transistor M12 in the pixel circuit of the nth row is electrically connected to the first output terminal of the nth-stage shift register, and the control terminal of the thirteenth transistor M13 in the pixel circuit of the nth row is electrically connected to the second output terminal of the nth-stage shift register; the control terminal of the seventeenth transistor M17 in the pixel circuit of the nth row is electrically connected to the second output terminal of the (n-1)th-stage shift register; the control terminal of the sixteenth transistor in the pixel circuit of the nth row is electrically connected to the first output terminal of the (n-1)th-stage shift register. The eleventh transistor M11, the twelfth transistor M12, the fourteenth transistor M14, the fifteenth transistor M15, and the sixteenth transistor M16 can be P-type low-temperature polysilicon (LTPS) transistors, while the thirteenth transistor M13 and the seventeenth transistor M17 can be oxide thin-film transistors, such as IGZO, so as to reduce the leakage phenomenon at the control terminal of the driving module and improve the stability. In this embodiment, the thirteenth transistor M13 and the seventeenth transistor M17 are turned on when their control terminals are at a high level, while the remaining transistors are turned on when their control terminals are at a low level; the driving process of the pixel circuit includes an initialization stage, a threshold compensation stage, and a light-emitting stage. In the initialization stage, the sixteenth transistor M16 and the seventeenth transistor M17 are turned on. The sixteenth transistor M16 initializes the light-emitting module with the initialization signal Vref to prevent the signal of the previous frame from affecting the light emission of this frame; the seventeenth transistor M17 initializes the control terminal of the eleventh transistor M11 with the initialization signal Vref. In the threshold compensation stage, the thirteenth transistor M13 is turned on, the twelfth transistor M12 is turned on, and the data signal Data is written into the control terminal of the eleventh transistor M11 through the twelfth transistor M12, the thirteenth transistor M13, and the eleventh transistor M11 until the eleventh transistor M11 is turned off. In this process, the threshold voltage of the eleventh transistor M11 is captured by the data signal Data. In the light-emitting stage, the fourteenth transistor M14, the eleventh transistor M11, and the fifteenth transistor M15 are turned on. With the cooperation of the first level signal VDD and the second level signal VSS, the light-emitting module emits light in response to the driving current of the driving module, and the driving current is independent of the threshold voltage of the driving module.As can be seen from the above driving process, in the initialization stage, the seventeenth transistor M17 and the sixteenth transistor M16 need to be turned on, and the seventeenth transistor M17 needs to be turned on with a high level, while the sixteenth transistor M16 needs to be turned on with a low level. In the threshold compensation stage, the thirteenth transistor M13 needs to be turned on, and its conduction level is high, and the twelfth transistor M12 needs to be turned on, and its conduction level is low; that is, the pixel circuit requires two different types of scan signals. Different types of scan signals can be understood as scan signals with different polarities, that is, one scan signal cannot be obtained by shifting another scan signal; and the shift register provided in this embodiment can provide scan signals for the thirteenth transistor M13 and the seventeenth transistor M17 of the pixel circuit, and can also provide scan signals for the twelfth transistor M12 and the sixteenth transistor M16, which can meet the driving requirements of the pixel circuit in the display panel for multiple scan signals; and the number of components and signal lines required by the shift register is small, which is beneficial to reducing the border of the display panel.

[0104] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A shift register, characterized in that, Comprising: A trigger write module for writing a trigger signal to a first node according to a first clock signal; A power supply introduction module for writing a first power supply signal to a second node according to the first clock signal; A first output adjustment module for adjusting a first output signal at a first output end of the shift register according to the trigger signal at the first node and the first power supply signal at the second node; A second output adjustment module for generating a second output signal at a second output end of the shift register opposite to the first output signal according to the trigger signal at the first node and the first output signal; The second output adjustment module includes: A first pull-up sub-module, a first end of the first pull-up sub-module is connected to a second power supply signal, and a second end of the first pull-up sub-module is electrically connected to the second output end; A first pull-down sub-module, a first end of the first pull-down sub-module is connected to the first power supply signal, and a second end of the first pull-down sub-module is electrically connected to the second output end; A control end of the first pull-up sub-module is electrically connected to the first output end, and a control end of the first pull-down sub-module is electrically connected to the first node; or, a control end of the first pull-up sub-module is electrically connected to the first node, and a control end of the first pull-down sub-module is electrically connected to the first output end; A conduction control signal of the first pull-up sub-module is opposite to a conduction control signal of the first pull-down sub-module.

2. The shift register according to claim 1, wherein The first pull-up sub-module includes a first transistor, a first end of the first transistor is the first end of the first pull-up sub-module, a second end of the first transistor is the second end of the first pull-up sub-module, and a control end of the first transistor is the control end of the first pull-up sub-module; The first pull-down sub-module includes a second transistor, a first end of the second transistor is the first end of the first pull-down sub-module, a second end of the second transistor is the second end of the first pull-down sub-module, and a control end of the second transistor is the control end of the first pull-down sub-module; A conduction control signal of the first transistor is opposite to a conduction control signal of the second transistor.

3. The shift register according to claim 1, characterized in that, It further includes a third transistor; A first end of the third transistor is electrically connected to the first node, a second end of the third transistor is electrically connected to the trigger write module, and a control end of the third transistor is connected to the first power supply signal; or, A first end of the third transistor is electrically connected to the first output adjustment module, a second end of the third transistor is electrically connected to the first node, and a control end of the third transistor is connected to the first power supply signal.

4. The shift register according to claim 1 or 3, characterized in that, It further includes: A first feedback sub-module for writing the first clock signal to the second node according to the trigger signal at the first node; A second feedback sub-module for writing a second power supply signal to the first node according to the first power supply signal at the second node and a second clock signal.

5. The shift register according to claim 1 or 3, characterized in that, The first output adjustment module includes: A second pull-up sub-module, a first end of the second pull-up sub-module is connected to a second power supply signal, a second end of the second pull-up sub-module is electrically connected to the first output end, and a control end of the second pull-up sub-module is electrically connected to the second node; A second pull-down sub-module, a first end of the second pull-down sub-module is connected to a second clock signal, a second end of the second pull-down sub-module is electrically connected to the first output end, and a control end of the second pull-down sub-module is electrically connected to the first node.

6. The shift register according to claim 1 or 3, characterized in that, The first output adjustment module further includes a first capacitor and a second capacitor; A first end of the first capacitor is connected to the second power supply signal, and a second end of the first capacitor is electrically connected to the second node; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first output end.

7. A display driver, characterized in that, The display driver includes a plurality of cascaded shift registers as described in any one of claims 1-6; Wherein, the trigger signal of the nth stage shift register is provided by the output signal of the first output end of the (n-1)th stage shift register, and n is an integer greater than or equal to 2.

8. A display panel, characterized in that, The display panel includes the display driver as described in claim 7 and a plurality of pixel circuits; The first output end and the second output end of the shift register are used to provide scan signals to corresponding pixel circuits.

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