Testing method for three-dimensional stacked memory chip and three-dimensional stacked memory chip

Abstract

The present application provides a testing method for a three-dimensional stacked memory chip and a three-dimensional stacked memory chip. The memory chip includes at least two stacked interconnected dies, and the testing method includes: controlling one of the at least two dies to obtain desired data; obtaining test data through the read / write data lines of another of the at least two dies, comparing the test data with the desired data to generate a corresponding comparison result, and thereby determining the connectivity between the at least two dies based on the comparison result; wherein the read / write data lines of the at least two stacked interconnected dies are connected to each other through a stacked interconnect structure between the at least two dies. This testing method can locate failures in three-dimensional stacked products caused by the interconnection process and provide accurate information on interconnection lines with interconnection problems, thereby indirectly or directly resolving the problem of low product yield of three-dimensional stacked memory chips caused by interconnection process problems.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a testing method for a three-dimensional stacked memory chip and the three-dimensional stacked memory chip. Background Art

[0002] Typically, memory chips are stacked in three dimensions, with tens of thousands of interconnect lines between different wafers using through-silicon vias (TSVs) or hybrid bonding integration processes. During wafer testing, when a chip on the wafer experiences a functional failure, existing technologies are unable to determine whether the failure is due to the 3D stacking interconnection process, nor can they accurately locate the failed interconnect line. Summary of the Invention

[0003] The present application provides a testing method for a three-dimensional stacked memory chip and a three-dimensional stacked memory chip, which can locate failures of three-dimensional stacked products caused by interconnection processes, and provide accurate information on interconnection lines with interconnection problems, thereby indirectly or directly solving the problem of low product yield of three-dimensional stacked memory chips caused by interconnection process problems.

[0004] To address the aforementioned technical issues, this application employs a technical solution: providing a method for testing a three-dimensional stacked memory chip. The memory chip comprises at least two stacked, interconnected dies. The testing method comprises: controlling one of the at least two dies to obtain desired data; obtaining test data via a read / write data line of another of the at least two dies; comparing the test data with the desired data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result; wherein the read / write data lines of the at least two stacked, interconnected dies are connected to each other via a stacked interconnect structure between the at least two dies.

[0005] Among them, at least two stacked interconnected grains include a first storage grain and a second storage grain, wherein the first storage grain and the second storage grain respectively include a control module, a read-write data line and a storage array; the first storage grain includes a first interface for communicating with the outside world, and the read-write data lines of the first storage grain and the second storage grain are connected to each other through a stacked interconnection structure between the two storage grains, the control module of the first storage grain is connected to the first interface, the control module of the second storage grain is connected to the control module of the first storage grain through the stacked interconnection structure between the two storage grains and is connected to the first interface through the control module of the first storage grain, or the control module of the second storage grain is connected to the first interface of the first storage grain through the stacked interconnection structure between the two storage grains; and the stacked interconnection structure between the two storage grains includes a stacked interconnection hole or a combination of other grains and stacked interconnection holes located between the two storage grains.

[0006] The step of controlling one of at least two crystal grains to obtain desired data includes:

[0007] The control module of the first memory chip receives a test input instruction through the first interface;

[0008] The control module of the second memory die obtains a test input instruction from the first interface through the stacked interconnect structure between the two memory die and the control module of the first memory die, or the stacked interconnect structure between the two memory die, and writes expected data to the read and write data lines of the second memory die based on the test input instruction;

[0009] Obtaining test data through a read / write data line of another one of the at least two dies, comparing the test data with expected data to generate a corresponding comparison result, and determining connectivity between the at least two dies based on the comparison result, including:

[0010] The read / write data line of the first memory chip obtains the data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips to obtain test data;

[0011] The first memory die compares the test data with the expected data to generate a corresponding comparison result, and the control module of the first memory die outputs the comparison result through the first interface, so that the test system determines the connectivity between at least two dies based on the comparison result.

[0012] The step of controlling one of at least two crystal grains to obtain desired data includes:

[0013] The control module of the first memory chip receives a test input instruction through the first interface;

[0014] The control module of the first memory chip writes the expected data to the read and write data lines of the first memory chip based on the test input instruction;

[0015] Obtaining test data through a read / write data line of another one of the at least two dies, comparing the test data with expected data to generate a corresponding comparison result, and determining connectivity between the at least two dies based on the comparison result, including:

[0016] The read / write data line of the second memory die acquires the data on the read / write data line of the first memory die through the stacked interconnect structure between the two memory die to obtain test data;

[0017] The second storage die compares the test data and the expected data to generate a corresponding comparison result, and the control module of the second storage die outputs the comparison result from the first interface through the stacked interconnection structure between the two storage die and the control module of the first storage die, or the stacked interconnection structure between the two storage die, so that the test system determines the connectivity between at least two die based on the comparison result.

[0018] The step of controlling one of at least two crystal grains to obtain desired data includes:

[0019] The control module of the first memory chip receives a test input instruction through the first interface;

[0020] The control module of the second memory die obtains a test input instruction from the first interface through the stacked interconnect structure between the two memory die and the control module of the first memory die, or the stacked interconnect structure between the two memory die, and writes expected data to the memory array of the second memory die based on the test input instruction;

[0021] Obtaining test data through a read / write data line of another one of the at least two dies, comparing the test data with expected data to generate a corresponding comparison result, and determining connectivity between the at least two dies based on the comparison result, including:

[0022] Controlling the read and write data lines of the second memory chip to read desired data from the memory array of the second memory chip;

[0023] The read / write data line of the first memory chip obtains the data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips to obtain test data;

[0024] The first memory die compares the test data with the expected data to generate a corresponding comparison result, and the control module of the first memory die outputs the comparison result through the first interface, so that the test system determines the connectivity between at least two dies based on the comparison result.

[0025] The step of controlling one of at least two crystal grains to obtain desired data includes:

[0026] The control module of the first memory chip receives a test input instruction through the first interface;

[0027] The control module of the first memory die writes the expected data into the memory array of the first memory die based on the test input instruction;

[0028] Obtaining test data through a read / write data line of another one of the at least two dies, comparing the test data with expected data to generate a corresponding comparison result, and determining connectivity between the at least two dies based on the comparison result, including:

[0029] Controlling the read and write data lines of the first memory chip to read desired data from the memory array of the first memory chip;

[0030] The read / write data line of the second memory die acquires the data on the read / write data line of the first memory die through the stacked interconnect structure between the two memory die to obtain test data;

[0031] The second storage die compares the test data and the expected data to generate a corresponding comparison result, and the control module of the second storage die outputs the comparison result from the first interface through the stacked interconnection structure between the two storage die and the control module of the first storage die, or the stacked interconnection structure between the two storage die, so that the test system determines the connectivity between at least two die based on the comparison result.

[0032] The step of controlling one of at least two crystal grains to obtain desired data includes:

[0033] The control module of the first memory chip receives a test input instruction through the first interface;

[0034] The control module of the first memory chip writes the expected data to the read and write data lines of the first memory chip based on the test input instruction;

[0035] Obtaining test data through a read / write data line of another one of the at least two dies to compare the test data with expected data to generate a corresponding comparison result, thereby determining connectivity between the at least two dies based on the comparison result, including:

[0036] The read / write data line of the second memory die obtains the data on the read / write data line of the first memory die through the stacked interconnect structure between the two memory die;

[0037] Writing the data on the read / write data line of the second storage die into the storage array of the second storage die to obtain test data;

[0038] The second storage chip reads the test data stored in its storage array, compares the test data with the expected data to generate a corresponding comparison result, and the control module of the second storage chip outputs the comparison result from the first interface through the stacked interconnection structure between the two storage chips and the control module of the first storage chip, or the stacked interconnection structure between the two storage chips.

[0039] The method of controlling one of the at least two memory chips to obtain expected data includes: a control module of the second memory chip obtaining a test input instruction from a first interface through a stacked interconnect structure between the two memory chips and a control module of the first memory chip, or a stacked interconnect structure between the two memory chips, and writing the expected data to a read / write data line of the second memory chip based on the test input instruction;

[0040] Obtaining test data through a read / write data line of another one of the at least two dies, comparing the test data with expected data to generate a corresponding comparison result, and determining connectivity between the at least two dies based on the comparison result, including:

[0041] The read / write data line of the first memory chip obtains the data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips;

[0042] Writing data on the read / write data line of the first storage die into the storage array of the first storage die to obtain test data;

[0043] The first storage die reads test data stored in its storage array, compares the test data with expected data to generate a corresponding comparison result, and a control module of the first storage die outputs the comparison result through a first interface, so that the test system determines the connectivity between at least two die based on the comparison result.

[0044] The at least two stacked interconnected dies include a logic die and at least one memory die, the logic die includes a control module, a read / write data line, and a data comparison module or a read / write data output module, and each memory die includes a control module, a read / write data line, and a memory array, wherein the read / write data lines in each memory die are connected to each other through a stacked interconnection structure between the two dies and are respectively connected to the read / write data lines in the logic die, the control modules in each memory die are respectively connected to each other and to the control module in the logic die through the stacked interconnection structure between the two dies, or the control modules in each memory die are respectively connected to the control module in the logic die through the stacked interconnection structure between the two dies, and the stacked interconnection structure between the two dies includes a stacked interconnection hole or a combination of other dies and stacked interconnection holes located between the two dies; the logic die includes a first interface and a second interface for communicating with the outside world, wherein the first interface is connected to the control module of the logic die, and the second interface is connected to the data comparison module or the read / write data line output module of the logic die;

[0045] Controlling one of at least two dies to obtain desired data includes:

[0046] The control module of the logic chip receives the test input instruction through the first interface;

[0047] Based on the test input instruction, controlling at least one of the at least one storage die to obtain expected data;

[0048] Obtaining test data through a read / write data line of another one of the at least two dies, comparing the test data with expected data to generate a corresponding comparison result, and determining connectivity between the at least two dies based on the comparison result, including:

[0049] The desired data is transmitted to the read and write data lines of the logic die through the stacked interconnect structure between the logic die and the storage die for obtaining the desired data, so as to obtain test data;

[0050] The test data and the expected data are compared by a data comparison module of the logic grain to generate a corresponding comparison result, and the comparison result is output through the second interface; or the test data is output through the second interface by a read / write data line output module of the logic grain, so that the test system compares the test data and the expected data to generate a corresponding comparison result, thereby determining the connectivity between at least two grains based on the comparison result.

[0051] Wherein, when determining that the connectivity between the at least two grains is abnormal, the testing method further includes:

[0052] Detecting whether the read / write data lines of the at least two dies with abnormal connectivity are failed;

[0053] In response to the read and write data lines of the at least two dies being normal, determining that the abnormal connectivity between the at least two dies is caused by a stacked interconnection structure between the at least two dies;

[0054] In response to the read / write data lines of the at least two dies being abnormal, the abnormal read / write data lines are repaired, and the step of controlling one of the at least two dies to obtain expected data is returned to be re-executed.

[0055] To solve the above technical problems, another technical solution adopted in the present application is: to provide a three-dimensional stacked memory chip, which includes at least two stacked and interconnected grains, wherein the three-dimensional stacked memory chip executes the above-mentioned test method.

[0056] The present application provides a testing method for a three-dimensional stacked memory chip and a three-dimensional stacked memory chip. The testing method obtains desired data by controlling one of at least two crystals; then obtains test data through the read / write data line of the other of the at least two crystals, compares the test data with the desired data to generate a corresponding comparison result, and thereby determines the connectivity between the at least two crystals based on the comparison result. This testing method can not only detect connectivity failures between any crystals to ensure the product yield of three-dimensional stacked memory chips entering the market, but also quickly and accurately locate the failed locations of interconnect lines on the three-dimensional stacked memory chip through analysis and comparison of the test data with the desired data, thereby providing accurate information on interconnect lines with interconnection problems, and then providing location information for the next repair plan, thereby indirectly or directly resolving the low product yield problem of three-dimensional stacked memory chips caused by interconnection problems, thereby reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A flowchart of a method for testing a three-dimensional stacked memory chip provided in one embodiment of the present application;

[0058] Figure 2aA flowchart of a method for testing a three-dimensional stacked memory chip provided in the first embodiment of the present application;

[0059] Figure 2b Provided for an embodiment of this application Figure 2a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0060] Figure 2c Another embodiment of the present application provides Figure 2a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0061] Figure 3a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a second embodiment of the present application;

[0062] Figure 3b Provided for an embodiment of this application Figure 3a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0063] Figure 3c Another embodiment of the present application provides Figure 3a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0064] Figure 4a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a third embodiment of the present application;

[0065] Figure 4b Provided for an embodiment of this application Figure 4a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0066] Figure 4c Another embodiment of the present application provides Figure 4a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0067] Figure 5a This is a flow chart of a method for testing a three-dimensional stacked memory chip provided in a fourth embodiment of the present application;

[0068] Figure 5b Provided for an embodiment of this application Figure 5a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0069] Figure 5c Another embodiment of the present application provides Figure 5a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0070] Figure 6a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a fifth embodiment of the present application;

[0071] Figure 6b Provided for an embodiment of this application Figure 6a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0072] Figure 6c Another embodiment of the present application provides Figure 6a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0073] Figure 7a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a sixth embodiment of the present application;

[0074] Figure 7b Provided for an embodiment of this application Figure 7a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0075] Figure 7c Another embodiment of the present application provides Figure 7a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0076] Figure 8a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a seventh embodiment of the present application;

[0077] Figure 8b Provided for an embodiment of this application Figure 8a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0078] Figure 8c Another embodiment of the present application provides Figure 8a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0079] Figure 8d Another embodiment of the present application provides Figure 8a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip;

[0080] Figure 9 A flowchart of a method for testing a three-dimensional stacked memory chip provided in another embodiment of the present application;

[0081] Figure 10 A simplified structural diagram of a three-dimensional stacked memory chip provided in one embodiment of the present application. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0083] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0084] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0085] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0086] See also Figure 1 , Figure 1A flow chart of a test method for a three-dimensional stacked memory chip provided in one embodiment of the present application; in this embodiment, a test method for a three-dimensional stacked memory chip is provided. Wherein, a three-dimensional stacked memory chip executes the test method. The three-dimensional stacked memory chip includes at least two stacked interconnected grains, and the read and write data lines of the at least two stacked interconnected grains are connected to each other through a stacked interconnection structure between at least two grains. Wherein, the stacked interconnection structure between the two storage grains includes a stacked interconnection hole or a combination of other grains and stacked interconnection holes located between the two storage grains. Specifically, the stacked interconnection hole can be a through-silicon via. The grains can also be replaced by wafers. The interconnection line between any two grains is defined below as a stacked interconnection structure of the read and write data lines of the two grains and the read and write data lines connecting the two grains.

[0087] Specifically, the test method includes:

[0088] Step S1: controlling one of at least two dies to obtain desired data.

[0089] That is, one of the at least two dies is controlled to obtain desired data, which may be a logic 0 / 1 level.

[0090] Step S2: obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with expected data to generate corresponding comparison results, and determining connectivity between the at least two dies based on the comparison results.

[0091] That is, test data is obtained from any one of the at least two dies except the one that obtained the expected data. If the test data is consistent with the expected data, the connectivity between the at least two dies is good; if the test data is inconsistent with the expected data, the connectivity between the at least two dies is abnormal.

[0092] The testing method for 3D stacked memory chips provided in this embodiment can not only detect connectivity failures between any die, thereby ensuring the product yield of 3D stacked memory chips entering the market, but also, by analyzing test data and expected data, promptly identify which interconnect circuit among multiple interconnects in the 3D stacked memory chip has a problem. This allows for the rapid and precise location of the interconnect failure on the 3D stacked memory chip, providing precise information about the interconnect failure, and subsequently providing location information for subsequent repair solutions. This indirectly or directly addresses the low product yield of 3D stacked memory chips caused by interconnect process problems, effectively improving product yield and reducing costs. It is understandable that during the testing process, if the expected data obtained by one die is 00000 and the test data obtained by another die is 00010, the interconnect corresponding to "1" can be accurately located as the failed circuit, thereby achieving rapid and precise location of the interconnect failure on the 3D stacked memory chip.

[0093] For details, please refer to Figures 2a to 2c ,in, Figure 2a A flowchart of a method for testing a three-dimensional stacked memory chip provided in the first embodiment of the present application; Figure 2b Provided for an embodiment of this application Figure 2a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 2c Another embodiment of the present application provides Figure 2a The data flow diagram of the corresponding three-dimensional stacked memory chip; the at least two stacked interconnected dies may include a first memory die (wafer1) and a second memory die (wafer2) arranged in a stacked manner. The first memory die includes a control module 1a, a read / write data line 3a, and a first interface 4 for communicating with the outside world; the second memory die includes a control module 1b and a read / write data line 3b. Figure 2b As shown, the read / write data line 3a of the first memory die and the read / write data line 3b of the second memory die are connected to each other through the stacked interconnection structure between the two memory die; the control module 1a of the first memory die is connected to the first interface 4, and the control module 1b of the second memory die is connected to the control module 1a of the first memory die through the stacked interconnection structure between the two memory die and is connected to the first interface 4 through the control module 1a of the first memory die. Or as Figure 2c As shown, the control module 1b of the second memory die is directly connected to the first interface 4 of the first memory die through the stacked interconnection structure between the two memory die. The first to sixth embodiments below all take this as an example.

[0094] In the first embodiment, as Figures 2a to 2c As shown, the testing method of the three-dimensional stacked memory chip specifically includes:

[0095] Step S11: The control module of the second storage grain obtains a test input instruction from the first interface through the stacked interconnection structure between the two storage grains and the control module of the first storage grain, or the stacked interconnection structure between the two storage grains, and writes the expected data to the read and write data lines of the second storage grain based on the test input instruction.

[0096] Step 12: The read / write data line of the first memory chip obtains data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips to obtain test data.

[0097] It can be understood that if the connectivity of the stacked interconnect structure between the first storage grain and the second storage grain is good, the test data obtained by the first storage grain is consistent with the expected data; if the connectivity of the stacked interconnect structure between the first storage grain and the second storage grain is abnormal, the test data obtained by the first storage grain is different from the expected data.

[0098] Step 13: The first memory die compares the test data and the expected data to generate a corresponding comparison result, and the control module of the first memory die outputs the comparison result through the first interface, so that the test system determines the connectivity between at least two dies based on the comparison result.

[0099] In this specific embodiment, the first storage die also includes a data comparison module 2a, which stores expected data. During implementation, the first storage die further writes test data on its read / write data line 3a into the data comparison module 2a, allowing the data comparison module 2a to compare the test data with the expected data. Specifically, if the test data matches the expected data, the connectivity between the first storage die and the second storage die is good; if the test data does not match the expected data, the connectivity between the first storage die and the second storage die is abnormal.

[0100] Of course, in a specific embodiment, the second storage die also includes a data comparison module 2b, which stores the expected data. The first storage die can also further write the test data on its read / write data line 3a into the data comparison module 2b of the second storage die via the stacked interconnect structure between the two storage die, so that the test data and the expected data can be compared via the data comparison module 2b.

[0101] In the second embodiment, see Figures 3a to 3c ,in, Figure 3a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a second embodiment of the present application; Figure 3b Provided for an embodiment of this application Figure 3a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 3cAnother embodiment of the present application provides Figure 3a The data trend diagram of the corresponding three-dimensional stacked memory chip. The testing method of the three-dimensional stacked memory chip specifically includes:

[0102] Step S21: The control module of the first memory chip receives a test input instruction through the first interface.

[0103] Step S22 : The control module of the first memory chip writes the expected data into the read / write data lines of the first memory chip based on the test input instruction.

[0104] Step S23: the read / write data line of the second memory chip acquires the data on the read / write data line of the first memory chip through the stacked interconnect structure between the two memory chips to obtain test data.

[0105] As shown in step S12, if the connectivity of the stacked interconnect structure between the first storage grain and the second storage grain is good, the test data obtained by the second storage grain is consistent with the expected data; if the connectivity of the stacked interconnect structure between the first storage grain and the second storage grain is abnormal, the test data obtained by the second storage grain is different from the expected data.

[0106] Step S24: The second storage die compares the test data and the expected data to generate a corresponding comparison result, and the control module of the second storage die outputs the comparison result from the first interface through the stacked interconnection structure between the two storage die and the control module of the first storage die, or the stacked interconnection structure between the two storage die, so that the test system determines the connectivity between at least two die based on the comparison result.

[0107] In this specific embodiment, the second storage die also includes a data comparison module 2b, which stores expected data. During implementation, the second storage die further writes test data on its read / write data line 3b into the data comparison module 2b, allowing the data comparison module 2b to compare the test data with the expected data. Specifically, if the test data matches the expected data, the connectivity between the first and second storage die is good; if the test data does not match the expected data, the connectivity between the first and second storage die is abnormal.

[0108] In the third embodiment, see Figures 4a to 4c ,in, Figure 4a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a third embodiment of the present application; Figure 4b Provided for an embodiment of this application Figure 4a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 4c Another embodiment of the present application provides Figure 4aThe data trend diagram of the corresponding three-dimensional stacked memory chip. The testing method of the three-dimensional stacked memory chip specifically includes:

[0109] Step S31: The control module of the second storage grain obtains a test input instruction from the first interface through the stacked interconnection structure between the two storage grains and the control module of the first storage grain, or the stacked interconnection structure between the two storage grains, and writes the expected data to the storage array of the second storage grain based on the test input instruction.

[0110] In this embodiment, if Figure 4b As shown, the second storage die further includes a storage array 5b, and the storage array 5b is respectively connected to the control module 1b and the read and write data lines 3b.

[0111] Step S32: controlling the read and write data lines of the second memory chip to read desired data from the memory array of the second memory chip.

[0112] Step S33: the read / write data line of the first memory chip acquires the data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips to obtain test data.

[0113] Among them, if the connectivity of the stacked interconnection structure between the first storage grain and the second storage grain is good, the test data obtained by the first storage grain is consistent with the expected data; if the connectivity of the stacked interconnection structure between the first storage grain and the second storage grain is abnormal, the test data obtained by the first storage grain is different from the expected data.

[0114] Step S34: the first memory die compares the test data and the expected data to generate a corresponding comparison result, and the control module of the first memory die outputs the comparison result through the first interface, so that the test system determines the connectivity between at least two dies based on the comparison result.

[0115] Step S34 is similar to step S14 in the first embodiment, and details can be found above.

[0116] In the fourth embodiment, see Figures 5a to 5c ,in, Figure 5a This is a flow chart of a method for testing a three-dimensional stacked memory chip provided in a fourth embodiment of the present application; Figure 5b Provided for an embodiment of this application Figure 5a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 5c Another embodiment of the present application provides Figure 5a The data trend diagram of the corresponding three-dimensional stacked memory chip. The testing method of the three-dimensional stacked memory chip specifically includes:

[0117] Step S41: The control module of the first memory chip receives a test input instruction through the first interface.

[0118] Step S42 : The control module of the first memory chip writes the expected data into the memory array of the first memory chip based on the test input command.

[0119] In this embodiment, Figure 5b As shown, the first memory chip further includes a memory array 5a, and the memory array 5a is respectively connected to the control module 1a and the read and write data lines 3a.

[0120] Step S43: controlling the read and write data lines of the first memory chip to read desired data from the memory array of the first memory chip.

[0121] Step S44: the read / write data line of the second memory chip acquires the data on the read / write data line of the first memory chip through the stacked interconnect structure between the two memory chips to obtain test data.

[0122] Step S45: The second storage grain compares the test data and the expected data to generate a corresponding comparison result, and the control module of the second storage grain outputs the comparison result from the first interface through the stacked interconnection structure between the two storage grains and the control module of the first storage grain, or the stacked interconnection structure between the two storage grains, so that the test system determines the connectivity between at least two grains based on the comparison result.

[0123] Among them, step S44 and step S45 are similar to step S23 and step S24 in the second embodiment, and the details can be found above.

[0124] In the fifth embodiment, see Figures 6a to 6c ,in, Figure 6a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a fifth embodiment of the present application; Figure 6b Provided for an embodiment of this application Figure 6a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 6c Another embodiment of the present application provides Figure 6a The data trend diagram of the corresponding three-dimensional stacked memory chip. The testing method of the three-dimensional stacked memory chip specifically includes:

[0125] Step S51: a control module of a first memory chip receives a test input instruction through a first interface.

[0126] Step S52 : The control module of the first memory chip writes the expected data into the read / write data lines of the first memory chip based on the test input instruction.

[0127] Step S53: the read / write data line of the second memory chip obtains the data on the read / write data line of the first memory chip through the stacked interconnect structure between the two memory chips.

[0128] Step S54: writing the data on the read / write data lines of the second memory chip into the memory array of the second memory chip to obtain test data.

[0129] Step S55: The second storage chip reads the test data stored in its storage array, compares the test data with the expected data to generate a corresponding comparison result, and the control module of the second storage chip outputs the comparison result from the first interface through the stacked interconnection structure between the two storage chips and the control module of the first storage chip, or the stacked interconnection structure between the two storage chips.

[0130] In this specific embodiment, the second storage die also includes a data comparison module 2b, which stores expected data. During implementation, the data comparison module 2b reads test data from the second storage die's storage array 5b and compares the test data with the expected data. Specifically, if the test data matches the expected data, the connectivity between the first and second storage die is good. If the test data does not match the expected data, the connectivity between the first and second storage die is abnormal.

[0131] In the sixth embodiment, see Figures 7a to 7c ,in, Figure 7a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a sixth embodiment of the present application; Figure 7b Provided for an embodiment of this application Figure 7a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 7c Another embodiment of the present application provides Figure 7a The data trend diagram of the corresponding three-dimensional stacked memory chip. The testing method of the three-dimensional stacked memory chip specifically includes:

[0132] Step S61: The control module of the second storage grain obtains a test input instruction from the first interface through the stacked interconnection structure between the two storage grains and the control module of the first storage grain, or the stacked interconnection structure between the two storage grains, and writes the expected data to the read and write data lines of the second storage grain based on the test input instruction.

[0133] Step S62: the read / write data line of the first memory chip obtains data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips.

[0134] Step S63: writing the data on the read / write data line of the first memory chip into the memory array of the first memory chip to obtain test data.

[0135] Among them, if the connectivity of the stacked interconnection structure between the first storage grain and the second storage grain is good, the test data stored in the storage array 5a is consistent with the expected data; if the connectivity of the stacked interconnection structure between the first storage grain and the second storage grain is abnormal, the test data stored in the storage array 5a is different from the expected data.

[0136] Step S64: The first storage chip reads the test data stored in its storage array, compares the test data with the expected data to generate a corresponding comparison result, and the control module of the first storage chip outputs the comparison result through the first interface, so that the test system determines the connectivity between at least two chips based on the comparison result.

[0137] In this specific embodiment, the first storage die also includes a data comparison module 2a, which stores expected data. During implementation, the data comparison module 2a reads test data from the storage array 5a of the first storage die and compares the test data with the expected data. Specifically, if the test data matches the expected data, the connectivity between the first storage die and the second storage die is good; if the test data does not match the expected data, the connectivity between the first storage die and the second storage die is abnormal.

[0138] In the seventh embodiment, see Figures 8a to 8d ,in, Figure 8a A flowchart of a method for testing a three-dimensional stacked memory chip provided in a seventh embodiment of the present application; Figure 8b Provided for an embodiment of this application Figure 8a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 8c Another embodiment of the present application provides Figure 8a A diagram showing the data flow in the corresponding three-dimensional stacked memory chip; Figure 8d Another embodiment of the present application provides Figure 8a The data flow diagram of the corresponding three-dimensional stacked memory chip. The at least two stacked interconnected dies include a logic die (logical wafer) and at least one memory die (wafer1-waferN); Figure 8b , the logic chip includes a control module 1c, a data comparison module 2c and a read / write data line 3c, or, as Figure 8dThe logic die includes a control module 1c, a read / write data output module 2c', and a read / write data line 3c. Each memory die includes a control module, a read / write data line, and a memory array, wherein the read / write data lines in each memory die are connected to each other via a stacked interconnect structure between the two die and are respectively connected to the read / write data lines 3c in the logic die. The control modules in each memory die are respectively connected to each other and to the control module 1c in the logic die via a stacked interconnect structure between at least two die; that is, the control modules in each memory die are respectively connected to the control module 1c in the logic die via the stacked interconnect structure between the two die and the control modules of the memory die connected thereto in sequence; or the control modules in each memory die are respectively directly connected to the control module 1c in the logic die via a stacked interconnect structure between at least two die. The stacked interconnect structure between the two die includes a stacked interconnect hole or a combination of other die and stacked interconnect holes located between the two die. The logic chip further includes a first interface 4c and a second interface 5c for communicating with the outside world. The first interface 4c is connected to the control module 1c of the logic chip, and the second interface 5c is connected to the data comparison module 2c of the logic chip or the read / write data output module 2c' of the logic chip.

[0139] In at least one memory die, the read and write data lines of two adjacent memory dies are connected to each other via a stacked interconnect structure between the two memory dies. The memory die adjacent to the logic die is defined below as the first memory die (wafer 1); the remaining memory die is defined below as the Nth memory die (wafer N), where N is a natural number greater than or equal to 2.

[0140] In this embodiment, the testing method of the three-dimensional stacked memory chip specifically includes:

[0141] Step S71 : The control module of the logic chip receives a test input instruction through the first interface.

[0142] Step S72: Based on the test input instruction, control at least one of the at least one storage die to obtain expected data.

[0143] Among them, at least one of the at least one storage grain refers to at least one storage grain in the at least one storage grain. In the specific implementation process, similar to the first embodiment above, step S72 specifically includes: Figure 8b As shown, the control module of at least one of the at least one storage die obtains the test input instruction from the control module 1c of the logic die through the control modules between the control module and each storage die between the logic die and the stacked interconnection structure between at least two die; or as shown in FIG. Figure 8cAs shown, the control module of at least one of the at least one storage die receives a test input instruction from the control module 1c of the logic die via a stacked interconnect structure between at least two die, and based on the test input instruction, writes desired data to the read / write data lines of at least one of the at least one storage die. The stacked interconnect structure between at least two die refers to all die between the storage die and the logic die to which the desired data is written.

[0144] Taking the second memory chip as an example, step 72 specifically includes: Figure 8b As shown, the control module 1b of the second memory die obtains the test input instruction from the control module 1c of the logic die through the stacked interconnection structure between the second memory die and the first memory die, the control module 1a of the first memory die, and the stacked interconnection structure between the first memory die and the logic die, or, as shown in FIG. Figure 8c As shown, the control module 1b of the second storage grain obtains the test input instruction from the control module 1c of the logic grain through the stacked interconnection structure between the second storage grain and the first storage grain and the stacked interconnection structure between the first storage grain and the logic grain, and writes the expected data to the read and write data line 3b of the second storage grain based on the test input instruction.

[0145] Of course, in other implementations, similar to the third embodiment described above, after the control module of at least one of the at least one storage die receives a test input instruction from the control module 1c of the logic die, it may also write the desired data into the storage array of at least one of the at least one storage die based on the test input instruction; and then control the read / write data lines of at least one of the at least one storage die to read the desired data from the storage array. Continuing with the second storage die as an example, after the control module of at least one of the at least one storage die receives a test input instruction from the control module 1c of the logic die, it may then write the desired data into the storage array 5b of the second storage die based on the test input instruction; and then control the read / write data lines 3b of the second storage die to read the desired data from the storage array 5b of the second storage die.

[0146] During a specific implementation, one of the at least one storage grains can be controlled to obtain desired data, so that, through steps S73 and S74, it can be promptly determined whether there is a connectivity problem between the storage grains in that layer and the logic grains. Of course, in other specific implementations, since the control modules in multiple storage grains are connected to the control module 1c in the logic grain via a stacked interconnect structure, step S72 can also control multiple storage grains in the at least one storage grain to simultaneously obtain desired data based on the test input instruction, so that, through steps S73 and S74, it can simultaneously determine whether there is a connectivity problem between multiple layers of storage grains and the logic grains. This not only accurately locates the failure location of the interconnection line between any grains, but also effectively improves test efficiency.

[0147] Step S73: transmitting the acquired desired data to the read and write data lines of the logic die through the stacked interconnection structure between the logic die and the storage die from which the desired data is acquired, so as to obtain test data.

[0148] Specifically, the logic die's read / write data line 3c acquires data from the desired data storage die's read / write data lines (3a / 3n) via the stacked interconnect structure between the logic die and the storage die, thereby obtaining test data. By analyzing the test data and the desired data, it is determined whether there are any issues with the stacked interconnect structure between the storage die and the logic die, thereby reducing the defective rate of the three-dimensional stacked memory chip. Furthermore, the failure location of any read / write data line between the storage die can be quickly and accurately located, providing precise information on interconnect lines with interconnection problems. This provides location information for subsequent repair solutions, effectively improving product yield and reducing costs.

[0149] It is understood that when the first memory die acquires desired data, the stacked interconnect structure between the memory die that acquires the desired data and the logic die is the stacked interconnect structure between the first memory die and the logic die. When testing the connectivity between the Nth memory die and the logic die, the stacked interconnect structure between the memory die that acquires the desired data and the logic die includes the stacked interconnect structure between the first memory die and the logic die and the stacked interconnect structure between the Nth memory die and the (N-1)th memory die.

[0150] Step S74: Compare the test data and the expected data through the data comparison module of the logic grain to generate a corresponding comparison result, and output the comparison result through the second interface; or output the test data through the read and write data line output module of the logic grain through the second interface, so that the test system compares the test data and the expected data to generate a corresponding comparison result, thereby determining the connectivity between at least two grains based on the comparison result.

[0151] Specifically, the data comparison module 2c of the logic die stores expected data. During implementation, the read / write data line 3c of the logic die further writes test data into the data comparison module 2c of the logic die, allowing the data comparison module 2c of the logic die to compare the test data with the expected data. The comparison result is then output via the second interface 5c of the logic die. Specifically, if the test data is consistent with the expected data, the connectivity of the stacked interconnect structure between the logic die and the storage die that received the expected data is good. If the test data is inconsistent with the expected data, the connectivity of the stacked interconnect structure between the logic die and the storage die that received the expected data is abnormal.

[0152] The testing method for three-dimensional stacked memory chips provided in this embodiment can not only simultaneously test the connectivity of the stacked interconnect structure between multi-layer memory grains and logic grains, with good testing efficiency; but also can quickly and accurately locate the failure position of the read and write data lines on the three-dimensional stacked memory chip through analysis and comparison of test data with expected data, thereby providing accurate information on interconnection lines with interconnection problems, and then providing location information for the next repair plan, thereby further improving the product yield and reducing costs.

[0153] In one embodiment, see Figure 9 , Figure 9 This is a flow chart of a method for testing a three-dimensional stacked memory chip provided in another embodiment of the present application. The method differs from the method for testing a three-dimensional stacked memory chip provided in any of the above embodiments in that, upon confirming that connectivity between any two of the at least two dies is abnormal, the method further includes:

[0154] Step S3: Detect whether the read / write data lines of at least two dies with abnormal connectivity are failed.

[0155] Specifically, the dies that can obtain expected data and test data are enabled to confirm whether the read / write data lines on these two dies are invalid. The specific detection method for confirming whether the read / write data lines are invalid can refer to the existing method for detecting whether the read / write data lines are invalid, which will not be repeated here.

[0156] Specifically, in response to the read / write data lines of at least two dies being normal, step S4 is executed; in response to the read / write data lines of at least two dies being abnormal, step S5 is executed.

[0157] Step S4: determining that the abnormal connectivity between at least two dies is caused by a stacked interconnection structure between the at least two dies.

[0158] Step S5: repair the abnormal read / write data line; and return to re-execute the step of controlling at least one of the two dies to obtain the expected data.

[0159] Specifically, if the read / write data lines on one or both of the two grains fail, the failed read / write data lines are repaired. For specific repair methods, refer to the existing read / write data line repair methods. Afterwards, return to and re-execute the above steps S1 and S2. If the test data is still inconsistent with the expected data, it is determined that there is a problem with the stacked interconnect structure connecting the two grains, and the abnormal connectivity between at least the two grains is caused by the stacked interconnect structure connecting the two grains. Of course, if the test data is consistent with the expected data, it is confirmed that the abnormal connectivity between the two grains is caused by the failure of the corresponding read / write data lines, and the stacked interconnect structure between the two is normal.

[0160] The test method for three-dimensional stacked memory chips provided in this embodiment, when determining that the connectivity between any two grains is abnormal, further detects whether the read / write data lines of the two grains with abnormal connectivity are abnormal, so that when the read / write data lines of at least two grains are normal, it is determined that the connectivity abnormality between the at least two grains is caused by the stacked interconnection structure between the at least two grains; and if the read / write data lines on one or two of the two grains fail, the failed read / write data lines are repaired and test data is re-acquired to further compare the test data with the expected data, and then determine whether there is a problem with the stacked interconnection structure connecting the two grains based on the comparison results, and then analyze and locate whether the current connectivity is caused by the stacked interconnection structure of the three-dimensional stacking process.

[0161] See also Figure 10 , Figure 10 A simplified structural diagram of a three-dimensional stacked memory chip provided in one embodiment of the present application. In this embodiment, a three-dimensional stacked memory chip is also provided, comprising at least two stacked and interconnected dies 10, wherein the three-dimensional stacked memory chip performs the test method involved in any of the above embodiments.

[0162] The above is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for testing a three-dimensional stacked memory chip, characterized in that: The memory chip includes at least two stacked and interconnected dies, and the testing method includes: controlling one of the at least two crystal grains to obtain desired data; Test data is obtained through the read / write data line of the other one of the at least two dies, and the test data is compared with the expected data to generate a corresponding comparison result, thereby determining the connectivity between the at least two dies based on the comparison result; wherein the read / write data lines of the at least two stacked interconnected dies are connected to each other through the stacked interconnection structure between the at least two dies; the expected data and the test data are obtained based on the same interface, and the expected data and the test data are generated based on the same test input instruction.

2. The testing method according to claim 1, wherein: The at least two stacked interconnected grains include a first storage grain and a second storage grain, wherein the first storage grain and the second storage grain respectively include a control module, a read-write data line and a storage array; the first storage grain includes a first interface for communicating with the outside world, and the read-write data lines of the first storage grain and the second storage grain are connected to each other through a stacked interconnection structure between the two storage grains, the control module of the first storage grain is connected to the first interface, the control module of the second storage grain is connected to the control module of the first storage grain through the stacked interconnection structure between the two storage grains and is connected to the first interface through the control module of the first storage grain, or the control module of the second storage grain is connected to the first interface of the first storage grain through the stacked interconnection structure between the two storage grains; and the stacked interconnection structure between the two storage grains includes a stacked interconnection hole or a combination of other grains and stacked interconnection holes located between the two storage grains.

3. The testing method according to claim 2, wherein: The controlling one of the at least two dies to obtain desired data includes: The control module of the second memory die obtains the test input instruction from the first interface through the stacked interconnect structure between the two memory die and the control module of the first memory die, or the stacked interconnect structure between the two memory die, and writes the expected data to the read and write data lines of the second memory die based on the test input instruction; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: The read / write data line of the first memory chip acquires data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips to obtain the test data; The first storage die compares the test data and the expected data to generate the corresponding comparison result, and the control module of the first storage die outputs the comparison result through the first interface, so that the test system determines the connectivity between the at least two die based on the comparison result.

4. The testing method according to claim 2, wherein: The controlling one of the at least two dies to obtain desired data includes: The control module of the first memory chip receives the test input instruction through the first interface; The control module of the first memory chip writes the expected data to the read / write data line of the first memory chip based on the test input instruction; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: The read / write data line of the second memory chip acquires the data on the read / write data line of the first memory chip through the stacked interconnect structure between the two memory chips to obtain the test data; The second storage die compares the test data and the expected data to generate the corresponding comparison result, and the control module of the second storage die outputs the comparison result from the first interface through the stacked interconnection structure between the two storage die and the control module of the first storage die, or the stacked interconnection structure between the two storage die, so that the test system determines the connectivity between the at least two die based on the comparison result.

5. The testing method according to claim 2, wherein: The controlling one of the at least two dies to obtain desired data includes: The control module of the second memory die obtains the test input instruction from the first interface through the stacked interconnect structure between the two memory die and the control module of the first memory die, or the stacked interconnect structure between the two memory die, and writes the expected data into the memory array of the second memory die based on the test input instruction; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: Controlling the read and write data lines of the second memory die to read the desired data from the memory array of the second memory die; The read / write data line of the first memory chip acquires data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips to obtain the test data; The first storage die compares the test data and the expected data to generate the corresponding comparison result, and the control module of the first storage die outputs the comparison result through the first interface, so that the test system determines the connectivity between the at least two die based on the comparison result.

6. The testing method according to claim 2, wherein: The controlling one of the at least two dies to obtain desired data includes: The control module of the first memory chip receives the test input instruction through the first interface; The control module of the first memory chip writes the expected data into the memory array of the first memory chip based on the test input instruction; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: Controlling the read and write data lines of the first memory chip to read the desired data from the memory array of the first memory chip; The read / write data line of the second memory chip acquires the data on the read / write data line of the first memory chip through the stacked interconnect structure between the two memory chips to obtain the test data; The second storage die compares the test data and the expected data to generate the corresponding comparison result, and the control module of the second storage die outputs the comparison result from the first interface through the stacked interconnection structure between the two storage die and the control module of the first storage die, or the stacked interconnection structure between the two storage die, so that the test system determines the connectivity between the at least two die based on the comparison result.

7. The testing method according to claim 2, characterized in that: The controlling one of the at least two dies to obtain desired data includes: The control module of the first memory chip receives the test input instruction through the first interface; The control module of the first memory chip writes the expected data to the read / write data line of the first memory chip based on the test input instruction; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: The read / write data line of the second memory die obtains the data on the read / write data line of the first memory die through the stacked interconnect structure between the two memory die; Writing the data on the read / write data line of the second storage die into the storage array of the second storage die to obtain the test data; The second storage chip reads the test data stored in its storage array, compares the test data with the expected data to generate the corresponding comparison result, and the control module of the second storage chip outputs the comparison result from the first interface through the stacked interconnection structure between the two storage chips and the control module of the first storage chip, or the stacked interconnection structure between the two storage chips.

8. The testing method according to claim 2, wherein: The controlling one of the at least two dies to obtain desired data includes: The control module of the second memory die obtains the test input instruction from the first interface through the stacked interconnect structure between the two memory die and the control module of the first memory die, or the stacked interconnect structure between the two memory die, and writes the expected data to the read and write data lines of the second memory die based on the test input instruction; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: The read / write data line of the first memory chip obtains data on the read / write data line of the second memory chip through the stacked interconnect structure between the two memory chips; Writing the data on the read / write data line of the first memory chip into the memory array of the first memory chip to obtain the test data; The first storage chip reads the test data stored in its storage array, compares the test data with the expected data to generate the corresponding comparison result, and the control module of the first storage chip outputs the comparison result through the first interface, so that the test system determines the connectivity between the at least two chips based on the comparison result.

9. The testing method according to claim 1, wherein: The at least two stacked interconnected dies include a logic die and at least one memory die, the logic die including a control module, a read / write data line, and a data comparison module or a read / write data output module, and each memory die includes a control module, a read / write data line, and a memory array, wherein the read / write data lines in each memory die are connected to each other through a stacked interconnect structure between the two dies and are respectively connected to the read / write data lines in the logic die, the control modules in each memory die are respectively connected to each other and to the control module in the logic die through the stacked interconnect structure between the at least two dies, or the control modules in each memory die are respectively connected to the control module in the logic die through the stacked interconnect structure between the at least two dies, and the stacked interconnect structure between the two dies includes a stacked interconnect hole or a combination of other dies and stacked interconnect holes located between the two dies; the logic die includes a first interface and a second interface for communicating with the outside world, wherein the first interface is connected to the control module of the logic die, and the second interface is connected to the data comparison module or the read / write data line output module of the logic die; The controlling one of the at least two dies to obtain desired data includes: The control module of the logic die receives a test input instruction through the first interface; Based on the test input instruction, controlling at least one of the at least one storage die to obtain the expected data; Obtaining test data through the read / write data line of the other one of the at least two dies, comparing the test data with the expected data to generate a corresponding comparison result, and determining the connectivity between the at least two dies based on the comparison result, includes: The desired data is transmitted to the read / write data line of the logic die through a stacked interconnection structure between the logic die and the storage die from which the desired data is obtained, so as to obtain the test data; The test data and the expected data are compared by a data comparison module of the logic grain to generate the corresponding comparison result, and the comparison result is output through the second interface; or the test data is output through the second interface by a read / write data line output module of the logic grain, so that the test system compares the test data and the expected data to generate the corresponding comparison result, thereby determining the connectivity between the at least two grains based on the comparison result.

10. The testing method according to any one of claims 2 to 9, characterized in that: When determining that the connectivity between the at least two grains is abnormal, the testing method further includes: Detecting whether the read / write data lines of the at least two dies with abnormal connectivity are failed; In response to the read and write data lines of the at least two dies being normal, determining that the abnormal connectivity between the at least two dies is caused by a stacked interconnection structure between the at least two dies; In response to the read / write data lines of the at least two dies being abnormal, the abnormal read / write data lines are repaired, and the step of controlling one of the at least two dies to obtain expected data is returned to be re-executed.

11. A three-dimensional stacked memory chip, characterized in that: The invention comprises at least two stacked interconnected dies, wherein the three-dimensional stacked memory chip performs the test method according to any one of claims 1 to 10.

Images