A crc hardware computing system and chip

Abstract

The application discloses a CRC hardware computing system and a chip, the CRC hardware computing system comprises i selected processing arrays; each selected processing array comprises m selected control modules, each bit of information value of the information field has a corresponding selected processing array in the CRC hardware computing system; in the generating polynomial, except the coefficient of the highest power of the generating polynomial, each power term has a corresponding selected control module in each selected processing array; each selected control module is used for selecting the exclusive or result of the information value of the corresponding bit in the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generating polynomial under the triggering of a clock signal, and transmitting the result to the associated selected control module except the selected processing array where the selected control module is located, so as to output the CRC code in parallel after several clock periods.

Description

Technical Field

[0001] This invention belongs to the technical field of cyclic redundancy check circuits, and particularly relates to a CRC hardware calculation system and chip. Background Technology

[0002] Cyclic Redundancy Check (CRC) is used to verify the correctness and integrity of data transmission. CRC operations have strong error detection capabilities and are easily implemented using encoders or detection circuits, such as Linear Feedback Shift Registers (LFSRs). The initial value of the LFSR is called the seed of the pseudo-random sequence, and its last flip-flop outputs a periodically repeating pseudo-random sequence. Traditionally disclosed CRC8 serial shift circuits can calculate the CRC checksum through shifting, and the corresponding generator polynomial is: G = g⁸X. 8 +g7X 7 +...+g1X 1 +1.

[0003] Traditional techniques have at least the following problems: In CRC circuits, processing multiple bits of information code values ​​in parallel for verification requires a long clock cycle. Moreover, each bit of information code value to be processed within one clock cycle requires a corresponding XOR gate circuit and multiplier. Therefore, a lot of time is needed to configure and process the coefficients of each power of the generator polynomial, and multiplication operations are also required for each coefficient and the associated information code, resulting in a long CRC verification time and excessive hardware resource consumption. Summary of the Invention

[0004] To overcome the aforementioned technical deficiencies, this invention discloses a CRC hardware calculation system and chip, the specific technical solution of which is as follows:

[0005] A CRC hardware computing system is disclosed. The system acquires configuration information and an information field, determines a generator polynomial based on the configuration information, and then provides a clock signal, coefficients of each power in the generator polynomial, and the information field to each selection processing array. The CRC hardware computing system includes i selection processing arrays. Each selection processing array is configured to be controlled by the coefficients of the corresponding powers in the generator polynomial, excluding the highest power term. Each selection processing array includes m selection control modules, each used to input the information value of the corresponding bit of the information field. Each bit of the information field has a corresponding selection processing array in the CRC hardware computing system. The generator polynomial... In the formula, apart from the coefficient of the highest power of the generator polynomial, each power term has a corresponding selection control module in each selection processing array; each selection control module is used, triggered by a clock signal, to select, according to the coefficient of the corresponding power in the generator polynomial, the XOR result of the information value of the corresponding bit in the information field and the associated value or the CRC initial value associated with the corresponding power, and transmit it to the associated selection control module other than the selection processing array where the selection control module is located; wherein, m is configured to be equal to the number of bits of the CRC initial value, and m is equal to the degree of the highest power term in the generator polynomial; i is configured to be the number of bits of the information field, and the information field is a binary sequence input to the CRC hardware calculation system within a clock cycle.

[0006] Furthermore, the CRC hardware computing system includes m x i selection control modules, all of which are arranged in an m x i column configuration, resulting in an i-column selection processing array in the CRC hardware computing system. Each selection processing array contains m rows of selection control modules. Each selection control module includes an XOR calculation unit, a storage unit, and a selector, such that the XOR calculation unit, storage unit, and selector are all arranged in an m x i column configuration in the CRC hardware computing system.

[0007] Furthermore, in addition to all selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, transmit it to the selection processing array corresponding to the relatively low-order information value of the information field, and output it to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array.

[0008] Further, the XOR calculation unit in row p and column j is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the power of (p-1), and the information value of the (ij-1)th bit of the information field, and outputs the XOR result of the XOR calculation unit in row p and column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit in row p and column j is used to store the CRC initial value corresponding to the power of (p-1), wherein the CRC initial value corresponding to the power of (p-1) is the CRC initial value associated with the corresponding power; the selector in row p and column j is used to generate multiple terms according to the... The coefficient of the power of p in the formula is selected from the XOR result of the XOR calculation unit in the p-th row and j-th column or the CRC initial value corresponding to the power of (p-1) stored in the storage unit in the p-th row and j-th column. The output result of the selector in the p-th row and j-th column is configured as the output value of the selection control module in the p-th row and j-th column. The selection control module in the p-th row and j-th column includes the XOR calculation unit in the p-th row and j-th column, the selector in the p-th row and j-th column, and the storage unit in the p-th row and j-th column. The selection control module in the p-th row and j-th column is located in the selection processing array in the j-th column. The selection control module in the p-th row and j-th column is used to select the output result of the selector in the p-th row and j-th column. The data is transmitted to the XOR calculation unit in the (p+1)th row and (j+1)th column and the storage unit in the (p+1)th row and (j+1)th column, and updated to the CRC initial value corresponding to the power of p under the trigger of the clock signal; wherein, the selection control module in the (p+1)th row and (j+1)th column includes the XOR calculation unit in the (p+1)th row and (j+1)th column and the storage unit in the (p+1)th row and (j+1)th column, and the selection control module in the (p+1)th row and (j+1)th column is located in the selection processing array in the (j+1)th column; wherein, p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i, and p are all positive integers, and j is an integer; the selection control module in the p-th row and j-th column is not one of the selection control modules corresponding to the coefficients of the second highest power, nor is the selection control module in the p-th row and j-th column located in the selection processing array corresponding to the least significant bit of the information field; all selection control modules corresponding to the coefficients of the second highest power are all selection control modules corresponding to the coefficients of the second highest power of the generator polynomial; wherein, the initial CRC value input by the selection control module in the 0th column is configured before the CRC hardware calculation system starts processing the information field, and can be updated under the trigger of the clock signal.

[0009] Further, the XOR calculation unit in row 0, column j is used to XOR the CRC initial value corresponding to the highest bit with the information value of the (ij-1)th bit of the information field, and outputs the XOR result of the XOR calculation unit in row 0, column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit in row 0, column j is used to store a preset constant, wherein the preset constant is the CRC initial value associated with the corresponding power; the selector in row 0, column j is used to select the XOR result of the XOR calculation unit in row 0, column j or the preset constant stored in the storage unit in row 0, column j according to the coefficient of the 0th power in the generator polynomial, and configure the output result of the selector in row 0, column j as the output value of the selection control module in row 0, column j; wherein, the selection control module in row 0, column j includes the XOR calculation unit in row 0, column j, the selector in row 0, column j, and the storage unit in row 0, column j, column j The column selection control module is located in the selection processing array of the j-th column; the selection control module of the 0th row and j-th column is used to transmit the output result of the selector of the 0th row and j-th column to the XOR calculation unit of the 1st row and (j+1)-th column and the storage unit of the 1st row and (j+1)-th column, and update it to the CRC initial value associated with the corresponding power under the trigger of the clock signal; wherein, the selection control module of the 1st row and (j+1)-th column includes the XOR calculation unit of the 1st row and (j+1)-th column and the storage unit of the 1st row and (j+1)-th column, and the selection control module of the 0th row and (j+1)-th column is located in the selection processing array of the (j+1)-th column; wherein, j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, and j is an integer; the selection control module of the 0th row and j-th column is not one of the selection control modules corresponding to the coefficient of the highest power, and the selection control module of the 0th row and j-th column is not located in the selection processing array corresponding to the least significant bit of the information value of the information field.

[0010] Furthermore, among all the selection control modules corresponding to the coefficients of the second-highest power, except for the selection control module in the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit it to all the selection control modules in the selection processing array corresponding to the relatively low significant bit of the information field.

[0011] Further, the XOR calculation unit in the (m-1)th row and j-th column is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2)th power, and the information value of the (ij-1)th bit of the information field, and outputs the XOR result of the XOR calculation unit in the (m-1)th row and 0th column, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit in the (m-1)th row and j-th column is used to store the CRC initial value corresponding to the (m-2)th power, wherein the CRC initial value corresponding to the (m-2)th power... The value is the CRC initial value associated with the corresponding power; the selector in the (m-1)th row and jth column is used to select the XOR result of the XOR calculation unit in the (m-1)th row and jth column or the CRC initial value corresponding to the (m-2)th power stored in the storage unit in the (m-1)th row and jth column according to the coefficient of the (m-1)th power in the generator polynomial, and output the result of the selector in the (m-1)th row and jth column as the output value of the selection control module in the (m-1)th row and jth column; wherein, the selection control module in the (m-1)th row and jth column includes the (m- 1) An XOR calculation unit in row j, column j, a storage unit in row (m-1) and column j, and a selector in row (m-1) and column j; the selection control module in row (m-1) and column j is used to transmit the output of the selector in row (m-1) and column j to all XOR calculation units in column (j+1), and update it to the CRC initial value corresponding to the highest bit required for XOR operation by all XOR calculation units in column (j+1) under the trigger of the clock signal; wherein, all XOR calculation units in column (j+1) are located in the relatively low bits of the information field. The selection control modules in the selection processing array corresponding to the information value; where j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; the selection control module in the (m-1)th row and jth column is the selection control module other than the selection control module in the selection processing array corresponding to the least significant bit of the information field among all the selection control modules corresponding to the coefficients of the second highest power; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the second highest power of the generator polynomial.

[0012] Furthermore, each selection control module in the selection processing array corresponding to the least significant bit of the information field is used to select the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, transmit it to the selection processing array corresponding to the most significant bit of the information field, and output it to the selection control module corresponding to the coefficient of the corresponding power in the selection processing array.

[0013] Further, the XOR calculation unit in the p-th row and (i-1)-th column is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1)-th power, and the information value of the lowest bit of the information field, and outputs the XOR result of the XOR calculation unit in the p-th row and (i-1)-th column, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit in the p-th row and (i-1)-th column is used to store the CRC initial value corresponding to the (p-1)-th power, wherein the CRC initial value corresponding to the (p-1)-th power is the CRC initial value associated with the corresponding power; the selector in the p-th row and (i-1)-th column is used to select the XOR result of the XOR calculation unit in the p-th row and (i-1)-th column or the value stored in the storage unit in the p-th row and (i-1)-th column according to the coefficient of the p-th power in the generator polynomial. The CRC initial value corresponding to the power of (p-1) is output, and the output result of the selector in the p-th row and (i-1)-th column is configured as the output value of the selection control module in the p-th row and (i-1)-th column; wherein, the selection control module in the p-th row and (i-1)-th column includes an XOR calculation unit in the p-th row and (i-1)-th column, a storage unit in the p-th row and (i-1)-th column, and a selector in the p-th row and (i-1)-th column, and the selection control module in the p-th row and (i-1)-th column is located in the selection processing array corresponding to the least significant bit of the information field; wherein, p is less than or equal to m-1, p is greater than 0, m is greater than 1, and i and m are both positive integers; the selection control module in the p-th row and (i-1)-th column is the selection control module in the selection processing array corresponding to the least significant bit of the information field, excluding the selection control module in the 0th row.

[0014] Further, the XOR calculation unit in row 0, column (i-1) is used to XOR the initial CRC value corresponding to the highest bit with the information value of the lowest bit of the information field, and outputs the XOR result of the XOR calculation unit in row 0, column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit in row 0, column (i-1) is used to store a preset constant, wherein the preset constant is the initial CRC value associated with the corresponding power; the selector in row 0, column (i-1) is used to select the XOR calculation unit in row 0, column (i-1) according to the coefficient of the 0th power in the generator polynomial. The XOR result of the calculation unit or the preset constant stored in the storage unit of the 0th row and (i-1)th column is output, and the output result of the selector in the 0th row and (i-1)th column is configured as the output value of the selection control module in the 0th row and (i-1)th column; wherein, the selection control module in the 0th row and (i-1)th column includes the XOR calculation unit in the 0th row and (i-1)th column, the selector in the 0th row and (i-1)th column, and the storage unit in the 0th row and (i-1)th column, and the selection control module in the 0th row and (i-1)th column is the selection control module in the 0th row of the selection processing array corresponding to the least significant bit of the information value of the information field.

[0015] Furthermore, each selection control module in column 0 is connected to a corresponding register. The data input of one selection control module is connected to the data output of one register. The data input of each register is connected to the selector in the same row and column (i-1), so that the selection control modules corresponding to the selection processing array in column 0 and column (i-1) with coefficients of the same power are connected via registers. The selection processing array in column 0 is the selection processing array corresponding to the highest bit of the information field, and the selection processing array in column (i-1) is the selection processing array corresponding to the lowest bit of the information field. The clock input of each register is connected to the clock signal, and each register is used to buffer the output result of the selector in the same row and column (i-1) when triggered by the clock signal.

[0016] Further, the method of selecting the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power based on the coefficient of the corresponding power in the generator polynomial includes: when the CRC hardware calculation system is configured such that the coefficient of the corresponding power in the generator polynomial is 1, the selection terminal of the selector inside the corresponding selection control module receives a first level signal, the selector selects the XOR calculation unit inside the selection control module and outputs the XOR result of the XOR calculation unit, wherein the XOR result of the information value of the corresponding bit of the information field and the associated value is the XOR result of the XOR calculation unit. The XOR result of the elements, wherein the associated value includes the CRC initial value corresponding to the highest bit and / or the CRC initial value associated with the corresponding power; the XOR calculation unit is an XOR logic gate circuit with three input terminals; the data stored in the storage unit can be refreshed; when the CRC hardware calculation system is configured such that the coefficient of the corresponding power in the generator polynomial is 0, the selection terminal of the selector inside the corresponding selection control module receives the second level signal, and the CRC initial value associated with the corresponding power stored in the storage unit inside the selection control module where the selector is selected is output, wherein the second level signal is different from the first level signal.

[0017] Further, the configuration information includes CRC type, coefficients of the generator polynomial, and initial CRC value; the method by which the CRC hardware calculation system determines the generator polynomial based on the configuration information includes: determining the type of the generator polynomial and the coefficients of each power in the generator polynomial based on the CRC type and the coefficients of each power; wherein, the initial CRC value is set according to the communication protocol followed by the information field before the CRC hardware calculation system starts processing the information field; wherein, the initial CRC value corresponding to the highest bit is the initial CRC value corresponding to the second highest power of the generator polynomial.

[0018] Furthermore, when the CRC type is CRC8, m is set to 8, i is set to 4, and the information field consists of 4-bit information values.

[0019] A chip comprising the aforementioned CRC hardware calculation system for cyclic redundancy check.

[0020] Furthermore, the CRC hardware computing system includes m x i selection control modules, all of which are arranged in an m x i column configuration, resulting in an i-column selection processing array in the CRC hardware computing system. Each selection processing array contains m rows of selection control modules. Each selection control module includes an XOR calculation unit, a storage unit, and a selector, such that the XOR calculation unit, storage unit, and selector are all arranged in an m x i column configuration in the CRC hardware computing system.

[0021] Furthermore, in addition to all selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, transmit it to the selection processing array corresponding to the relatively low-order information value of the information field, and output it to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array.

[0022] Furthermore, among all the selection control modules corresponding to the coefficients of the second-highest power, except for the selection control module in the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit it to all the selection control modules in the selection processing array corresponding to the relatively low significant bit of the information field.

[0023] Furthermore, each selection control module in the selection processing array corresponding to the least significant bit of the information field is used to select the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, transmit it to the selection processing array corresponding to the most significant bit of the information field, and output it to the selection control module corresponding to the coefficient of the corresponding power in the selection processing array.

[0024] Furthermore, each selection control module in column 0 is connected to a corresponding register. The data input of one selection control module is connected to the data output of one register. The data input of each register is connected to the selector in the same row and column (i-1), so that the selection control modules corresponding to the selection processing array in column 0 and column (i-1) with coefficients of the same power are connected via registers. The selection processing array in column 0 is the selection processing array corresponding to the highest bit of the information field, and the selection processing array in column (i-1) is the selection processing array corresponding to the lowest bit of the information field. The clock input of each register is connected to the clock signal. Each register is used to buffer the output result of the selector in the same row and column (i-1) under the trigger of the clock signal, in order to obtain the iterative result of the CRC hardware calculation system.

[0025] Compared with existing technologies, the CRC hardware calculation system disclosed in this invention configures the coefficients of the corresponding powers in the generator polynomial of the specified CRC (excluding the highest power term) as selection control signals. These signals are input to the selection terminals of the selectors in the corresponding rows and columns of the selection control module. This allows each selection control module to select, within the current clock cycle, the XOR calculation result of the information value of the corresponding bit in the information field and the associated value, or the initial CRC value associated with the corresponding power, based on the coefficients of the corresponding powers in the generator polynomial. This result is then transmitted to the selection control module corresponding to the lower bit of the information field in a selection processing array. This allows other selection control modules in the selection processing array to begin XOR operations on the other bits of the information field in the next clock cycle. During the verification process using the generator polynomial, the introduction of a number of zeros after the highest power term in the information field is avoided. The XOR operation can advance the CRC verification process of the information field bit by bit. This not only reduces iterative processing of constant terms such as 0, but also allows for flexible configuration of the coefficients of each power to adapt to various CRC calculation needs.

[0026] Based on this, the present invention uses combinational logic to concatenate the XOR operations performed by two adjacent selection control modules in two adjacent clock cycles, and uses combinational logic to connect the first and last selection control modules to form a feedback loop. This can control each selection processing array to update the initial CRC value in each clock cycle, and obtain the CRC code after the corresponding clock cycle. This achieves the optimization of combinational logic circuit by combining periodic feedback and selection circuit, and also achieves the effect of running multi-bit CRC operation in a single clock cycle.

[0027] Furthermore, when the code corresponding to the generating polynomial is added to the information field of the input CRC hardware calculation system (to form a CRC code through CRC operation), since the CRC hardware calculation system for cyclic redundancy check designed in this invention abandons the use of multipliers and instead uses selectors in conjunction with XOR calculation units to reduce multiplication operations on 0, it is not necessary to add the highest power of zeros (the highest power of the polynomial corresponding to the CRC code) after the corresponding bit information value in the information field, nor is it necessary to directly use matrices to perform division operations in hardware, thus consuming less hardware resources. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of a CRC hardware calculation system provided in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of the structure of a CRC hardware calculation system that uses the CRC8 type and processes four-bit information values, according to an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the description of this application, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating a relative order of arrangement or implying relative importance.

[0031] As those skilled in the art will know, the principle of CRC check is to append an R-bit binary check code to a K-bit binary data sequence, thus forming a binary sequence of total length N = K + R bits. There is a specific relationship between the check code appended to the data sequence and the content of the data sequence. If one or more bits in the data sequence are erroneous due to interference or other reasons, this specific relationship is disrupted. Therefore, by verifying this relationship through a CRC check algorithm or CRC check circuit, the correctness of the data sequence can be verified. Thus, the CRC hardware calculation system for cyclic redundancy check disclosed in this embodiment belongs to the CRC check circuit category.

[0032] In existing CRC verification techniques, the sender and receiver need to pre-agree on a divisor, i.e., a generator polynomial, whose most and least significant bits must be 1. For error checking, an R-bit redundancy code (binary check code) needs to be added after the K-bit information field (K-bit binary data sequence). The codeword length N is equal to the sum of K and R. The sender and receiver pre-agree on an R-degree polynomial (the CRC generator polynomial), whose most and least significant bits must be 1. The CRC code consists of a K-degree information polynomial and an R-1 degree check polynomial. Specifically, the code corresponding to the R-1 degree check polynomial is the redundancy code, which is added to the original information field to form the CRC code. The R-1 degree check polynomial is calculated by adding R zeros after the K-bit information field, then dividing by the code sequence corresponding to the R-degree polynomial; the remainder is the code corresponding to the R-1 degree check polynomial.

[0033] For example: the information field code is 1011001; corresponding to m(x) = x 6 +x 4 +x 3 +1.

[0034] Suppose the generating polynomial is: g(x) = x 4 +x 3 +1; then the code for g(x) is: 11001 (corresponding to the coefficients of each power).

[0035] x 4 m(x)=x 10 +x 8 +x 7 +x 4 The corresponding code is 10110010000 (corresponding to the coefficients of each power).

[0036] Using polynomial division, the remainder is 1010, which means the code corresponding to the R-1 degree check polynomial is 1010 (i.e., CRC check code).

[0037] The transmission field sent by the sender is: 10110011010 (the check field is added after the information field).

[0038] Receiver: Use the code corresponding to the same generator polynomial for verification. If the received field can be divided evenly by the code corresponding to the generator polynomial (binary division), then the verification is correct.

[0039] In order to improve the speed of cyclic redundancy check of input information fields by using combinational logic, and to flexibly configure the corresponding generator polynomial according to the communication protocol requirements to calculate the CRC check code more quickly or accurately in hardware, this invention discloses a CRC hardware calculation system.

[0040] It should be noted that before performing cyclic redundancy check on the input information field, the CRC hardware calculation system obtains configuration information and the information field, determines the generator polynomial of the CRC based on the configuration information, and then provides a clock signal, the coefficients of each power in the generator polynomial, and the information field to each selected processing array, making the generator polynomial configurable. Specifically, the configuration information includes the CRC type, the coefficients of each term of the generator polynomial, and the initial CRC value. The method by which the CRC hardware calculation system determines the generator polynomial based on the configuration information includes: determining the type of the generator polynomial and the coefficients of each power in the generator polynomial based on the CRC type and the coefficients of each term of the generator polynomial. The initial CRC value is set according to the communication protocol followed by the information field before the CRC hardware calculation system starts processing the information field, and supports being updated by the XOR result in subsequent verification processes. Based on this, in this embodiment, the initial CRC value corresponding to the highest bit is the initial CRC value corresponding to the second highest power of the generator polynomial, and also the initial CRC value corresponding to the second highest power term of the generator polynomial. The CRC hardware calculation system can determine the coefficients of the generator polynomial based on the CRC type, and then determine the initial CRC value associated with each power based on the coefficients of the generator polynomial defined by the protocol, thereby realizing flexible configuration of the generator polynomial.

[0041] The CRC hardware calculation system includes i selection processing arrays; each selection processing array is configured to be controlled by the coefficients of the corresponding powers in the generator polynomial, excluding the highest power term (the coefficient of the highest power); each selection processing array includes m selection control modules, each selection control module being used to process the information value of the corresponding bit of the information field; wherein, each bit of the information field has a corresponding selection processing array in the CRC hardware calculation system, and all selection control modules within a selection processing array correspond to the same bit of the information field; in the generator polynomial, except for the coefficient corresponding to the highest power, each power-related coefficient has a corresponding selection control module in each selection processing array; equivalently, in the generator polynomial, except for the coefficient corresponding to the highest power, each power term has a corresponding selection control module in each selection processing array, such that each power-related coefficient has a corresponding selection control module in each selection processing array. In the CRC hardware calculation system described in this embodiment, during the cyclic redundancy check process, the coefficients of the highest power of the generator polynomial are not processed. This is equivalent to deleting the highest power term of the generator polynomial and then performing the check calculation on the remaining polynomial. In this embodiment, each selection control module, triggered by a clock signal, selects the XOR result of the information value of the corresponding bit in the information field and the associated value, or the CRC initial value associated with the corresponding power, based on the coefficients of the corresponding power in the generator polynomial, and transmits it to the associated selection control module outside the selection processing array where the selection control module is located. Thus, a selection control module only transmits its selection output result to the selection control modules in other selection processing arrays. Specifically, this corresponds to... Figure 1 After several clock cycles, the selection control modules in the other columns output the check code in parallel. The coefficients of the corresponding powers in the generator polynomial are configured as selection control signals in the selection control module. These signals are used to select the circuit that generates the XOR result of the information value of the corresponding bit in the information field and the associated value, or the circuit that stores the CRC initial value associated with the corresponding power, and connect it to the selection processing array of other columns. In some embodiments, in response to the clock signal, a selection control module, under the selection of the coefficients of the corresponding powers in the generator polynomial, transmits the XOR result of the information value of the corresponding bit in the information field and the associated value, or the CRC initial value associated with the corresponding power, to the selection control module for processing the information value of the relevant bit in the information field in the next clock cycle. This achieves the iterative processing required during the execution of cyclic redundancy check, and calculates the check code (CRC code) in parallel in hardware.

[0042] It should be noted that m is configured to be equal to the number of bits in the initial CRC value, and m is equal to the degree of the highest-degree term in the generator polynomial; it is worth noting that in this invention, i is configured as the number of bits in the information field, and the information field is configured as a binary sequence input to the CRC hardware calculation system within one clock cycle, and the number of bits in the information field input within each clock cycle is equal; preferably, the information field may be updated to a different one within each clock cycle, i.e. Figure 1 The inputs from left to right, D[i-1] to D[0], will be refreshed, thereby obtaining the CRC code based on the generator polynomial.

[0043] In this embodiment, the configuration information is used to instruct the CRC hardware calculation system to select the XOR result or the corresponding power-related CRC initial value to complete the CRC check. It can also obtain the latest value of the CRC initial value associated with each power in each clock cycle. This information is pre-set. The CRC initial value is used to initialize the selection processing array. The CRC initial value can be a protocol-defined value or the output value of the selection control module in the previous iteration. The number of bits in the CRC initial value is equal to the number of iteration bits of the selection control module.

[0044] CRC types include, but are not limited to, CRC4, CRC7, CRC8, CRC12, CRC16, and CRC32. The generator polynomial includes the generator polynomial type and the coefficients corresponding to each power in the generator polynomial. The generator polynomial type corresponds to the CRC type, and users can define the generator polynomial type and the coefficients corresponding to each power in the generator polynomial according to protocol or product requirements. In some embodiments, the CRC type is CRC8, and the generator polynomial corresponding to CRC8 is 1+X. 1 +X 2 +X 8The CRC hardware calculation system selects the generator polynomial corresponding to CRC8 for verification and determines that g[0] = 1, g[1] = 1, g[2] = 1, g[3] = g[4] = g[5] = g[6] = g[7] = 0, g[8] = 1. Thus, the coefficients of the generator polynomial corresponding to CRC8 are: the coefficients of the 0th power, the 1st power, the 2nd power, and the 8th power are all 1, and the coefficients of the 3rd power, the 4th power, the 5th power, the 6th power, and the 7th power are all 0. Except for the highest power coefficient g[8], there are a total of 8 coefficients. The selection processing array in the CRC hardware calculation system only uses g[0] to g[7] as parameters. With cyclic redundancy check, where g[7] is the coefficient of the second highest power and g[0] is the coefficient of the lowest power; since the number m of the selection control modules included in a selection processing array is equal to the degree of the highest power term in the generator polynomial, and m is configured to be equal to the number of bits of the CRC initial value, m is set to 8, the CRC initial value is set to C[7:0], C[7:0] is preferably 01010101, then the CRC initial value corresponding to the highest bit is C[7], and the CRC initial values ​​associated with the corresponding powers (the CRC initial values ​​corresponding to the p powers, where p is an integer between 0 and 7) are C[0], C[1], C[2], C[3], C[4], C[5] and C[6] from low to high power.

[0045] Based on the aforementioned embodiments, the CRC hardware computing system includes m x i selection control modules. All selection control modules are arranged in an m x i column configuration, resulting in an i-column selection processing array. Each column of the selection processing array is a selection processing array, and each selection processing array contains m rows of selection control modules. Each row of selection control modules in a selection processing array is a selection control module, and each row of selection control modules in the CRC hardware computing system contains i selection control modules. Each selection control module includes an XOR calculation unit, a storage unit, and a selector, such that the XOR calculation unit, storage unit, and selector are all arranged in an m x i column configuration in the CRC hardware computing system. Figure 1 In this configuration, the row and column numbers of the XOR calculation unit, storage unit, and selector are all counted starting from 0. In some embodiments, the selection control module is also connected to a register, which is used to cache the CRC initial value or the result of the associated selector selection output (the iteration result in the cyclic redundancy check process) transmitted by other selection control modules in the previous clock cycle. Further, the coefficients of each power of the generator polynomial and the corresponding CRC initial values ​​are processed in parallel on the information field for multiple clock cycles in the selection processing array, and finally the CRC code is obtained in hardware.

[0046] Specifically, such as Figure 1 As shown, the CRC hardware calculation system includes i selection processing arrays arranged in columns, namely a first selection processing array, a second selection processing array, ..., the i-th selection processing array, where i is a positive integer; the i selection processing arrays are used to process the CRC data in each clock cycle under the trigger of the clock signal CLK. Figure 1 The information field, represented by the i-bit array, is processed. Each selected processing array can process one bit of the information field (consisting of multiple bit information values). The information field is the communication data to be verified, which is a binary sequence with i bits.

[0047] In this embodiment, each selection processing array is configured to be controlled by the corresponding signal of the coefficients of the corresponding powers in the generator polynomial, excluding the coefficient of the highest power. The selection control module in the 0th row of each selection processing array ( Figure 1 The selection control module (located in the XOR calculation unit of the 0th row) corresponds to the coefficient g[0] of the 0th power of the generator polynomial and is controlled by its corresponding signal; the selection control module in the 1st row of each selection processing array ( Figure 1 The selection control module where the XOR calculation unit in the first row is located corresponds to and is controlled by the coefficient g[1] of the first power of the generator polynomial; and so on, the selection control module in the (m-1)th row of each selection processing array ( Figure 1 The selection control module where the XOR calculation unit in the (m-1)th row is located corresponds to and is controlled by the coefficient g[M-1] of the (m-1)th power of the generator polynomial.

[0048] Each selection processing array includes m selection control modules. Each selection control module processes the information value of the corresponding bit of the information field under the trigger of a clock signal, such that each bit of the information field has a corresponding selection processing array in the CRC hardware calculation system. The specific column number of the selection processing array is associated with the bit number to which the input information value belongs in the information field, corresponding to... Figure 1 In the CRC hardware computing system, each selection control module in the first selection processing array located in the 0th column inputs the (i-1)th bit information value D[i-1] of the information field, each selection control module in the second selection processing array located in the 1st column inputs the (i-2)th bit information value D[i-2] of the information field, and so on, each selection control module in the i-th selection processing array located in the (i-1)th column inputs the 0th bit information value D[0] of the information field.

[0049] It should be added that the selection control modules in the same row of each selection processing array correspond to the coefficients of the same power in the generator polynomial. This ensures that, except for the coefficient of the highest power in the generator polynomial, each power coefficient in each selection processing array has a corresponding selection control module. Therefore, except for the highest power term of the generator polynomial, each power term in each selection processing array has a corresponding selection control module. Specifically, the selection control modules in the same row of each selection processing array are configured to be controlled by the coefficients of the same power in the generator polynomial. The row number of the selection control module is equal to the degree of the power term containing the coefficient controlling that selection control module. Figure 1 In the diagram, all selection control modules in row 0 correspond to and are controlled by the coefficient g[0] of the generator polynomial to the power of 0. All selection control modules in row 1 correspond to and are controlled by the coefficient g[1] of the generator polynomial to the power of 1. Similarly, all selection control modules in row (m-1) correspond to and are controlled by the coefficient g[m-1] of the generator polynomial to the power of (m-1) on the hardware port, and are subject to the constraints of the corresponding clock cycle.

[0050] It should be noted that Exclusive OR, also known as the XOR operation, is implemented by the XOR calculation unit in this embodiment. That is, the result is 0 for identical bits and 1 for different bits, meaning binary addition and subtraction operations do not consider carry or borrow, such as: 10011011 + 11001010 = 01010001. The XOR calculation unit disclosed in this invention is an XOR logic gate circuit with three input terminals. Since the data stored in the memory unit supports being refreshed, the memory unit can be composed of a register or a dynamic random access memory.

[0051] As an example, in addition to all selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power, based on the coefficient of the corresponding power in the generator polynomial. This initial value can be used as the verification code output by the current selection control module (which can also be regarded as the result of one iteration, belonging to the CRC initial value), transmitted to the selection processing array corresponding to the relatively low-order information value of the information field, and output to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array, so as to advance the CRC calculation process. In addition to all selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the least significant bit of the information field, one selection control module is connected to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array corresponding to the relatively low-order information value of the information field. The coefficient of the corresponding power in the generator polynomial is used as a selection control signal, and the coefficient of the corresponding power in the generator polynomial corresponds to the selection control module currently making the selection. In this embodiment, the relatively low-order information value of the information field is an information value that is one bit lower than the number of bits of the information value corresponding to the selection processing array where the selection control module for outputting the verification information code is located, and the coefficient of the relatively high power is a coefficient that is one order higher than the power of the power term corresponding to the selection control module for outputting the verification information code.

[0052] As an example, the XOR calculation unit in row p and column j is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the power of (p-1), and the information value of the (ij-1)th bit of the information field, and outputs the XOR result of the XOR calculation unit in row p and column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. In this example, the XOR calculation unit in row p and column j is respectively input with the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the power of (p-1), and the information value of the (ij-1)th bit of the information field. Then the information value of the (ij-1)th bit of the information field (actually the binary number of the (ij)th bit from right to left) is the information value of the corresponding bit of the information field, and the CRC initial value corresponding to the highest bit and the CRC initial value corresponding to the power of (p-1) are the associated values. When the XOR calculation unit is an XOR logic gate circuit with three input terminals, the first input terminal of the XOR logic gate circuit is used to input the CRC initial value corresponding to the highest bit. The second input terminal of the circuit is used to input the CRC initial value corresponding to the power of (p-1), and the third input terminal of the XOR logic gate is used to input the information value of the (ij-1)th bit of the information field. The CRC initial value corresponding to the highest bit is updated according to the clock cycle triggered by the clock signal. The CRC initial value input by the selection control module of column 0 is configured before the CRC hardware calculation system begins processing the information value of the (i-1)th bit of the information field, and it supports being updated under the trigger of the clock signal. Specifically, it is updated according to the clock cycle to the CRC initial value corresponding to the power of (p-1), and can be transferred from the register. It should be noted that, corresponding to... Figure 1It is known that p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i, and p are all positive integers, and j is an integer; therefore, the selection control module in the p-th row and j-th column is not one of the selection control modules corresponding to the coefficients of the second highest power, nor is it the selection processing array corresponding to the least significant bit of the information field; all selection control modules corresponding to the coefficients of the second highest power are all selection control modules corresponding to the coefficients of the (m-1)th power of the generator polynomial. The storage unit in the p-th row and j-th column is used to store the CRC initial value corresponding to the (p-1)th power, where the CRC initial value corresponding to the (p-1)th power is the CRC initial value associated with the corresponding power, which may be the CRC initial value updated from the previous clock cycle, or it may be transmitted from the selection control module in the previous column. The selector in row p, column j is used to select the XOR result of the XOR calculation unit in row p, column j or the CRC initial value corresponding to the power of (p-1) stored in the storage unit in row p, column j, based on the coefficients of the power of p in the generator polynomial, and to output the result of the selector in row p, column j as the output value of the selection control module in row p, column j. The selection control module in row p, column j includes an XOR calculation unit in row p, column j, a selector in row p, column j, and a storage unit in row p, column j. One input terminal of the selector in row p, column j is connected to the output terminal of the XOR calculation unit in row p, column j, and the other input terminal of the selector in row p, column j is connected to the output terminal of the storage unit in row p, column j. The gating terminal of the selector in row p, column j is used to input the configurable coefficients of the power of p in the generator polynomial (corresponding signals). The output of the selector in row p, column j is connected to one input of the XOR calculation unit in row (p+1), column (j+1), and the output of the selector in row p, column j is connected to one input of the storage unit in row (p+1), column (j+1). The selection control module in row p, column j transmits the output of the selector in row p, column j to the XOR calculation unit in row (p+1), column (j+1) and the storage unit in row (p+1), and at the clock... The initial CRC value is updated to the power of p under the trigger of the signal, and is used as the parameter for XOR operation in the selection control module in row (p+1) and column (j+1) of the next clock cycle. The selection control module in row (p+1) and column (j+1) includes an XOR calculation unit in row (p+1) and column (j+1) and a storage unit in row (p+1) and column (j+1). The selection control module in row (p+1) and column (j+1) is located in the selection processing array in column (j+1).When j is greater than 0, one input terminal of the XOR calculation unit in row p and column j is connected to the output terminal of the selector in row (p-1) and column (j-1); when j equals 0, one input terminal of the XOR calculation unit in row p and column j is used to input the pre-configured CRC initial value corresponding to the highest bit. The CRC initial value corresponding to the highest bit is updated according to the clock cycle under the triggering action of the clock information. Specifically, the update configuration is performed by the relevant configuration module inside the CRC hardware calculation system.

[0053] In summary, this embodiment only requires a single clock cycle to control the information field to perform parallel iterative processing of the coefficients of all powers in the generator polynomial, except for the highest power term, the second highest power term, and the power term corresponding to the least significant bit of the information field, thereby improving the efficiency of CRC calculation. Furthermore, it allows for flexible configuration of various settings to adapt to diverse CRC calculation needs.

[0054] Combination Figure 1 and Figure 2 As can be seen, based on Embodiment 1, when the CRC type is CRC8, m is set to 8 and i is set to 4, so that the four selection processing arrays process the four-bit information value sequentially under the trigger of the clock signal, wherein the most significant bit is processed first and the least significant bit is processed last; the information field is composed of four-bit information values; wherein, all selection control modules in one selection processing array process the input CRC initial value in parallel; the information field is a binary sequence. Since the selection control module in row p and column j is not one of all selection control modules corresponding to the coefficients of the second highest power, and the selection control module in row p and column j is not the selection processing array corresponding to the least significant information value in the information field, and p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i, and p are all positive integers, and j is an integer, the selection control module in row p and column j includes the selection control module in row 1 and column 0, the selection control module in row 1 and column 1, the selection control module in row 1 and column 2, the selection control module in row 2 and column 0, the selection control module in row 2 and column 1, the selection control module in row 2 and column 2, ..., the selection control module in row 6 and column 0, the selection control module in row 6 and column 1, and the selection control module in row 6 and column 2.

[0055] Corresponding to Figure 2 The second selection processing array in the first row and 0th column, the selection control module includes an XOR calculation unit in the first row and 0th column. Figure 2 The box marked with C[0]^C[7]^D[3]), the storage unit in the 1st row and 0th column ( Figure 2The box marked C[0] in the middle) and the selector S1[1] in the first row and the 0th column, the XOR calculation unit in the first row and the 0th column respectively obtain the CRC initial value C[7] corresponding to the highest bit, the CRC initial value C[0] corresponding to the power of 0 (from register REG1), and the information value D[3] of the third bit of the information field (the highest bit of the information field), and perform C[0]^C[7]^D[3], and output the XOR result of these three values; the storage unit in the first row and the 0th column is used to store the CRC initial value C[0] corresponding to the power of 0. The selector S1[1] in the first row and the 0th column is used to select the XOR result of the XOR calculation unit in the first row and the 0th column when the coefficient g[1] of the power of 1 in the generator polynomial is not equal to 0, or to select the C[0] stored in the storage unit in the first row and the 0th column when the coefficient g[1] of the power of 1 in the generator polynomial is equal to 0. The selection control module in row 1, column 0 configures the output of the selector in row 1, column 0 as the output value of the selection control module in row 1, column 0, and then transmits it to the XOR calculation unit in row 2, column 1 and the storage unit in row 2, column 1, and updates it to the CRC initial value L[1] corresponding to the power of 1 under the trigger of the clock signal. Among them, the selection control module in row 2, column 1 includes the XOR calculation unit in row 2, column 1 and the storage unit in row 2, column 1. When g[1] equals 0, L[1] equals C[0], then the CRC initial value corresponding to the power of 1 required by the selection control module in row 2, column 1 is not the XOR result of the XOR calculation unit in row 1, column 0, but is retained as the CRC initial value C[0] corresponding to the power of 0.

[0056] Corresponding to Figure 2 The second selection processing array in the first row and first column includes a selection control module for the first row and first column, comprising an XOR calculation unit (…). Figure 2 The box marked with L[0]^L[7]^D[2]), the storage unit in the first row and second column ( Figure 2The box marked L[0] in the middle) and the selector S2[1] in the first row and first column, the XOR calculation unit in the first row and first column respectively obtains the CRC initial value L[7] corresponding to the highest bit (from the selection control module in the 7th row and 0th column), the CRC initial value L[0] corresponding to the power of 0 (from the selection control module in the 0th row and 0th column), and the information value D[2] of the second bit of the information field (the second highest bit of the information field), and performs L[0]^L[7]^D[2], and outputs the XOR result of these three values; the storage unit in the first row and first column is used to store the CRC initial value L[0] corresponding to the power of 0 (from the selection control module in the 0th row and 0th column). The selector S2[1] in the first row and first column is used to select the XOR result output of the XOR calculation unit in the first row and first column when the coefficient g[1] of the first power in the generator polynomial is not equal to 0, or to select the L[0] stored in the storage unit in the first row and first column when the coefficient g[1] of the first power in the generator polynomial is equal to 0. The selection control module in the first row and first column configures the output result of the selector in the first row and first column as the output value of the selection control module in the first row and first column, and then transmits it to the XOR calculation unit in the second row and second column and the storage unit in the second row and second column, and updates it to the CRC initial value M[1] corresponding to the first power under the trigger of the clock signal. When g[1] is equal to 0, M[1] is equal to L[0], then the CRC initial value corresponding to the first power required by the selection control module in the second row and second column is not updated by the XOR result of the XOR calculation unit in the first row and first column, but is retained as the CRC initial value L[0] corresponding to the 0 power. It should be noted that the CRC initial value C[0] corresponding to the power of 0 and the CRC initial value L[0] corresponding to the power of 0 are the CRC initial values ​​of two adjacent clock cycles, respectively.

[0057] In two embodiments, the XOR calculation unit in row 0, column j is used to XOR the initial CRC value corresponding to the highest bit with the information value of the (ij-1)th bit (counting from right to left, starting from 0 in the binary sequence) of the information field, and outputs the XOR result of the XOR calculation unit in row 0, column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. In this embodiment, the XOR calculation unit in row 0, column j is input with the initial CRC value corresponding to the highest bit and the information value of the (ij-1)th bit of the information field, respectively. Then, the information value of the (ij-1)th bit of the information field is the information value of the corresponding bit of the information field, and the initial CRC value corresponding to the highest bit is the associated value. The XOR calculation unit is an XOR function with three input terminals. When using logic gates, the first input of the XOR logic gate is used to input the initial CRC value corresponding to the highest bit, and the third input of the XOR logic gate is used to input the information value of the (ij-1)th bit of the information field. The initial CRC value corresponding to the highest bit is updated according to the clock cycle triggered by the clock information, specifically by the relevant configuration module within the CRC hardware calculation system. If j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, and j is an integer, then the selection control module in row 0 and column j is not one of the selection control modules corresponding to the coefficient of the highest power, nor is the selection processing array located (excluding) at the lowest bit of the information field. The storage unit in row 0 and column j is used to store a preset constant, which is the initial CRC value associated with the corresponding power. This preset constant can be stored before starting cyclic redundancy check, and preferably 0 to shield the influence of feedback from the previous stage (previous clock cycle). The selector in row 0, column j is used to select the XOR result of the XOR calculation unit in row 0, column j or the preset constant output stored in the storage unit in row 0, column j, based on the coefficient of the 0th power in the generator polynomial, and configure the output result of the selector in row 0, column j as the output value of the selection control module in row 0, column j; the selection control module in row 0, column j is used to transmit the output result of the selector in row 0, column j to the XOR calculation unit in row 1, column (j+1) and the storage unit in row 1, column (j+1), and update it to the CRC initial value associated with the corresponding power under the trigger of the clock signal, and update it to the CRC initial value corresponding to the 0th power under the trigger of the clock signal, as the parameter for XOR and selection in the selection control module in row 1, column (j+1) in the next clock cycle.In some embodiments, when the selector in row 0, column j selects the preset constant output stored in the storage unit in row 0, column j, it can avoid the selection control module in row 1, column (j+1) being affected by the XOR result generated in the previous clock cycle. The selection control module in row 0, column j includes an XOR calculation unit in row 0, column j, a selector in row 0, column j, and a storage unit in row 0, column j. The selection control module in row 0, column j is located in the selection processing array in column j. The selection control module in row 0, column j includes an XOR calculation unit in row 0, column j, a selector in row 0, column j, and a storage unit in row 0, column j. One input terminal of the selector in row 0, column j is connected to the output terminal of the XOR calculation unit in row 0, column j, and the other input terminal of the selector in row 0, column j is connected to the output terminal of the storage unit in row 0, column j. The gating terminal of the selector in row 0, column j is used to input the coefficients (corresponding signals) of the 0th power in the configurable generator polynomial. The selection control module in row 1, column (j+1) includes an XOR calculation unit in row 1, column (j+1) and a storage unit in row 1, column (j+1). The selection control module in row 0, column (j+1) is located in the selection processing array in column (j+1). The output of the selector in row 0, column j is connected to one input of the XOR calculation unit in row 1, column (j+1).

[0058] Combination Figure 1 and Figure 2 It can be seen that when the CRC type is CRC8, m is set to 8 and i is set to 4, and the information field is composed of 4-bit information values. The CRC hardware calculation system can process the information field. The information field is composed of D[3], D[2], D[1] and D[0] from left to right. Optionally, the CRC hardware calculation system inputs D[3] in the first clock cycle, D[2] in the second clock cycle, D[1] in the third clock cycle, and D[0] in the fourth clock cycle. Since the selection control module in row 0 and column j is not one of the selection control modules corresponding to the coefficient of the second highest power, and the selection control module in row 0 and column j is not the selection processing array corresponding to the information value D[0] located at the lowest bit of the information field, and j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, and j is an integer, the selection control module in row 0 and column j includes the selection control module in row 0 and column j, the selection control module in row 0 and column j, the selection control module in row 0 and column j, and the selection control module in row 0 and column j.

[0059] Corresponding to Figure 2 In the middle, the selection control module in row 0 and column 0 includes an XOR calculation unit in row 0 and column 0. Figure 2 The box marked with C[7]^D[3]), the storage unit in row 0 and column 0 ( Figure 2 The box marked with 0) and the selector S1[0] in row 0 and column 0, the XOR calculation unit in row 0 and column 0 respectively obtain the CRC initial value C[7] corresponding to the highest bit and the information value D[3] of the third bit of the information field (the highest bit of the information field), and perform C[7]^D[3], and output the XOR result of the two values; in some embodiments, the register REG0 is used to cache the CRC value fed back in the previous clock cycle (equivalent to the check information code output by the previous stage), and transmit it to the XOR calculation unit in row 0 and column 0 in the current clock cycle to update the CRC initial value C[7] corresponding to the highest bit. The storage unit in row 0 and column 0 is used to store the constant 0. The selector S1[0] in row 0 and column 0 is used to select the XOR result output of the XOR calculation unit in row 0 and column 0 when the coefficient g[0] of the power of 0 in the generator polynomial is not equal to 0, or to select the constant 0 stored in the storage unit in row 0 and column 0 when the coefficient g[0] of the power of 0 in the generator polynomial is equal to 0. The selection control module in row 0 and column 0 configures the output result of the selector S1[0] in row 0 and column 0 as the output value of the selection control module in row 0 and column 0, and then transmits it to the XOR calculation unit in row 1 and column 1 and the storage unit in row 1 and column 1, and updates it to the CRC initial value L[0] corresponding to the power of 0 under the trigger of the clock signal.

[0060] Similarly, corresponding to Figure 2 In the middle, the selection control module in row 0 and column 1 includes an XOR calculation unit in row 0 and column 1. Figure 2 The box marked L[7]^D[2]), the storage unit in row 0 and column 1 ( Figure 2 The box marked with 0) and the selector S2[0] in the 0th row and 1st column, the XOR calculation unit in the 0th row and 1st column respectively obtain the CRC initial value L[7] corresponding to the highest bit (from the selection control module in the 7th row and 0th column) and the information value D[2] of the second bit of the information field (the second highest bit of the information field), and perform L[7]^D[2], and output the XOR result of these two values; the storage unit in the 0th row and 1st column is used to store the constant 0. The selector S2[0] in the 0th row and 1st column is used to select the XOR result of the XOR calculation unit in the 0th row and 1st column when the coefficient g[0] of the 0th power in the generator polynomial is not equal to 0, or to select the constant 0 stored in the storage unit in the 0th row and 1st column when the coefficient g[0] of the 0th power in the generator polynomial is equal to 0. The selection control module in row 0 and column 1 configures the output result of the selector in row 0 and column 1 as the output value of the selection control module in row 0 and column 1, and then transmits it to the XOR calculation unit in row 1 and column 2 and the storage unit in row 1 and column 2, and updates it to the CRC initial value M[0] corresponding to the power of 0 under the trigger of the clock signal.

[0061] As an embodiment two, among all the selection control modules corresponding to the coefficients of the second-highest power, except for the selection control module in the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select, based on the coefficients of the corresponding power in the generator polynomial, the XOR result of the information value of the corresponding bit of the information field and the associated value, or the CRC initial value associated with the corresponding power, as the verification information code output by the current selection control module (which can also be regarded as the result of a hardware iteration, belonging to the CRC initial value), and transmit it to all selection control modules in the selection processing array corresponding to the relatively low-order information value of the information field. Here, the coefficients of the corresponding power in the generator polynomial serve as selection control signals, and the corresponding power terms and their coefficients in the generator polynomial correspond to the selection control module currently making the selection. In this embodiment, the relatively low-order information value of the information field is an information value one bit lower than the information value corresponding to the selection processing array where the selection control module outputting the verification information code is located.

[0062] As in Embodiment 2, the XOR calculation unit in the (m-1)th row and jth column is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2)th power, and the information value of the (ij-1)th bit of the information field, and outputs the XOR result of the XOR calculation unit in the (m-1)th row and 0th column, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; in this embodiment, the XOR calculation unit in the (m-1)th row and jth column is respectively input with the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2)th power, and the information value of the (ij-1)th bit of the information field, then the information value of the (ij-1)th bit of the information field (actually the binary number of the (ij)th bit from right to left) is the information value of the corresponding bit of the information field, and the CRC initial value corresponding to the highest bit and the (m-1)th power are XORed. The initial CRC value corresponding to the power is an associated value; when the XOR calculation unit is an XOR logic gate circuit with three input terminals, the first input terminal of the XOR logic gate circuit is used to input the initial CRC value corresponding to the most significant bit, the second input terminal of the XOR logic gate circuit is used to input the initial CRC value corresponding to the (m-2)th power, and the third input terminal of the XOR logic gate circuit is used to input the information value of the (ij-1)th bit of the information field; wherein, the initial CRC value corresponding to the most significant bit is updated according to the clock cycle under the triggering action of the clock information; the initial CRC value input by the selection control module of column 0 is configured before the CRC hardware calculation system starts processing the information field, and supports being updated under the triggering action of the clock signal, specifically updated according to the clock cycle to the initial CRC value corresponding to the (m-2)th power, which can be transmitted from the register. It should be noted that, corresponding to Figure 1 It can be seen that j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; the selection control module in the (m-1)th row and jth column is the selection control module other than the selection control module in the selection processing array corresponding to the least bit information value of the information field among all the selection control modules corresponding to the coefficients of the second highest power; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the (m-1)th power of the generator polynomial. The storage unit in row (m-1) and column (j) is used to store the CRC initial value corresponding to the power of (m-2), where the CRC initial value corresponding to the power of (m-2) is the CRC initial value associated with the corresponding power. The selector in row (m-1) and column (j) is used to select the XOR result of the XOR calculation unit in row (m-1) and column (j) or the CRC initial value corresponding to the power of (m-2) stored in the storage unit in row (m-1) and column (j) according to the coefficient g[m-1] of the power of (m-1) in the generator polynomial, and output the result. The output result of the selector in row (m-1) and column (j) is configured as the output value of the selection control module in row (m-1) and column (j). In this embodiment, the selection control module in row (m-1) and column (j) includes the XOR calculation unit in row (m-1) and column (j), the storage unit in row (m-1) and column (j), and the selector in row (m-1) and column (j). The selection control module in row (m-1) and column j is used to transmit the output of the selector in row (m-1) and column j to all XOR calculation units in column (j+1), and, triggered by the clock signal, updates it with the initial CRC value corresponding to the highest bit required for XOR calculation units in column (j+1) to perform XOR operations, serving as the parameter for XOR operations in all selection control modules in column (j+1) in the next clock cycle. Preferably, the selector in row (m-1) and column 0 outputs the corresponding value in the first clock cycle. Figure 1 L[m-1], the selector in the (m-1)th row and first column outputs the corresponding value in the second clock cycle. Figure 1 The selector in row (m-1) and column (i-2) of M[m-1] outputs the value in the (i-1)th clock cycle. Figure 1N[m-1]. Here, one input of the selector in row (m-1) and column (j) is connected to the output of the XOR calculation unit in row (m-1) and column (j), and the other input of the selector in row (m-1) and column (j) is connected to the output of the storage unit in row (m-1) and column (j). The gating terminal of the selector in row (m-1) and column (j) is used to input the coefficient g[m-1] of the (m-1)th power in the configurable generator polynomial. The output of the selector in row (m-1) and column (j) is connected to the inputs of all XOR calculation units in column (j+1) to obtain the initial CRC value corresponding to the highest bit. One input of the XOR calculation unit in row (m-1) and column (j+1) is connected to the output of the selector in row (m-1) and column (j), and one input of the storage unit in row (m-1) and column (j+1) is connected to the output of the selector in row (m-1) and column (j). The CRC initial value corresponding to the highest bit is the CRC initial value corresponding to the second highest power; all XOR calculation units in column (j+1) are all selection control modules in the selection processing array corresponding to the information value D[ij-1] of the relatively low bit of the information field. All XOR calculation units in column (j+1) are located in the selection processing array of column (j+1). In summary, except for the power term corresponding to the least significant bit of the information field, this embodiment only requires a clock signal of one clock cycle to control the information field to complete the parallel iterative processing (verification process) of the coefficients of the second highest power in the generator polynomial, thereby improving the efficiency of CRC calculation in the hardware circuit. On the other hand, it can flexibly configure various configuration information according to the protocol to adapt to a variety of CRC calculation needs.

[0063] Combination Figure 1 and Figure 2 As can be seen, based on Embodiment 21, when the CRC type is CRC8, m is set to 8 and i is set to 4; wherein, the information field is a 4-bit binary sequence. Since the selection control module in the (m-1)th row and jth column is the selection control module other than the selection control module in the selection processing array corresponding to the least significant bit of the information field among all selection control modules corresponding to the coefficients of the second highest power, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; therefore, the selection control module in the (m-1)th row and jth column includes the selection control module in the 7th row and 0th column, the selection control module in the 7th row and 1st column, and the selection control module in the 7th row and 2nd column.

[0064] Corresponding to Figure 2 In the middle, the selection control module in row 7, column 0 includes an XOR calculation unit in row 7, column 0. Figure 2 The box marked with C[6]^C[7]^D[3]), the storage unit in the 7th row and 0th column ( Figure 2The box marked C[6] and the selector S1[7] in the 7th row and 0th column are used to obtain the CRC initial value C[7] corresponding to the highest bit, the CRC initial value C[6] corresponding to the 6th power (from register REG7), and the information value D[3] of the 3rd bit of the information field (the highest bit of the information field), and perform C[6]^C[7]^D[3] to output the XOR result of these three values; the storage unit in the 7th row and 0th column is used to store the CRC initial value C[6] corresponding to the 6th power. The selector S1[7] in the 7th row and 0th column is used to select the XOR result of the XOR calculation unit in the 7th row and 0th column when the coefficient g[7] of the 7th power in the generator polynomial is not equal to 0, or to select the C[6] stored in the storage unit in the 7th row and 0th column when the coefficient g[7] of the 7th power in the generator polynomial is equal to 0. The selection control module in row 7, column 0 configures the output of the selector in row 7, column 0 as the output value of the selection control module in row 7, column 0, and then transmits it to all XOR calculation units in column 1, including... Figure 2 The box marked with L[7]^D[2] in the middle, Figure 2 The boxes marked with L[0]^L[7]^D[2], ..., and Figure 2 The boxes marked with L[6]^L[7]^D[2] are updated to the CRC initial value L[7] corresponding to the highest bit in the next clock cycle when triggered by the clock signal.

[0065] Corresponding to Figure 2 In the middle, the selection control module in row 7, column 1 includes an XOR calculation unit in row 7, column 1. Figure 2 The box marked with L[6]^L[7]^D[2]), the storage unit in the 7th row and 1st column ( Figure 2 The box marked L[6] and the selector S2[7] in the 7th row and 1st column, the XOR calculation unit in the 7th row and 1st column respectively obtain the CRC initial value L[7] corresponding to the highest bit (from the selection control module in the 7th row and 0th column) and the CRC initial value L[6] corresponding to the 6th power (from the selection control module in the 6th row and 0th column, corresponding to the highest bit). Figure 1The information value of the second bit of the information field, L[m-2], and the information value of the second bit of the information field, D[2] (the second highest bit of the information field), are XORed with L[6]^L[7]^D[2], and the result of the XOR of these three values ​​is output. The storage unit in the 7th row and 1st column is used to store the initial CRC value L[6] corresponding to the power of 6 (from the selection control module in the 6th row and 0th column). The selector S2[7] in the 7th row and 1st column is used to select the XOR result of the XOR calculation unit in the 7th row and 1st column when the coefficient g[7] of the power of 7 in the generator polynomial is not equal to 0, or to select the L[6] stored in the storage unit in the 7th row and 1st column when the coefficient g[7] of the power of 7 in the generator polynomial is equal to 0. The selection control module in row 7, column 1 configures the output result of the selector in row 7, column 1 to the output value of the selection control module in row 7, column 1, and then transmits it to all XOR calculation units in column 2, and updates it to the CRC initial value M corresponding to the highest bit in the next clock cycle under the trigger of the clock signal [7].

[0066] As an embodiment three, each selection control module in the selection processing array corresponding to the least significant bit of the information field is as follows: Figure 1 Each selection control module in the i-th selection processing array is used to select the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power, according to the coefficient of the corresponding power in the generator polynomial, and transmit it to the selection processing array corresponding to the information value of the highest bit of the information field. For example, it is transmitted to the register of the selection processing array corresponding to the information value of the highest bit of the information field and buffered therein. Then, the register outputs the coefficient of the corresponding power to the selection control module corresponding to the selection processing array, that is, to the selection control module in the same row of the selection processing array corresponding to the information value of the highest bit of the information field.

[0067] As in Embodiment 3, the XOR calculation unit in the p-th row and (i-1)-th column is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1)-th power, and the information value of the lowest bit of the information field, and outputs the XOR result of the XOR calculation unit in the p-th row and (i-1)-th column, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; in this embodiment, the XOR calculation unit in the p-th row and (i-1)-th column is respectively input with the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1)-th power, and the information value of the lowest bit of the information field, then the information value of the lowest bit of the information field (actually the 0th binary number from right to left) is the information value of the lowest bit of the information field. The information values ​​of the corresponding bits in the information field, the initial CRC value corresponding to the highest bit and the initial CRC value corresponding to the power of (p-1) are associated values; when the XOR calculation unit is an XOR logic gate circuit with three input terminals, the first input terminal of the XOR logic gate circuit is used to input the initial CRC value corresponding to the highest bit, the second input terminal of the XOR logic gate circuit is used to input the initial CRC value corresponding to the power of (p-1), and the third input terminal of the XOR logic gate circuit is used to input the information value of the lowest bit of the information field; wherein, the initial CRC value corresponding to the highest bit is updated according to the clock cycle under the triggering action of the clock information, specifically updated to N[m-1] output by the selection control module in the (m-1)th row and (i-2)th column. It should be noted that p is less than or equal to m-1, p is greater than 0, m is greater than 1, and i and m are positive integers; the selection control module in the pth row and (i-1)th column is the selection control module in the selection processing array corresponding to the information value of the lowest bit of the information field, excluding the selection control module in the 0th row. The storage unit in row p and column (i-1) is used to store the CRC initial value corresponding to the power of (p-1). The CRC initial value corresponding to the power of (p-1) is the CRC initial value associated with the corresponding power, which is the CRC initial value updated from the previous clock cycle and is transmitted from the selection control module in row (p-1) and column (i-2).The selector in row p, column (i-1) is used to select, based on the coefficients of the p-th power in the generator polynomial, the XOR result of the XOR calculation unit in row p, column (i-1) or the CRC initial value corresponding to the (p-1)-th power stored in the storage unit in row p, column (i-1), and configure the output of the selector in row p, column (i-1) as the output value of the selection control module in row p, column (i-1); wherein, the selection control module in row p, column (i-1) includes the XOR calculation unit in row p, column (i-1). The p-th row (i-1)-th column storage unit and the p-th row (i-1)-th column selector are located in the selection processing array corresponding to the least significant bit of the information field. The p-th row (i-1)-th column selection control module is used to transfer the output result of the p-th row (i-1)-th column selector to the p-th row (i-1)-th column selection control module through a register to form a feedback path, and can be used as a parameter for XOR operation in the p-th row (i-1)-th column selection control module in the next clock cycle. One input terminal of the p-th row (i-1)-th column selector is connected to the output terminal of the p-th row (i-1)-th column XOR calculation unit, and the other input terminal of the p-th row (i-1)-th column selector is connected to the output terminal of the p-th row (i-1)-th column storage unit. The gating terminal of the p-th row (i-1)-th column selector is used to input the coefficients of the p-th power in the generator polynomial, which can be configured. One input of the XOR calculation unit in row p, column (i-1) is connected to the output of the selector in row (i-2) of column (i-1 ...

[0068] In summary, this embodiment controls the least significant bit of the information field to perform parallel iterative processing of the coefficients of all powers in the generator polynomial except for the least significant term, thereby improving the efficiency of CRC calculation. Furthermore, it allows for flexible configuration of various settings to adapt to diverse CRC calculation needs.

[0069] Combination Figure 1 and Figure 2It can be seen that when the CRC type is CRC8, m is set to 8 and i is set to 4. The composition of the information field from left to right is D[3], D[2], D[1] and D[0]. D[3] is input into the CRC hardware calculation system first, and D[0] is input into the CRC hardware calculation system last. Since the selection control module of the p-th row and (i-1)-th column is the selection control module in the selection processing array corresponding to the lowest bit of the information value of the information field, except for the selection control module of the 0-th row, the selection control module of the p-th row and (i-1)-th column includes the selection control module of the 1st row and 3rd column, the selection control module of the 2nd row and 3rd column, the selection control module of the 3rd row and 3rd column, ..., and the selection control module of the 7th row and 3rd column. Corresponding to Figure 2 In the middle, the selection control module in the 1st row and 3rd column includes an XOR calculation unit in the 1st row and 3rd column ( Figure 2 The box marked with N[0]^D[0]^N[7]), the storage unit in the 1st row and 3rd column ( Figure 2 The box marked N[0]) and the selector S4[1] in the 1st row and 3rd column (corresponding to Figure 1The XOR calculation unit in the first row and third column of Si[1] obtains the CRC initial value N[7] corresponding to the highest bit, the CRC initial value N[0] corresponding to the power of 0, and the information value D[0] of the lowest bit of the information field, and performs N[0]^D[0]^N[7] to output the XOR result of these three values; the storage unit in the first row and third column is used to store the CRC initial value N[0] corresponding to the power of 0, wherein the CRC initial value N[0] corresponding to the power of 0 is from the selection control module in the second column of the first row; the selector S4[1] in the first row and third column is used to select the XOR result of the XOR calculation unit in the first row and third column when the coefficient g[1] of the power of 1 in the generator polynomial is not equal to 0, or to select the N[0] stored in the storage unit in the first row and third column when the coefficient g[1] of the power of 1 in the generator polynomial is equal to 0. The selection control module in row 1, column 3 configures the output result of the selector in row 1, column 3 as the output value of the selection control module in row 1, column 3, and then transmits it to register REG1 in row 1. Under the trigger of the clock signal, it is updated to the CRC initial value O corresponding to the power of 0 [1]. When the CRC initial value associated with the corresponding power received by register REG1 is 0, register REG1 cannot transmit a feedback signal to lock the register, and the selection control module in row 1, column 0 does not receive the feedback information from the selection control module in row 1, column 3. In this embodiment, register REG1 is used to cache the CRC value fed back in the previous clock cycle (equivalent to the check information code output by the previous stage), and transmits it to the XOR calculation unit in row 1, column 0 in the current clock cycle to update the CRC initial value C corresponding to the power of 0 input to the XOR calculation unit in row 1, column 0 [0].

[0070] The selection control module in row 7, column 3 includes an XOR calculation unit in row 7, column 3. Figure 2 The box marked with N[6]^D[0]^N[7]), the storage unit in the 7th row and 3rd column ( Figure 2 The box marked N[6] and the selector S4[7] in the 7th row and 3rd column (corresponding to Si[m-1]), the XOR calculation unit in the 7th row and 3rd column respectively obtain the CRC initial value N[7] corresponding to the highest bit (corresponding to Figure 1 The CRC initial value N[6] corresponding to the power of N[m-1]) and the 6th power (corresponding to the N[m-1]) Figure 1The information value of the least significant bit of the information field, N[m-2], is used to perform N[6]^D[0]^N[7], and the XOR result of these three values ​​is output. The storage unit in the 7th row and 3rd column is used to store the CRC initial value N[6] corresponding to the power of 6, wherein the CRC initial value N[6] corresponding to the power of 6 is from the selection control module in the 6th row and 2nd column. The selector S4[7] in the 7th row and 3rd column is used to select the XOR result of the XOR calculation unit in the 7th row and 3rd column when the coefficient g[7] of the power of 7 in the generator polynomial is not equal to 0, or to select the N[6] stored in the storage unit in the 7th row and 3rd column when the coefficient g[7] of the power of 7 in the generator polynomial is equal to 0. The selection control module in row 7, column 3 configures the output result of the selector in row 7, column 3 as the output value of the selection control module in row 7, column 3, and then transmits it to register REG7 in row 7. Under the trigger of the clock signal, it is updated to the CRC initial value O corresponding to the power of 6 [7]. When the CRC initial value associated with the corresponding power received by register REG7 is 0, register REG7 cannot transmit a feedback signal to lock the register, and the selection control module in row 7, column 0 does not receive the feedback information from the selection control module in row 7, column 3. In this embodiment, register REG7 is used to cache the CRC value fed back in the previous clock cycle (equivalent to the check information code output by the previous stage), and transmits it to the XOR calculation unit in row 7, column 0 in the current clock cycle to update the CRC initial value C corresponding to the power of 6 input to the XOR calculation unit in row 7, column 0 [6].

[0071] As in Embodiment 32, the XOR calculation unit in row 0, column (i-1) is used to XOR the initial CRC value corresponding to the highest bit with the information value of the lowest bit of the information field, and outputs the XOR result of the XOR calculation unit in row 0, column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit in row 0, column (i-1) is used to store a preset constant, wherein the preset constant is the initial CRC value associated with the corresponding power, which can be stored before the start of cyclic redundancy check, and the preset constant is preferably 0. When the XOR calculation unit is an XOR logic gate circuit with three input terminals, the first input terminal of the XOR logic gate circuit is used to input the initial CRC value corresponding to the highest bit, and the third input terminal of the XOR logic gate circuit is used to input the information value of the lowest bit of the information field. In this embodiment, the XOR calculation unit in row 0 and column (i-1) is input with the initial CRC value corresponding to the highest bit and the information value of the lowest bit of the information field. In the XOR calculation unit in row 0 and column (i-1), the initial CRC value corresponding to the highest bit is updated according to the clock cycle under the triggering action of the clock information. Specifically, it is updated to N[m-1] output by the selection control module in row (m-1) and column (i-2). The selector in row 0, column (i-1) is used to select the XOR result of the XOR calculation unit in row 0, column (i-1) or the value 0 stored in the storage unit in row 0, column (i-1) according to the coefficient g[0] of the 0th power in the generator polynomial, and output the value 0. The output result of the selector in row 0, column (i-1) is configured as the output value of the selection control module in row 0, column (i-1). The selection control module in row 0, column (i-1) includes the XOR calculation unit in row 0, column (i-1), the selector in row 0, column (i-1), and the storage unit in row 0, column (i-1). The selection control module in row 0, column (i-1) is the selection control module in row 0 of the selection processing array corresponding to the least significant bit of the information value of the information field. The selection control module in row 0, column (i-1) transmits the output of the selector in row 0, column (i-1) to the register in the same module to form a feedback path. This output can also be used as a parameter for XOR operation in the same module for the next clock cycle. One input of the selector in row 0, column (i-1) is connected to the output of the XOR calculation unit in row 0, column (i-1). The other input is connected to the output of the storage unit in row 0, column (i-1). The strobe of the selector in row 0, column (i-1) is used to input the coefficients of the 0th power in the configurable generator polynomial. The output of the selector in row 0, column (i-1) is connected to the data input of the register in row 0, column (i-1).

[0072] Combination Figure 1 and Figure 2 It can be seen that when the CRC type is CRC8, m is set to 8 and i is set to 4. The components of the information field from left to right are D[3], D[2], D[1] and D[0]. Since the selection control module in row 0 and column (i-1) is the selection control module in row 0 of the selection processing array corresponding to the least significant bit of the information field, the selection control module in row 0 and column (i-1) is the selection control module in row 0 and column 3. Corresponding to Figure 2 In the middle, the selection control module in row 0 and column 3 includes an XOR calculation unit in row 0 and column 3. Figure 2 The box marked with N[7]^D[0]), the storage unit in row 0 and column 3 ( Figure 2 The box marked with 0) and the selector S4[0] in the 0th row and 3rd column (corresponding to Figure 1 The XOR calculation unit in the 0th row and 3rd column of Si[0] obtains the CRC initial value N[7] corresponding to the highest bit and the information value D[0] of the lowest bit of the information field, respectively, and performs N[7]^D[0], and outputs the XOR result of the two values; the storage unit in the 0th row and 3rd column is used to store the value 0; the selector S4[0] in the 0th row and 3rd column is used to select the XOR result of the XOR calculation unit in the 1st row and 3rd column when the coefficient g[0] of the 0th power in the generator polynomial is not equal to 0, or to select the 0 stored in the storage unit in the 0th row and 3rd column when the coefficient g[0] of the 0th power in the generator polynomial is equal to 0. The selection control module in the 0th row and 3rd column configures the output result of the selector in the 0th row and 3rd column as the output value of the selection control module in the 0th row and 3rd column, and then transmits it to the register REG0 in the 0th row, and updates it to the CRC initial value O[0] corresponding to the 0th power under the trigger of the clock signal. In some embodiments, register REG0 is used to cache the CRC value fed back in the previous clock cycle (equivalent to the check information code output by the previous stage), and transmit it to the XOR calculation unit in the first row and 0 column in the current clock cycle to update the CRC initial value C[7] corresponding to the highest bit of the input XOR calculation unit in the first row and 0 column, which is also equivalent to updating the CRC initial value C[7] corresponding to the second highest power of the generator polynomial (the CRC initial value corresponding to the second highest power term of the generator polynomial), wherein the CRC initial value C[8] corresponding to the highest power term of the generator polynomial (the CRC initial value corresponding to the highest power term of the generator polynomial). When the CRC initial value associated with the corresponding power received by register REG0 is 0, register REG0 cannot transmit a feedback signal to lock the register, and the selection control module in the 0th row and 0th column does not receive the feedback information from the selection control module in the 0th row and 3rd column.

[0073] Based on the above embodiment three, in the CRC hardware calculation system, each selection control module in column 0 is connected to a corresponding register, wherein the register exists in the selection processing array in column 0 (corresponding to...). Figure 1 and Figure 2 In each row of the first selection processing array, the data input of one selection control module is connected to the data output of one register. The data input of each register is connected to the selector in the (i-1)th column of the same row, corresponding to... Figure 2 In the above, the output of selector S4[0] in row 0 and column 3 is connected to the data input D of register REG0 in row 0, the output of selector S4[1] in row 1 and column 3 is connected to the data input D of register REG1 in row 1, ..., the output of selector S4[7] in row 7 and column 3 is connected to the data input D of register REG7 in row 7, so that the selection control module corresponding to the selection processing array (first selection processing array) in column 0 and the selection control module corresponding to the selection processing array (i-1) in column (i-1) are connected through registers; wherein, the selection processing array in column 0 is the selection processing array corresponding to the highest bit of the information field, and the selection processing array in column (i-1) is the selection processing array corresponding to the lowest bit of the information field. The clock input of each register is connected to the clock signal CLK, and the clock inputs of registers from row 0 to row (m-1) are all connected to the clock signal CLK; each register is used to buffer the output result of the selector in the (i-1)th column of the same row when triggered by the clock signal, corresponding to... Figure 1 The registers in rows 0 to (m-1) respectively cache O[0] to O[m-1] and update them with the corresponding power-related CRC initial values. Then, the m registers of the first selection processing array sequentially repeat a combination of certain check codes, which can form a pseudo-random sequence with a period of m based on the XOR logic circuit unit involved in the aforementioned embodiment, corresponding to the feedback polynomial of the maximum-length pseudo-random sequence. The CRC code can be obtained after several clock cycles to complete the verification of the information field.

[0074] Based on the foregoing embodiments, the method of selecting the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power based on the coefficient of the corresponding power in the generator polynomial includes: when the CRC hardware calculation system is configured such that the coefficient of the corresponding power in the generator polynomial is 1, the selection terminal of the selector inside the corresponding selection control module receives a first level signal, the selector selects the XOR calculation unit inside the selection control module and outputs the XOR result of the XOR calculation unit, wherein the XOR result of the information value of the corresponding bit of the information field and the associated value is the XOR result of the XOR calculation unit, and the associated value includes the CRC initial value corresponding to the highest bit and / or the CRC initial value associated with the corresponding power; XOR calculation The unit is an XOR logic gate circuit with three input terminals. When the coefficient of the corresponding power in the generator polynomial is configured to be 0 in the CRC hardware calculation system, the selection terminal of the selector inside the corresponding selection control module receives the second level signal. The storage unit inside the selection control module where the selector is selected stores the CRC initial value associated with the corresponding power, which is output to the associated selection control module (the associated selection control module in the adjacent column selection processing array) other than the selection control module where the selection control module is located. However, the CRC initial value associated with the corresponding power or the CRC initial value corresponding to the highest bit received by this type of selection control module does not change, thereby shielding the XOR result fed back from the previous stage to advance the CRC calculation process.

[0075] Preferably, the second level signal is different from the first level signal. When the first level signal is configured to be high, the second level signal is configured to be low, serving as the selection control signal of the selector in the aforementioned selection control module. It is input to the selection terminal of the selector to change the switching path of the selector.

[0076] Combining embodiments one to three, this invention uses combinational logic to concatenate the XOR operations performed by two adjacent selection control modules in two adjacent clock cycles, and uses combinational logic to connect the first and last selection control modules to form a feedback loop. This enables each selection processing array to update the initial CRC value in each clock cycle, obtaining the CRC code after the corresponding clock cycle. This achieves the optimization of combinational logic circuits by combining periodic feedback and selection circuits, and also achieves the effect of running multi-bit CRC operations in a single clock cycle. Furthermore, when the code corresponding to the generator polynomial is added to the information field of the input CRC hardware calculation system (to form the CRC code through CRC operation), since the CRC hardware calculation system designed in this invention for cyclic redundancy check abandons the use of multipliers and instead uses selectors in conjunction with XOR calculation units, the multiplication operation on 0 is reduced during the cyclic redundancy check of the information field in each clock cycle. Therefore, it is not necessary to add the highest power of zeros (the highest power of the polynomial corresponding to the CRC code) to the corresponding bit information value of the information field, thus consuming fewer hardware resources.

[0077] In a combination of embodiments one through three, the CRC hardware calculation system configures the coefficients of the corresponding powers in the generator polynomial of the specified CRC (excluding the highest power term) as selection control signals. These signals are input to the selectors of the corresponding rows and columns in the selection control module. This allows each selection control module to select, within the current clock cycle, the XOR calculation result of the information value of the corresponding bit in the information field and the associated value, or the initial CRC value associated with the corresponding power, based on the coefficients of the corresponding powers in the generator polynomial. This result is then transmitted to the selection control module corresponding to the lower bit of the information field in a selection processing array. This allows other selection control modules in the selection processing array to begin XOR operations on the other bits of the information field in the next clock cycle. During the verification process using the generator polynomial, the introduction of a number of zeros after the highest power term in the information field is avoided. The XOR operation can advance the CRC verification process of the information field bit by bit, reducing iterative processing of constant terms such as zeros and allowing for flexible configuration of the coefficients of each power to adapt to various CRC calculation needs.

[0078] Based on this, the present invention uses combinational logic to concatenate the XOR operations performed by two adjacent selection control modules in two adjacent clock cycles, and uses combinational logic to connect the first and last selection control modules to form a feedback loop. This can control each selection processing array to update the initial CRC value in each clock cycle, and obtain the CRC code after the corresponding clock cycle. This achieves the optimization of combinational logic circuit by combining periodic feedback and selection circuit, and also achieves the effect of running multi-bit CRC operation in a single clock cycle.

[0079] Furthermore, when the code corresponding to the generating polynomial is added to the information field of the input CRC hardware calculation system (to form a CRC code through CRC operation), since the CRC hardware calculation system for cyclic redundancy check designed in this invention abandons the use of multipliers and instead uses selectors in conjunction with XOR calculation units to reduce multiplication operations on 0, it is not necessary to add the highest power of zeros (the highest power of the polynomial corresponding to the CRC code) after the corresponding bit information value in the information field, nor is it necessary to directly use matrices to perform division operations in hardware, thus consuming less hardware resources.

[0080] Based on the foregoing embodiments, this invention provides a chip comprising a CRC hardware calculation system for cyclic redundancy check as described in the foregoing embodiments. Within the chip, the CRC hardware calculation system includes i selection processing arrays, i.e., the chip integrates i selection processing arrays; each selection processing array is configured to be controlled by the coefficients of the corresponding powers in the generator polynomial, excluding the highest power term (the coefficient of the highest power); each selection processing array includes m selection control modules, each selection control module being used to process the information value of a corresponding bit of the information field; wherein, each bit of the information field has a corresponding selection processing array in the CRC hardware calculation system, and all selection control modules within a selection processing array correspond to the same bit of the information field; in the generator polynomial, except for the coefficient corresponding to the highest power, each power-related coefficient has a corresponding selection control module in each selection processing array; equivalently, in the generator polynomial, except for the coefficient corresponding to the highest power, each power term has a corresponding selection control module in each selection processing array, such that each power-related coefficient has a corresponding selection control module in each selection processing array. In this embodiment, the CRC hardware calculation system does not process the coefficients of the highest power of the generator polynomial during cyclic redundancy check. This is equivalent to deleting the highest power term of the generator polynomial and then checking the remaining polynomial. In this embodiment, each selection control module, triggered by a clock signal, selects the XOR result of the information value of the corresponding bit in the information field and the associated value, or the CRC initial value associated with the corresponding power, based on the coefficients of the corresponding power in the generator polynomial. This result is then transmitted to an associated selection control module outside the selection processing array where the selection control module is located. Thus, a selection control module only transmits its selection output result to the selection control modules in other selection processing arrays. Specifically, this corresponds to... Figure 1The selection control modules in other columns then receive the corresponding selection output results. In the next clock cycle, the selection control modules repeatedly execute the aforementioned XOR operation and selection operation. After several clock cycles, all selection control modules in the selection processing array of the (i-1)th column output the check code in parallel. The coefficients of the corresponding powers in the generator polynomial are configured as selection control signals in the selection control modules. These signals are used to select the circuit that generates the XOR result of the information value of the corresponding bit in the information field and the associated value, or the circuit that stores the CRC initial value associated with the corresponding power, and connect it to the selection processing array of other columns. In some embodiments, in response to the clock signal, a selection control module, under the selection of the coefficients of the corresponding powers in the generator polynomial, transmits the XOR result of the information value of the corresponding bit in the information field and the associated value, or the CRC initial value associated with the corresponding power, to the selection control module in the next clock cycle that processes the information value of the relevant bit in the information field. This achieves the iterative processing required during the execution of cyclic redundancy check, so as to obtain the iterative results corresponding to each power except for the highest power.

[0081] Based on the aforementioned embodiments, the CRC hardware computing system includes m x i selection control modules. All selection control modules are arranged in an m x i column configuration, resulting in an i-column selection processing array. Each column of the selection processing array is a selection processing array, and each selection processing array contains m rows of selection control modules. Each row of selection control modules in a selection processing array is a selection control module, and each row of selection control modules in the CRC hardware computing system contains i selection control modules. Each selection control module includes an XOR calculation unit, a storage unit, and a selector, such that the XOR calculation unit, storage unit, and selector are all arranged in an m x i column configuration in the CRC hardware computing system. Figure 1In this configuration, the row and column numbers of the XOR calculation unit, storage unit, and selector are all counted starting from 0. In some embodiments, the selection control module is also connected to a register, which is used to cache the CRC initial value or the result of the selected output of the associated selector transmitted by other selection control modules in the previous clock cycle (the iteration result in the cyclic redundancy check process). Optionally, the generator polynomial and the information field are the code values ​​output by the m selection control modules of the selection processing array after parallel processing for i clock cycles. The chip is designed to: configure the coefficients of the corresponding powers in the generator polynomial of the specified CRC (excluding the highest power term) as selection control signals; then, each selection control module, within the current clock cycle, selects the XOR result of the information value of the corresponding bit in the information field and the associated value, or the initial CRC value associated with the corresponding power, based on the coefficients of the corresponding powers in the generator polynomial, and transmits it to the selection control module corresponding to the lower bit of the information field in a selection processing array. This allows the selection control modules in other selection processing arrays to perform XOR operations on the information values ​​of other bits in the information field for the next clock cycle, avoiding the introduction of the highest power term's number of zeros after the information field during the generator polynomial verification process; this not only reduces iterative processing of constant terms such as 0, but also allows for flexible configuration of the coefficients of each power to adapt to various CRC calculation needs.

[0082] It should be added that the chip can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), microcontroller, ARM (Acorn RISC Machine) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. When an external device sends communication data to the chip, the CRC hardware calculation system included in the chip uses a preset generator polynomial to check and encapsulate the communication data, thereby making the transmission of communication data more reliable. The segment of communication data received in each clock cycle is the information field.

[0083] As one embodiment of the chip, besides all selection control modules corresponding to the coefficients of the second-highest power and the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select, based on the coefficients of the corresponding power in the generator polynomial, the XOR result of the information value of the corresponding bit of the information field and the associated value, or the CRC initial value associated with the corresponding power, as the verification information code output by the current selection control module (which can also be regarded as the result of one iteration, belonging to the CRC initial value), and transmit it to the selection processing array corresponding to the relatively low-order information value of the information field, and output it to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array. Here, the coefficients of the corresponding power in the generator polynomial serve as selection control signals, and the coefficients of the corresponding power in the generator polynomial correspond to the selection control module currently making the selection. In this embodiment, the information value of the relatively low-order information field is one bit lower than the information value corresponding to the selection processing array where the selection control module outputting the verification information code is located, and the coefficients of the relatively high power are one level higher than the degree of the power term corresponding to the selection control module outputting the verification information code.

[0084] As one embodiment of this chip, among all the selection control modules corresponding to the coefficients of the second-highest power, except for the selection control module in the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select, based on the coefficients of the corresponding power in the generator polynomial, the XOR result of the information value of the corresponding bit of the information field and the associated value, or the CRC initial value associated with the corresponding power, as the verification information code output by the current selection control module (which can also be regarded as the result of one iteration, belonging to the CRC initial value), and transmit it to all selection control modules in the selection processing array corresponding to the relatively low-order information value of the information field. Here, the coefficients of the corresponding power in the generator polynomial serve as selection control signals, and the corresponding power terms and their coefficients in the generator polynomial correspond to the selection control module currently making the selection. In this embodiment, the relatively low-order information value of the information field is an information value one bit lower than the information value corresponding to the selection processing array where the selection control module outputting the verification information code is located.

[0085] As one embodiment of this chip, each selection control module in the selection processing array corresponding to the least significant bit of the information field is as follows: Figure 1Each selection control module in the i-th selection processing array is used to select the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power, according to the coefficient of the corresponding power in the generator polynomial, and transmit it to the selection processing array corresponding to the information value of the highest bit of the information field. For example, it is transmitted to the register of the selection processing array corresponding to the information value of the highest bit of the information field and buffered therein. Then, the register outputs the coefficient of the corresponding power to the selection control module corresponding to the selection processing array, that is, to the selection control module in the same row of the selection processing array corresponding to the information value of the highest bit of the information field.

[0086] Based on the above embodiments, in the chip, each selection control module in column 0 is connected to a corresponding register, wherein the register exists in the selection processing array in column 0 (corresponding to...). Figure 1 and Figure 2 In each row of the first selection processing array, the data input of one selection control module is connected to the data output of one register. The data input of each register is connected to the selector in the (i-1)th column of the same row, corresponding to... Figure 2 In the above, the output of selector S4[0] in row 0 and column 3 is connected to the data input D of register REG0 in row 0, the output of selector S4[1] in row 1 and column 3 is connected to the data input D of register REG1 in row 1, ..., the output of selector S4[7] in row 7 and column 3 is connected to the data input D of register REG7 in row 7, so that the selection control module corresponding to the selection processing array (first selection processing array) in column 0 and the selection control module corresponding to the selection processing array (i-1) in column (i-1) are connected through registers; the clock terminal of each register is connected to the clock signal CLK, and the clock terminals of the registers from row 0 to row (m-1) are connected to the clock signal CLK; each register is used to buffer the output result of the selector in column (i-1) of the same row under the trigger of the clock signal, corresponding to Figure 1The registers in rows 0 to (m-1) cache O[0] to O[m-1] respectively and update them to the CRC initial values ​​associated with the corresponding powers. Then, the m registers of the first selection processing array repeatedly produce a combination of a certain check code, thereby forming a pseudo-random sequence with a period of i based on the XOR logic involved in the aforementioned embodiment, and generating a feedback polynomial of the maximum length pseudo-random sequence. After i clock cycles, the m-bit check code (CRC code) of the CRC hardware calculation system is obtained from these m registers. As the iteration result, it is configured as the verification result in some embodiments. After obtaining the verification result, the chip can directly or through peripheral devices send out the verification success information, and encapsulate the information field according to the iteration result, making the information field of the chip's external communication more reliable.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A CRC hardware calculation system, characterized in that, The CRC hardware calculation system is used to obtain configuration information and information fields, then determine the generator polynomial based on the configuration information, and then provide clock signals, coefficients of each power in the generator polynomial, and information fields to each selected processing array. The CRC hardware calculation system includes i selection processing arrays; Each selection processing array is configured to be controlled by the coefficients of the corresponding powers in the generator polynomial, excluding the highest power term; each selection processing array includes m selection control modules, each selection control module being used to input the information value of the corresponding bit of the information field; wherein, each information value of the information field has a corresponding selection processing array in the CRC hardware calculation system; in the generator polynomial, excluding the coefficient of the highest power term, each power term has a corresponding selection control module in each selection processing array; Each selection control module is used, triggered by a clock signal, to select, based on the coefficient of the corresponding power in the generator polynomial, the XOR result of the information value of the corresponding bit in the information field and the associated value or the CRC initial value associated with the corresponding power, and transmit it to the associated selection control module other than the selection processing array where the selection control module is located. Wherein, m is configured to be equal to the number of bits of the initial CRC value, and m is equal to the degree of the highest-degree term in the generator polynomial; i is configured to be the number of bits of the information field, which is a binary sequence input to the CRC hardware calculation system within one clock cycle; In addition to all selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, transmit it to the selection processing array corresponding to the relatively low-order information value of the information field, and output it to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array. The XOR calculation unit in row p and column j is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the power of (p-1), and the information value of the (ij-1)th bit of the information field, and output the XOR result of the XOR calculation unit in row p and column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. The storage unit in row p and column j is used to store the CRC initial value corresponding to the power of (p-1), where the CRC initial value corresponding to the power of (p-1) is the CRC initial value associated with the corresponding power. The selector in row p and column j is used to select the XOR result of the XOR calculation unit in row p and column j or the CRC initial value corresponding to the power of (p-1) stored in the storage unit in row p and column j according to the coefficient of the power of p in the generator polynomial, and to configure the output result of the selector in row p and column j as the output value of the selection control module in row p and column j; wherein, the selection control module in row p and column j includes the XOR calculation unit in row p and column j, the selector in row p and column j, and the storage unit in row p and column j, and the selection control module in row p and column j is located in the selection processing array in column j; The selection control module in row p and column j is used to transmit the output of the selector in row p and column j to the XOR calculation unit in row (p+1) and column (j+1) and the storage unit in row (p+1) and column (j+1), and to update it to the CRC initial value corresponding to the power of p under the trigger of the clock signal; wherein, the selection control module in row (p+1) and column (j+1) includes the XOR calculation unit in row (p+1) and column (j+1) and the storage unit in row (p+1) and column (j+1), and the selection control module in row (p+1) and column (j+1) is located in the selection processing array in column (j+1); Where p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i and p are all positive integers, and j is an integer; the selection control module in the p-th row and j-th column is not one of the selection control modules corresponding to the coefficients of the second highest power, and the selection control module in the p-th row and j-th column is not located in the selection processing array corresponding to the least significant information value of the information field; all selection control modules corresponding to the coefficients of the second highest power are all selection control modules corresponding to the coefficients of the second highest power of the generator polynomial; The initial CRC value input by the selection control module in column 0 is configured before the CRC hardware calculation system begins processing the information field, and can be updated under the trigger of the clock signal.

2. The CRC hardware calculation system according to claim 1, characterized in that, The CRC hardware computing system includes m x i selection control modules, all of which are arranged in an m x i column configuration, resulting in an i-column selection processing array in the CRC hardware computing system; wherein each selection processing array has m rows of selection control modules. Each selection control module includes an XOR calculation unit, a storage unit, and a selector, such that the XOR calculation unit, storage unit, and selector are arranged in an m-row i-column configuration in the CRC hardware calculation system.

3. The CRC hardware calculation system according to claim 2, characterized in that, The XOR calculation unit in row 0 and column j is used to XOR the CRC initial value corresponding to the highest bit with the information value of the (ij-1)th bit of the information field, and output the XOR result of the XOR calculation unit in row 0 and column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. The storage unit in row 0 and column j is used to store a preset constant, wherein the preset constant is the CRC initial value associated with the corresponding power; The selector in row 0, column j is used to select the XOR result of the XOR calculation unit in row 0, column j or the preset constant output stored in the storage unit in row 0, column j, based on the coefficients of the zero power in the generator polynomial, and configure the output result of the selector in row 0, column j as the output value of the selection control module in row 0, column j; wherein, the selection control module in row 0, column j includes the XOR calculation unit in row 0, column j, the selector in row 0, column j, and the storage unit in row 0, column j, and the selection control module in row 0, column j is located in the selection processing array in column j; The selection control module in row 0 and column j is used to transmit the output of the selector in row 0 and column j to the XOR calculation unit in row 1 and column (j+1) and the storage unit in row 1 and column (j+1), and update it to the CRC initial value associated with the corresponding power under the trigger of the clock signal; wherein, the selection control module in row 1 and column (j+1) includes the XOR calculation unit in row 1 and column (j+1) and the storage unit in row 1 and column (j+1), and the selection control module in row 0 and column (j+1) is located in the selection processing array in column (j+1); Where j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, and j is an integer; the selection control module in row 0 and column j is not one of the selection control modules corresponding to the coefficient of the highest power, and the selection control module in row 0 and column j is not located in the selection processing array corresponding to the lowest bit information value of the information field.

4. The CRC hardware calculation system according to claim 2, characterized in that, In all the selection control modules corresponding to the coefficients of the second highest power, except for the selection control module in the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit it to all the selection control modules in the selection processing array corresponding to the relatively low significant bit of the information field.

5. The CRC hardware calculation system according to claim 4, characterized in that, The XOR calculation unit in the (m-1)th row and jth column is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2)th power, and the information value of the (ij-1)th bit of the information field, and outputs the XOR result of the XOR calculation unit in the (m-1)th row and 0th column, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. The storage unit in the (m-1)th row and jth column is used to store the CRC initial value corresponding to the (m-2)th power, where the CRC initial value corresponding to the (m-2)th power is the CRC initial value associated with the corresponding power. The selector in row (m-1) and column (j) is used to select the XOR result of the XOR calculation unit in row (m-1) and column (j) or the CRC initial value corresponding to the power of (m-2) stored in the storage unit in row (m-1) and column (j) based on the coefficients of the power of (m-1) in the generator polynomial, and to configure the output result of the selector in row (m-1) and column (j) as the output value of the selection control module in row (m-1) and column (j); wherein, the selection control module in row (m-1) and column (j) includes the XOR calculation unit in row (m-1) and column (j), the storage unit in row (m-1) and column (j), and the selector in row (m-1) and column (j); The selection control module in row (m-1) and column j is used to transmit the output of the selector in row (m-1) and column j to all XOR calculation units in column (j+1), and update it to the CRC initial value corresponding to the highest bit required for XOR calculation units in column (j+1) to perform XOR operations under the trigger of the clock signal; wherein, all XOR calculation units in column (j+1) are all selection control modules in the selection processing array corresponding to the information value of the relatively low bit of the information field; Where j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; the selection control module in the (m-1)th row and jth column is the selection control module other than the selection control module in the selection processing array corresponding to the least significant bit of the information field among all the selection control modules corresponding to the coefficients of the second highest power; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the second highest power of the generator polynomial.

6. The CRC hardware calculation system according to claim 2, characterized in that, Each selection control module in the selection processing array corresponding to the least significant bit of the information field is used to select the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power, based on the coefficient of the corresponding power in the generator polynomial, and transmit it to the selection processing array corresponding to the most significant bit of the information field, and output it to the selection control module corresponding to the coefficient of the corresponding power in the selection processing array.

7. The CRC hardware calculation system according to claim 6, characterized in that, The XOR calculation unit in the p-th row and (i-1)-th column is used to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1)-th power, and the information value of the lowest bit of the information field, and output the XOR result of the XOR calculation unit in the p-th row and (i-1)-th column, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. The storage unit in row p and column (i-1) is used to store the CRC initial value corresponding to the power of (p-1), where the CRC initial value corresponding to the power of (p-1) is the CRC initial value associated with the corresponding power. The selector in row p, column (i-1) is used to select the XOR result of the XOR calculation unit in row p, column (i-1) or the CRC initial value corresponding to the power of (p-1) stored in the storage unit in row p, column (i-1) based on the coefficients of the power p in the generator polynomial. The selector's output is then configured as the output value of the selection control module in row p, column (i-1). The selection control module in row p, column (i-1) includes the XOR calculation unit in row p, column (i-1), the storage unit in row p, column (i-1), and the selector in row p, column (i-1). The selection control module in row p, column (i-1) is located in the selection processing array corresponding to the least significant bit of the information field. Where p is less than or equal to m-1, p is greater than 0, m is greater than 1, and i and m are both positive integers; the selection control module in the p-th row and (i-1)-th column is the selection control module in the selection processing array corresponding to the least bit information value of the information field, excluding the selection control module in the 0-th row.

8. The CRC hardware calculation system according to claim 6, characterized in that, The XOR calculation unit in row 0 and column (i-1) is used to XOR the initial CRC value corresponding to the highest bit with the information value of the lowest bit of the information field, and output the XOR result of the XOR calculation unit in row 0 and column j, which is determined as the XOR result of the information value of the corresponding bit of the information field and the associated value. The storage unit in row 0 and column (i-1) is used to store a preset constant, wherein the preset constant is the CRC initial value associated with the corresponding power; The selector in row 0, column (i-1) is used to select the XOR result of the XOR calculation unit in row 0, column (i-1) or the preset constant output stored in the storage unit in row 0, column (i-1) according to the coefficient of the 0th power in the generator polynomial, and configure the output result of the selector in row 0, column (i-1) as the output value of the selection control module in row 0, column (i-1); wherein, the selection control module in row 0, column (i-1) includes the XOR calculation unit in row 0, column (i-1), the selector in row 0, column (i-1), and the storage unit in row 0, column (i-1). The selection control module in row 0, column (i-1) is the selection control module in row 0 of the selection processing array corresponding to the least significant bit of the information value of the information field.

9. The CRC hardware calculation system according to claim 6, characterized in that, Each selection control module in column 0 is connected to a corresponding register. The data input of one selection control module is connected to the data output of one register. The data input of each register is connected to the selector in the (i-1)th column of the same row. This allows the selection control modules corresponding to the selection processing array in column 0 and the selection processing array in column (i-1) with coefficients of the same power to be connected via registers. The selection processing array in column 0 is the selection processing array corresponding to the highest bit of the information field, and the selection processing array in column (i-1) is the selection processing array corresponding to the lowest bit of the information field. The clock input of each register is connected to the clock signal, and each register is used to buffer the output result of the selector in the (i-1)th column of the same row when triggered by the clock signal.

10. The CRC hardware computing system according to any one of claims 2 to 9, characterized in that, The method of selecting the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power based on the coefficient of the corresponding power in the generator polynomial includes: When the coefficient of the corresponding power in the generator polynomial is configured to be 1 in the CRC hardware calculation system, the selection terminal of the selector inside the corresponding selection control module receives the first level signal. The selector selects the XOR calculation unit inside the selection control module and outputs the XOR result of the XOR calculation unit. The XOR result of the information value of the corresponding bit of the information field and the associated value is the XOR result of the XOR calculation unit. The associated value includes the CRC initial value corresponding to the highest bit and / or the CRC initial value associated with the corresponding power. The XOR calculation unit is an XOR logic gate circuit with three input terminals. The data stored in the storage unit can be refreshed. When the coefficient of the corresponding power in the generator polynomial is configured to be 0 in the CRC hardware calculation system, the selection terminal of the selector inside the corresponding selection control module receives the second level signal, and the storage unit inside the selection control module where the selector is selected outputs the CRC initial value associated with the corresponding power, wherein the second level signal is different from the first level signal.

11. The CRC hardware calculation system according to claim 10, characterized in that, The configuration information includes the CRC type, the coefficients of the generator polynomial, and the initial CRC value; The CRC hardware calculation system uses the following methods to determine the generator polynomial based on the configuration information: Based on the CRC type and the coefficients of each term in the generator polynomial, determine the type of the generator polynomial and the coefficients of each power in the generator polynomial; The initial CRC value is set according to the communication protocol followed by the information field and can be updated before the CRC hardware calculation system starts processing the information field. The initial CRC value corresponding to the highest bit is the initial CRC value corresponding to the second highest power of the generator polynomial.

12. The CRC hardware calculation system according to claim 11, characterized in that, When the CRC type is CRC8, m is set to 8, i is set to 4, and the information field consists of 4-bit information values.

13. A chip, characterized in that, Includes the CRC hardware calculation system as described in any one of claims 1 to 12.

14. The chip according to claim 13, characterized in that, The CRC hardware computing system includes m x i selection control modules, all of which are arranged in an m x i column configuration, resulting in an i-column selection processing array in the CRC hardware computing system; wherein each selection processing array has m rows of selection control modules. Each selection control module includes an XOR calculation unit, a storage unit, and a selector, such that the XOR calculation unit, storage unit, and selector are arranged in an m-row i-column configuration in the CRC hardware calculation system.

15. The chip according to claim 13, characterized in that, Apart from all the selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, transmit it to the selection processing array corresponding to the relatively low-order information value of the information field, and output it to the selection control module corresponding to the coefficient of the relatively high power in the selection processing array.

16. The chip according to claim 13, characterized in that, In all the selection control modules corresponding to the coefficients of the second highest power, except for the selection control module in the selection processing array corresponding to the least significant bit of the information field, each selection control module is used to select the XOR result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit it to all the selection control modules in the selection processing array corresponding to the relatively low significant bit of the information field.

17. The chip according to claim 13, characterized in that, Each selection control module in the selection processing array corresponding to the least significant bit of the information field is used to select the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power, based on the coefficient of the corresponding power in the generator polynomial, and transmit it to the selection processing array corresponding to the most significant bit of the information field, and output it to the selection control module corresponding to the coefficient of the corresponding power in the selection processing array.

18. The chip according to claim 14, characterized in that, Each selection control module in column 0 is connected to a corresponding register. The data input of one selection control module is connected to the data output of one register. The data input of each register is connected to the selector in the (i-1)th column of the same row. This allows the selection control modules corresponding to the selection processing array in column 0 and the selection processing array in column (i-1) with coefficients of the same power to be connected via registers. The selection processing array in column 0 is the selection processing array corresponding to the highest bit of the information field, and the selection processing array in column (i-1) is the selection processing array corresponding to the lowest bit of the information field. The clock input of each register is connected to the clock signal, and each register is used to buffer the output result of the selector in the (i-1)th column of the same row when triggered by the clock signal.

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