Method for using synchronization resources

Abstract

The present invention provides a method for using synchronization resources for multiple parallel thread bundles, including: parsing these thread bundles to obtain all instructions related to synchronization resources included in each thread bundle, each instruction having a synchronization resource identifier; dividing all instructions included in each thread bundle according to the instruction category of each instruction to obtain one or more vertices, each vertex including at least one instruction, and the instruction category including consumer instructions and producer instructions; establishing paths between all vertices included in the thread bundle to obtain a first directed acyclic graph; deleting redundant arcs between multiple vertices in the first directed acyclic graph to obtain a second directed acyclic graph; grouping the synchronization resources used by all vertices included in the second directed acyclic graph to obtain a third directed acyclic graph; establishing a topologically sorted sequence of all vertices in the first directed acyclic graph; and mapping logical synchronization resources to physical synchronization resources based on the topologically sorted sequence and the third directed acyclic graph.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for using synchronization resources, and particularly relates to a method for using synchronization resources for parallel thread bundles. BACKGROUND

[0002] The producer-consumer problem is a synchronization problem in parallel programs, which describes that multiple parallel thread bundles can communicate through instructions of synchronization resources. The producer instruction and the consumer instruction are two different instruction categories of the synchronization resources. For data dependency, the producer prepares data for the consumer, i.e. the producer produces data to write into memory, and the consumer consumes data in the memory; for memory (including various caches) dependency, the producer vacates memory for the consumer, i.e. the producer consumes data in the memory, and the consumer produces data to write into memory. From the perspective of memory dependency and from the perspective of data dependency, the roles are reversed. If the producer does not prepare data or memory, the consumer cannot start consuming data or memory. The allocation of the synchronization resources occurs in the generation phase of the parallel program, not in the execution phase of the parallel program. It is difficult to know the execution order of the parallel program in the generation phase, resulting in not knowing which allocated synchronization resources have been recycled when allocating the synchronization resources next time. Accordingly, due to the limitation of the synchronization resources, if the synchronization resources cannot be recycled in time, the synchronization resources cannot be fully utilized. Moreover, in the parallel program, the allocation of the synchronization resources is prone to conflict. Therefore, how to fully utilize all the synchronization resources, so that the allocation of the synchronization resources does not conflict, is not idle, and can be recycled in time is a problem to be solved at present. SUMMARY

[0003] The present invention is directed to a method for using synchronization resources, which can fully utilize the synchronization resources and solve the problem of conflict in the allocation of the synchronization resources in the parallel program.

[0004] The method for using synchronization resources of the present application is used for parallel multiple thread bundles, and includes the following steps: parsing the multiple thread bundles to obtain all instructions related to synchronization resources included in each thread bundle; dividing all instructions included in each thread bundle to obtain one or more vertices according to the instruction category of each instruction; establishing paths between all vertices included in the multiple thread bundles to obtain a first directed acyclic graph; deleting redundant arcs between multiple vertices in the first directed acyclic graph to obtain a second directed acyclic graph, wherein the arcs are used to connect two vertices in the all vertices, and each path is a set of one or more arcs; grouping synchronization resources used by all vertices included in the second directed acyclic graph to obtain a third directed acyclic graph; establishing a topological sorting sequence of the all vertices in the first directed acyclic graph; and mapping logical synchronization resources to physical synchronization resources based on the topological sorting sequence and the third directed acyclic graph.

[0005] In an embodiment according to the present application, each instruction has a synchronization resource identifier, each vertex includes at least one instruction, and the instruction category includes consumer instructions and producer instructions. The step of establishing paths between all vertices included in the multiple thread bundles to obtain the first directed acyclic graph includes: establishing intra-thread bundle arcs between two vertices belonging to the same thread bundle based on instruction execution order; and establishing inter-thread bundle arcs between two vertices belonging to different thread bundles based on the instruction category and the synchronization resource identifier, wherein the arcs include the intra-thread bundle arcs and the inter-thread bundle arcs.

[0006] In an embodiment according to the present application, the intra-thread bundle arcs are used to connect adjacent two vertices belonging to the same thread bundle and are directed from a vertex with earlier execution order to a vertex with later execution order, and the inter-thread bundle paths are used to connect two vertices belonging to different thread bundles with the same synchronization resource identifier and are directed from a producer instruction to a consumer instruction.

[0007] In an embodiment according to the present application, the step of dividing all instructions included in each thread bundle to obtain the vertices according to the instruction category of each instruction includes: in each thread bundle, dividing all instructions from a consumer instruction to the next consumer instruction to the same vertex. If the initial instruction in each thread bundle belongs to a producer instruction, all instructions from the initial instruction to the next consumer instruction are divided to the same vertex.

[0008] In an embodiment according to the present application, before deleting the redundant arcs between the plurality of vertices in the first directed acyclic graph, further comprising: determining whether each of the arcs in the first directed acyclic graph is a redundant arc. An arc is determined to be a redundant arc if there is another path formed by a plurality of arcs between the head and tail of the arc.

[0009] In an embodiment according to the present application, after determining that the arc is a redundant arc, further comprising: if the producer instruction on the redundant arc is a first producer instruction, and the producer instruction corresponding to the first arc on the other path formed by a plurality of arcs between the head and tail of the redundant arc is a second producer instruction, determining whether the execution order of the first producer instruction is before the execution order of the second producer instruction; and if the execution order of the first producer instruction is before the execution order of the second producer instruction, deleting the first producer instruction on the redundant arc and its corresponding consumer instructions and the redundant arc in the first directed acyclic graph.

[0010] In an embodiment according to the present application, grouping the synchronization resources used by the all vertices included in the second directed acyclic graph to obtain the third directed acyclic graph comprises: selecting, from the all vertices included in the second directed acyclic graph, vertices with in-degree of 0, vertices pointed by vertices with out-degree greater than or equal to 2, and vertices with in-degree greater than or equal to 2 as determination targets; and abstracting a set of synchronization resources used by all vertices from a determination target to a next determination target (excluding the next determination target) into a vertex of the third directed acyclic graph.

[0011] In an embodiment according to the present application, mapping the logical synchronization resources to the physical synchronization resources based on the topological sorting sequence and the third directed acyclic graph comprises: mapping the logical synchronization resources of all vertices in the first directed acyclic graph to the physical synchronization resources according to the topological sorting sequence one by one based on a mapping rule, the mapping rule comprising: any vertex in the third directed acyclic graph can reuse the physical synchronization resources recycled by the predecessor vertices of the any vertex and the any vertex; and the physical synchronization resources used by vertices on different paths in the third directed acyclic graph are in mutual exclusion; wherein the predecessor vertices are vertices located before the any vertex on the same path.

[0012] An electronic device for synchronization resources according to the present application comprises: a memory including one or more code segments; and a processor coupled to the memory and configured to execute the code segments to implement the method of using the synchronization resources.

[0013] Based on the above, the present disclosure utilizes the instruction execution order, instruction category, and synchronization resource identifier to generate a connection relationship for the instructions included in different thread bundles, and then determines the utilization of the synchronization resource based on the connection relationship. Accordingly, the synchronization resource can be fully utilized and the problem of synchronization resource allocation conflict in a parallel program can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a block diagram of an electronic device for a synchronization resource according to an embodiment of the present disclosure.

[0015] Figure 2A is a flowchart of a method for using a synchronization resource according to an embodiment of the present disclosure.

[0016] Figure 2B is a flowchart of a method for establishing an arc according to an embodiment of the present disclosure.

[0017] Figure 3 is a schematic diagram of generating vertices of two thread bundles according to a first embodiment of the present disclosure.

[0018] Figure 4 is a schematic diagram of a first directed acyclic graph according to a first embodiment of the present disclosure.

[0019] Figure 5 is a schematic diagram of a second directed acyclic graph according to a first embodiment of the present disclosure.

[0020] Figure 6 is a schematic diagram of a third directed acyclic graph according to a first embodiment of the present disclosure.

[0021] Figures 7(a) to 7(g) is a schematic diagram of a topological sorting sequence according to a first embodiment of the present disclosure.

[0022] Figure 8 is a schematic diagram of generating vertices of multiple thread bundles according to a second embodiment of the present disclosure.

[0023] Figure 9 is a schematic diagram of a first directed acyclic graph according to a second embodiment of the present disclosure.

[0024] Figure 10 is a schematic diagram of a second directed acyclic graph according to a second embodiment of the present disclosure.

[0025] Figure 11 is a schematic diagram of a third directed acyclic graph according to a second embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0027] Figure 1 is a block diagram of an electronic device for synchronizing resources according to an embodiment of the present application. In this embodiment, the electronic device is implemented by an electronic device with computing capability. Please refer to Figure 1 , the electronic device A includes at least a processor 10 and a memory 20. The processor 10 is, for example, a central processing unit (CPU), a physics processing unit (PPU), a programmable microprocessor, an embedded control chip, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or other similar devices. The memory 20 is, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk, or other similar devices or combinations thereof. The memory unit includes one or more code segments, and each step of the method for synchronizing resources is executed by the processor 10 after the program code is installed.

[0028] Figure 2A is a flowchart of a method for synchronizing resources according to an embodiment of the present application. This embodiment is applicable to a parallel program that has multiple parallel thread bundles, and each thread bundle includes multiple parallel threads.

[0029] Please refer to Figure 2A , in step S105, the multiple thread bundles are parsed to obtain all instructions related to the synchronization resources included in each thread bundle. That is, all instructions whose instruction categories are consumer instructions or producer instructions are found by the processor 10. Each instruction has a synchronization resource identifier. The synchronization resource identifier is used to indicate the synchronization resource that the instruction wants to access. A (logical) synchronization resource has a corresponding synchronization resource identifier, and is used by a producer instruction and a consumer instruction.

[0030] Next, in step S110, one or more vertices are obtained by partitioning all instructions included in each thread bundle according to the instruction categories of the instructions. Each vertex includes at least one instruction. In one embodiment, the processor 10 partitions the vertices according to the consumer instructions. In one embodiment, all instructions from the beginning of a consumer instruction to the next consumer instruction in each thread bundle are partitioned into the same vertex. If the initial instruction is a producer instruction, all instructions from the beginning of the initial instruction to the next consumer instruction are partitioned into the same vertex. That is, each thread bundle is traversed from front to back, and all instructions from the consumer instruction or the first instruction to the next consumer instruction are partitioned into the same vertex. If all instructions after a consumer instruction in a thread bundle are producer instructions, i.e., there is no other consumer instruction, the consumer instruction and all producer instructions after the consumer instruction are partitioned into the same vertex.

[0031] Next, in step S115, paths between all vertices included in the plurality of thread bundles are established to obtain a first directed acyclic graph. The arcs include intra-thread bundle arcs between vertices in the same thread bundle and inter-thread bundle arcs between vertices in different thread bundles. An arc connects two of the vertices in the plurality of vertices. The direction of an arc is from the tail of the arc to the head of the arc, where the tail and the head are the two vertices connected by the arc. Both intra-thread bundle arcs and inter-thread bundle arcs are established based on different conditions. Step S115 is further explained below. Figure 2B Step S115 can further include step S115a and step S115b.

[0032] Figure 2B is a flowchart of a method of establishing arcs according to one embodiment of the present application. Referring to FIG. 2, in step S115a, intra-thread bundle arcs are established between two vertices belonging to the same thread bundle based on the instruction execution order. The intra-thread bundle arc connects two adjacent vertices belonging to the same thread bundle and is directed from the vertex with earlier execution order to the vertex with later execution order.

[0033] In step S115b, inter-thread bundle arcs are established between two vertices belonging to different thread bundles based on the instruction categories and the synchronization resource identifiers. The inter-thread bundle arc connects two vertices belonging to different thread bundles with the same synchronization resource identifier and is directed from the producer instruction to the consumer instruction. The execution order of step S115a and step S115b is not limited.

[0034] Returning to FIG. 1, Figure 2AAfter the paths between all the vertices are established, in step S120, redundant arcs between the vertices in the first directed acyclic graph are deleted to obtain a second directed acyclic graph. That is, in the first directed acyclic graph, starting from the initial vertex with an in-degree of 0, for each arc that connects two vertices, it is determined whether there is another path formed by multiple arcs between the head and tail of each arc. If there is no other path formed by multiple arcs between the head and tail of each arc, the arc is retained. If there is another path formed by multiple arcs between the head and tail of the arc, the arc is determined to be a redundant arc and is deleted. For example, assuming that an arc Rl is from vertex A to vertex B, if there is a path formed by both "arc R2 from vertex A to vertex C" and "arc R3 from vertex C to vertex B" between vertex A and vertex B, the arc Rl is determined to be a redundant arc and is deleted.

[0035] After the redundant arcs between the vertices are deleted, the second directed acyclic graph is obtained. Next, in step S125, all the vertices included in the second directed acyclic graph are grouped to obtain a third directed acyclic graph. Among the vertices included in the second directed acyclic graph, the vertices with an in-degree of 0, the vertices pointed to by the vertices with an out-degree greater than or equal to 2, and the vertices with an in-degree greater than or equal to 2 are taken as the determination targets, and the traversal is started for each determination target until the traversal reaches the next determination target, at which point the traversal of the determination target is stopped. That is, the set of synchronization resources used by all the vertices from each determination target to the next determination target (excluding the next determination target) is abstracted into one vertex of the third directed acyclic graph. The paths between the vertices of the third directed acyclic graph follow the paths of the second directed acyclic graph, except that in the case where one vertex of the third directed acyclic graph includes multiple vertices of the second directed acyclic graph, the paths between the multiple vertices of the second directed acyclic graph are deleted. (For details, refer to the subsequent description of step S125.) Figure 6 、 Figure 11 ).

[0036] After that, in step S130, a topological order sequence of all the vertices in the first directed acyclic graph is established. For example, (1) a vertex with an in-degree of 0 is selected from the first directed acyclic graph and is output to the topological order sequence. After that, (2) the vertex with an in-degree of 0 and all the arcs starting from it are deleted from the first directed acyclic graph. When there are multiple vertices with an in-degree of 0, one of them can be arbitrarily selected and output to the topological order sequence, and the other vertices can be selected and output to the topological order sequence, respectively. Steps (1) and (2) are repeated until the current first directed acyclic graph is empty or there is no vertex with an in-degree of 0.

[0037] Finally, in step S135, the logical synchronization resources are mapped to the physical synchronization resources based on the topological sorting sequence and the third directed acyclic graph. Specifically, the processor 10 maps the logical synchronization resources of all vertices in the first directed acyclic graph to the physical synchronization resources one by one according to the topological sorting sequence based on a mapping rule, the mapping rule including that any vertex in the third directed acyclic graph can reuse the physical synchronization resources recycled by the predecessor vertices of the any vertex and the any vertex, and the physical synchronization resources used between the vertices on different paths of the third directed acyclic graph are in a mutual exclusion relationship; wherein the predecessor vertex is a vertex located before the any vertex on the same path. The mutual exclusion relationship means that the vertices on different paths do not use the same physical synchronization resource.

[0038] The third directed acyclic graph includes the pointing relationship between the producer instructions and the consumer instructions, so that the pairing relationship between the producer instructions and the corresponding consumer instructions in different thread bundles can be clearly known, and it can be further judged whether the producer instructions and the consumer instructions having the connection relationship will conflict to decide whether to be allocated to the same physical synchronization resource. The mutual exclusion relationship between the vertices on different paths can avoid the problem that the parallel thread bundles simultaneously compete for the same physical synchronization resource.

[0039] A application example is shown below to further illustrate the use method of the synchronization resource.

[0040] Figure 3 is a schematic diagram of generating vertices of two thread bundles according to the first embodiment of the application. Figure 4 is a schematic diagram of the first directed acyclic graph according to the first embodiment of the application. Figure 5 is a schematic diagram of the second directed acyclic graph according to the first embodiment of the application. Figure 6 is a schematic diagram of the third directed acyclic graph according to the first embodiment of the application.

[0041] Figure 3 Two thread bundles are shown, which are numbered as 2 and 3 (hereinafter referred to as thread bundle 2 and thread bundle 3) and each include a plurality of instructions related to synchronization resources. The thread bundle 2 includes instructions p1, p2, c3, p5, c4, p6, and the synchronization resource identifiers thereof are 1, 2, 3, 5, 4, and 6 respectively. The thread bundle 3 includes instructions c1, p3, c2, p4, c5, c6, and the synchronization resource identifiers thereof are 1, 3, 2, 4, 5, and 6 respectively. The "p" indicates that the instruction belongs to the producer instruction, and the "c" indicates that the instruction belongs to the consumer instruction. In each thread bundle, all instructions from the front to the back, starting from the consumer instruction or the first instruction to the next consumer instruction, are divided into the same vertex.

[0042] In thread bundle 2, first, all instructions from initial instruction pi (first instruction) to instruction c3 (consumer instruction) before next (i.e., instruction pi and instruction p2) are divided to vertex C2_0. Then, all instructions from instruction c3 (consumer instruction) to instruction c4 before (i.e., instruction c3 and instruction p5) are divided to vertex C2_1. After that, since there is no other consumer instruction after instruction c4, instruction c4 and its subsequent remaining instruction p6 are divided to vertex C2_2. In this way, instructions of thread bundle 3 are divided into vertices C3_0, C3_1, C3_2, C3_3. Then, paths between vertices are established.

[0043] Referring to Figure 3 and Figure 4 simultaneously, for vertices C2_0 to C2_2 belonging to thread bundle 2, based on instruction execution order, an arc (intra-bundle arc) R11, R12 is established between two adjacent vertices (vertex C2_0 and vertex C2_1; vertex C2_1 and vertex C2_2) from the vertex in front of execution order pointing to the vertex behind execution order. In this way, for vertices C3_0 to C3_3 belonging to thread bundle 3, arcs (intra-bundle arcs) R21, R22, R23 are established.

[0044] And, for vertices between different thread bundles, two instructions in vertices with the same synchronization resource identifier and belonging to different thread bundles are found, and an arc (inter-bundle arc) R31 to R36 is established from the vertex including the producer instruction pointing to the vertex including the consumer instruction. In this way, the first directed acyclic graph 400 is obtained.

[0045] After that, referring to Figure 4 and Figure 5 simultaneously, deletion of redundant arcs is performed. As for arc R11, since there is still a path formed by multiple arcs (R31, R33) between vertex C2_0 (head vertex) and vertex C2_1 (tail vertex), arc R11 is determined to be a redundant arc, and arc R11 is deleted. As for arc R12, since there is only arc R12 between vertex C2_1 (arc tail) and vertex C2_2 (arc head) and there is no other path formed by multiple arcs, arc R12 is kept. In this way, the second directed acyclic graph 500 as shown in Figure 5 is obtained.

[0046] In addition, in an embodiment, in the first directed acyclic graph, the producer instruction on the redundant arc is a first producer instruction, the producer instruction corresponding to the first arc of the other path formed by multiple arcs between the head and tail of the redundant arc is a second producer instruction, and whether the execution order of the first producer instruction is before the execution order of the second producer instruction is determined in the case of the first producer instruction and the second producer instruction. In the case where the execution order of the first producer instruction is before the execution order of the second producer instruction, the first producer instruction on the redundant arc and the corresponding consumer instruction and the redundant arc are deleted in the first directed acyclic graph 400.

[0047] For example, the first producer instruction corresponding to the redundant arc is denoted as instruction p_x, and the second producer instruction corresponding to the first path of the other path except the arc is denoted as instruction p_y (the instruction p_x and the instruction p_y are in the same thread bundle). If the instruction p_x is in front of the instruction p_y, the redundant arc and the instruction p_x corresponding to the redundant arc and the corresponding consumer instruction are deleted. If the instruction p_x is not in front of the instruction p_y, the redundant arc and the instruction p_x corresponding to the redundant arc and the corresponding consumer instruction are not deleted.

[0048] After the redundant arc is deleted, all vertices included in the second directed acyclic graph 500 are grouped. Referring to FIG. 5 and FIG. 6 simultaneously, Figure 5 and Figure 6 In the second directed acyclic graph 500, the vertex with an in-degree of 0 (vertex C2_0), the vertex pointed to by the vertex with an out-degree greater than or equal to 2 (vertex C2_1, vertex C3_1, vertex C2_2, vertex C3_2), and the vertex with an in-degree greater than or equal to 2 (vertex C3_3) are taken as the determination target. Based on the connection relationship of the second directed acyclic graph 500, traversal is started for each determination target, and the traversed vertex is abstracted into a vertex of the third directed acyclic graph until the next determination target is traversed, and the traversal of the determination target is stopped.

[0049] In terms of the traversal starting from the judgment target vertex C2_0 to the next judgment target (vertex C3_1), the traversed vertices (i.e., vertex C2_0 and vertex C3_0) are saved to the vertex (vertex Group_C2_0) of the third DAG corresponding thereto. In terms of the judgment target vertex C2_1, since its subsequent vertex is also a judgment target, the traversal of this judgment target is stopped, and the vertex Group_C2_1 of the third DAG corresponding thereto only includes this vertex. The other judgment targets, i.e., vertex C3_1, vertex C2_2, vertex C3_2, and vertex C3_3, are the same as vertex C2_1. Thus, all the vertices in the second DAG 500 have been provided with the vertex of the third DAG corresponding thereto. In terms of the path of the third DAG, the path continues to follow the path between the second DAGs, but since, for example, the third DAG vertex Group_C2_0 includes multiple vertices C2_0 and C3_0 of the second DAG, the path formed by a single arc between vertex C2_0 and vertex C3_0 is deleted. Thus, the third DAG 600 is obtained. The third DAG 600 includes vertices Group_C2_0, Group_C2_1, Group_C2_2, Group_C3_1, Group_C3_2, and Group_C3_3.

[0050] Figures 7(a) to 7(g) Fig. 7(a) is a schematic diagram of the first DAG according to the first embodiment of the present application. The producer instruction on the redundant arc is the first producer instruction, the first arc on the other path formed by multiple arcs between the head and tail of the redundant arc corresponds to the second producer instruction, and in the case of the first producer instruction and the second producer instruction, it is determined whether the execution order of the first producer instruction is before the execution order of the second producer instruction. In the case where the execution order of the first producer instruction is before the execution order of the second producer instruction, the first producer instruction on the redundant arc and the corresponding consumer instruction and the redundant arc are deleted in the first DAG. In this embodiment, the first producer instruction on the redundant arc R11 is p2, the other path formed by multiple arcs between the head C2_1 and the tail C2_0 of the redundant arc is R31 and R33, and the first producer instruction on R31 and R33 is pi, i.e., the second producer instruction is pi, at this time, the execution order of the first producer instruction is after the execution order of the second producer instruction, and thus the first producer instruction and the corresponding consumer instruction and the redundant arc do not need to be deleted.

[0051] Next, a topological order sequence is established according to the first directed acyclic graph processed as above. First, the vertex C2_0 with an in-degree of 0 is selected in Fig. 7(a) and output to the order queue Q{C2_0}. Then, the vertex C2_0 and all arcs R11, R31 originating from it are deleted, as shown in Fig. 7(b). Next, the vertex C3_0 with an in-degree of 0 is selected in Fig. 7(b) and output to the order queue Q{C2_0, C3_0}. Next, the vertex C3_0 and all arcs R33, R21 originating from it are deleted, as shown in Fig. 7(c). In Fig. 7(c), there are two vertices C2_1 and C3_1 with an in-degree of 0, either of which can be selected at this time. Here, the selection of C2_1 is taken as an example. Therefore, the vertex C2_1 with an in-degree of 0 is selected in Fig. 7(c) and output to the order queue Q{C2_0, C3_0, C2_1}.

[0052] Then, the vertex C2_1 and all arcs R12, R34 originating from it are deleted, as shown in Fig. 7(d). Next, the vertex C3_1 with an in-degree of 0 is selected in Fig. 7(d) and output to the order queue Q{C2_0, C3_0, C2_1, C3_1}. Next, the vertex C3_1 and all arcs R35, R22 originating from it are deleted, as shown in Fig. 7(e). Next, the vertex C2_2 with an in-degree of 0 is selected in Fig. 7(e) and output to the order queue Q{C2_0, C3_0, C2_1, C3_1, C2_2}.

[0053] Then, the vertex C2_2 and the arc R36 originating from it are deleted, as shown in Fig. 7(f). Next, the vertex C3_2 with an in-degree of 0 is selected in Fig. 7(f) and output to the order queue Q{C2_0, C3_0, C2_1, C3_1, C2_2, C3_2}. After the vertex C3_2 and the arc R23 originating from it are deleted, the last vertex C3_3 is left, as shown in Fig. 7(g), and the final vertex C3_3 is output to the order queue Q{C2_0, C3_0, C2_1, C3_1, C2_2, C3_2, C3_3}.

[0054] Next, another application example is taken to further illustrate the method of using the synchronization resource.

[0055] Figure 8 Fig. 4 is a schematic diagram of generating a plurality of thread bundles of vertices according to the second embodiment of the present application. Figure 9 Fig. 5 is a schematic diagram of a first directed acyclic graph according to the second embodiment of the present application. Figure 10 Fig. 6 is a schematic diagram of a second directed acyclic graph according to the second embodiment of the present application. Figure 11 Fig. 7 is a schematic diagram of a third directed acyclic graph according to the second embodiment of the present application.

[0056] Figure 8The 5 thread bundles are shown, numbered as 2, 3, 4, 5, 6 (hereinafter referred to as thread bundle 2~thread bundle 6). First, based on the instruction category, thread bundle 2 divides vertex 2_0, thread bundle 3 divides vertex 3_0~vertex 3_2, thread bundle 4 divides vertex 4_0~vertex 4_2, thread bundle 5 divides vertex 5_0, and thread bundle 6 divides vertex 6_0~vertex 6_1. Then, based on the instruction execution order, intra-bundle arcs are established between two vertices belonging to the same thread bundle, and inter-bundle arcs are established between two vertices belonging to different thread bundles based on the instruction category and the synchronization resource identifier, to obtain the first directed acyclic graph 900 shown in Figure 9

[0057] After that, whether each arc is redundant is determined based on whether there is only the path formed by the arc between the head and the tail of the arc (for details, refer to the related description above). After the redundant arcs are deleted, the second directed acyclic graph 1000 shown in Figure 10

[0058] Referring to Figure 10 and Figure 11 In the second directed acyclic graph 1000, the vertices with an in-degree of 0 (vertex 2_0, vertex 5_0), the vertices pointed to by the vertices with an out-degree greater than or equal to 2 (vertex 3_0, vertex 4_0, vertex 6_0, vertex 4_1), and the vertices with an in-degree greater than or equal to 2 (vertex 6_1) are taken as judgment targets, and corresponding vertices G2_0, G5_0, G3_0, G4_0, G6_0, G4_1, G6_1 of the third directed acyclic graph are set, respectively. Among them, vertex 3_0 and vertex 4_0 are vertices pointed to by vertex 2_0 (out-degree is 2), and vertex 6_0 and vertex 4_1 are vertices pointed to by vertex 4_0 (out-degree is 2). Then, starting from each judgment target, traversal is performed, and the traversed vertices are abstracted into a vertex of the third directed acyclic graph, and the traversal of the judgment target is stopped until the next judgment target is reached.

[0059] Starting from the judgment target vertex 3_0, traversing along vertex 3_1, vertex 3_2 to the other judgment target vertex 6_1, the traversed vertex 3_0, vertex 3_1, vertex 3_2 are set to the same vertex G3_0 as vertex 3_0. As for vertex 4_1, starting from vertex 4_1 and traversing to the end vertex 4_2, vertex 4_1, vertex 4_2 are set to the same vertex G4_1 as vertex 4_1.

[0060] ​​For vertex 2_0, since its subsequent vertex is also a target, traversal stops at this target. Its corresponding vertex G2_0 only includes this vertex. Vertices 4_0, 5_0, and 6_0 are similar to vertex 2_0. Furthermore, vertex 6_1 is the ending vertex, so its corresponding vertex G6_1 only includes this vertex.

[0061] Finally obtained Figure 11 A third directed acyclic graph 1100 is shown.

[0062] In addition, based on Figures 7(a) to 7(g) The way to establish a topological sorting sequence is shown in Figure 9 The first directed acyclic graph 900 shown establishes a topologically sorted sequence, namely, {2_0, 5_0, 3_0, 4_0, 3_1, 4_1, 6_0, 3_2, 4_2, 6_1}.

[0063] Below Figure 9 The topological sorting sequence of the first directed acyclic graph 900 is shown, namely, {2_0, 5_0, 3_0, 4_0, 3_1, 4_1, 6_0, 3_2, 4_2, 6_1} and Figure 11 The third directed acyclic graph 1100 shown is used to illustrate the mapping relationship between logical synchronization resources and physical synchronization resources.

[0064] Figure 11 In the third directed acyclic graph 1100, there are four paths between the zero-indegree vertices (G2_0, G5_0) and the zero-outdegree vertices (G6_1, G4_1). The first path is: Vertex G2_0 → Vertex G3_0 → Vertex G6_1. The second path is: Vertex G2_0 → Vertex G4_0 → Vertex G6_0 → Vertex G6_1. The third path is: Vertex G2_0 → Vertex G4_0 → Vertex G4_1. The fourth path is: Vertex G5_0 → Vertex G4_1.

[0065] The mapping of the logical synchronization resource to the physical synchronization resource needs to satisfy the mapping rules, including: any vertex in the third DAG can reuse the physical synchronization resource recycled by the predecessor vertex of the any vertex and the any vertex; and the physical synchronization resources used between the vertices on different paths of the third DAG are in mutual exclusion; wherein the predecessor vertex is a vertex located before the any vertex on the same path. That is, the physical synchronization resources on the same path can be reused. After the predecessor vertex or the vertex to be allocated the physical synchronization resource releases the physical synchronization resource, the vertex to be allocated the physical synchronization resource can reuse the physical synchronization resource. The vertices on different paths can be executed in parallel, and therefore the physical synchronization resources used between the vertices on different paths must be in mutual exclusion. The vertices on different paths cannot be mapped to the same physical synchronization resource.

[0066] For example, for the vertex G6_0, it can reuse the physical synchronization resources recycled by the vertices G2_0, G4_0 and itself on the same path. And for the vertex G6_0 on the second path, since the vertex G6_0 can be executed in parallel with the vertices G3_0, G4_1, G5_0 on different paths, the physical synchronization resources used between the vertex G6_0 and the vertices G3_0, G4_1, G5_0 on different paths are in mutual exclusion.

[0067] When all the physical synchronization resources used by the previous vertex are reused by the subsequent vertex, other physical synchronization resources are allocated to the subsequent vertex.

[0068] Based on the topological sorting sequence {2_0, 5_0, 3_0, 4_0, 3_1, 4_1, 6_0, 3_2, 4_2, 6_1} of the first DAG 900, each instruction in each vertex is processed in turn. For example, the vertex 2_0 ranked first is taken out first, and the producer instructions p1, p2, p3, p8 in the vertex 2_0 are allocated the physical synchronization resource 1, the physical synchronization resource 2, the physical synchronization resource 3 and the physical synchronization resource 4 respectively.

[0069] Then, the vertex 5_0 is taken out. The third DAG vertex G5_0 to which the first DAG vertex 5_0 belongs is on a different path from the third DAG vertex G2_0 to which the first DAG vertex 2_0 belongs, and the vertex 5_0 cannot reuse the physical synchronization resource 1, the physical synchronization resource 2, the physical synchronization resource 3 and the physical synchronization resource 4. Therefore, the producer instructions p9, p10 in the vertex 5_0 are allocated the physical synchronization resource 5 and the physical synchronization resource 6 respectively.

[0070] Next, vertex 3_0 is taken out, which includes the consumer instruction c1 corresponding to the producer instruction p1. Therefore, the physical synchronization resource 1 corresponding to the producer instruction p1 is recovered in vertex 3_0.

[0071] Next, we extract vertex 4_0, which includes consumer instruction c8 and producer instruction p11, corresponding to producer instruction p8. The physical synchronization resource 4 corresponding to producer instruction p8 is reclaimed in vertex 4_0. Therefore, the reclaimed synchronization resource 4 is allocated to producer instruction p11. Next, we extract vertex 3_1, which includes consumer instruction c2, corresponding to producer instruction p2. Therefore, the physical synchronization resource 2 corresponding to producer instruction p2 is reclaimed in vertex 3_0.

[0072] Next, vertex 4_1 is taken out, which includes the consumer instruction c9 corresponding to the producer instruction p9. Therefore, the physical synchronization resource 5 corresponding to the producer instruction p9 is recovered in vertex 4_1.

[0073] Next, the vertex 6_0 is taken out, which includes the consumer instruction c11 corresponding to the producer instruction p11. Therefore, the physical synchronization resource 4 corresponding to the producer instruction p11 is recovered in the vertex 6_0.

[0074] Next, take out vertex 3_2, which includes the consumer instruction c3 and producer instruction p12 corresponding to the producer instruction p3. In vertex 3_2, the physical synchronization resource 3 corresponding to the producer instruction p3 is recycled. At this time, physical synchronization resources need to be allocated for the producer instruction p12. Vertex 3_2 of the first directed acyclic graph is abstracted in vertex G3_0 of the third directed acyclic graph. All vertices included in the same path of the third directed acyclic graph are able to reuse the predecessor vertex of each vertex of all the vertices and the physical synchronization resources of each vertex. It can be understood that the reused physical synchronization resources should have been recycled on this path. At this time, physical synchronization resource 1, physical synchronization resource 2 and physical synchronization resource 3 have been recycled in vertex G3_0. While satisfying that the vertices included in the same path are able to reuse the physical synchronization resources of their predecessor vertices, it is also necessary to satisfy that the physical synchronization resources used by multiple vertices on different vertex paths are mutually exclusive. Vertex G3_0 and vertices G4_0, G6_0, G4_1, and G5_0 are on different paths. Therefore, the physical synchronization resources allocated to vertex G3_0 are mutually exclusive with those allocated to vertices G4_0, G6_0, G4_1, and G5_0. That is, vertex G3_0 cannot use physical synchronization resources 4, 5, or 6. Therefore, producer instruction p12 can reuse any of physical synchronization resources 1, 2, and 3.

[0075] By analogy, the logical synchronization resources of the vertices 4_2 and 6_1 are mapped to the physical synchronization resources in sequence according to the following mapping rules: any vertex in the third directed acyclic graph can reuse the physical synchronization resources recycled by the predecessor vertex of the any vertex and the any vertex; and the physical synchronization resources used between the vertices on different paths of the third directed acyclic graph are in a mutually exclusive relationship; wherein the predecessor vertex is a vertex located before the any vertex on the same path.

[0076] In summary, the present disclosure generates connection relationships for the instructions included in different thread bundles by using instruction execution sequences, instruction categories, and synchronization resource identifiers, and then determines the utilization of synchronization resources based on the connection relationships. Accordingly, the synchronization resources can be recycled in time, the synchronization resources can be fully utilized, and the problem of synchronization resource allocation conflicts in parallel programs can be solved.

[0077] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for using synchronization resources for multiple parallel thread warps, characterized in that: include: Parsing the plurality of thread warps to obtain all instructions related to synchronization resources included in each of the thread warps; Dividing all the instructions included in each of the thread warps according to an instruction category of each of the instructions to obtain one or more vertices, wherein the instruction category includes consumer instructions and producer instructions, and each of the instructions has a synchronization resource identifier; establishing paths between all vertices included in the plurality of warps based on the synchronization resource identifiers to obtain a first directed acyclic graph; Deleting redundant arcs between a plurality of vertices in the first directed acyclic graph to obtain a second directed acyclic graph, wherein the arcs are used to connect two of the vertices among all the vertices, and each path is a set of one or more arcs; Grouping synchronization resources used by all vertices included in the second directed acyclic graph to obtain a third directed acyclic graph; Establishing a topologically sorted sequence of all vertices in the first directed acyclic graph; and Mapping logical synchronization resources to physical synchronization resources based on mapping rules, the topological sorting sequence and the third directed acyclic graph, The mapping rules include: Any vertex in the third directed acyclic graph reuses a predecessor vertex of the vertex and a physical synchronization resource recovered by the vertex; and The physical synchronization resources used by multiple vertices on different paths of the third directed acyclic graph are mutually exclusive; wherein the predecessor vertex is a vertex located before any vertex on the same path.

2. The method for using synchronization resources according to claim 1, wherein: Each of said vertices comprises at least one instruction; The step of establishing paths between all vertices included in the plurality of warps based on the synchronization resource identifiers to obtain the first directed acyclic graph includes: Based on the instruction execution order, an intra-warp arc is established between two vertices belonging to the same warp; as well as An inter-warp arc is established between two vertices belonging to different warps based on the instruction class and the synchronization resource identifier, wherein the arc includes the intra-warp arc and the inter-warp arc.

3. The method for using synchronization resources according to claim 2, characterized in that: The arc within the warp is used to connect two adjacent vertices in the same warp, and points from the vertex in the earlier execution order to the vertex in the later execution order; The inter-warp arc is used to connect two vertices belonging to different warps and having the same synchronization resource identifier, and is directed from the producer instruction to the consumer instruction.

4. The method for using synchronization resources according to claim 1, wherein: Each of said vertices comprises at least one instruction, The step of dividing all the instructions included in each of the warps according to the instruction category of each of the instructions to obtain the vertices includes: In each of the warps, all instructions from the consumer instruction to the next consumer instruction are grouped into the same vertex.

5. The method for using synchronization resources according to claim 4, characterized in that: If the initial instruction in each of the warps is the producer instruction, all instructions from the initial instruction to the next consumer instruction are grouped into the same vertex.

6. The method for using synchronization resources according to claim 1, characterized in that: Before deleting redundant arcs between the plurality of vertices in the first directed acyclic graph, the method further includes: In the first directed acyclic graph, determining whether each of the arcs is a redundant arc, If there is another path formed by multiple arcs between the arc head and the arc tail, the arc is determined to be the redundant arc.

7. The method for using synchronization resources according to claim 6, characterized in that: After determining that the arc is the redundant arc, the method further includes: The producer instruction on the redundant arc is a first producer instruction, and the producer instruction corresponding to the first arc on another path formed by multiple arcs between the arc head and arc tail of the redundant arc is a second producer instruction, and determining whether an execution order of the first producer instruction is before an execution order of the second producer instruction; and When it is determined that the execution order of the first producer instruction is before the execution order of the second producer instruction, the first producer instruction and its corresponding consumer instruction and the redundant arc on the redundant arc are deleted in the first directed acyclic graph.

8. The method for using synchronization resources according to claim 1, characterized in that: The step of grouping the synchronization resources used by all the vertices included in the second directed acyclic graph to obtain the third directed acyclic graph includes: Among all the vertices included in the second directed acyclic graph, vertices with an in-degree of 0, vertices pointed to by vertices with an out-degree greater than or equal to 2, and vertices with an in-degree greater than or equal to 2 are used as judgment targets; and A set of synchronization resources used by all vertices from each judgment target to the next judgment target, excluding the next judgment target, is abstracted into a vertex of the third directed acyclic graph.

9. The method for using synchronization resources according to claim 8, characterized in that: Based on the mapping rules, the topological sorting sequence and the third directed acyclic graph, the step of mapping the logical synchronization resources to the physical synchronization resources includes: based on the mapping rules, according to the topological sorting sequence, mapping the logical synchronization resources of all vertices in the first directed acyclic graph to the physical synchronization resources one by one.

10. An electronic device for synchronizing resources, characterized in that: include: a memory including one or more code segments; as well as a processor, coupled to the memory, and configured to execute the code segments to: Parsing multiple parallel warps to obtain all instructions related to synchronization resources included in each of the warps; Dividing all the instructions included in each of the thread warps according to an instruction category of each of the instructions to obtain one or more vertices, wherein the instruction category includes consumer instructions and producer instructions, and each of the instructions has a synchronization resource identifier; establishing paths between all vertices included in the plurality of warps based on the synchronization resource identifiers to obtain a first directed acyclic graph; Deleting redundant arcs between a plurality of vertices in the first directed acyclic graph to obtain a second directed acyclic graph, wherein the arcs are used to connect two of the vertices among all the vertices, and each path is a set of one or more arcs; Grouping synchronization resources used by all vertices included in the second directed acyclic graph to obtain a third directed acyclic graph; Establishing a topologically sorted sequence of all vertices in the first directed acyclic graph; and Mapping logical synchronization resources to physical synchronization resources based on mapping rules, the topological sorting sequence and the third directed acyclic graph, The mapping rules include: Any vertex in the third directed acyclic graph reuses a predecessor vertex of the vertex and a physical synchronization resource recovered by the vertex; and The physical synchronization resources used by multiple vertices on different paths of the third directed acyclic graph are mutually exclusive; wherein the predecessor vertex is a vertex located before any vertex on the same path.

Images