A Continuous / Discrete Hybrid Bandpass Sigma-Delta ADC

Abstract

The present invention discloses a continuous / discrete hybrid structure bandpass Sigma-Delta ADC, which belongs to the field of frequency digitization signal reception. A second-order LC type continuous time resonator module couples the output signal of an off-chip LC resonant cavity to a second-order RC type continuous time resonator module through an off-chip DC blocking capacitor; the second-order RC type continuous time resonator module is connected to the output of the second-order LC type continuous time resonator module as an intermediate stage, and the center frequency accurately resonates to a certain frequency; the second-order SC type discrete time resonator module is connected to the output of the second-order RC type continuous time resonator module; the multi-bit Flash type quantizer module compares the differential output signal of the second-order SC type discrete time resonator module with the differential reference voltage, converts it into an 8-bit thermometer code output, and converts it into a four-bit binary original code as a modulator output signal to the subsequent digital circuit for processing. The present invention adopts a six-order bandpass multi-bit quantization structure, which can obtain a higher dynamic range and has a natural anti-aliasing characteristic.

Description

Technical Field

[0001] The invention relates to the technical field of intermediate frequency digital signal reception, and in particular to a continuous / discrete hybrid structure bandpass Sigma-Delta ADC. Background Art

[0002] With the development of communication technology, the demand for the compatibility of communication equipment has become increasingly prominent. As a new technology in the field of wireless communications in the new era, software radio has attracted the attention of more and more scholars.

[0003] Software radio is more adaptable to the communication needs of the new era with its programmable parameters, high degree of softwareization and good versatility. Digital receivers are an important part of it. Compared with the zero intermediate frequency solution, the intermediate frequency digital receiver has better amplitude and phase orthogonal accuracy. Therefore, as the intermediate frequency digital technology gradually matures, it has become the most suitable solution for today's era. The so-called intermediate frequency digital receiver system is to amplify the high-frequency input signal through the RF front end, mix it to a lower intermediate frequency, and then directly perform analog-to-digital conversion on the intermediate frequency signal for subsequent digital processing. At present, the intermediate frequency digital receiver processing solution has been widely used in communications, military, radar and other fields.

[0004] Therefore, it is very necessary to design a continuous / discrete hybrid structure Sigma-Delta ADC for intermediate frequency digital receiver in the system. Summary of the invention

[0005] The object of the present invention is to provide a continuous / discrete hybrid structure bandpass Sigma-Delta ADC to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a continuous / discrete hybrid structure bandpass Sigma-Delta ADC, including a second-order LC type continuous time resonator module, a second-order RC type continuous time resonator module, a second-order SC type discrete time resonator module, a multi-bit Flash type quantizer module, a current steering feedback DAC1 and DAC2 modules, and a capacitive feedback DAC3 module;

[0007] The second-order LC type continuous-time resonator module couples the output signal of the off-chip LC resonant cavity to the input end of the second-order RC type continuous-time resonator module through the off-chip DC blocking capacitor;

[0008] The second-order RC type continuous time resonator module is connected to the output of the second-order LC type continuous time resonator module of the previous stage as an intermediate stage, and the center frequency is precisely resonated to a certain frequency;

[0009] The second-order SC discrete-time resonator module is connected to the output of the second-order RC continuous-time resonator module of the previous stage;

[0010] The multi-bit Flash quantizer module compares the differential output signal of the second-order SC discrete-time resonator module with the differential reference voltage and converts it into an 8-bit thermometer code output; the 8-bit thermometer code is converted into a four-bit binary original code as a modulator output signal to the subsequent digital circuit for processing by the encoder;

[0011] The current steering feedback DAC1, DAC2 modules and the capacitive feedback DAC3 module perform real-time automatic gain control on the input signal.

[0012] Optionally, the second-order LC type continuous-time resonator module includes an off-chip LC resonant cavity and a variable capacitor array;

[0013] The off-chip LC resonant cavity converts the current signal output by the mixer into a voltage signal; the variable capacitor array is used for digital calibration, so that the center frequency of the second-order LC type continuous time resonator module and the second-order RC type continuous time resonator module are accurately calibrated to the resonant frequency;

[0014] The off-chip LC resonant cavity includes two identical inductors, two identical DC-isolating capacitors, a capacitor bridging the two inductors, and a resistor; wherein,

[0015] Two inductors are connected in parallel, with the upper ends of the inductors connected, connected to VCC through a series resistor, and the capacitors connected to the lower ends of the two inductors; the bottoms of the two inductors are connected to one end of the two DC blocking capacitors respectively, and the other ends of the two DC blocking capacitors are output ports IF2P and IF2N.

[0016] Optionally, the second-order RC continuous-time resonator module includes a transconductance unit for converting voltage into current at the input end, and two identical RC continuous-time integrators connected in series, wherein each stage of the RC continuous-time integrator includes a fully differential operational amplifier and a variable capacitor array connected in parallel to the positive output and negative input of the operational amplifier, and another variable capacitor array connected in parallel to the negative output and positive input of the operational amplifier, wherein:

[0017] A resistor R is connected in series between the positive output end of the first-stage RC integrator and the negative input end of the second-stage RC integrator, and between the positive output end of the first-stage RC integrator and the negative input end of the second-stage RC integrator; a feedback resistor R' is connected in parallel between the positive output end of the second-stage RC integrator and the positive input end of the first-stage RC integrator, and between the positive output end of the second-stage RC integrator and the positive input end of the first-stage RC integrator.

[0018] Optionally, the second-order SC discrete-time resonator module includes two identical SC integrators connected in series and two identical feedback capacitors Cz; wherein each SC integrator includes a fully differential operational amplifier,

[0019] The positive input terminal of the operational amplifier is connected to a switch CLK1_d, a sampling capacitor Cs1, and a switch CLK2_d, and the negative input terminal is connected to a switch CLK3_d, a sampling capacitor Cs2, and a switch CLK4_d; a switch branch is connected in parallel between the switch CLK1_d and the sampling capacitor Cs1, between the sampling capacitor Cs1 and the switch CLK2_d, between the switch CLK3_d and the sampling capacitor Cs2, and between the sampling capacitor Cs2 and the switch CLK4_d, and the branch is connected to the ground terminal;

[0020] An integrating capacitor Ci is connected in parallel between the positive output terminal and the negative output terminal, and between the negative input terminal and the positive output terminal of each operational amplifier;

[0021] The left ends of the two identical feedback capacitors Cz are respectively connected between the sampling capacitor Cs1 and the switch CLK1_d, and between the sampling capacitor Cs2 and the switch CLK3_d in the first-stage SC integrator, and the right ends are respectively connected in series with a switch to the reverse voltage output terminal or ground of the second-stage SC integrator, and the forward voltage output terminal or ground of the second-stage SC integrator.

[0022] Optionally, the multi-bit Flash type quantizer module includes a ladder resistor network composed of 9 resistors and 8 fully differential comparator modules; the ladder resistor network divides the reference voltages VREFP and VREFN; the fully differential comparator module compares the reference voltages VREFP and VREFN with the input voltage;

[0023] The input differential signals VIN, VIP and the clock signal CLK are connected to the VIP, VIN and CLK input ports of the eight fully differential comparator modules respectively, nine resistors of equal resistance are connected in series, the differential reference voltages VREFP and VREFN are connected to one end of the first resistor and the other end of the ninth resistor respectively, the VREFP end of the first comparator module and the VREFN end of the eighth comparator module are connected between the first resistor and the second resistor, the second resistor and the third resistor are connected to the VREFP end of the second comparator module, ..., the VREFN end of the second comparator module is connected between the seventh resistor and the eighth resistor, and the VREFN end of the first comparator module and the VREFP end of the eighth comparator module are connected between the eighth resistor and the ninth resistor.

[0024] Optionally, the fully differential comparator module includes a switched capacitor module, a preamplifier and a latch module;

[0025] The preamplifier and latch module includes MOS tubes M1 to M15 and two NAND gates; wherein the gate of the NMOS tube M5 is connected to the signal Vbias, the source is grounded, and the drain is connected to the source of the NMOS tube M6 and the source of the NMOS tube M7;

[0026] The gates of the NMOS tubes M6 and M7 are connected to the signals VP and VN passing through the switch capacitors respectively, the drain of the NMOS tube M6 is connected to the drains of the PMOS tubes M8, M9 and M10, the drain of the NMOS tube M7 is connected to the drains of the PMOS tubes M9, M10 and M11, the sources of the PMOS tubes M8, M9, M10 and M11 are all connected to VDD, and the gates of the PMOS tubes M8 and M11 are connected to the gates of the PMOS tubes M13 and M14 respectively;

[0027] The sources of PMOS tubes M12, M13, M14, and M15 are all connected to VDD, the drains of PMOS tube M12 and M13 are all connected to the source of PMOS tube M3, the drains of PMOS tube M14 and M15 are all connected to the source of PMOS tube M4, and the gates of PMOS tubes M12 and M15 are all connected to the enable terminal.

[0028] The drains of the PMOS tubes M3 and M4 are connected to the drains of the NMOS tubes M1 and M2 respectively, the gates of the PMOS tubes M3 and M1 are connected to the drain of the PMOS tube M4, and the gates of the PMOS tubes M4 and M2 are connected to the drain of the PMOS tube M3. The sources of the NMOS tubes M1 and M2 are connected to the ground;

[0029] Two NAND gates are cross-coupled, a first input terminal of one NAND gate is connected to the drain of the NMOS tube M1, a second input terminal is connected to the output OUTN of another NAND gate, and the output is OUTP; a first input terminal of another NAND gate is connected to the drain of the NMOS tube M2, a second input terminal is connected to the output OUTP, and the output is OUTN.

[0030] Optionally, in the first stage of the preamplifier circuit, the NMOS tube M5 is a tail current tube, the NMOS tubes M6 and M7 are differential input pair tubes, and the PMOS tubes M9 and M10 constitute a cross-coupled pair tube load acceleration result establishment to reduce internal delay; the PMOS tubes M13, M3, NMOS tube M1 and the PMOS tubes M14, M4, NMOS tube M2 are the second stage of the amplifier circuit respectively; due to the difference in the input differential signals VP and VN, the difference in the two currents in the first stage differential pair of the amplifier circuit leads to the difference in the two currents in the second stage, and under the positive feedback of the PMOS tubes M3 and M4, one of the nodes R or S will eventually stabilize at a low level, and the other will stabilize at a high level; the two output the final comparator results OUTP and OUTN after passing through the RS latch.

[0031] Optionally, the current steering feedback DAC1 and DAC2 modules include 8 current source units and 9 NMOS tubes respectively; the sources of the 9 NMOS tubes are all grounded, the drain of the first NMOS tube flows into the current IBIAS, and its gate is connected to the gates of the following 8 NMOS tubes; the 8 current source units are controlled by the 8-bit thermometer code S0~S7 generated at the output end of the quantizer to control the current at the OUTP' and OUTN' output ends.

[0032] Optionally, the capacitive feedback DAC3 module includes 8 identical capacitors and 8 selection switches controlled by thermometer codes, the 8 capacitors are respectively connected in series with the 8 selection switches, the selection switches are connected to the level VREFP or VREFN, and the capacitors are connected to ground or Vout.

[0033] In the continuous / discrete hybrid structure bandpass Sigma-Delta ADC provided by the present invention, an off-chip LC resonant cavity is used, and the chip area is smaller; the capacitance of the second-order LC type continuous time resonator module and the second-order RC type continuous time resonator module adopts a variable capacitor array, and the capacitance value is calibrated by a digital calibration method, so that the center frequency of the two continuous time resonator modules is calibrated to fclk / 8; a data weighting (DWA) algorithm is used to achieve dynamic component matching, and the distortion power spectrum caused by the nonlinear error of the multi-bit DAC is effectively shaped in the first order; the automatic gain control loop adjusts the gain of the input signal by adjusting the ADC full-scale amplitude, eliminating the variable gain amplifier in the traditional structure, and significantly saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural schematic diagram of a continuous / discrete hybrid bandpass Sigma-Delta ADC provided by the present invention;

[0035] Figure 2 It is a schematic diagram of the off-chip LC resonant cavity structure in a second-order LC type continuous-time resonator module;

[0036] Figure 3 It is a structural diagram of a second-order RC type continuous-time resonator module;

[0037] Figure 4 It is a schematic diagram of the structure of a second-order SC type discrete time resonator module;

[0038] Figure 5 It is a schematic diagram of the structure of a multi-bit Flash type quantizer module;

[0039] Figure 6 It is a circuit diagram of a preamplifier and a latch module in a multi-bit Flash type quantizer module;

[0040] Figure 7 This is the circuit diagram of the current steering feedback DAC1 and DAC2 modules;

[0041] Figure 8 It is the circuit diagram of the capacitive feedback DAC3 module. DETAILED DESCRIPTION

[0042] The following is a further detailed description of a continuous / discrete hybrid bandpass Sigma-Delta ADC proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and in an inaccurate scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] The present invention provides a continuous / discrete hybrid bandpass Sigma-Delta ADC, the structure of which is as follows: Figure 1 As shown, it includes a second-order LC type continuous-time resonator module, a second-order RC type continuous-time resonator module, a second-order SC type discrete-time resonator module, a multi-bit Flash type quantizer module, a current steering feedback DAC1 and DAC2 modules, and a capacitive feedback DAC3 module. The second-order LC continuous-time resonator module couples the output signal of the off-chip LC resonant cavity to the input end of the second-order RC continuous-time resonator module through an off-chip DC blocking capacitor; the second-order RC continuous-time resonator module is connected to the output of the second-order LC continuous-time resonator module of the previous stage, and the center frequency is precisely resonated to a certain frequency; the second-order SC discrete-time resonator module is connected to the output of the second-order RC continuous-time resonator module of the previous stage; the multi-bit Flash quantizer module compares the differential output signal of the second-order SC discrete-time resonator module with the differential reference voltage, and converts it into an 8-bit thermometer code output; the 8-bit thermometer code is converted into a four-bit binary original code by an encoder as a modulator output signal for subsequent digital circuit processing; the current steering feedback DAC1, DAC2 modules and the capacitive feedback DAC3 module are used to perform real-time automatic gain control on the input signal.

[0044] The second-order LC type continuous-time resonator module includes an off-chip LC resonant cavity and a variable capacitor array. The structure of the off-chip LC resonant cavity is as follows: Figure 2As shown. The off-chip LC resonant cavity converts the current signal output by the mixer into a voltage signal. The off-chip LC resonant cavity includes two identical inductors, two identical DC-blocking capacitors, a capacitor bridging the two inductors, and a resistor. Among them, the two inductors are connected in parallel, the upper ends of the inductors are connected, and VCC is connected between them through a series resistor; the capacitor is connected to the lower ends of the two inductors; and the two inductors are connected to one end of the two DC-blocking capacitors respectively under the two inductors, and the other ends of the two DC-blocking capacitors are output ports IF2P and IF2N.

[0045] The structure of the second-order RC continuous-time resonator module can be found in Figure 3 The RC type continuous time resonator module includes a transconductance unit for converting voltage into current at the input end, and two identical RC continuous time integrators connected in series; each stage of RC continuous time integrator includes a fully differential operational amplifier, a variable capacitor array C connected in parallel to the positive output and negative input of the operational amplifier, and another variable capacitor array C connected in parallel to the negative output and positive input of the operational amplifier. Wherein: the resistor R is connected in series between the positive (negative) output of the first stage RC integrator and the negative (positive) input of the second stage RC integrator, and the feedback resistor R' is connected in parallel to the positive (negative) output of the second stage RC integrator and the positive (negative) input of the first stage RC integrator.

[0046] The second-order SC type discrete-time resonator module is as Figure 4 As shown, it includes two stages of identical SC integrators connected in series; each stage of SC integrators is composed of 8 switches, two sampling capacitors Cs (including capacitor Cs1 and capacitor Cs2), two integrating capacitors Ci and a fully differential operational amplifier. In each stage of SC integrator, the positive input end is connected in series with switch CLK1_d, sampling capacitor Cs1, and switch CLK2_d in sequence, and the negative input end is connected in series with switch CLK3_d, sampling capacitor Cs2, and switch CLK4_d in sequence; and as shown in FIG. Figure 4 As shown, a switch branch is connected in parallel between switch CLK1_d and sampling capacitor Cs1, between sampling capacitor Cs1 and switch CLK2_d, between switch CLK3_d and sampling capacitor Cs2, and between sampling capacitor Cs2 and switch CLK4_d, and the branch is connected to the ground. An integrating capacitor Ci is connected in parallel between the positive voltage input terminal and the negative voltage output terminal, and between the positive voltage output terminal and the negative voltage input terminal of each fully differential operational amplifier. The left ends of two identical feedback capacitors Cz are respectively connected between the sampling capacitor Cs1 and switch CLK1_d, and between the sampling capacitor Cs2 and switch CLK3_d in the first-stage SC integrator, and the right ends are respectively connected in series with a switch connected to the negative voltage output terminal or ground of the second-stage SC integrator, and the forward voltage output terminal or ground of the second-stage SC integrator.

[0047] The structure of the multi-bit Flash quantizer module is as follows Figure 5 As shown, it includes a ladder resistor network composed of 9 resistors and 8 full differential comparator modules. The ladder resistor network divides the differential reference voltages VREFP and VREFN; the full differential comparator module compares the differential reference voltages VREFP, VREFN and the differential input voltage. The input differential signals VIN, VIP and the clock signal CLK are respectively connected to the VIP, VIN and CLK input ports of the 8 full differential comparator modules in sequence, and nine equal resistance resistors are connected in series. The differential reference voltages VREFP and VREFN are respectively connected to one end of the first resistor and the other end of the ninth resistor. The first resistor and the second resistor are connected to the VREFP end of the first comparator module and the VREFN end of the eighth comparator module. The second resistor and the third resistor are connected to the VREFP end of the second comparator module. By analogy, the seventh resistor and the eighth resistor are connected to the VREFN end of the second comparator module, and the eighth resistor and the ninth resistor are connected to the VREFN end of the first comparator module and the VREFP end of the eighth comparator module.

[0048] The fully differential comparator module includes a switched capacitor module and a Figure 6 The preamplifier and latch module shown. The preamplifier and latch module includes MOS tubes M1 to M15 and two NAND gates; the gate of NMOS tube M5 is connected to the signal Vbias, the source is grounded, and the drain is connected to the source of NMOS tube M6 and the source of NMOS tube M7; the gates of NMOS tubes M6 and M7 are respectively connected to the signals VP and VN passing through the switch capacitor, the drain of NMOS tube M6 is connected to the drains of PMOS tubes M8, M9, and M10, the drain of NMOS tube M7 is connected to the drains of PMOS tubes M9, M10, and M11, and the drain of PMOS tube M8 is connected to the drain of PMOS tube M9, M10, and M11. The sources of the PMOS tubes M8, M9, M10 and M11 are all connected to VDD, the gates of the PMOS tubes M8 and M11 are respectively connected to the gates of the PMOS tubes M13 and M14; the sources of the PMOS tubes M12, M13, M14 and M15 are all connected to VDD, the drain of the PMOS tube M12 and the drain of the PMOS tube M13 are all connected to the source of the PMOS tube M3, the drain of the PMOS tube M14 and the drain of the PMOS tube M15 are all connected to the source of the PMOS tube M4, and the gates of the PMOS tubes M12 and M15 are all connected to the enable terminal The drains of the PMOS tubes M3 and M4 are connected to the drains of the NMOS tubes M1 and M2 respectively, the gates of the PMOS tubes M3 and M1 are connected to the drain of the PMOS tube M4, and the gates of the PMOS tubes M4 and M2 are connected to the drain of the PMOS tube M3. The sources of the NMOS tubes M1 and M2 are connected to the ground; two NAND gates are cross-coupled, the first input end of one NAND gate is connected to the drain of the NMOS tube M1, the second input end is connected to the output OUTN of the other NAND gate, and the output is OUTP, and the first input end of the other NAND gate is connected to the drain of the NMOS tube M2, the second input end is connected to the output OUTP, and the output is OUTN.

[0049] Please continue reading Figure 6 In the first stage of the preamplifier circuit, NMOS tube M5 is the tail current tube, NMOS tubes M6 and M7 are differential input pairs, and PMOS tubes M9 and M10 form a cross-coupling pair to accelerate the establishment of the load result and reduce internal delay. PMOS tubes M13, M3, NMOS tube M1 and PMOS tubes M14, M4, NMOS tube M2 are the second stage of the amplifier circuit. Due to the difference in the input differential signals VP and VN, the difference in the two currents in the first stage differential pair of the amplifier circuit leads to the difference in the two currents in the second stage. Under the positive feedback of PMOS tubes M3 and M4, one of the nodes R or S will eventually stabilize at a low level, and the other will stabilize at a high level. After passing through the RS latch, the two output the final comparator results OUTP and OUTN.

[0050] The current steering feedback DAC1 module and the current steering feedback DAC2 module adopt the current steering structure. Figure 7 The current steering feedback DAC1 and DAC2 modules include 8 current source units I0-I7 respectively. The sources of the 9 NMOS tubes are all grounded, the drain of the first NMOS tube flows into the current IBIAS, and its gate is connected to the gates of the following 8 NMOS tubes. The 8-bit current source unit is controlled by the 8-bit thermometer code S0-S7 generated by the output end of the quantizer to control the current of the output ends OUTP' and OUTN'.

[0051] The capacitive feedback DAC3 module adopts a capacitive structure, see Figure 8 The structure is simple in principle and easy to implement. The capacitive feedback DAC3 module includes 8 identical capacitors and 8 selection switches controlled by thermometer codes. The 8 capacitors are connected in series with the 8 selection switches, the selection switches are connected to the level VREFP or VREFN, and the capacitors are connected to the ground or Vout.

[0052] The continuous / discrete hybrid bandpass Sigma-Delta ADC of the present invention adopts a sixth-order bandpass multi-bit quantization structure, can obtain a higher dynamic range, and has a natural anti-aliasing characteristic. The loop filter of the modulator includes a second-order LC type continuous time resonator, a second-order RC type continuous time resonator and a second-order SC type discrete time resonator. The continuous / discrete time hybrid structure is adopted, and the advantages of the continuous time modulator and the discrete time modulator are combined. The capacitor digital calibration technology is adopted so that the resonant frequency of the LC resonator and the RC resonator is accurately calibrated to fclk / 8. The quantizer is implemented by a 3bit flash ADC, and the feedback DAC is implemented by a current steering DAC and a switch capacitor respectively. At the same time, the data weighted average (DWA) algorithm is used to calibrate the mismatch between the feedback DAC units to reduce the nonlinearity caused by the feedback DAC. The 8-bit thermometer code output by the quantizer is converted by the encoder into a 4-bit binary original code as the output signal of the modulator and sent to the subsequent IQ frequency converter and digital filter for processing.

[0053] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A continuous / discrete hybrid bandpass Sigma-Delta ADC, characterized in that: Including second-order LC type continuous time resonator module, second-order RC type continuous time resonator module, second-order SC type discrete time resonator module, multi-bit Flash type quantizer module, current steering feedback DAC1 and DAC2 modules, capacitive feedback DAC3 module; The second-order LC type continuous-time resonator module couples the output signal of the off-chip LC resonant cavity to the input end of the second-order RC type continuous-time resonator module through the off-chip DC blocking capacitor; The second-order RC type continuous time resonator module is connected to the output of the second-order LC type continuous time resonator module of the previous stage as an intermediate stage, and the center frequency is precisely resonated to a certain frequency; The second-order SC discrete-time resonator module is connected to the output of the second-order RC continuous-time resonator module of the previous stage; The multi-bit Flash quantizer module compares the differential output signal of the second-order SC discrete-time resonator module with the differential reference voltage and converts it into an 8-bit thermometer code output; the 8-bit thermometer code is converted into a four-bit binary original code as a modulator output signal to the subsequent digital circuit for processing by the encoder; The current steering feedback DAC1, DAC2 modules and the capacitive feedback DAC3 module perform real-time automatic gain control on the input signal; The second-order LC type continuous-time resonator module includes an off-chip LC resonant cavity and a variable capacitor array; The off-chip LC resonant cavity converts the current signal output by the mixer into a voltage signal; the variable capacitor array is used for digital calibration, so that the center frequency of the second-order LC type continuous time resonator module and the second-order RC type continuous time resonator module are accurately calibrated to the resonant frequency; The off-chip LC resonant cavity includes two identical inductors, two identical DC-isolating capacitors, a capacitor bridging the two inductors, and a resistor; wherein, Two inductors are connected in parallel, the upper ends of the inductors are connected, and VCC is connected between them through a series resistor. The capacitors are connected to the lower ends of the two inductors. The lower ends of the two inductors are connected to one end of the two DC blocking capacitors respectively, and the other ends of the two DC blocking capacitors are output ports IF2P and IF2N. The second-order RC continuous-time resonator module includes a transconductance unit for converting voltage into current at the input end, and two identical RC continuous-time integrators connected in series, wherein each stage of the RC continuous-time integrator includes a fully differential operational amplifier and a variable capacitor array connected in parallel to the positive output and negative input of the operational amplifier, and another variable capacitor array connected in parallel to the negative output and positive input of the operational amplifier, wherein: A resistor R is connected in series between the positive output end of the first-stage RC integrator and the negative input end of the second-stage RC integrator, and between the positive output end of the first-stage RC integrator and the negative input end of the second-stage RC integrator; a feedback resistor R' is connected in parallel between the positive output end of the second-stage RC integrator and the positive input end of the first-stage RC integrator, and between the positive output end of the second-stage RC integrator and the positive input end of the first-stage RC integrator.

2. The continuous / discrete hybrid bandpass Sigma-Delta ADC according to claim 1, characterized in that: The second-order SC discrete-time resonator module comprises two identical SC integrators connected in series and two identical feedback capacitors Cz; wherein each SC integrator comprises a fully differential operational amplifier, The positive input terminal of the operational amplifier is connected to a switch CLK1_d, a sampling capacitor Cs1, and a switch CLK2_d, and the negative input terminal is connected to a switch CLK3_d, a sampling capacitor Cs2, and a switch CLK4_d; a switch branch is connected in parallel between the switch CLK1_d and the sampling capacitor Cs1, between the sampling capacitor Cs1 and the switch CLK2_d, between the switch CLK3_d and the sampling capacitor Cs2, and between the sampling capacitor Cs2 and the switch CLK4_d, and the branch is connected to the ground terminal; An integrating capacitor Ci is connected in parallel between the positive output terminal and the negative output terminal, and between the negative input terminal and the positive output terminal of each operational amplifier; The left ends of the two identical feedback capacitors Cz are respectively connected between the sampling capacitor Cs1 and the switch CLK1_d, and between the sampling capacitor Cs2 and the switch CLK3_d in the first-stage SC integrator, and the right ends are respectively connected in series with a switch to the reverse voltage output terminal or ground of the second-stage SC integrator, and the forward voltage output terminal or ground of the second-stage SC integrator.

3. The continuous / discrete hybrid bandpass Sigma-Delta ADC according to claim 1, characterized in that: The multi-bit Flash quantizer module includes a ladder resistor network composed of 9 resistors and 8 fully differential comparator modules; the ladder resistor network divides the reference voltages VREFP and VREFN; the fully differential comparator module compares the reference voltages VREFP and VREFN with the input voltage; The input differential signals VIN, VIP and the clock signal CLK are connected to the VIP, VIN and CLK input ports of the eight fully differential comparator modules respectively, nine resistors of equal resistance are connected in series, the differential reference voltages VREFP and VREFN are connected to one end of the first resistor and the other end of the ninth resistor respectively, the VREFP end of the first comparator module and the VREFN end of the eighth comparator module are connected between the first resistor and the second resistor, the second resistor and the third resistor are connected to the VREFP end of the second comparator module, ..., the VREFN end of the second comparator module is connected between the seventh resistor and the eighth resistor, and the VREFN end of the first comparator module and the VREFP end of the eighth comparator module are connected between the eighth resistor and the ninth resistor.

4. The continuous / discrete hybrid bandpass Sigma-Delta ADC according to claim 3, characterized in that: The fully differential comparator module includes a switched capacitor module, a preamplifier and a latch module; The preamplifier and latch module includes MOS tubes M1-M15 and two NAND gates; wherein the gate of the NMOS tube M5 is connected to the signal Vbias, the source is grounded, and the drain is connected to the source of the NMOS tube M6 and the source of the NMOS tube M7; The gates of the NMOS tubes M6 and M7 are connected to the signals VP and VN passing through the switch capacitors respectively, the drain of the NMOS tube M6 is connected to the drains of the PMOS tubes M8, M9 and M10, the drain of the NMOS tube M7 is connected to the drains of the PMOS tubes M9, M10 and M11, the sources of the PMOS tubes M8, M9, M10 and M11 are all connected to VDD, and the gates of the PMOS tubes M8 and M11 are connected to the gates of the PMOS tubes M13 and M14 respectively; The sources of PMOS tubes M12, M13, M14, and M15 are all connected to VDD, the drains of PMOS tube M12 and M13 are all connected to the source of PMOS tube M3, the drains of PMOS tube M14 and M15 are all connected to the source of PMOS tube M4, and the gates of PMOS tubes M12 and M15 are all connected to the enable terminal. ; The drains of the PMOS tubes M3 and M4 are connected to the drains of the NMOS tubes M1 and M2 respectively; the gates of the PMOS tubes M3 and M1 are connected to the drain of the PMOS tube M4; the gates of the PMOS tubes M4 and M2 are connected to the drain of the PMOS tube M3; the sources of the NMOS tubes M1 and M2 are connected to the ground; Two NAND gates are cross-coupled, a first input terminal of one NAND gate is connected to the drain of the NMOS tube M1, a second input terminal is connected to the output OUTN of another NAND gate, and the output is OUTP; a first input terminal of another NAND gate is connected to the drain of the NMOS tube M2, a second input terminal is connected to the output OUTP, and the output is OUTN.

5. The continuous / discrete hybrid bandpass Sigma-Delta ADC according to claim 4, characterized in that: In the first stage of the preamplifier circuit, the NMOS tube M5 is a tail current tube, the NMOS tubes M6 and M7 are differential input pair tubes, and the PMOS tubes M9 and M10 constitute a cross-coupled pair tube load acceleration result establishment to reduce internal delay; the PMOS tubes M13, M3, NMOS tube M1 and the PMOS tubes M14, M4, NMOS tube M2 are the second stage of the amplifier circuit respectively; due to the difference in the input differential signals VP and VN, the difference in the two currents in the first stage differential pair of the amplifier circuit leads to the difference in the two currents in the second stage, and under the positive feedback of the PMOS tubes M3 and M4, one of the nodes R or S will eventually stabilize at a low level, and the other will stabilize at a high level; the two output the final comparator results OUTP' and OUTN' after passing through the RS latch.

6. The continuous / discrete hybrid bandpass Sigma-Delta ADC according to claim 1, characterized in that: The current steering feedback DAC1 and DAC2 modules include 8 current source units and 9 NMOS tubes respectively; the sources of the 9 NMOS tubes are all grounded, the drain of the first NMOS tube flows into the current IBIAS, and its gate is connected to the gates of the following 8 NMOS tubes; the 8 current source units are controlled by the 8-bit thermometer code S0~S7 generated at the output end of the quantizer to control the current at the output ends OUTP' and OUTN'.

7. The continuous / discrete hybrid bandpass Sigma-Delta ADC according to claim 1, characterized in that: The capacitive feedback DAC3 module includes 8 identical capacitors and 8 selection switches controlled by thermometer codes. The 8 capacitors are respectively connected in series with the 8 selection switches. The selection switches are connected to the level VREFP or VREFN, and the capacitors are connected to the ground or Vout.

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