FPGA-based SRIO multi-channel control method, device and system

Abstract

This invention relates to the field of embedded system communication technology, specifically disclosing an FPGA-based SRIO multi-channel control method, comprising: acquiring transmission data from N transmission channels, wherein the interface timing of each transmission channel is a preset channel interface timing, and the transmission data of each transmission channel is stored in the memory corresponding to the transmission channel; prioritizing the transmission data from the N transmission channels to obtain information to be transmitted arranged in priority order; sequentially transmitting the information to be transmitted through the transmission interface of the SRIO IP; acquiring the received data from the receiving interface of the SRIO IP and parsing the received data to determine the corresponding receiving channel; and writing the parsed received data into the memory corresponding to the receiving channel. This invention also discloses an FPGA-based SRIO multi-channel control device and system. The FPGA-based SRIO multi-channel control method provided by this invention can simultaneously support direct expansion of up to 64 transmission and reception channels.

Description

Technical Field

[0001] This invention relates to the field of embedded system communication technology, and in particular to an FPGA-based SRIO multi-channel control method, an FPGA-based SRIO multi-channel control device, and an FPGA-based SRIO multi-channel control system. Background Technology

[0002] With the rapid improvement of embedded system performance, the requirements for data bandwidth, reliability, and flexibility in board-to-board and on-board chip interconnects are gradually increasing, making it difficult for traditional parallel transmission methods to meet practical needs. SRIO (Serial RapidIO), a high-speed serial bus protocol, has become a widely used high-speed protocol. SRIO is a packet-switched interconnect architecture that has been widely used in chip interconnects, real-time video transmission, and miniaturized systems.

[0003] In the research of SRIO literature at home and abroad, the most studied topics are communication between SRIO and FPGA and FPGA implementation of SRIO data transmission. However, the existing technology has problems such as complex implementation of data transmission and reception code, single interface support, inability to be applied to multiple protocols, and data congestion caused by multi-channel data transmission when dealing with large data volume transmission in current high-speed signal processing systems. Summary of the Invention

[0004] This invention provides an FPGA-based SRIO multi-channel control method, an FPGA-based SRIO multi-channel control device, and an FPGA-based SRIO multi-channel control system, which at least solves the problem of limited interface support in related technologies.

[0005] As a first aspect of the present invention, an FPGA-based SRIO multi-channel control method is provided, comprising:

[0006] Sending process:

[0007] Obtain the transmission data of N transmission channels, where N is a natural number greater than 1. The interface timing of each transmission channel is a preset channel interface timing. The transmission data of each transmission channel is stored in the memory corresponding to the transmission channel.

[0008] The data transmitted from N transmission channels are processed according to priority order to obtain the information to be transmitted in order of priority.

[0009] The information to be sent is sequentially transmitted through the SRIO IP transmission interface;

[0010] Receiving process:

[0011] The received data from the SRIO IP's receive interface is obtained, and the received data is parsed to determine the corresponding receive channel, wherein the number of receive channels is the same as the number of transmit channels;

[0012] The parsed received data is written into the memory corresponding to the receiving channel.

[0013] Furthermore, the data transmitted from the N transmission channels are processed according to priority order to obtain the information to be transmitted arranged in priority order, including:

[0014] The data transmitted from N transmission channels are processed according to priority order using a round-robin scheduling algorithm to obtain the information to be transmitted, arranged from high to low priority.

[0015] Furthermore, the data transmitted from the N transmission channels is processed in order of priority, including:

[0016] Determine the priority number and frequency change value for each transmission channel, where a priority number of 1 indicates the highest priority and a priority number of N indicates the lowest priority. The priority number of each transmission channel is used as the initial value for the frequency change value of that transmission channel.

[0017] The data transmitted through N transmission channels are sorted from highest to lowest priority. When data is transmitted through one of the transmission channels, the change in the number of transmissions for each transmission channel that has transmitted data is decremented by 1.

[0018] Furthermore, the sending process also includes actions performed after the step of sequentially sending the information to be sent through the SRIO IP sending interface:

[0019] Receive send confirmation messages through the SRIO IP send confirmation interface.

[0020] Furthermore, the receiving process also includes actions performed after the step of writing the parsed received data into the memory corresponding to the receiving channel:

[0021] Send a reception confirmation message through the SRIO IP receive feedback interface.

[0022] Furthermore, the transmitted data includes multiple SRIO data packets, each SRIO data packet including a header, a valid data payload, and a CRC check bit. The header includes an MSG packet and a RESP packet from the HELLO packet. The MSG packet contains parameters indicating the number of channels in the current transmitting channel, and the RESP packet contains parameters indicating the number of channels in the current receiving channel.

[0023] Furthermore, the preset channel interface timing includes: a clock signal, a reset signal, a data valid flag signal, an address signal, a data signal, and a ready flag signal.

[0024] As another aspect of the present invention, an FPGA-based SRIO multi-channel control device is provided for implementing the FPGA-based SRIO multi-channel control method described above, wherein the FPGA-based SRIO multi-channel control device comprises:

[0025] The sending module is used to acquire the transmission data from N transmission channels, where N is a natural number greater than 1. The interface timing of each transmission channel is a preset channel interface timing, and the transmission data of each transmission channel is stored in the memory corresponding to the transmission channel. The transmission data from the N transmission channels is processed according to priority order to obtain the information to be sent arranged in priority order. The information to be sent is then sent sequentially through the transmission interface of the SRIO IP.

[0026] The receiving module is used to acquire received data from the receiving interface of the SRIO IP, parse the received data to determine the corresponding receiving channel, wherein the number of receiving channels is the same as the number of transmitting channels; and write the parsed received data into the memory corresponding to the receiving channel.

[0027] As another aspect of the present invention, an FPGA-based SRIO multi-channel control system is provided, comprising: N transmit channels, N receive channels, a transmit interface of SRIO IP, a receive interface of SRIO IP, and the aforementioned FPGA-based SRIO multi-channel control device. Each transmit channel is connected to a first memory, and each receive channel is connected to a second memory. Each first memory is communicatively connected to a transmit module in the FPGA-based SRIO multi-channel control device. The transmit module in the FPGA-based SRIO multi-channel control device is connected to the transmit interface of the SRIO IP. Each second memory is communicatively connected to a receive module in the FPGA-based SRIO multi-channel control device. The receive module in the FPGA-based SRIO multi-channel control device is connected to the receive interface of the SRIO IP. N is a natural number greater than 1.

[0028] Furthermore, it also includes: a transmit acknowledgment interface for SRIO IP and a receive feedback interface for SRIO IP, wherein the transmit acknowledgment interface for SRIO IP is connected to the transmit module in the FPGA-based SRIO multi-channel control device, and the receive feedback interface for SRIO IP is connected to the receive module in the FPGA-based SRIO multi-channel control device.

[0029] The FPGA-based SRIO multi-channel control method provided by this invention can reduce the complexity of using SRIO IP, while being compatible with direct expansion of up to 64 transmit and receive channels. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0031] Figure 1 The structural block diagram of the FPGA-based SRIO multichannel control system provided by this invention.

[0032] Figure 2 This is a schematic diagram illustrating the specific communication between the local SRIO and the remote SRIO provided by the present invention.

[0033] Figure 3 The following is a structural block diagram of the sending module provided by the present invention.

[0034] Figure 4 A detailed structural block diagram of the receiving module provided by the present invention.

[0035] Figure 5 The flowchart shows the FPGA-based SRIO multi-channel control method provided by the present invention.

[0036] Figure 6 This is a schematic diagram of the HELLO frame header format provided by the present invention.

[0037] Figure 7 This is a timing diagram of the preset channel interface provided by the present invention.

[0038] Figure 8 The specific workflow diagram of the Round-Robin provided by this invention.

[0039] Figure 9 This is a schematic diagram illustrating the specific sending process provided by the present invention.

[0040] Figure 10 This is a schematic diagram illustrating the specific receiving process provided by the present invention.

[0041] Figure 11 The timing simulation diagram of the sending interface provided by this invention.

[0042] Figure 12 MSGIREQ simulation diagram provided for this invention.

[0043] Figure 13 The simulation diagram of the MSGIRESP interface provided by this invention.

[0044] Figure 14 Simulation diagrams of the MSGTREQ and MSGTRESP interfaces provided for this invention. Detailed Implementation

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] To effectively control data congestion that may occur when multiple channels transmit data simultaneously, this invention provides an FPGA-based SRIO multi-channel control system, comprising: N transmit channels, N receive channels, a transmit interface of SRIO IP, a receive interface of SRIO IP, and an FPGA-based SRIO multi-channel control device. Each transmit channel is connected to a first memory, and each receive channel is connected to a second memory. Each first memory is communicatively connected to a transmit module in the FPGA-based SRIO multi-channel control device. The transmit module in the FPGA-based SRIO multi-channel control device is connected to the transmit interface of the SRIO IP. Each second memory is communicatively connected to a receive module in the FPGA-based SRIO multi-channel control device. The receive module in the FPGA-based SRIO multi-channel control device is connected to the receive interface of the SRIO IP. N is a natural number greater than 1.

[0049] In embodiments of the present invention, such as Figure 1The diagram shown is a block diagram of an FPGA-based SRIO multichannel control system.

[0050] Specifically, both the first and second memories are dual-port RAMs, or more specifically, simple dual-port RAMs, where port A contains 16 bits of data and port B contains 64 bits of data.

[0051] Specifically, the FPGA-based SRIO multi-channel control system further includes: a transmit acknowledgment interface for SRIO IP and a receive feedback interface for SRIO IP. The transmit acknowledgment interface for SRIO IP is connected to the transmit module in the FPGA-based SRIO multi-channel control device, and the receive feedback interface for SRIO IP is connected to the receive module in the FPGA-based SRIO multi-channel control device.

[0052] In this embodiment of the invention, all interfaces exposed by the SRIO IP are AXI4-stream interfaces. The transmit interface MSGIREQ and the transmit acknowledgment interface MSGIRESP are the interfaces connected to the transmit module 100. Data from all transmit channels of the local SRIO node needs to be converted into HELLO packets using these two sets of interfaces. The receive interface MSGTREQ and the receive feedback interface MSGTRESP are the interfaces received from the peer SRIO. The receive module 200 processes the HELLO packets and converts them into data output from the receive channel.

[0053] Specifically, in combination Figure 2 As shown, the sending module 100 can fill the mailbox parameter of the MSGIREQ packet with the number of sending channels to be sent (assuming it is channel M) to realize local SRIO data transmission; after the transmission is completed, the sending channel (M) enters the waiting confirmation state, and the sending module 100 can still continue to send data to other sending channels.

[0054] When MSGIRESP receives a RESP packet (with TargetTID information equal to M), the sending channel M transitions from the waiting-for-acknowledgment state to the received-acknowledgment state. At this point, the sending channel M assumes that the peer SRIO has correctly received the previously sent data.

[0055] In the receive control processing logic, the initial state is that an MSG packet header has been received from the MSGTREQ interface. Based on the mailbox parameter (assumed to be N, with a maximum support of 64), the receive channel for this MSG packet is N. At the same time, the valid data payload is extracted and converted into the output timing of the receive channel N. After completion, an RESP packet is sent to the MSGTRESP interface, with its TargetTID parameter filled with N, to realize the response feedback of the peer's SRIO packet.

[0056] The above FPGA-based SRIO multi-channel control system enables the transmission of multiple data streams with different time domains and speeds between SRIO links.

[0057] The specific working process of the above-mentioned FPGA-based SRIO multi-channel control device is described below.

[0058] In this embodiment of the invention, an FPGA-based SRIO multi-channel control device is provided for implementing the FPGA-based SRIO multi-channel control method described above. The FPGA-based SRIO multi-channel control device includes:

[0059] The sending module is used to acquire the transmission data from N transmission channels, where N is a natural number greater than 1. The interface timing of each transmission channel is a preset channel interface timing, and the transmission data of each transmission channel is stored in the memory corresponding to the transmission channel. The transmission data from the N transmission channels is processed according to priority order to obtain the information to be sent arranged in priority order. The information to be sent is then sent sequentially through the transmission interface of the SRIO IP.

[0060] The receiving module is used to acquire received data from the receiving interface of the SRIO IP, parse the received data to determine the corresponding receiving channel, wherein the number of receiving channels is the same as the number of transmitting channels; and write the parsed received data into the memory corresponding to the receiving channel.

[0061] In this embodiment of the invention, the sending module mainly includes a priority control module and a sending control state machine, specifically as follows: Figure 3 As shown, the core of the dual-port RAM module is a simple dual-port RAM, where port A contains 16 bits of data and port B contains 64 bits of data.

[0062] The write section writes data from the multi-channel interface timing transmission section to port A of the dual-port RAM. When I_srio_tx_enable is high, the I_srio_tx_addr[15:0] / I_srio_tx_datain[15:0] signals are written to the address and data sections of the dual-port RAM, respectively. The data stored at address 0 has its highest bit as the status bit and its lowest bit as the number of words. The read section is controlled by the "transmission control state machine".

[0063] The Round-Robin priority control module processes the order of SRIO packets sent by channels of different importance according to the priority order of different input channels.

[0064] The principle of Round-Robin is to distribute requests from the input interfaces to the internal sending and processing logic in turn, starting from priority 1 (highest priority) and going up to priority N (lowest priority), and then restarting the loop to achieve sequential execution of each task. At the same time, each input interface has an Aging (changing value) to ensure that tasks that have been waiting for a long time can still be executed.

[0065] Each channel is assigned a priority number, which serves as the starting value for the Aging Countdown. In other words, processes with higher priority will count down to 0 earlier (i.e., the highest priority) and thus be executed sooner.

[0066] The sending control state machine is a module that reads data from the corresponding RAM output by the priority control module and converts it into the timing of the MSGIREQ and MSGIRESP interfaces.

[0067] like Figure 4 As shown, the receiving module mainly includes a receive control state machine. Data transmitted via the SRIO interfaces MSGTREQ and MSGTRESP first enters the "receive control state machine." After parsing the MSG packets, the number of channels in the mailbox is determined and written to the corresponding "receive dual-port RAM." Finally, the RESP packet is sent to the MSGTRESP interface. After completing this operation, the reception of SRIO multi-channel data is complete.

[0068] The receive control state machine implements the logic for processing the MSGTREQ and MSGTRESP interfaces of the SRIO IP. This module receives data from the MSGTREQ interface, parses the mailbox value in the frame header of the MSG packet to determine the receive channel corresponding to the received SRIO packet, and simultaneously receives the payload of the SRIO packet and writes it to the subsequent receive dual-port RAM module. After completing this operation, it sends the RESP packet to the MSGTRESP interface.

[0069] Accordingly, this embodiment provides an FPGA-based SRIO multi-channel control method. Figure 5 This is a flowchart of an FPGA-based SRIO multi-channel control method according to an embodiment of the present invention, as shown below. Figure 5 As shown, it includes:

[0070] S100, Sending Process:

[0071] S110. Obtain the transmission data of N transmission channels, where N is a natural number greater than 1. The interface timing of each transmission channel is a preset channel interface timing. The transmission data of each transmission channel is stored in the memory corresponding to the transmission channel.

[0072] In this embodiment of the invention, the transmitted data includes multiple SRIO data packets. Each SRIO data packet includes a header, a valid data payload, and a CRC checksum. The header includes an MSG packet and a RESP packet from a HELLO packet. The MSG packet contains parameters indicating the number of channels in the current transmitting channel, and the RESP packet contains parameters indicating the number of channels in the current receiving channel. Figure 6 The image shown is a schematic diagram of the HELLO frame header format.

[0073] In this embodiment of the invention, the mailbox parameter of the MSG packet and the TargetTID parameter unique to the RESP packet are used to represent the channel number information of the current sending channel and receiving channel.

[0074] It should be understood that, in this embodiment of the invention, the preset channel interface timing includes: a clock signal, a reset signal, a data valid flag signal, an address signal, a data signal, and a ready flag signal.

[0075] like Figure 7 The figure shows the preset channel interface timing used in this embodiment of the invention, which includes 6 signals: clock CLK, reset RST_N, data valid flag ENABLE, address ADDR, data DATA, and readiness flag READY. The data bit width is 16 bits.

[0076] Specifically, all signals are synchronization signals under the CLK clock. RST_N is low for reset. ENABLE, ADDR, and DATA must be valid when READY is high. When ENABLE is high, the DATA value at address ADDR=0 is the CTRL value. The CTRL value contains information such as the data length of one SRIO packet. The highest bit = 1 indicates that the SRIO transmission packet is valid, and the lower bits represent the packet length. The DATA value in the range of ADDR=1 to ADDR=N is the valid data for one SRIO transmission packet. Since an SRIO packet supports a maximum of 256 bytes, the maximum value of address bit N is 128.

[0077] When multiple data interfaces with different clock domains and different transmit / receive speeds are connected to the SRIO system, they can all be converted into the timing of the interface through extremely simple control logic, enabling the rapid application of SRIO.

[0078] The following example illustrates the process of converting the UART low-speed interface -RX to the timing of this preset channel interface:

[0079] (1) UART data starts with 0x55, CNT is the second byte, and ends with 0xAA;

[0080] (2) First, the module receives 0x55 and then starts the state machine;

[0081] (3) Received CNT;

[0082] (4) At this point, byte counting begins. After receiving CNT bytes, it is determined whether it is 0xAA. If it is not 0xAA, an error is output and the process returns to step 2. If it is 0xAA, then CNT represents the number of data bytes received.

[0083] (5) After receiving 0xAA, output the timing sequence shown in the figure above, where ENABLE; ADDR; DATA; correspond to the enable signal, address information (from address 1 to address CNT, and then to address 0), and data (from the first value to the CNT value, and then to the control bit).

[0084] S120. Prioritize the data transmitted from the N transmission channels to obtain the information to be transmitted arranged in priority order.

[0085] Specifically, in embodiments of the present invention, it may include:

[0086] The data transmitted from N transmission channels are processed according to priority order using a round-robin scheduling algorithm to obtain the information to be transmitted, arranged from high to low priority.

[0087] More specifically, the priority number and frequency change value of each transmission channel are determined, where a priority number of 1 indicates the highest priority and a priority number of N indicates the lowest priority, and the priority number of each transmission channel is used as the initial value of the frequency change value of that transmission channel;

[0088] The data transmitted through N transmission channels are sorted from highest to lowest priority. When data is transmitted through one of the transmission channels, the change in the number of transmissions for each transmission channel that has transmitted data is decremented by 1.

[0089] It is understood that the polling scheduling algorithm in this embodiment of the invention is specifically Round-Robin, which realizes the sequential processing of SRIO packets sent by channels of different importance according to the priority order of different input channels.

[0090] The principle of Round-Robin is to distribute requests from the input interfaces to the internal sending and processing logic in turn, starting from priority 1 (highest priority) and going up to priority N (lowest priority), and then restarting the loop to achieve sequential execution of each task. Meanwhile, each input interface has an Aging (timeout value) to ensure that tasks that have been waiting for a long time can still be executed.

[0091] Each channel is assigned a priority number, which serves as the starting value for the Aging Countdown. In other words, processes with higher priority will count down to 0 earlier (i.e., the highest priority) and thus be executed sooner.

[0092] like Figure 8 As shown, each transmission channel has a priority, for example, transmission channel 1 has priority X1; transmission channel 2 has priority X2... transmission channel N has priority Xn.

[0093] After completing the SRIO link initialization (both port_initialized and link_initialized are 1), it first enters the idle query state, and then enters the read channel X mode. The idle query and read channel X states cycle back and forth, that is, after reading the data of a certain channel, it first returns to the idle query state, and then enters the read channel X state.

[0094] First, read the highest priority channel MAX (Xmax). Simultaneously, decrement the Aging counter (Aging(max)) by 1. Check if the query status (by reading the most significant bit of I_srio_tx_datain when address I_srio_tx_addr is 0) is 1. If it is 1, begin reading data from channel MAX. If it is 0, proceed to query other channels X. After reading the data from channel MAX, enter the idle query state.

[0095] By repeating this process, both the priority order and the problem of low-priority polling failing for a long time can be addressed.

[0096] S130. The information to be sent is sequentially transmitted through the SRIO IP transmission interface;

[0097] In this embodiment of the invention, if it is necessary to confirm the sent message before continuing to send other channel messages, a send confirmation message is received through the send confirmation interface of SRIO IP.

[0098] Specifically, such as Figure 9 As shown, after power-on, in the C_idle state, after completing the SRIO link initialization (both port_initialized and link_initialized are 1), the transmit state machine enters the C_tx_idle state.

[0099] In the C_tx_idle state, it directly enters the C_tx_read_ram0 state.

[0100] In the C_tx_read_ram0 state, data at address 0 in the transmit dual-port RAM-0 of channel 0 is read. If the highest bit of the data at address 0 is 1, it means that there is data to be sent on this channel, and then the system enters the C_tx_send_start0 state.

[0101] If the highest bit is 0, then it enters the C_tx_read_ramn state.

[0102] In the C_tx_send_start0 state, it enters the C_tx_send_header state.

[0103] In the C_tx_read_ramn state, data is read from RAM address 0 of the channel according to the read channel order output by the Round-Robin module. If the highest bit of the data is 1, it means that there is data to be sent in the channel, and then enters the C_tx_send_header state; if the highest bit is 0, it returns to the C_tx_read_ram0 state and goes back to the read RAM-0 state.

[0104] In the C_tx_send_header state, check the msgireq_tready value of the MSGIREQ interface. If it is equal to 1, the MSGIREQ interface can be considered to be ready to send data, and then enter the C_tx_send_ready state.

[0105] In the C_tx_send_ready state, the data in the msgireq_tvalid and msgireq_tdata[63:0] = MSG packet header is output. Then, it enters the C_tx_send_data0_idle state.

[0106] In the C_tx_send_data0_idle state, it is necessary to determine whether the length of the data packet to be sent is 8 bytes. If it is less than or equal to 8 bytes, it directly enters the C_tx_send_last state; if it is greater than 8 bytes, it enters the C_tx_send_data state.

[0107] The C_tx_send_data status outputs msgireq_tvalid=1 and msgireq_tdata[63:0]=payload data to the MSGIREQ interface.

[0108] The C_tx_send_last status outputs msgireq_tvalid = 1.

[0109] msgireq_tvalid = 1, msgireq_tdata[63:0] = payload data sent to the MSGIREQ interface. In this state, the transmission of a complete SRIO packet is finished. After completion, it enters the C_tx_send_end state.

[0110] In the C_tx_send_end state, it returns to the C_tx_idle state. At the same time, the corresponding channel's receive response state will be activated, waiting for the response packet from the peer's SRIO. Using this method, the continued transmission of channel data is not affected.

[0111] If the current transmission is for the Y-th channel, the receive response state of channel Y will enter the C_tx_receive_header state. At this time, this channel needs to wait for the MSGIRESP to respond with the corresponding channel's response packet. If the MSGIRESP interface receives msgiresp_tvalid = 1, and the msgiresp_tdata[63:54] value, i.e. the TargetTID value, is equal to Y, then the response to the data transmission from channel Y has been received. At this point, the entire transmission process for channel Y is complete.

[0112] Based on the above method, a pipelined data transmission across N channel interfaces can be achieved. After completing the transmission of one channel, data transmission from other channels can continue. Simultaneously, RESP packets can be received, ensuring the reliability of data transmission from each channel.

[0113] S200, Receiving Procedure:

[0114] S210. Obtain the received data from the receiving interface of the SRIO IP, and parse the received data to determine the corresponding receiving channel, wherein the number of receiving channels is the same as the number of sending channels;

[0115] S220. Write the parsed received data into the memory corresponding to the receiving channel.

[0116] In this embodiment of the invention, a reception confirmation message is sent through the SRIO IP receive feedback interface.

[0117] Specifically, when data is received from the MSGTREQ interface, the mailbox value in the frame header of the MSG packet is parsed to determine the receiving channel corresponding to the received SRIO packet. At the same time, the payload part of the SRIO packet is received and written to the subsequent receiving dual-port RAM module. After completing this operation, the RESP packet is sent to the MSGTRESP interface.

[0118] like Figure 10As shown, after power-on, the receiver state machine enters the C_idle state. After completing the SRIO link initialization, the transmitter state machine enters the C_rx_idle state.

[0119] In the C_rx_idle state, check if msgtreq_tvalid=1 has been received. If it has, directly enter the C_rx_treq_header state.

[0120] In the C_rx_treq_header state, if msgtreq_tvalid=1 is received, it is considered that the frame header of the MSG packet has been received, and the state enters the C_rx_treq_data state; if msgtreq_tlast=1 is received, it is considered that the last 64-bit payload data of the MSG has been received, and the state enters the C_rx_treq_data state; if neither of these states is received, the state enters the C_rx_treq_idle state.

[0121] In the C_rx_treq_data state, if msgtreq_tlast=1 is received, then the last 64-bit payload data of MSG has been received, and the system enters the C_rx_treq_last state; if no data is received, the system enters the C_rx_treq_idle state.

[0122] In the C_rx_treq_idle state, if msgtreq_tvalid=1 is received, it is considered that the payload data of the MSG packet has been received, and the state enters the C_rx_treq_data state; if msgtreq_tlast=1 is received, it is considered that the last 64-bit payload data of the MSG has been received, and the state enters the C_rx_treq_last state; if neither of these states is received, the state remains unchanged.

[0123] In the C_rx_treq_last state, it is considered that an SRIO receive process is complete, and the data in the SRIO payload needs to be stored in the receive RAM module. The state then transitions to the C_rx_treq_end state.

[0124] In the C_rx_treq_end state, it enters the C_rx_resp_valid state, and the subsequent processing is the MSGTRESP interface.

[0125] In the C_rx_resp_valid state, check if msgtresp_tready is 1. If so, enter the C_rx_resp_ready state; if so, continue in the current state.

[0126] The C_rx_resp_ready state indicates that the RESP response packet has been sent.

[0127] In the C_rx_treq_header state, the SRIO channel of the received packet is determined from the TargetTID bit in the received SRIO packet header. At the same time, based on the msg_treq_data received in the C_rx_treq_last state, the payload part is parsed out and written to port A of the dual-port RAM.

[0128] The real-time monitoring flag bit of address 0 of port B is used to read the data stored in port B and convert it into the channel general timing. When the flag bit = 1, the data is read and converted into the channel general timing.

[0129] In summary, the FPGA-based SRIO multi-channel control method provided in this embodiment of the invention can reduce the complexity of using SRIO IP, while being compatible with direct expansion of up to 64 transmit and receive channels.

[0130] The following description, based on simulation, illustrates the effectiveness of the FPGA-based SRIO multi-channel control method.

[0131] like Figure 11 The figure shows the transmission timing simulation of the SRIO 3-channel system.

[0132] The priority order for this simulation is: Channel 2 > Channel 1 > Channel 3.

[0133] I_srio_tx_enable[0] / under I_sys_clk clock

[0134] I_srio_tx_addr[15:0] / I_srio_tx_datain[15:0] is the first channel. During the first four clock cycles, data 16'h1234, 16'h5678, 16'h9ABC, and 16'hDEF0 were written to addresses 1, 2, 3, and 4, respectively. During the fifth clock cycle, control data 16'h8004 was written to address 0. The highest bit = 1 represents the flag bit, and 4 represents the presence of 4 words.

[0135] I_srio_tx_enable[1] / I_srio_tx_addr[31:16] / I_srio_tx_datain[31:16] is the second channel. In the first four clock cycles, 16'h2345, 16'h6789, 16'hABCD, and 16'hEF10 data were written to addresses 1, 2, 3, and 4 respectively. In the fifth clock cycle, control data 16'h8004 was written to address 0. The highest bit = 1 represents the flag bit, and 4 represents that there are 4 words stored.

[0136] The simulation timing for converting the transmit channel to an MSGIREQ interface is as follows: Figure 12 As shown.

[0137] As shown in the diagram, the frame header data is 64'h00B0207000000012, and the transmitted data is 64'hEF10ABCD67892345. The mailbox bit is 1, representing channel 2. The diagram also shows that channel 2 sends data first, implementing priority-based transmission order control.

[0138] The timing of the transmission channel receiving the response packet from the peer's SRIO is as follows: Figure 13 As shown.

[0139] exist Figure 13 At approximately 212,600 ns, the MSGIRESP interface receives a RESP packet with a header of 64'h01D1400000000000. The RESP packet's TargetTID = 1, indicating it is a response packet from MSG channel 2. Compared to the transmission channel MSGIREQ interface, its delay is (212600-208475) = 4125 ns, or 4.125 μs (SRIO line rate is 2.5 Gbps).

[0140] Timing simulation of data received by the receiving channel as follows: Figure 14 As shown, from Figure 14 As can be seen, the MSGTREQ of the receiving channel is 64'h00B0207000000002, and the MSG packet can be analyzed from the packet header as channel 1. The output interface of the receiving channel is also channel 1 enabled (O_srio_rx_enable[0]=1), and the receiving timing is consistent with the design.

[0141] In summary, through code implementation and simulation, the actual latency from packet transmission to acknowledgment on the same channel can be as low as approximately 4µs (2.5G line rate), demonstrating good reliability. Furthermore, since the number of transmit and receive channels is not limited and can be increased or decreased, multi-channel applications can be implemented by adding or removing transmit and receive channels without modifying SRIO.

[0142] In addition, the above-mentioned FPGA-based SRIO multi-channel control method, when applied to an FPGA-based SRIO multi-channel control system, can significantly save communication cables, improve system stability and reliability, and provide users with convenient interface use, which can greatly accelerate the application development of SRIO.

[0143] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An FPGA-based SRIO multi-channel control method, characterized in that, Comprise: Send flow: Obtain sending data of N sending channels, where N is a natural number greater than 1, the interface timing of each sending channel is a preset channel interface timing, and the sending data of each sending channel is stored in a memory corresponding to the sending channel; The sending data of the N sending channels are processed in priority order to obtain to-be-sent information arranged in priority order; The to-be-sent information is sent through a sending interface of an SRIO IP in sequence; After power-on, in the C_idle state, after completing SRIO link initialization, the sending state machine enters the C_tx_idle state; In the C_tx_idle state, directly enter the C_tx_read_ram0 state; In the C_tx_read_ram0 state, read the data at address 0 in the sending dual-port RAM-0 of channel 0, if the highest bit of the data at address 0 is 1, it means that the channel has to-be-sent data, then enter the C_tx_send_start0 state; if the highest bit is 0, enter the C_tx_read_ramn state; In the C_tx_send_start0 state, enter the C_tx_send_header state; In the C_tx_read_ramn state, read the data in the RAM address 0 of the channel according to the read channel order output by the Round-Robin module, if the highest bit of the data is 1, it means that the channel has to-be-sent data, then enter the C_tx_send_header state; if the highest bit is 0, return to the C_tx_read_ram0 state and return to the read RAM-0 state; In the C_tx_send_header state, judge the msgireq_tready value of the MSGIREQ interface, if it is equal to 1, it means that the MSGIREQ interface can send data, then enter the C_tx_send_ready state; In the C_tx_send_ready state, output msgireq_tvalid and msgireq_tdata[63:0]=MSG packet header data, and then enter the C_tx_send_data0_idle state; In the C_tx_send_data0_idle state, judge whether the length of the to-be-sent data packet is 8 bytes, if less than or equal to 8 bytes, directly enter the C_tx_send_last state; if greater than 8 bytes, enter the C_tx_send_data state; In the C_tx_send_data state, output msgireq_tvalid=1 and msgireq_tdata[63:0]=payload data to the MSGIREQ interface; C_tx_send_last state, output msgireq_tvalid=1, msgireq_tvalid=1, msgireq_tdata[63:0]=payload data to the MSGIREQ interface; after completion, enter the C_tx_send_end state; In the C_tx_send_end state, return to the C_tx_idle state; at the same time, the receiving response state machine of the corresponding channel is started, waiting for the response packet of the SRIO at the other end; If the current sending is the Yth channel, the receiving response state machine of the channel Y enters the C_tx_receive_header state, at which time the channel needs to wait for the MSGIRESP response to the response packet of the corresponding channel. If msgiresp_tvalid=1 is received from the MSGIRESP interface, and the value of msgiresp_tdata[63:54] is equal to Y, that is, the TargetTID value, the response to the Y channel sending data is received; Receiving process: Obtain the received data of the receiving interface of the SRIO IP, and parse the received data to determine the corresponding receiving channel, wherein the number of receiving channels is the same as the number of sending channels; Write the parsed received data into the memory corresponding to the receiving channel.

2. The FPGA-based SRIO multi-lane control method of claim 1, wherein, The sending data of the N sending channels is processed in priority order to obtain the to-be-sent information arranged in priority order, including: The sending data of the N sending channels is processed in priority order according to the round-robin scheduling algorithm to obtain the to-be-sent information arranged in priority order from high to low.

3. The FPGA-based SRIO multi-lane control method of claim 2, wherein, The sending data of the N sending channels is processed in priority order, including: Determine the priority number and the number change value of each sending channel, wherein the priority number 1 represents the highest priority, the priority number N represents the lowest priority, and the priority number of each sending channel is used as the initial value of the number change value of the sending channel. The sending data of the N sending channels is sorted in priority from high to low, and when the sending data of one of the sending channels is sent out, the number change value of each sending channel with sending data is calculated by subtracting 1.

4. The FPGA-based SRIO multi-lane control method of claim 1, wherein, The sending process further includes, after the step of sequentially sending the to-be-sent information through the sending interface of the SRIO IP: Receive a sending confirmation message through the sending confirmation interface of the SRIO IP.

5. The FPGA-based SRIO multi-lane control method of claim 1, wherein, The receiving process further includes, after the step of writing the parsed received data into the memory corresponding to the receiving channel: Send a receiving confirmation message through the receiving feedback interface of the SRIO IP.

6. The FPGA-based SRIO multi-lane control method of claim 1, wherein, The sending data includes a plurality of SRIO data packets, each of which includes a packet header, a valid data payload, and a CRC check bit, wherein the packet header includes a MSG packet and a RESP packet in the HELLO packet, the MSG packet is provided with a parameter representing the channel number information of the current sending channel, and the RESP packet is provided with a parameter representing the channel number information of the current receiving channel.

7. The FPGA-based SRIO multi-lane control method of claim 1, wherein, The preset channel interface timing includes a clock signal, a reset signal, a data valid flag signal, an address signal, a data signal and a preparation flag signal.

8. An FPGA-based SRIO multi-lane control device for implementing the FPGA-based SRIO multi-lane control method of any one of claims 1 to 7, characterized in that, The SRIO multi-channel control device based on the FPGA includes: The sending module is configured to: acquire sending data of N sending channels, where N is a natural number greater than 1, the interface timing of each sending channel is a preset channel interface timing, and the sending data of each sending channel is stored in a memory corresponding to the sending channel; perform priority order processing on the sending data of the N sending channels to obtain to-be-sent information arranged in a priority order; and send the to-be-sent information through a sending interface of the SRIO IP in sequence. The receiving module is configured to: acquire receiving data of a receiving interface of the SRIO IP, analyze the receiving data to determine a corresponding receiving channel, where the number of the receiving channels is the same as that of the sending channels, and write the analyzed receiving data into a memory corresponding to the receiving channel.

9. An FPGA-based SRIO multi-channel control system, characterized in that, The SRIO multi-channel control device based on the FPGA includes: N sending channels, N receiving channels, a sending interface of the SRIO IP, a receiving interface of the SRIO IP and the SRIO multi-channel control device based on the FPGA, each sending channel is connected with a first memory, each receiving channel is connected with a second memory, each first memory is in communication connection with a sending module in the SRIO multi-channel control device based on the FPGA, the sending module in the SRIO multi-channel control device based on the FPGA is connected with the sending interface of the SRIO IP, each second memory is in communication connection with a receiving module in the SRIO multi-channel control device based on the FPGA, and the receiving module in the SRIO multi-channel control device based on the FPGA is connected with the receiving interface of the SRIO IP, and N is a natural number greater than 1.

10. The FPGA-based SRIO multi-lane control system of claim 9, wherein, The SRIO multi-channel control device based on the FPGA further includes: The SRIO multi-channel control device based on the FPGA further includes: The SRIO multi-channel control device based on the FPGA further includes:

Images