A method and system for monitoring virtualization performance based on an airborne multi-core processing platform

Abstract

This invention belongs to the field of airborne computers in avionics systems, and specifically relates to a performance monitoring method and system based on an airborne multi-core processing platform virtualization. The method includes: configuring the PMU's event counter and period counter and enabling counting; reading the values ​​of the PMU's event counter and period counter to obtain performance data and obtaining monitoring results based on the performance data; after monitoring is completed, clearing the PMU counter configuration and deactivating the counting function. This improves self-monitoring capabilities and supports high-security design.

Description

Technical Field

[0001] This invention belongs to the field of airborne computers in avionics systems, and specifically relates to a method and system for monitoring the virtualization performance of an airborne multi-core processing platform. Background Technology

[0002] In recent years, with the rapid development of airborne avionics equipment in my country, embedded multi-core processors have begun to be widely used in core equipment of military and civilian airborne avionics. Typical examples include the PowerPC T1040 and T2080 series, the ARM-based IMX, LS1026, Xilinx MPSOC, domestic Phytium (dual-core, quad-core, octa-core) processors, HiSilicon processors, and Loongson processors based on the MIPS architecture. According to current processor development trends, embedded SoCs such as the Xilinx Zynq UltraScale MPSOC, applicable to avionics, and even those with integrated processor cores in the tens of thousands, will be increasingly used, leading to a rapid increase in processor integration and complexity.

[0003] Consequently, the design difficulty of the avionics software running on these systems has significantly increased. Currently, the core avionics hardware already in engineering application has become a highly generalized resource platform. It leverages the high integration of multi-core processors to support dozens or even hundreds of applications with different functions and security levels, while simultaneously ensuring that these applications are isolated from each other and can securely, reliably, and in real-time share external resources. In the context of the increasing emphasis on agile development in the avionics field, the application of multi-core processors not only places higher demands on application-oriented avionics system design but also presents unprecedented challenges to the design and implementation of processor-level software, operating systems, and even application software. Summary of the Invention

[0004] Purpose of the invention: To provide a virtualization performance monitoring method based on an airborne multi-core processing platform, which solves the problem of monitoring the software operation status of avionics systems when high integration and high security coexist, and provides a performance monitoring mechanism for the processor platform of airborne general computing platforms.

[0005] Technical solution:

[0006] A method for monitoring virtualization performance based on an onboard multi-core processing platform is provided, executed on an ARMv8 architecture processor, including:

[0007] Configure the PMU's event counter and period counter and enable counting;

[0008] Read the values ​​of the PMU's event counter and period counter to obtain performance data and obtain monitoring results based on the performance data;

[0009] After monitoring is complete, clear the PMU counter configuration and clear the counting enable.

[0010] Further, configure the PMU's event counter and enable counting, specifically including:

[0011] Enable EL0 to access all PMU registers;

[0012] Configure ELn's counting filter to record the number of events occurring at a specific level;

[0013] Configure the event number counted by each event counter by passing parameters;

[0014] Enable counter overflow interrupt;

[0015] Clear the counter to zero and enable counting.

[0016] Further, configure the PMU's cycle counter and enable counting, specifically including:

[0017] Enable EL0 to access all PMU registers;

[0018] Configure ELn counting filters to record application runtime at a specific level;

[0019] Clear the counter to zero and enable counting.

[0020] Furthermore, configuring the PMU's event counter also includes:

[0021] Add a counter for custom trigger events. When a custom event is triggered, the counter of user-triggered events is used to monitor the custom trigger events.

[0022] A virtualization performance monitoring system based on an airborne multi-core processing platform is also provided. This system is based on an ARMv8 architecture processor and includes:

[0023] The performance monitoring unit configuration module is used to configure the PMU's event counters and period counters and enable counting.

[0024] The performance monitoring unit reading module is used to read the values ​​of the PMU's event counter and period counter to obtain performance data and obtain monitoring results based on the performance data;

[0025] The performance monitoring unit stops the counting module to clear the PMU counter configuration and clear the counting enable after monitoring is completed.

[0026] Furthermore, the performance monitoring unit configuration module is specifically used for:

[0027] Enable EL0 to access all PMU registers;

[0028] Configure ELn's counting filter to record the number of events occurring at a specific level;

[0029] Configure the event number counted by each event counter by passing parameters;

[0030] Enable counter overflow interrupt;

[0031] Clear the counter to zero and enable counting.

[0032] Furthermore, the performance monitoring unit configuration module is specifically used for:

[0033] Enable EL0 to access all PMU registers;

[0034] Configure ELn counting filters to record application runtime at a specific level;

[0035] Clear the counter to zero and enable counting.

[0036] Furthermore, the performance monitoring unit configuration module is also used for:

[0037] Add a counter for custom trigger events. When a custom event is triggered, the counter of user-triggered events is used to monitor the custom trigger events.

[0038] Beneficial effects: This invention combines the performance monitoring function of the ARMv8 processor architecture and studies its application in the aviation field. It provides a performance monitoring software system for the virtualized software execution environment of the high-security and high-real-time airborne multi-core processor platform, thereby improving the self-monitoring capability of the airborne computer platform under the conditions of high-complexity software operation environment and high security requirements, and supporting high-security design. Attached Figure Description

[0039] Figure 1 This is a diagram of the components of a virtualization performance monitoring system based on an airborne multi-core processing platform.

[0040] Figure 2 This is a diagram illustrating the deployment method of a performance monitoring system;

[0041] Figure 3 This is a schematic diagram illustrating the steps involved in obtaining system performance data statistics.

[0042] Figure 4 This is a diagram illustrating the steps for obtaining statistics on custom-triggered events. Detailed Implementation

[0043] This invention combines embedded virtualization technology to research and explore its application in the aviation field, providing a performance monitoring method and system for the underlying support software of high-security and high-real-time airborne multi-core processor platforms.

[0044] 1. System Composition and Execution Method

[0045] This invention provides a performance monitoring system based on an airborne avionics embedded ARMv8 architecture multi-core hardware platform virtualization environment. The system includes four parts: a performance monitoring unit configuration module, a performance monitoring unit reading module, a performance monitoring unit stop counting module, and a performance monitoring unit user-triggered event counting module.

[0046] (1) System Composition

[0047] like Figure 1 As shown, this system collects processor performance data by accessing the Performance Monitoring Unit (PMU), provides an interface for selecting and configuring target parameters for monitoring, and provides an interface for obtaining performance data.

[0048] The performance monitoring unit configuration module provides performance monitoring configuration functions. By configuring the PMU's event counter and period counter, it enables the selection and configuration of target events to be monitored, the filtering of monitored events, and the enabling of counting.

[0049] The performance monitoring unit reading module provides the function of reading monitoring information, and obtains performance data by reading the values ​​of the PMU's event counter and period counter.

[0050] The performance monitoring unit's stop counting module is responsible for clearing the PMU counter configuration and clearing the counting enable.

[0051] The performance monitoring unit's custom trigger event counting module is responsible for increasing the count of custom trigger events. Users can monitor custom trigger events by calling the interface provided by the module.

[0052] (2) Execution method

[0053] This system, such as Figure 2 The performance monitoring system shown supports performance monitoring at three levels: EL0, EL1, and EL2. The EL2 level performance monitoring system is deployed within the hypervisor, while the EL1 and EL0 levels are deployed within the virtual machines responsible for managing the platform. The EL2 level performance monitoring function invokes the monitoring interfaces under EL2 through system calls from the performance monitoring systems _EL0 / EL1 within the managed virtual machines. Ultimately, this system is used by application software responsible for platform functionality, such as the management software within the virtual machines.

[0054] like Figure 3 The steps for obtaining system performance data statistics are as follows:

[0055] 1) Configure the PMU event counter or period counter;

[0056] 2) Read the event counter or period counter;

[0057] 3) Clear the PMU event counter or period counter configuration.

[0058] This system provides a special processor event (SW_INCR 0x00) monitoring feature. This event can be configured to an event counter, whose count increases as the user operates on the relevant registers. The user can customize the event trigger location to monitor user-defined events.

[0059] like Figure 4 The acquisition of user-triggered event statistics generally involves the following steps:

[0060] 1) Configure a PMU event counter as the SW_INCR event;

[0061] 2) Increase the event counter when a custom trigger event is executed;

[0062] 3) Read the event counter;

[0063] 4) Clear the event counter configuration.

[0064] 2. Performance Monitoring Unit Configuration Module

[0065] The Performance Monitoring Unit (PMU) configuration module is responsible for configuring the period counters and event counters of the Performance Monitoring Unit (PMU) and supports two operating modes: AArch32 and AArch64.

[0066] (1) Periodic counter configuration

[0067] The PMU (Power Management Unit) of an ARMv8 architecture processor includes a 64-bit cycle counter. This PMU cycle counter counts the CPU clock cycles, starts counting when enabled, and can be reset to zero, serving as a timer. The configuration function provided by this system allows for the configuration of the PMU cycle counter, enabling and disabling its operation. The PMU cycle counter configuration interface includes the following operations: enabling EL0 access, configuring ELn counting filtering based on passed parameters, resetting the count to zero, and enabling counting.

[0068] Step 1: Enable EL0 access.

[0069] By default, PMU registers cannot be accessed at the EL0 level. Since this system runs on EL0 and requires configuration of PMU registers, the cycle counter configuration interface first enables EL0 to access all PMU registers.

[0070] The period counter configuration interface is implemented by configuring PMUSERENR_EL0 in kernel mode (in AArch64 running mode) or PMUSERENR (in Aarch32 running mode).

[0071] Step 2: Configure ELn counting filter.

[0072] The ARMv8 architecture classifies software execution privileges into four exception levels: EL0, EL1, EL2, and EL3. EL0 has the lowest software execution privileges; execution at EL0 is called unprivileged execution. EL1 provides support for the (Supervisor, Abort, IRQ, FIQ, Undefined, System) mode set. EL2 provides support for processor virtualization. EL3 provides support for security monitoring. Exception levels from 1 to 3 represent increases in software execution privileges, and the exception level changes upon exception occurrence and return.

[0073] The cycle counter configuration module provides parameter selection for whether the cycle counter increments under different exception levels. For example, disabling EL1 counting will prevent the cycle counter value from incrementing under the EL1 exception level, effectively filtering the EL1 count. The cycle counter configuration interface is implemented by configuring PMCCFILTR_EL0 (in AArch64 running mode) or PMCCFILTR (in Aarch32 running mode). Through ELn's counting filtering function, the application's runtime at specific levels can be recorded.

[0074] Step 3: Reset the counter to zero.

[0075] Before enabling the counter, the count value in the current cycle counter needs to be cleared to zero. The cycle counter configuration interface is implemented by configuring PMCR_EL0 (in AArch64 running mode) or PMCR (in Aarch32 running mode).

[0076] (2) Event counter configuration

[0077] The PMU of the ARMv8 architecture contains up to 31 event counters, the number of which can be obtained from the register PMCR_EL0 (PMCR).

[0078] Each event counter can count 32-bit or 64-bit (PMU Extensions v3.5), but different processors may have different numbers of event counters, such as ARM. The A53's PMU contains six 32-bit event counters:

[0079] The PMU's event counters can count CPU architecture and microarchitecture events, each with a unique event number. This system provides configuration functionality to configure the PMU's event counters. The interface parameters include the event counter number (0-31), ELn filter configuration, and count event number configuration.

[0080] The PMU event counter configuration interface includes the following operations: enabling EL0 access, configuring ELn count filtering according to the passed parameters, configuring the count event number of each counter according to the passed parameters, enabling count overflow interrupt, clearing the count to zero, and enabling counting.

[0081] Step 1: Enable EL0 access.

[0082] By default, PMU registers cannot be accessed at EL0 level. Since this system runs at EL0 and requires configuration of PMU registers, the event counter configuration interface will first enable EL0 to access all PMU registers.

[0083] The period counter configuration interface is implemented by configuring PMUSERENR_EL0 in kernel mode (in AArch64 running mode) or PMUSERENR (in Aarch32 running mode).

[0084] Step 2, Configure ELn counting filter

[0085] The execution privileges of software in the ARMv8 architecture are divided into four exception levels: EL0, EL1, EL2, and EL3. EL0 has the lowest software execution privileges, and execution at EL0 is called unprivileged execution. EL1 provides support for the (Supervisor, Abort, IRQ, FIQ, Undefined, System) mode set. EL2 provides support for processor virtualization. EL3 provides support for security monitoring.

[0086] The period counter configuration function allows you to select whether each event counter increments its count under different exception levels. For example, if you do not enable EL1 counting for event counter 1, then event counter 1 will not count events that occur under the EL1 exception level, i.e., EL1 counting is filtered out.

[0087] The event counter configuration interface is configured through PMEVTYPER. <n>_EL0 (while AArch64 is running) or PMEVTYPER <n>(This is implemented while Aarch32 is running)

[0088] ELn's counting and filtering function can be used to record the number of times events occur at a specific level.

[0089] Step 3, Configure event types

[0090] The event counter configuration interface configures the event number for each event counter by passing parameters. The event counter configuration interface is accessed by configuring PMEVTYPER. <n>_EL0 (while AArch64 is running) or PMEVTYPER <n>(This is implemented while Aarch32 is running)

[0091] Step 4: Enable counter overflow interrupt

[0092] Since the event counter may overflow, this system needs to enable the overflow interrupt. When the count overflows, the overflow interrupt is triggered. The number of overflow triggers is counted in the overflow interrupt handling function. The calculation is performed when reading the PMU count value, and the actual count is returned.

[0093] The PMU's cycle counter supports 64-bit counting, which is sufficient to count the CPU clock cycles (at a CPU frequency of 4GHz, cycle count overflow would take more than 136 years), so there is no need to handle count overflow in the configuration of the cycle counter. Similarly, when the effective count bits of the event counter are 64-bit (in Aarch64 mode), the event count value is also unlikely to overflow.

[0094] Therefore, the PMU's count overflow interrupt is only set when the valid count bits of the event counter are 32-bit (in Aarch32 state). The event counter configuration interface is implemented by configuring PMINTENSET.

[0095] Step 5: Reset the counter to zero.

[0096] Before enabling the counting function, the count values ​​in all current event counters need to be cleared to zero. The overflow count should also be cleared to zero.

[0097] The event counter configuration interface is implemented by configuring PMCR_EL0 (in AArch64 running mode) or PMCR (in Aarch32 running mode).

[0098] Step 6, Enable Counting

[0099] The count value will only start accumulating after the PMU's event counter is enabled. The period counter configuration interface is implemented by configuring PMCNTENSET_EL0 (in AArch64 running mode) or PMCNTENSET (in Aarch32 running mode).

[0100] 3 Performance monitoring unit reading module

[0101] The performance monitoring unit's reading module is responsible for reading the period counter and event counter.

[0102] (1) Periodic counter reading

[0103] The PMU contains a 64-bit period counter. This system provides a read interface to read the current period counter value. Before reading, it is necessary to ensure that access to the PMU via EL0 is enabled. The PMU's period counter read interface reads the period counter value and returns the 64-bit period counter value.

[0104] The cycle counter reading module reads the value of the cycle counter by reading PMCCNTR_EL0 (in AArch64 running mode) or PMCCNTR (in Aarch32 running mode) and returns the 64-bit cycle counter value.

[0105] (2) Event counter reading

[0106] The PMU contains multiple event counters. This system provides an interface to read the count value of a specified event counter and return the current count value and the actual count value. The read interface includes a parameter specifying the event counter number. Before reading, it is necessary to ensure that access to the PMU via EL0 is enabled. The PMU's periodic counter read interface reads the value of the event counter and returns the actual count value.

[0107] The event counter reading module reads PMEVCNTR. <n>_EL0 (while AArch64 is running) or PMEVCNTR <n>(While Aarch32 is running) Read the count value v1 of the currently specified event counter.

[0108] Since the overflow interrupt is set only when the effective count bits of the event counter are 32-bit, the number of overflow triggers must be multiplied by the effective count bits of the event counter (32 bits) to get v2, and v1 and v2 are returned together. The actual count value is v2+v1.

[0109] When the effective count bits of the event counter are 64-bit, the actual count value returned is the count value v1 of the currently specified event counter.

[0110] Take the three events Exception taken, Last Level cache access, and Last Level cache mis as examples.

[0111] When it is necessary to monitor the serial port data response capability within a specified time range t, the number of serial port interrupts can be recorded by monitoring the Exceptiontaken event. After reading the count of the event, the number of interrupts generated per unit time can be calculated, thereby determining whether the actual response frequency of the serial port can reach the expected value.

[0112] When it's necessary to evaluate the impact of cache misses on the overall performance of virtualization software on a multi-core processor platform across multiple scenarios, monitoring can be performed by configuring and enabling Last Level cache access and Last Level cache miss events in each scenario. By comparing the number of these events, a reference can be provided for cache utilization efficiency, allowing for the selection of more optimized operating scenarios to improve the overall software performance.

[0113] (3) Custom event monitoring method

[0114] When users perform custom event monitoring using this system, they can utilize the event counter with event number 0x00 (SW_INCR event). The custom trigger event counter increment interface is implemented by configuring PMSW INC_EL0 (in AArch64 running mode) or PMSWINC (in Aarch32 running mode).

[0115] When configuring the performance monitoring unit, enable custom events.

[0116] Application software or real-time operating systems within the upper-level virtual machine can call the system's custom event triggering interface to trigger events. The counter value for the configured event number 0x00 (SW_INCR event) will increment by 1 for each event.

[0117] For example, when it is necessary to perform periodic deterministic monitoring of a periodic task within a virtual machine, a custom event-triggered monitoring function can be configured, and custom event triggering instructions can be inserted into the periodic task. By counting the number of custom events at different time periods (such as 100us, 500us, 1ms, 5ms, etc.), the accuracy of the actual period of the periodic task can be calculated, thereby determining the determinism of the periodic task.

[0118] 4. Performance monitoring unit stop counting module

[0119] When monitoring is complete and it is necessary to stop monitoring, the monitoring can be stopped through the performance monitoring unit's stop technology module.

[0120] The performance monitoring unit's stop counting module is responsible for stopping the counting of the event counter and the period counter.

[0121] The cycle counter stop counting module can be enabled by configuring PMCNTENSET_EL0 (in AArch64 running mode) or PMCNTENSET (in Aarch32 running mode).

[0122] Based on the parameters input to the event counter stop counting module: event counter number, clear the enable of the corresponding event counter.

[0123] The event counter stop counting interface is implemented by configuring PMCNTENSET_EL0 (in AArch64 running mode) or PMCNTENSET (in Aarch32 running mode).

[0124] This invention combines airborne multi-core virtualization technology to study ARMv8 performance monitoring functions, providing a performance monitoring software system for the underlying support software of high-security, high-real-time airborne multi-core processor platforms. It can improve the performance monitoring capabilities of the underlying airborne multi-core processor platform to a certain extent, which is beneficial to improving the reliability of the airborne multi-core processor virtualization software operating environment and can effectively control the impact of processor resources between virtual machines and applications under high integration. This system effectively improves the reliability of the operating system and underlying software of airborne computers in avionics systems. The application of this patent is independent of the hardware platform, has a wide range of applications, and has significant market prospects and economic benefits.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A virtualization performance monitoring method based on an airborne multi-core processing platform, executed on an ARMv8 architecture processor, characterized in that, include: Configure the PMU event counters and enable counting, specifically including: enabling EL0 to access all PMU registers; configuring ELn's counting filter to record the number of events at a specific level; configuring the event number counted by each event counter through parameter passing; enabling the count overflow interrupt; clearing the count and enabling counting again. Configure the PMU's cycle counter and enable counting, specifically including: enabling EL0 to access all PMU registers; configuring ELn count filtering to record application runtime at a specific level; clearing the count and enabling counting; Read the values ​​of the PMU's event counter and period counter to obtain performance data and obtain monitoring results based on the performance data; After monitoring is complete, clear the PMU counter configuration and clear the counting enable.

2. The method according to claim 1, characterized in that, Configuring the PMU's event counter also includes: Add a counter for custom trigger events. When a custom event is triggered, the counter of user-triggered events is used to monitor the custom trigger events.

3. A virtualization performance monitoring system based on an airborne multi-core processing platform, the system being based on an ARMv8 architecture processor, characterized in that... include: The performance monitoring unit configuration module is used to configure the PMU event counter to enable EL0's access to all PMU registers; Configure ELn's count filter to record the number of events occurring at a specific level; configure the event number counted by each event counter via parameters; enable the count overflow interrupt; clear the count and enable counting; used to configure the cycle counter and enable counting, specifically for: enabling EL0's access to all PMU registers; configuring ELn's count filter to record the application's runtime at a specific level; clearing the count and enabling counting; The performance monitoring unit reading module is used to read the values ​​of the PMU's event counter and period counter to obtain performance data and obtain monitoring results based on the performance data; The performance monitoring unit stops the counting module to clear the PMU counter configuration and clear the counting enable after monitoring is completed.

4. The system according to claim 3, characterized in that, The performance monitoring unit configuration module is also used for: Add a counter for custom trigger events. When a custom event is triggered, the counter of user-triggered events is used to monitor the custom trigger events.

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