A quantum computing task scheduling method, device and quantum computer operating system

Abstract

This application belongs to the field of quantum computing and discloses a quantum computing task scheduling method, device, and quantum computer operating system. The method includes: obtaining the current topology of a quantum chip; for quantum computing tasks represented by quantum circuits received up to the current moment, obtaining a quantum circuit that matches the current topology of the quantum chip based on the number of quantum bits contained in the quantum circuit as a quantum circuit to be processed; compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip; determining the execution time of the executable quantum circuit based on the timing of the executable quantum circuit; and determining the quantum computing task to be scheduled based on the priority of each executable quantum circuit. This application greatly improves the utilization rate of the computing resources of the quantum chip as a whole, improves the efficiency of quantum computing task scheduling, and jointly improves the computational efficiency of quantum computing.

Description

Technical Field

[0001] The present application relates to the field of quantum computing, and in particular to a method and device for scheduling quantum computing tasks and a quantum computer operating system. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, and to store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is considered a quantum computer. Quantum computers are a key technology under research because they can handle mathematical problems more efficiently than conventional computers. For example, they can reduce the time required to crack RSA keys from hundreds of years to just hours.

[0003] Current quantum computing only considers the waiting time of quantum computing tasks and the number of fully available complete quantum chips when scheduling tasks. Tasks are scheduled to unoccupied quantum chips on a first-come, first-served basis. This scheduling method greatly wastes quantum chip computing resources and affects computing efficiency. Summary of the Invention

[0004] The purpose of this application is to provide a quantum computing task scheduling method, device and quantum computer operating system to address the deficiencies in the existing technology. It can improve the utilization efficiency of quantum chip computing resources and improve computing efficiency.

[0005] One aspect of the present application provides a quantum computing task scheduling method, the method comprising:

[0006] Get the current topology of the quantum chip;

[0007] For quantum computing tasks represented by quantum circuits received up to the current moment, a quantum circuit matching the current topological structure of the quantum chip is obtained according to the number of quantum bits included in the quantum circuit as the quantum circuit to be processed;

[0008] Compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip;

[0009] determining an execution time of the executable quantum circuit according to the timing of the executable quantum circuit;

[0010] The quantum computing task to be scheduled is determined according to the priority of each executable quantum circuit, wherein the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

[0011] In the quantum computing task scheduling method described above, preferably, for the quantum computing tasks represented by quantum circuits received up to the current moment, obtaining a quantum circuit that matches the current topological structure of the quantum chip as the quantum circuit to be processed based on the number of quantum bits contained in the quantum circuit includes:

[0012] For the quantum computing tasks received up to the current moment, determine the quantum computing tasks to be analyzed in order from shortest to longest waiting time of the quantum computing tasks;

[0013] For the determined current quantum computing task to be analyzed, obtaining the number of quantum bits included in the corresponding quantum circuit;

[0014] Determining whether the number of corresponding quantum bits is less than or equal to the number of quantum bits contained in the current topological structure of the quantum chip;

[0015] If so, it is determined that the quantum circuit corresponding to the current quantum computing task to be analyzed is a quantum circuit to be processed.

[0016] In the quantum computing task scheduling method as described above, preferably, compiling the quantum circuit to obtain an executable quantum circuit that can be executed on the quantum chip includes:

[0017] Establishing a quantum bit mapping relationship between the quantum bits contained in the quantum circuit and the quantum bits contained in the current topological structure of the quantum chip;

[0018] The quantum circuit is processed based on the quantum bit mapping relationship to obtain an executable quantum circuit in which each quantum logic gate can be directly executed on the quantum chip.

[0019] In the quantum computing task scheduling method as described above, preferably, the processing of the quantum circuit based on the quantum bit mapping relationship includes:

[0020] Decomposition processing of the two-qubit logic gates and / or multi-qubit logic gates contained in the quantum circuit based on the qubit mapping relationship.

[0021] In the quantum computing task scheduling method as described above, preferably, the processing of the quantum circuit based on the quantum bit mapping relationship includes:

[0022] Optimizing the quantum circuit.

[0023] In the quantum computing task scheduling method as described above, preferably, determining the execution time of the executable quantum circuit according to the timing of the executable quantum circuit includes:

[0024] hierarchically dividing the timing of the executable quantum circuit according to the parallelism of the quantum computation;

[0025] The task execution time required for each layer of timing is determined based on the type of quantum logic gates contained in the sub-quantum circuits within the timing layer;

[0026] The execution time required for the quantum circuit is determined based on the task execution time required by all layer timings.

[0027] In the quantum computing task scheduling method described above, preferably, the task execution time required for each layer of the time sequence is determined based on the type of quantum logic gates contained in the sub-quantum circuit within the time sequence, including:

[0028] Get the first time it takes for each type of quantum logic gate to run on a quantum chip;

[0029] The longest first time corresponding to the quantum logic gate in each layer is determined as the task execution time required by the timing of this layer.

[0030] In the above-mentioned quantum computing task scheduling method, preferably, the priority calculation formula is as follows:

[0031]

[0032] The priority of each executable quantum circuit determines the quantum computing task to be scheduled, including:

[0033] The quantum computing tasks to be scheduled are determined from high to low priority.

[0034] The quantum computing task scheduling method as described above, wherein preferably, the method further comprises:

[0035] Obtaining the proportion of quantum bits required for the executable quantum circuit in the quantum bits contained in the current topology of the quantum chip;

[0036] The quantum computing tasks to be scheduled are determined from low to high according to the proportions.

[0037] The quantum computing task scheduling method as described above, wherein preferably, the method further comprises:

[0038] The determined quantum computing task to be scheduled is sent to quantum computer hardware including the quantum chip to perform quantum computing.

[0039] Another aspect of the present application provides a quantum computing task scheduling device, the device comprising:

[0040] The quantum bit management service module is used to obtain the current topological structure of the quantum chip;

[0041] A quantum computing task scheduling management service module is configured to obtain, for quantum computing tasks represented by quantum circuits received up to a current moment, a quantum circuit that matches the current topological structure of the quantum chip based on the number of quantum bits contained in the quantum circuit as a quantum circuit to be processed;

[0042] A compilation optimization service module, configured to compile each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip;

[0043] an execution time determination module, configured to determine the execution time of the executable quantum circuit according to the timing of the executable quantum circuit;

[0044] The quantum computing task scheduling management service module is further configured to determine the quantum computing task to be scheduled according to the priority of each executable quantum circuit, wherein the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

[0045] Another aspect of the present application provides a storage medium storing a computer program, wherein the computer program is configured to execute any one of the above methods when running.

[0046] Another aspect of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute any one of the methods described above.

[0047] Another aspect of the present application provides a quantum computer operating system, which implements the scheduling of the quantum computing task according to any of the above-mentioned quantum computing task scheduling methods.

[0048] Yet another aspect of the present application provides a quantum computer, which includes the above-mentioned quantum computer operating system.

[0049] Compared with the prior art, in the process of scheduling quantum computing tasks, the present application obtains the dynamic resources of the quantum chip by obtaining the current topological structure of the quantum chip, and then obtains a quantum circuit that matches the current topological structure of the quantum chip according to the number of quantum bits contained in the quantum circuit to achieve preliminary matching of the quantum computing tasks to be scheduled. The preliminary matching quantum computing tasks are accurately matched with the dynamic resources of the quantum chip by compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip. Finally, the priority is scheduled, and the priority also takes into account the waiting time and execution time of the quantum computing tasks. This improves the overall utilization of the computing resources of the quantum chip, improves the efficiency of scheduling quantum computing tasks, and jointly improves the computing efficiency of quantum computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A hardware structure block diagram of a computer terminal for the quantum computing task scheduling method provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram of a quantum computing task scheduling method provided in an embodiment of the present application;

[0052] Figure 3.1 A quantum circuit for use in one embodiment;

[0053] Figure 3.2 A quantum chip topology used in one embodiment;

[0054] Figure 3.3 A quantum chip topology used in one embodiment;

[0055] Figure 4.1 A quantum circuit for use in one embodiment;

[0056] Figure 4.2 for Figure 4.1 The quantum circuit timing partitioning results of the embodiment shown;

[0057] Figure 5 Another embodiment of the present application provides a quantum computing task scheduling device. DETAILED DESCRIPTION

[0058] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0059] The embodiment of the present invention first provides a quantum computing task scheduling method, which can be applied to electronic devices such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0060] The following describes it in detail by taking running on a computer terminal as an example. Figure 1 The hardware structure block diagram of a computer terminal for a quantum computing task scheduling method provided by an embodiment of the present invention. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data. Optionally, the computer terminal may also include a transmission device 106 for communication functions and an input and output device 108. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0061] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / modules corresponding to the quantum computing task scheduling method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0062] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0063] It's important to note that a true quantum computer has a hybrid architecture, consisting of two main components: a classical computer, responsible for performing classical computations and control, and a quantum device, responsible for running quantum programs and thus achieving quantum computations. A quantum program is a sequence of instructions written in a quantum language, such as QRunes, that can be executed on a quantum computer. This supports quantum logic gate operations and ultimately enables quantum computations. Specifically, a quantum program is a sequence of instructions that operate quantum logic gates in a specific time sequence.

[0064] Quantum circuits, as a manifestation of quantum programs, also known as quantum logic circuits, are the most commonly used general quantum computing model. They represent circuits that operate on quantum bits in an abstract concept. They are composed of quantum bits, circuits (timelines), and various quantum logic gates. Finally, the results often need to be read out through quantum measurement operations.

[0065] Unlike traditional circuits, which are connected by metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as connected by time. In other words, the state of the quantum bit naturally evolves over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated.

[0066] A quantum program as a whole corresponds to a single quantum circuit. The quantum program described in this disclosure refers to this quantum circuit, where the total number of qubits in this quantum circuit is the same as the total number of qubits in the quantum program. A quantum program can be understood as consisting of a quantum circuit, measurement operations on the qubits in the quantum circuit, registers storing the measurement results, and control flow nodes (jump instructions). A quantum circuit can contain tens, hundreds, or even thousands of quantum logic gate operations. The execution of a quantum program is the process of executing all quantum logic gates in a specific time sequence. It should be noted that the time sequence refers to the chronological order in which individual quantum logic gates are executed.

[0067] It's important to note that in classical computing, the most fundamental unit is the bit, and the most basic control mode is the logic gate. Circuits can be controlled by combining logic gates. Similarly, quantum logic gates are used to manipulate qubits. Quantum logic gates enable the evolution of quantum states. Quantum logic gates are the foundation of quantum circuits and are generally represented using unitary matrices. Unitary matrices are not only a matrix form but also a type of operation and transformation. Quantum logic gates are defined based on the number of qubits they act on. For example, the operation on one quantum bit is defined as a single-bit quantum logic gate, such as the common basic single-qubit logic gates: Hadamard gate (H gate, Hadamard gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, etc.; the operation on two quantum bits is defined as a two-bit quantum logic gate, such as the common basic two-bit quantum logic gates, such as CNOT gate, CR gate, CZ gate, iSWAP gate. The operation matrix corresponding to the basic two-bit quantum logic gate is 4*4 dimensional, and the values of the elements in the operation matrix are determined. There is also any two-qubit logic gate U acting on two quantum bits, and the corresponding operation matrix is 4*4 dimensional, but the values of the elements in the operation matrix are uncertain and are set by the programmer as needed; multi-bit quantum logic gates include Toffoli gate, etc.

[0068] like Figure 2 A quantum computing task scheduling method provided by an embodiment of the present application is shown, and the method includes:

[0069] S1, obtain the current topological structure of the quantum chip;

[0070] Specifically, a quantum chip is the processor that performs quantum computations in a quantum computer, and the qubits it contains are the processing units of the processor. Due to the development of quantum chip hardware manufacturing technology, the increase in the number and utilization of qubits on quantum chips is one of the factors that constrains quantum computing power. Therefore, it is necessary to rationally and fully utilize the qubits on the quantum chip when scheduling quantum computing tasks.

[0071] The topological structure of a quantum chip reflects the spatial characteristics of the quantum bits on the quantum chip. These spatial characteristics determine the usability of the quantum chip as a computing resource. The spatial characteristics of the quantum bits include the number, position, and connection relationship of the quantum bits contained in the quantum chip.

[0072] The current topology of a quantum chip reflects the current availability of the quantum chip as a computing resource, and can be determined based on the availability of qubits on the quantum chip. Examples of qubit availability include qubit occupancy and qubit fidelity, which determine whether the qubit is usable.

[0073] S2, for the quantum computing tasks represented by quantum circuits received up to the current moment, obtaining a quantum circuit that matches the current topological structure of the quantum chip according to the number of quantum bits contained in the quantum circuit as the quantum circuit to be processed;

[0074] Specifically, the number of quantum bits contained in the quantum circuit represents the quantum bit resources required to perform the corresponding quantum computing task. According to the number of quantum bits contained in the quantum circuit, a quantum circuit matching the current topological structure of the quantum chip can be obtained as the quantum circuit to be processed.

[0075] S3, compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip;

[0076] Specifically, the execution on the quantum chip requires, on the one hand, the current computing resources of the quantum chip, which is determined by the number of quantum bits contained in the current topological structure of the quantum chip; on the other hand, the quantum logic gates contained in the quantum circuit must be implementable on the quantum bits of the quantum chip. For example, if one or two quantum logic gates contained in the quantum circuit correspond to two characteristic bits, there must be an edge connection between the two mapped bits when the two characteristic bits are mapped to the quantum chip, then the two quantum logic gates can be directly implemented on the quantum chip.

[0077] Therefore, in order to obtain an executable quantum circuit that can be executed on the quantum chip, it is necessary to compile the quantum circuit to be processed according to the current topological structure of the quantum chip, so as to process the quantum logic gates contained in the quantum circuit to be processed into quantum logic gates that can be directly executed on the quantum chip. The quantum circuit composed of the latter is an executable quantum circuit.

[0078] S4, determining the execution time of the executable quantum circuit according to the time sequence of the executable quantum circuit;

[0079] Specifically, the timing of a quantum circuit represents the execution order and time of each quantum logic gate contained in the quantum circuit. The time required to execute the quantum circuit can be obtained based on the timing.

[0080] S5. Determine the quantum computing task to be scheduled according to the priority of each executable quantum circuit, wherein: the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

[0081] The quantum task scheduling method provided by the embodiment described in steps S1 to S5 determines the quantum circuits to be processed corresponding to the quantum computing tasks to be processed based on the current topological structure of the quantum chip, compiles each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip; determines the execution time of the executable quantum circuit based on the timing of the executable quantum circuit; and determines the quantum computing tasks to be scheduled based on the priority of each executable quantum circuit, wherein the priority is determined based on the execution time and the waiting time of the corresponding quantum computing task, thereby realizing the scheduling determination of the quantum computing tasks represented by the quantum circuit.

[0082] Compared with the prior art, which only considers the waiting time of quantum computing tasks and adopts a first-submit-first-run scheduling method without considering the dynamic resources of the quantum chip, the present application obtains the dynamic resources of the quantum chip by obtaining the current topological structure of the quantum chip during the scheduling of quantum computing tasks. Then, according to the number of quantum bits contained in the quantum circuit, a quantum circuit matching the current topological structure of the quantum chip is obtained to achieve preliminary matching of the quantum computing tasks to be scheduled. The preliminary matching quantum computing tasks are accurately matched with the dynamic resources of the quantum chip by compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip. Finally, the priority is scheduled, and the priority also takes into account the waiting time and execution time of the quantum computing tasks. This improves the overall utilization of the computing resources of the quantum chip, improves the efficiency of scheduling quantum computing tasks, and jointly improves the computing efficiency of quantum computing.

[0083] As one implementation of this embodiment, for a quantum computing task represented by a quantum circuit received up to the current moment, obtaining a quantum circuit that matches the current topological structure of the quantum chip as the quantum circuit to be processed based on the number of quantum bits included in the quantum circuit can be achieved by the following steps:

[0084] For quantum computing tasks received up to the current moment, the quantum computing tasks to be analyzed are determined in order from short to long according to the waiting time of the quantum computing tasks; for the determined current quantum computing task to be analyzed, the number of quantum bits corresponding to the quantum circuit is obtained; it is determined whether the number of corresponding quantum bits is less than or equal to the number of quantum bits included in the current topological structure of the quantum chip; if so, it is determined that the current quantum computing task to be analyzed is a quantum computing task to be processed.

[0085] It should be noted that the above process is implemented in a cyclic iterative manner. Specifically, a quantum computing task to be analyzed is determined each time according to the waiting time of the quantum computing task from short to long. For the current quantum computing task to be analyzed, a cyclic operation is started, that is, obtaining the number of quantum bits corresponding to the quantum circuit; judging whether the number of corresponding quantum bits is less than or equal to the number of quantum bits contained in the current topological structure of the quantum chip; if so, determining that the current quantum computing task to be analyzed is a quantum computing task to be processed, and compiling the quantum circuit to be processed (that is, the quantum computing task to be processed) to obtain an executable quantum circuit that can be executed on the quantum chip; and determining the execution time of the executable quantum circuit according to the timing of the executable quantum circuit.

[0086] If not, the next quantum computing task to be analyzed is determined by increasing the waiting time, and then the operation in the next cycle is started for the determined quantum computing task to be analyzed.

[0087] As an implementation manner of this embodiment, compiling the quantum circuit to obtain an executable quantum circuit that can be executed on the quantum chip includes:

[0088] Establishing a quantum bit mapping relationship between the quantum bits included in the quantum circuit and the quantum bits included in the current topological structure of the quantum chip; and processing the quantum circuit based on the quantum bit mapping relationship to obtain an executable quantum circuit in which each quantum logic gate can be directly executed on the quantum chip.

[0089] Specifically, establishing a quantum bit mapping relationship between the quantum bits contained in the quantum circuit and the quantum bits contained in the current topological structure of the quantum chip requires consideration of the mapping relationship between the number of quantum bits and the mapping relationship between the quantum bits. The connection relationship between the quantum bits is determined in the quantum circuit through quantum logic gates; the connection relationship between the quantum bits is determined in the current topological structure of the quantum chip based on the spatial characteristics of the quantum bits on the aforementioned quantum chip.

[0090] For example, a mapping example is provided in which both the number of qubits and the qubit connection relationship are satisfied, such as Figure 3.1The quantum circuits H1, U(1,2), CNOT(2,3), and CNOT(2,4) shown represent an H gate acting on q1, a U gate acting simultaneously on q1 and q2, a CNOT gate acting simultaneously on q2 and q3, and a CNOT gate acting simultaneously on q2 and q4. This quantum circuit contains four qubits and requires a connection between q1 and q2, a connection between q2 and q3, and a connection between q2 and q4.

[0091] like Figure 3.2 The quantum chip topology shown in the figure contains 6 quantum bits, Q1, Q2, Q3, Q4, Q5 and Q6. Figure 3.2 The quantum chip topology shown is similar to Figure 3.1 The quantum circuit shown satisfies the basic quantum bit number mapping conditions; considering that Figure 3.1 The connection relationship between the quantum bits in the quantum circuit shown and Figure 3.2 The connection relationship between the quantum bits in the quantum chip topology structure shown is determined, and the mapping result is determined to be q2 mapped to Q3 or Q4, and then the mapping bits corresponding to q1, q3 and q4 are determined as needed, illustratively, Q1, Q4 and Q5 respectively.

[0092] At this point, the process of processing the quantum circuit based on the quantum bit mapping relationship to obtain an executable quantum circuit in which each quantum logic gate can be directly executed on the quantum chip is entered. This process processes the quantum circuit, illustratively, such as optimizing the quantum circuit; the optimization operation of the quantum circuit can illustratively be a quantum circuit simplification optimization achieved by deleting two adjacent quantum logic gates whose common operation results are the unit matrix, or other optimization operations performed on the quantum circuit, without specific limitation.

[0093] For example, a mapping example is provided in which the number of qubits satisfies the requirement but the connection relationship of qubits does not satisfy the requirement, such as Figure 3.1 The quantum circuits H1, U(1,2), CNOT(2,3), and CNOT(2,4) shown represent the H gate acting on q1, the CNOT gate acting simultaneously on q1 and q2 for the first time, the CNOT gate acting simultaneously on q2 and q3, and the CNOT gate acting simultaneously on q2 and q4. This quantum circuit contains four qubits and requires a connection between q1 and q2, a connection between q2 and q3, and a connection between q2 and q4.

[0094] like Figure 3.3 The quantum chip topology when Q3 cannot be used is shown, which contains 5 quantum bits, Q1, Q2, Q4, Q5 and Q6. Figure 3.3 The quantum chip topology shown is similar to Figure 3.1The quantum circuit shown satisfies the basic quantum bit mapping conditions; considering that Figure 3.1 The connection relationship between the quantum bits in the quantum circuit shown and Figure 3.3 The connection relationship between quantum bits in the quantum chip topology structure shown is determined, and the mapping result is determined to be q2 mapped to Q4, and then the mapping bits corresponding to q1, q3 and q4 are determined as needed, illustratively, Q1, Q2 and Q6 respectively.

[0095] At this time, if Figure 3.1 The U(1, 2) gate in the quantum circuit shown cannot be directly implemented. At this time, the process of processing the quantum circuit based on the quantum bit mapping relationship to obtain an executable quantum circuit in which each quantum logic gate can be directly executed on the quantum chip is entered. This process processes the quantum circuit, illustratively including one of the decomposition of any two-qubit logic gate and the decomposition of a multi-qubit logic gate, or a combination thereof.

[0096] As an implementation manner of this embodiment, determining the execution time of the executable quantum circuit according to the time sequence of the executable quantum circuit includes:

[0097] The timing of the executable quantum circuit is divided into layers according to the parallelism of the quantum computation; the task execution time required for each layer of the timing is determined according to the type of quantum logic gates contained in the sub-quantum circuit within the timing layer; and the execution time required for the quantum circuit is determined according to the task execution time required for all layers of the timing.

[0098] The hierarchical division of the timing of the executable quantum circuit according to the parallelism of the quantum computation is exemplified as follows.

[0099] like Figure 4.1 In the quantum circuit shown, for each quantum bit, the first (first) quantum logic gate executed is H, H, RY, CNOT, and H respectively. Due to the parallelism of quantum computing, the single-qubit logic gate operations H(q[0]), H(q[1]), RY(q[2]), and H(q[4]) do not affect each other and can be divided into the same time sequence as quantum logic gates executed simultaneously in the first time sequence; however, for the two-quantum logic gate CNOT executed by q[3], the quantum bit operated by the CNOT gate at the same time is also q[4]. Compared with q[4], the CNOT gate belongs to the second quantum logic gate executed. q[4] can only be executed after the execution of the H gate is completed. If the CNOT gate is divided into the first time sequence, q[4] will execute the H gate and the CNOT gate at the same time, resulting in a conflict. Therefore, the CNOT gate can be postponed to the next time sequence for execution. The result of the time sequence hierarchical division is as follows: Figure 4.2 shown.

[0100] The task execution time required for each layer of timing is determined based on the quantum logic gate types contained in the sub-quantum circuits within the timing layer, including: obtaining the first time required for each type of quantum logic gate to run on the quantum chip; and determining the longest first time corresponding to the quantum logic gates in each layer as the task execution time required for the timing layer.

[0101] Will combine Figure 4.2 The second sequence shown illustrates the implementation process of determining the task execution time required for each layer of sequence based on the type of quantum logic gates contained in the sub-quantum circuit within the layer of sequence; Figure 4.2 The second sequence shown includes single-qubit logic gates RX(q[0]), X(q[1]) and two-qubit logic gates CNOT(q[4],q[3]). The quantum chip executes the single-qubit logic gate t1 and the two-qubit logic gate t2. The specific values of t1 and t2 are related to the performance of the quantum computing-related hardware built including the quantum chip. However, empirically, the specific value of t2 is greater than the specific value of t1, so t2 is determined to be the task execution time required for the second sequence.

[0102] Then, Figure 4.2 The execution time required for the quantum circuit is obtained by adding up the task execution times required for the first to sixth time sequences shown.

[0103] The execution time required for the quantum circuit determined through the above process takes into account the timing characteristics of the quantum circuit, that is, the inherent parallelism characteristics of the quantum computing task based on the quantum circuit, which can be used to improve the efficiency of task scheduling.

[0104] As an implementation of this embodiment, the priority calculation formula is as follows:

[0105]

[0106] Determining the quantum computing tasks to be scheduled based on the priorities of the executable quantum circuits includes: determining the quantum computing tasks to be scheduled according to the priorities from high to low.

[0107] The priority determined by the above description is used to determine the quantum computing tasks to be scheduled from high to low, which fully considers the parallelism of quantum computing. Priority is also introduced through task duration and waiting time, so that quantum computing tasks with long waiting time and short execution time can be scheduled and executed first, thereby improving task scheduling efficiency.

[0108] As an implementation of this embodiment, the method further includes:

[0109] Obtaining a proportion of quantum bits required for the executable quantum circuit in the quantum bits contained in the current topological structure of the quantum chip; and determining quantum computing tasks to be scheduled from low to high according to the proportion.

[0110] As an implementation of this embodiment, the method further includes: determining the quantum computing tasks to be scheduled based on the priorities from low to high and the proportions from low to high. This improves the efficiency of task scheduling and the utilization rate of the quantum bits on the quantum chip.

[0111] As an implementation of this embodiment, the method further includes a scheduling execution process, namely:

[0112] The determined quantum computing task to be scheduled is sent to quantum computer hardware including the quantum chip to perform quantum computing.

[0113] It can be seen that in the scheduling process of quantum computing tasks in this embodiment, the dynamic resources of the quantum chip are obtained by obtaining the current topological structure of the quantum chip, and then a quantum circuit matching the current topological structure of the quantum chip is obtained according to the number of quantum bits contained in the quantum circuit to achieve preliminary matching of the quantum computing tasks to be scheduled. The preliminary matching quantum computing tasks are accurately matched with the dynamic resources of the quantum chip by compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip. Finally, scheduling is performed according to priority, and the priority also takes into account the waiting time and execution time of the quantum computing tasks. This greatly improves the overall utilization of the computing resources of the quantum chip, improves the efficiency of scheduling quantum computing tasks, and jointly improves the computing efficiency of quantum computing.

[0114] like Figure 5 As shown, another embodiment of the present application provides a quantum computing task scheduling device, the device comprising:

[0115] The quantum bit management service module 501 is used to obtain the current topological structure of the quantum chip;

[0116] The quantum computing task scheduling management service module 502 is configured to obtain, for quantum computing tasks represented by quantum circuits received up to a current moment, a quantum circuit that matches the current topology of the quantum chip based on the number of quantum bits contained in the quantum circuit as a quantum circuit to be processed;

[0117] A compilation optimization service module 503 is configured to compile the quantum computing task to be processed to obtain an executable quantum circuit that can be executed on the quantum chip;

[0118] An execution time determination module 504 is configured to determine the execution time of the executable quantum circuit according to the timing of the executable quantum circuit;

[0119] The quantum computing task scheduling management service module 502 is further configured to determine the quantum computing task to be scheduled according to the priority of each executable quantum circuit, wherein the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

[0120] Another embodiment of the present application provides a storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0121] Specifically, in this embodiment, the above-mentioned storage medium may be configured to store a computer program for performing the following steps:

[0122] S1, obtain the current topological structure of the quantum chip;

[0123] S2, for the quantum computing tasks represented by quantum circuits received up to the current moment, obtaining a quantum circuit that matches the current topological structure of the quantum chip according to the number of quantum bits contained in the quantum circuit as the quantum circuit to be processed;

[0124] S3, compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip;

[0125] S4, determining the execution time of the executable quantum circuit according to the time sequence of the executable quantum circuit;

[0126] S5. Determine the quantum computing task to be scheduled according to the priority of each executable quantum circuit, wherein: the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

[0127] Specifically, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0128] Another embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0129] Specifically, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0130] Specifically, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0131] S1, obtain the current topological structure of the quantum chip;

[0132] S2, for the quantum computing tasks represented by quantum circuits received up to the current moment, obtaining a quantum circuit that matches the current topological structure of the quantum chip according to the number of quantum bits contained in the quantum circuit as the quantum circuit to be processed;

[0133] S3, compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip;

[0134] S4, determining the execution time of the executable quantum circuit according to the time sequence of the executable quantum circuit;

[0135] S5. Determine the quantum computing task to be scheduled according to the priority of each executable quantum circuit, wherein: the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

[0136] Another embodiment of the present application provides a quantum computer operating system, wherein the quantum computer operation system implements the scheduling of the quantum computing tasks according to the quantum computing task scheduling method described in any of the above method embodiments.

[0137] Another embodiment of the present application provides a quantum computer, which includes the quantum computer operating system described in the above embodiment.

[0138] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present application.

Claims

1. A quantum computing task scheduling method, characterized in that: The method comprises: Get the current topology of the quantum chip; For quantum computing tasks represented by quantum circuits received up to the current moment, a quantum circuit matching the current topological structure of the quantum chip is obtained according to the number of quantum bits contained in the quantum circuit as the quantum circuit to be processed; Compiling each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip; determining an execution time of the executable quantum circuit according to the timing of the executable quantum circuit; The quantum computing task to be scheduled is determined according to the priority of each executable quantum circuit, wherein the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

2. The quantum computing task scheduling method according to claim 1, characterized in that: The step of obtaining, for a quantum computing task represented by a quantum circuit received up to a current moment, a quantum circuit matching the current topological structure of the quantum chip according to the number of quantum bits included in the quantum circuit as a quantum circuit to be processed includes: For the quantum computing tasks received up to the current moment, determine the quantum computing tasks to be analyzed in order from shortest to longest waiting time of the quantum computing tasks; For the determined current quantum computing task to be analyzed, obtaining the number of quantum bits included in the corresponding quantum circuit; Determining whether the number of corresponding quantum bits is less than or equal to the number of quantum bits contained in the current topological structure of the quantum chip; If so, it is determined that the quantum circuit corresponding to the current quantum computing task to be analyzed is a quantum circuit to be processed.

3. The quantum computing task scheduling method according to claim 1, characterized in that: Compiling the quantum circuit to be processed to obtain an executable quantum circuit that can be executed on the quantum chip includes: Establishing a quantum bit mapping relationship between the quantum bits included in the quantum circuit to be processed and the quantum bits included in the current topological structure of the quantum chip; The quantum circuit to be processed is processed based on the quantum bit mapping relationship to obtain an executable quantum circuit in which each quantum logic gate can be directly executed on the quantum chip.

4. The quantum computing task scheduling method according to claim 3, characterized in that: The processing of the quantum circuit based on the quantum bit mapping relationship includes: Decomposition processing of the two-qubit logic gates and / or multi-qubit logic gates contained in the quantum circuit based on the qubit mapping relationship.

5. The quantum computing task scheduling method according to claim 3, characterized in that: The processing of the quantum circuit based on the quantum bit mapping relationship includes: Optimizing the quantum circuit.

6. The quantum computing task scheduling method according to claim 1, characterized in that: The determining the execution time of the executable quantum circuit according to the time sequence of the executable quantum circuit includes: hierarchically dividing the timing of the executable quantum circuit according to the parallelism of the quantum computation; The task execution time required for each layer of timing is determined based on the type of quantum logic gates contained in the sub-quantum circuits within the timing layer; The execution time required for the quantum circuit is determined based on the task execution time required by all layer timings.

7. The quantum computing task scheduling method according to claim 6, characterized in that: The task execution time required for each layer of timing is determined based on the type of quantum logic gates contained in the sub-quantum circuit within the timing layer, including: Get the first time it takes for each type of quantum logic gate to run on a quantum chip; The longest first time corresponding to the quantum logic gate in each layer is determined as the task execution time required by the timing of this layer.

8. The quantum computing task scheduling method according to claim 1, characterized in that: The priority is calculated as follows: ； The priority of each executable quantum circuit determines the quantum computing task to be scheduled, including: The quantum computing tasks to be scheduled are determined from high to low priority.

9. The quantum computing task scheduling method according to claim 1, characterized in that: The method further comprises: Obtaining the proportion of quantum bits required for the executable quantum circuit in the quantum bits contained in the current topology of the quantum chip; The quantum computing tasks to be scheduled are determined from low to high according to the proportions.

10. The quantum computing task scheduling method according to any one of claims 1 to 9, characterized in that: The method further comprises: The determined quantum computing task to be scheduled is sent to quantum computer hardware including the quantum chip to perform quantum computing.

11. A quantum computing task scheduling device, characterized in that: The device comprises: The quantum bit management service module is used to obtain the current topological structure of the quantum chip; A quantum computing task scheduling management service module is configured to obtain, for quantum computing tasks represented by quantum circuits received up to a current moment, a quantum circuit that matches the current topological structure of the quantum chip based on the number of quantum bits contained in the quantum circuit as a quantum circuit to be processed; A compilation optimization service module, configured to compile each of the quantum circuits to be processed to obtain an executable quantum circuit that can be executed on the quantum chip; an execution time determination module, configured to determine the execution time of the executable quantum circuit according to the timing of the executable quantum circuit; The quantum computing task scheduling management service module is further configured to determine the quantum computing task to be scheduled according to the priority of each executable quantum circuit, wherein the priority is determined according to the execution time and the waiting time of the corresponding quantum computing task.

12. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 10 when executed.

13. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 10.

14. A quantum computer operating system, characterized in that: The quantum computer operating system implements the scheduling of the quantum computing task according to the quantum computing task scheduling method according to any one of claims 1 to 10.

15. A quantum computer, characterized in that The quantum computer comprises the quantum computer operating system according to claim 14.

Images