Display device

Abstract

A display device is provided. The display device comprises: a base substrate including a display area and a peripheral area other than the display area, wherein the peripheral area includes a bending area; a first test signal line and a second test signal line located on the peripheral area of ​​the base substrate and at least partially separated from each other; a crack detection line including at least a portion located on the bending area of ​​the base substrate and electrically connected to the first test signal line and the second test signal line; and a data line and a driving voltage line located on the display area of ​​the base substrate, wherein the data line and the driving voltage line are located on different layers, the data line and the crack detection line are located on different layers, and the crack detection line and the first test signal line and the second test signal line are located on different layers.

Description

[0001] This application is a divisional application of a patent application with an application date of May 7, 2018, application number 201810424931.2, and title “Display Device”. Technical Field

[0002] Aspects of embodiments of the inventive concept are directed to a display device. Background Art

[0003] As information technology develops, the market for display devices, which are a connection medium between users and information, is increasing. Therefore, the use of display devices such as liquid crystal displays and organic light emitting displays is increasing.

[0004] If the display device has flexibility, it can be bent, folded, or rolled up so as to be carried around. Therefore, the flexibility of the display device can make a significant contribution to ensuring portability while expanding the screen of the display device.

[0005] In this regard, research on flexible display devices is ongoing, and various attempts are being made to reduce the area of ​​a non-display region of the display device.

[0006] When at least a portion of a display device is bent, a conductive pattern such as a wiring located in the bent portion may be broken, thereby reducing the reliability of the display device. Summary of the invention

[0007] According to an aspect of the embodiments, a display device has a structure in which at least a portion of a peripheral area may be bent.

[0008] According to another aspect of the embodiment, a display device can detect a crack generated in a bent portion.

[0009] According to one or more embodiments, a display device includes: a base substrate including a display area and a peripheral area other than the display area, wherein the peripheral area includes a bending area; a first test signal line and a second test signal line located on the peripheral area of ​​the base substrate and at least partially separated from each other; a lower insulating layer located on the first test signal line and the second test signal line; a first test connection pattern located on the lower insulating layer and connected to the first test signal line; a second test connection pattern located on the lower insulating layer, separated from the first test connection pattern, and connected to the second test signal line; an upper insulating layer located on the first test connection pattern and the second test connection pattern; and a first crack detection line located on the upper insulating layer, connected to the first test connection pattern and the second test connection pattern, and having at least a portion overlapping with the bending area of ​​the base substrate.

[0010] According to one or more embodiments, a display device includes: a base substrate including a display area and a peripheral area other than the display area, wherein the peripheral area includes a bending area; a first test signal line and a second test signal line located on the peripheral area of ​​the base substrate and at least partially separated from each other; a crack detection line having at least a portion located on the bending area of ​​the base substrate and electrically connected to the first test signal line and the second test signal line; and a data line and a driving voltage line located on the display area of ​​the base substrate, wherein the data line and the driving voltage line are located on different layers, the data line and the crack detection line are located on different layers, and the crack detection line and the first test signal line and the second test signal line are located on different layers.

[0011] According to one or more embodiments, a display device includes: a base substrate including a display area and a peripheral area other than the display area, wherein the peripheral area includes a bending area; a first test signal line and a second test signal line located on the peripheral area of ​​the base substrate and at least partially separated from each other; a crack detection line having at least a portion located on the bending area of ​​the base substrate and electrically connected to the first test signal line and the second test signal line; a data line located on the display area of ​​the base substrate; a connection pad located on the peripheral area of ​​the base substrate; and a bridge wiring electrically connecting the data line and the connection pad, wherein the data line and the bridge wiring are located on different layers, the crack detection line and the bridge wiring are located on different layers, and the crack detection line and the first test signal line and the second test signal line are located on different layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] These and / or other aspects will become apparent and more readily understood through the following description of some example embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a plan view of a display device according to an embodiment;

[0014] Figure 2 is a diagram showing the bending along the bending area Figure 1 A perspective view of a display device;

[0015] Figure 3 yes Figure 2 A schematic cross-sectional view of a display device shown in FIG.

[0016] Figure 4 yes Figure 1 An equivalent circuit diagram of an embodiment of a pixel shown in FIG.

[0017] Figure 5 It is further shown in detail Figure 4 A plan view of an exemplary structure of a pixel;

[0018] Figure 6is along Figure 5 A cross-sectional view taken along line X1-X2;

[0019] Figure 7 is along Figure 5 A cross-sectional view taken along line X3-X4;

[0020] Figure 8 yes Figure 1 An enlarged plan view of area "Q1";

[0021] Fig. 9 is along Figure 8 A cross-sectional view taken along line X5-X6;

[0022] Fig.10 yes Figure 1 an enlarged plan view of area "Q2";

[0023] Fig.11 is along Fig.10 A cross-sectional view taken along line X7-X8;

[0024] Fig.12 is along Fig.10 A cross-sectional view taken along line X9-X10;

[0025] Fig.13 is along Fig.10 A sectional view taken along line X11-X12;

[0026] Fig.14 yes Figure 1 An enlarged plan view of area "Q3";

[0027] Fig.15 is along Fig.14 A sectional view taken along line X13-X14;

[0028] Fig.16 is along Fig.14 A sectional view taken along line X15-X16;

[0029] Fig.17 It is used to explain the use Fig.14 FIG. 1 is a diagram of a process for detecting cracks using a structure shown in FIG.

[0030] Fig.18 yes Fig.14 A plan view of a modified example of the structure shown in FIG.

[0031] Fig.19 is along Fig.18 A sectional view taken along line X17-X18;

[0032] Fig. 20 yes Fig.14 A plan view of a modified example of the structure shown in FIG.

[0033] Fig.21 is along Fig. 20 A sectional view taken along line X19-X20;

[0034] Fig. 22 It is used to explain the use Fig. 20 FIG. 1 is a diagram of a process for detecting cracks using a structure shown in FIG.

[0035] Fig.23 is along with Fig.10 A cross-sectional view of the display device according to the embodiment taken along a line corresponding to line X7-X8;

[0036] Fig.24 is along with Fig.10 The line X9-X10 corresponding to the line intercepted Fig.23 A cross-sectional view of a display device;

[0037] Fig.25 is along with Fig.10 The line X11-X12 corresponding to the line intercepted Fig.23 A cross-sectional view of a display device;

[0038] Fig.26 is along with Fig.14 A cross-sectional view of the display device according to the embodiment taken along a line corresponding to line X13-X14;

[0039] Fig. 27 is along with Fig.18 A cross-sectional view of the display device according to the embodiment taken along a line corresponding to line X17 - X18 ; and

[0040] Fig.28 is along with Fig. 20 A cross-sectional view of the display device according to the embodiment is taken along a line corresponding to line X19 - X20 . DETAILED DESCRIPTION

[0041] Some example embodiments are described with reference to the accompanying drawings. Example embodiments may be implemented in many different forms and should not be construed as being limited. Like reference numerals may represent like elements in the description.

[0042] Although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the "first" element discussed below can be named as the "second" element. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used here to distinguish different categories or element groups. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0043] The terms used herein are used to describe specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" may also include plural forms. The terms "include" and / or "comprise" may indicate that there are stated steps and / or elements, but may not exclude or add one or more other steps and / or elements.

[0044] When a first element is referred to as being "on", "connected to" or "coupled to" a second element, the first element may be directly on, directly connected to or directly coupled to the second element, or one or more intermediate elements may be present between the first and second elements. Conversely, when a first element (element) is referred to as being "directly on", "directly connected to" or "directly coupled to" a second element (element), no intermediate elements (elements) are intended to exist between the first element (element) and the second element (element) (except for ambient elements such as air). The term "and / or" may include any and all combinations of one or more of the relevant listed items.

[0045] Spatially relative terms such as "under," "beneath," "below," "above," and "above" may be used to describe the relationship of one element or feature to another element or feature. In addition to the described orientation, spatially relative terms may encompass different orientations of the device in use or operation. For example, if the device is turned over, an element described as "under" or "beneath" another element or feature will subsequently be positioned "above" the other element or feature. Thus, the term "under" may encompass both above and below positions. The device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors may be interpreted accordingly.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the context of the relevant art and their meaning in this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0047] In the drawings, the sizes of components may be exaggerated or reduced for convenience of explanation.

[0048] The term "pattern" may mean "component", "unit" or "element". The term "profile" may mean "cross-section". The term "connection" may mean "electrical connection". The term "insulation" may mean "electrical insulation" or "electrical isolation". The term "comprising" may mean "formed by..." and / or "including". The terms "overlay" or "cover" may be in a direction perpendicular to the bottom surface of the base substrate or according to a direction perpendicular to the bottom surface of the base substrate; that is, when a first element of a device overlaps or covers a second element of the device, the second element is partially or completely blocked by the first element when the device (or a combination of the first element and the second element) is viewed in a direction perpendicular to the base substrate of the device.

[0049] Throughout the specification, the same reference numerals in the drawings refer to the same or similar elements.

[0050] Here, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0051] Figure 1 is a plan view of a display device according to an embodiment. Figure 2 is a diagram showing the bending along the bending area BA Figure 1 A perspective view of a display device. Figure 3 yes Figure 2 Schematic cross-sectional view of a display device shown in FIG.

[0052] Reference Figures 1 to 3 , the display device may include: a base substrate 110; a display structure DS disposed on the base substrate 110; a scan driver 20; a conductor for detecting bending or cracking; a common voltage supply wiring ELVSSL; a driving voltage supply wiring ELVDDL; and a pad. The display structure DS may include a pixel structure PXS and an encapsulation layer 300. In some embodiments, the display device may further include a driver IC.

[0053] The base substrate 110 may be an insulating substrate and may include a plurality of regions. For example, the base substrate 110 may include a display area DA and a peripheral area NDA located around the display area DA, and the peripheral area NDA may include a bending area BA.

[0054] The base substrate 110 may include any of various materials (e.g., polymer materials) having flexible or bendable properties. For example, the polymer material may be polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination of these materials.

[0055] The display area DA of the base substrate 110 is an area for displaying an image. The pixel structure PXS may be disposed on the display area DA of the base substrate 110, and the encapsulation layer 300 may be located on the pixel structure PXS. Among the structures located on the display area DA of the base substrate 110, the pixel structure PXS may be defined as a structure located between the base substrate 110 and the encapsulation layer 300.

[0056] The pixel structure PXS may include: a plurality of scan lines S1, Si and Sn extending in a first direction y; a plurality of data lines D1, D2, D3 and Dm crossing the scan lines S1, Si and Sn and extending in a second direction x; a plurality of driving voltage wirings PL; and a plurality of pixels PX.

[0057] In some embodiments, each of the pixels PX may include a self-luminous element. In an exemplary embodiment, the self-luminous element may include at least one of an organic light emitting diode, a quantum dot light emitting diode, and an inorganic ultra-small light emitting diode (e.g., a micro-LED). In the embodiment, for ease of description, the case where the self-luminous element is an organic light emitting diode will be described as an example.

[0058] In some embodiments, each of the pixels PX may emit one of red light, green light, and blue light. However, the inventive concept is not limited to this case. For example, each of the pixels PX may emit light having a color such as cyan, magenta, yellow, or white.

[0059] The pixel PX will be described in more detail later.

[0060] The encapsulation layer 300 may prevent or substantially prevent moisture and air that may be introduced from the outside from penetrating the pixel structure PXS In an embodiment, the encapsulation layer 300 may include a first inorganic layer 310 , an organic layer 330 , and a second inorganic layer 350 .

[0061] The first inorganic layer 310 may be disposed on the pixel structure PXS. In an embodiment, the first inorganic layer 310 may include silicon oxide (SiO x), silicon nitride (SiN x ) and silicon oxynitride (SiON).

[0062] The organic layer 330 may be disposed on the first inorganic layer 310. In an embodiment, the organic layer 330 may include any one of epoxy, acrylate, and urethane acrylate.

[0063] The second inorganic layer 350 may be disposed on the organic layer 330. In an embodiment, the second inorganic layer 350 may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiON) any one or more.

[0064] exist Figure 3 , each of the first inorganic layer 310, the organic layer 330, and the second inorganic layer 350 is shown as a single layer. However, the inventive concept is not limited to this case. That is, at least one of the first inorganic layer 310, the organic layer 330, and the second inorganic layer 350 may have a multilayer structure.

[0065] In addition, when at least one of the first inorganic layer 310 and the second inorganic layer 350 has a multilayer structure, at least one of the first inorganic layer 310 and the second inorganic layer 350 having a multilayer structure may be a hexamethyldisiloxane (HMDSO) layer. The HMDSO layer can absorb stress. Therefore, the encapsulation layer 300 can be made more flexible. Alternatively, in an embodiment, the organic layer 330 can be changed to a HMDSO layer.

[0066] The peripheral area NDA of the base substrate 110 may be located around the display area DA. In some embodiments, the peripheral area NDA may surround the display area DA. The pixel structure PXS may not be disposed on the peripheral area NDA of the base substrate 110. That is, the peripheral area NDA of the base substrate 110 may be a non-display area where no image is displayed.

[0067] The scan driver 20, the common voltage supply wiring ELVSSL, the driving voltage supply wiring ELVDDL, the driving voltage supply pad VDP, the common voltage supply pad VSP, the connection wiring portions CL1, CL2, and CL3, the bridge wirings BL1, BL2, and BL3, the connection pad CN, the first crack detection line RL1, the first and second test signal lines TL1 and TL2, and the first and second test pads TP1 and TP2 may be disposed on the peripheral area NDA of the base substrate 110. In some embodiments, a driver IC and an input pad PP may also be disposed on the peripheral area NDA of the base substrate 110.

[0068] The scan driver 20 is connected to the scan lines S1, Si, and Sn, and generates a scan signal and transmits the scan signal to the pixel PX through the scan lines S1, Si, and Sn. In some embodiments, the scan driver 20 may be disposed on the left and right sides of the display area DA. In an embodiment, one scan driver 20 may be disposed on the left or right side of the display area DA.

[0069] The driving voltage supply wiring ELVDDL is connected to the driving voltage wiring PL and supplies the driving voltage to the pixel PX through the driving voltage wiring PL. The driving voltage supply wiring ELVDDL may be disposed on the base substrate 110 to surround at least a portion of the peripheral area NDA. In an embodiment, the driving voltage supply wiring ELVDDL may be disposed on one side of the display area DA to partially surround the display area DA, such as Figure 1 as shown in .

[0070] At least a portion of the driving voltage supply wiring ELVDDL may extend in the first direction y on the peripheral area NDA, and the other portion of the driving voltage supply wiring ELVDDL may extend in the second direction x to be connected to the driving voltage supply pad VDP on the peripheral area NDA of the base substrate 110 .

[0071] The common voltage supply wiring ELVSSL may provide a common voltage to the pixel PX. In an embodiment, the common voltage supply wiring ELVSSL may be electrically connected to a cathode electrode CD (see FIG. 1 ) to be described later in the peripheral area NDA. Figure 6 ) to provide a common voltage to the cathode CD.

[0072] The common voltage supply wiring ELVSSL may be disposed on the base substrate 110 to surround at least a portion of the peripheral area NDA, such as Figure 1 In an embodiment, the common voltage supply wiring ELVSSL may completely surround the display area DA.

[0073] At least a portion of the common voltage supply wiring ELVSSL may extend on the peripheral area NDA along the second direction x to be connected to the common voltage supply pad VSP located on the peripheral area NDA of the base substrate 110 .

[0074] The connection wiring portions CL1 , CL2 , and CL3 including the bridge wiring BL may be located on the peripheral area NDA of the base substrate 110 .

[0075] The first connection wiring portion CL1 among the connection wiring portions CL1, CL2, and CL3 electrically connects the first data line D1 to any one of the connection pads CN. The first connection wiring portion CL1 may include a first bridge wiring BL1 located on the bending area BA of the base substrate 110 among the bridge wirings BL. Similarly, the second connection wiring portion CL2 may electrically connect the second data line D2 to another one of the connection pads CN and may include a second bridge wiring BL2 located on the bending area BA among the bridge wirings BL. The third connection wiring portion CL3 may electrically connect the third data line D3 to another one of the connection pads CN and may include a third bridge wiring BL3 located on the bending area BA among the bridge wirings BL.

[0076] The structures of the connection wiring portions CL1 , CL2 , and CL3 will be described later in further detail.

[0077] In some embodiments, the driver IC may be disposed on the peripheral area NDA of the base substrate 110. In this case, the driver IC may be connected to the connection pad CN. The driver IC may generate and transmit a driving signal (e.g., a data signal) for driving the pixel PX. When the driver IC is disposed on the peripheral area NDA of the base substrate 110, an input pad PP electrically connected to the driver IC may be disposed on the peripheral area NDA of the base substrate 110.

[0078] In some embodiments, the driver IC may be a driver chip.

[0079] When the driver IC is disposed on the peripheral area NDA of the base substrate 110 , the input pad PP may be electrically connected to a printed circuit board (PCB) (not shown).

[0080] However, the inventive concept is not limited to this case. In an embodiment, if the driver IC is not disposed on the peripheral area NDA of the base substrate 110, the input pad PP may not be disposed. In this case, the connection pad CN may be electrically connected to the PCB, and the driver IC may be disposed on the PCB.

[0081] The first crack detection line RL1 may be located on the peripheral area NDA of the base substrate 110. The first crack detection line RL1 may be located on the bending area BA of the peripheral area NDA of the base substrate 110, and may include a plurality of bending portions.

[0082] When a crack occurs in the first crack detection line RL1 , the possibility that a crack will occur in wirings disposed on the bending area BA, such as the bridge wirings BL1 , BL2 , and BL3 , can be estimated.

[0083] In some embodiments, the first crack detection line RL1 may be disposed on both sides of the bridge wiring BL along the second direction x. Figure 1 However, in an embodiment, the first crack detection line RL1 may be disposed only on one side of the bridge wiring BL along the second direction x.

[0084] A first test signal line TL1 connected to one side of the first crack detection line RL1, a first test pad TP1 connected to the first test signal line TL1, a second test signal line TL2 connected to the other side of the first crack detection line RL1, and a second test pad TP2 connected to the second test signal line TL2 may be located on the peripheral area NDA of the base substrate 110.

[0085] A test signal for crack detection may be transmitted to the first test pad TP1 and the second test pad TP2. The test signal may be provided to the first crack detection line RL1 via the first test signal line TL1 and the second test signal line TL2. In addition, an output signal generated in response to the test signal may be output to the first test pad TP1 and the second test pad TP2 via the first test signal line TL1 and the second test signal line TL2.

[0086] In some embodiments, the first test signal line TL1 may include a first sub-test signal line TL1a and a second sub-test signal line TL1b connected to one side of the first crack detection line RL1. The first test pad TP1 may include a first sub-test pad TP1a connected to the first sub-test signal line TL1a and a second sub-test pad TP1b connected to the second sub-test signal line TL1b. Similarly, the second test signal line TL2 may include a third sub-test signal line TL2a and a fourth sub-test signal line TL2b connected to the other side of the first crack detection line RL1. The second test pad TP2 may include a third sub-test pad TP2a connected to the third sub-test signal line TL2a and a fourth sub-test pad TP2b connected to the fourth sub-test signal line TL2b.

[0087] In some embodiments, the first test signal line TL1 , the second test signal line TL2 , the first test pad TP1 , and the second test pad TP2 may be located on an area of ​​the peripheral area NDA of the base substrate 110 excluding the bending area BA.

[0088] The peripheral area NDA includes a bending area BA. The bending area BA may be disposed between the connection pad CN and the display area DA. The bending area BA may extend in a direction crossing the bridge wiring BL located on the peripheral area NDA. For example, the bending area BA may extend in a first direction y while having a certain width (e.g., a predetermined width) in a second direction x.

[0089] The display device according to the current embodiment may be bent at the bending area BA in a direction opposite to the third direction z. For example, a portion of the base substrate 110 of the display device may be bent in a direction opposite to the third direction z, such as Figure 2 As shown in . For example, the base substrate 110 may be bent about a bending axis extending in the first direction y. Therefore, the display device may also have a curved shape like the base substrate 110. That is, the area of ​​the peripheral area NDA visible to the user may be reduced by bending a portion of the peripheral area NDA in a direction opposite to the third direction z.

[0090] As mentioned above, the bridge wiring BL and the first crack detection line RL1 are located on the bending area BA of the peripheral area NDA of the base substrate 110. In addition, a portion of the driving voltage supply wiring ELVDDL and a portion of the common voltage supply wiring ELVSSL may be located on the bending area BA of the base substrate 110.

[0091] If the bridge wiring BL, a portion of the driving voltage supply wiring ELVDDL, and a portion of the common voltage supply wiring ELVSSL located on the bending area BA of the base substrate 110 are collectively referred to as a bending line BNC, the bending line BNC may be broken in the bending area BA due to tensile stress or compressive stress, thereby deteriorating the reliability of the display device. However, in the display device according to the current embodiment, the first crack detection line RL1 is located on the bending area BA of the base substrate 110. In addition, it is possible to detect whether a crack has occurred in the first crack detection line RL1 in the manufacturing process of the display device, and it is possible to judge that the bending line BNC has been broken from the crack in the first crack detection line RL1. That is, since the crack can be detected in the manufacturing process, the reliability of the display device can be improved.

[0092] In addition, it is possible to detect whether the first crack detection line RL1 has been broken even during use of the display device, and if the first crack detection line RL1 has been broken, the operation of the display device is stopped. This can prevent inconvenience to the user due to a malfunction.

[0093] Figure 4 yes Figure 1 An equivalent circuit diagram of an embodiment of a pixel PX is shown in FIG. Figure 4 , for ease of description, a pixel PX connected to a j-th data line Dj, an (i-1)-th scan line Si-1, an i-th scan line Si, and an (i+1)-th scan line Si+1 is shown.

[0094] Reference Figure 4, the pixel PX according to the current embodiment includes an organic light emitting diode OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0095] The anode of the organic light emitting diode OLED may be connected to the first transistor T1 via the sixth transistor T6, and the cathode of the organic light emitting diode OLED may be connected to a common power supply provided with a common voltage ELVSS. The organic light emitting diode OLED may generate light at a brightness level corresponding to the amount of current supplied from the first transistor T1.

[0096] The driving voltage ELVDD may be set to a voltage higher than the common voltage ELVSS so that current may flow through the organic light emitting diode OLED.

[0097] The seventh transistor T7 is connected between an initialization power supply provided with an initialization voltage Vint and an anode of the organic light emitting diode OLED. A gate electrode of the seventh transistor T7 is connected to the (i+1)th scan line Si+1. The seventh transistor T7 is turned on when a scan signal is transmitted to the (i+1)th scan line Si+1 to supply the initialization voltage Vint to the anode of the organic light emitting diode OLED. Here, the voltage of the initialization voltage Vint may be set to be lower than a data voltage supplied to the jth data line Dj.

[0098] The sixth transistor T6 is connected between the first transistor T1 and the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 is connected to the i-th emission control wiring Ei. The sixth transistor T6 is turned off when an emission control signal is supplied to the i-th emission control wiring Ei, and is turned on in other cases.

[0099] The fifth transistor T5 is connected between a driving power source supplied with a driving voltage ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 is connected to the i-th emission control wiring Ei. The fifth transistor T5 is turned off when an emission control signal is supplied to the i-th emission control wiring Ei, and is turned on in other cases.

[0100] A first electrode of the first transistor T1 (driving transistor) is connected to a driving power source provided with a driving voltage ELVDD via a fifth transistor T5, and a second electrode of the first transistor T1 is connected to an anode of the organic light emitting diode OLED via a sixth transistor T6. In addition, a gate electrode of the first transistor T1 is connected to a first node N1. The first transistor T1 controls the amount of current flowing from the driving power source provided with the driving voltage ELVDD via the organic light emitting diode OLED to the common voltage ELVSS according to the voltage of the first node N1.

[0101] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the i-th scan line Si. The third transistor T3 is turned on when the scan signal is supplied to the i-th scan line Si to electrically connect the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode form.

[0102] The fourth transistor T4 is connected between the first node N1 and the initialization voltage Vint. The gate electrode of the fourth transistor T4 is connected to the (i-1)th scan line Si-1. The fourth transistor T4 is turned on when the scan signal is transmitted to the (i-1)th scan line Si-1 to supply the voltage of the initialization voltage Vint to the first node N1.

[0103] The second transistor T2 is connected between the jth data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the ith scan line Si. The second transistor T2 is turned on when a scan signal is supplied to the ith scan line Si to electrically connect the jth data line Dj and the first electrode of the first transistor T1.

[0104] The storage capacitor Cst is connected between a driving power source supplied with the driving voltage ELVDD and the first node N1. The storage capacitor Cst stores a voltage corresponding to the data voltage and a threshold voltage of the first transistor T1.

[0105] Figure 5 It is further shown in detail Figure 4 A plan view of an exemplary structure of a pixel PX. Figure 6 is along Figure 5 A cross-sectional view taken along line X1-X2. Figure 7 is along Figure 5 A cross-sectional view taken along line X3-X4.

[0106] exist Figures 5 to 7 In FIG. 1 , three scanning lines Si-1, Si, and Si+1, an emission control wiring Ei, a driving voltage wiring PL, and a data line Dj connected to one pixel PX disposed in the i-th row and the j-th column are shown. Figures 5 to 7 In the figure, for ease of description, the scan line in the (i-1)th row will be referred to as the "(i-1)th scan line Si-1", the scan line in the i-th row will be referred to as the "i-th scan line Si", the scan line in the (i+1)th row will be referred to as the "(i+1)th scan line Si+1", the emission control wiring in the i-th row will be referred to as the "emission control wiring Ei", the data line in the j-th column will be referred to as the "data line Dj", and the drive voltage wiring in the j-th column will be referred to as the "drive voltage wiring PL".

[0107] Reference Figures 4 to 7, the display device according to the embodiment may include a base substrate 110 , a wiring portion, and a pixel PX.

[0108] The base substrate 110 includes a transparent insulating material and is capable of transmitting light. Since the base substrate 110 has been described above, a description of the base substrate 110 will be omitted.

[0109] The wiring portion supplies signals to the pixels PX, and may include scan lines Si-1, Si, and Si+1, a data line Dj, an emission control wiring Ei, a driving voltage wiring PL, and an initialization driving voltage wiring IPL.

[0110] The scan lines Si-1, Si, and Si+1 may extend in a first direction y. The scan lines Si-1, Si, and Si+1 may include an (i-1)th scan line Si-1, an i-th scan line Si, and an (i+1)th scan line Si+1 sequentially arranged along a second direction x intersecting the first direction y. Scan signals may be transmitted to the scan lines Si-1, Si, and Si+1. For example, the (i-1)th scan signal may be transmitted to the (i-1)th scan line Si-1, the i-th scan signal may be transmitted to the i-th scan line Si, and the (i+1)th scan signal may be transmitted to the (i+1)th scan line Si+1.

[0111] In one or more embodiments, three scan lines Si-1, Si and Si+1 are configured to transmit scan signals to the pixel PX. However, the scan signals may also be transmitted to the pixel PX via two scan lines Si-1 and Si. In this case, the i-th scan line Si among the two scan lines Si-1 and Si may be branched into two lines, and the lines branched from the i-th scan line Si may be connected to different transistors. For example, the i-th scan line Si may include an upper i-th scan line adjacent to the (i-1)th scan line Si-1 and a lower i-th scan line configured to be farther away from the (i-1)th scan line Si-1 than the upper i-th scan line.

[0112] The emission control wiring Ei extends in the first direction y and is disposed between the i-th scan line Si and the (i+1)-th scan line Si+1 to be separated or spaced apart from the i-th scan line Si and the (i+1)-th scan line Si+1. The emission control signal is transmitted to the emission control wiring Ei.

[0113] The data lines Dj may extend in the second direction x. Each of the data lines Dj may be sequentially arranged along the first direction y. A data signal (or a data voltage) may be provided to the data lines Dj.

[0114] The driving voltage wiring PL may extend in the second direction x. The driving voltage wiring PL may be separated or spaced apart from the data line Dj. Figure 4) may be applied to the driving voltage wiring PL. The driving voltage wiring PL may be double-layered. For example, the driving voltage wiring PL may include a driving voltage line PLb and an additional driving voltage line PLa. When viewed from above, the driving voltage line PLb may be disposed on the additional driving voltage line PLa to overlap with the additional driving voltage line PLa. The driving voltage line PLb may be electrically connected to the additional driving voltage line PLa through the twelfth contact hole CH12.

[0115] The initialization driving voltage wiring IPL may extend along the first direction y. The initialization driving voltage wiring IPL may be disposed between the (i+1)th scan line Si+1 and the (i-1)th scan line Si-1 of the pixel PX in the next row. An initialization voltage Vint may be applied to the initialization driving voltage wiring IPL.

[0116] The pixel PX may include an organic light emitting diode OLED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0117] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , a first drain electrode DE1 , and a first connection electrode CNL1 .

[0118] The first gate electrode GE1 may be connected to the third drain electrode DE3 of the third transistor T3 and the fourth drain electrode DE4 of the fourth transistor T4. The first connection electrode CNL1 may connect the first gate electrode GE1 to the third drain electrode DE3 and the fourth drain electrode DE4. One end of the first connection electrode CNL1 may be connected to the first gate electrode GE1 through the first contact hole CH1, and the other end of the first connection electrode CNL1 may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through the second contact hole CH2.

[0119] In an embodiment, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be made of a semiconductor layer doped or not doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 may be made of a semiconductor layer doped with impurities, and the first active pattern ACT1 may be made of a semiconductor layer not doped with impurities. That is, one semiconductor layer may form the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1, and may be divided into the first source electrode SE1, the first drain electrode DE1, and the first active pattern ACT1 according to whether or not they are doped with impurities.

[0120] The first active pattern ACT1 may be shaped like a strip extending in a certain direction (e.g., a predetermined direction) and may be bent multiple times along the longitudinal extension direction. When viewed from above, the first active pattern ACT1 may overlap the first gate electrode GE1. Since the first active pattern ACT1 is long, the channel region of the first transistor T1 may also be long. Therefore, the driving range of the gate voltage applied to the first transistor T1 becomes widened, and therefore, the grayscale of the light emitted from the organic light emitting diode OLED may be finely controlled.

[0121] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. In addition, the first drain electrode DE1 may be connected to the third source electrode SE3 of the third transistor T3 and the sixth source electrode SE6 of the sixth transistor T6.

[0122] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0123] The second gate electrode GE2 may be connected to the i-th scan line Si. The second gate electrode GE2 may be provided as a part of the i-th scan line Si, or may protrude from the i-th scan line Si. In an embodiment, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be made of a semiconductor layer doped with or not doped with impurities. For example, the second source electrode SE2 and the second drain electrode DE2 may be made of a semiconductor layer doped with impurities, and the second active pattern ACT2 may be made of a semiconductor layer not doped with impurities. The second active pattern ACT2 overlaps the second gate electrode GE2. The second source electrode SE2 has one end connected to the second active pattern ACT2 and the other end connected to the data line Dj through the sixth contact hole CH6. The second drain electrode DE2 has one end connected to the second active pattern ACT2 and the other end connected to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0124] In some embodiments, the third transistor T3 may have a dual-gate structure to prevent or substantially prevent leakage current. That is, the third transistor T3 may include a 3a-th transistor T3a and a 3b-th transistor T3b. The 3a-th transistor T3a may include a 3a-th gate electrode GE3a, a 3a-th active pattern ACT3a, a 3a-th source electrode SE3a, and a 3a-th drain electrode DE3a. The 3b-th transistor T3b may include a 3b-th gate electrode GE3b, a 3b-th active pattern ACT3b, a 3b-th source electrode SE3b, and a 3b-th drain electrode DE3b. In an embodiment, for ease of description, the 3a gate electrode GE3a and the 3b gate electrode GE3b will be referred to as the third gate electrode GE3, the 3a active pattern ACT3a and the 3b active pattern ACT3b will be referred to as the third active pattern ACT3, the 3a source electrode SE3a and the 3b source electrode SE3b will be referred to as the third source electrode SE3, and the 3a drain electrode DE3a and the 3b drain electrode DE3b will be referred to as the third drain electrode DE3.

[0125] The third gate electrode GE3 may be connected to the i-th scan line Si. The third gate electrode GE3 may be provided as a portion of the i-th scan line Si, or may protrude from the i-th scan line Si.

[0126] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be made of a semiconductor layer doped or not doped with impurities. For example, the third source electrode SE3 and the third drain electrode DE3 may be made of a semiconductor layer doped with impurities, and the third active pattern ACT3 may be made of a semiconductor layer not doped with impurities. The third active pattern ACT3 overlaps the third gate electrode GE3. One end of the third source electrode SE3 may be connected to the third active pattern ACT3. The other end of the third source electrode SE3 may be connected to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 may be connected to the third active pattern ACT3. The other end of the third drain electrode DE3 may be connected to the fourth drain electrode DE4 of the fourth transistor T4. In addition, the third drain electrode DE3 may be connected to the first gate electrode GE1 of the first transistor T1 through the first connection electrode CNL1, the second contact hole CH2, and the first contact hole CH1.

[0127] The fourth transistor T4 may have a dual-gate structure to prevent or substantially prevent leakage current. That is, the fourth transistor T4 may include a 4a-th transistor T4a and a 4b-th transistor T4b. The 4a-th transistor T4a may include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a. The 4b-th transistor T4b may include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. In an embodiment, for ease of description, the 4a gate electrode GE4a and the 4b gate electrode GE4b will be referred to as the fourth gate electrode GE4, the 4a active pattern ACT4a and the 4b active pattern ACT4b will be referred to as the fourth active pattern ACT4, the 4a source electrode SE4a and the 4b source electrode SE4b will be referred to as the fourth source electrode SE4, and the 4a drain electrode DE4a and the 4b drain electrode DE4b will be referred to as the fourth drain electrode DE4.

[0128] The fourth gate electrode GE4 may be connected to the (i-1)th scan line Si-1. The fourth gate electrode GE4 may be provided as a portion of the (i-1)th scan line Si-1, or may protrude from the (i-1)th scan line Si-1.

[0129] The fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 may be made of a semiconductor layer doped or not doped with impurities. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 may be made of a semiconductor layer doped with impurities, and the fourth active pattern ACT4 may be made of a semiconductor layer not doped with impurities. The fourth active pattern ACT4 overlaps the fourth gate electrode GE4.

[0130] One end of the fourth source electrode SE4 may be connected to the fourth active pattern ACT4. The other end of the fourth source electrode SE4 may be connected to the initialization drive voltage wiring IPL of the pixel PX in the (i-1)th row and the seventh drain electrode DE7 of the seventh transistor T7 of the pixel PX in the (i-1)th row. The auxiliary connection wiring AUX may be provided between the fourth source electrode SE4 and the initialization drive voltage wiring IPL. One end of the auxiliary connection wiring AUX may be connected to the fourth source electrode SE4 through the ninth contact hole CH9. The other end of the auxiliary connection wiring AUX may be connected to the initialization drive voltage wiring IPL of the pixel PX in the (i-1)th row through the eighth contact hole CH8 of the pixel PX in the (i-1)th row. One end of the fourth drain electrode DE4 may be connected to the fourth active pattern ACT4. The other end of the fourth drain electrode DE4 may be connected to the third drain electrode DE3 of the third transistor T3. The fourth drain electrode DE4 is also connected to the first gate electrode GE1 of the first transistor T1 through the first connection electrode CNL1, the second contact hole CH2, and the first contact hole CH1.

[0131] The fifth transistor T5 may include a fifth gate electrode GE5 , a fifth active pattern ACT5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0132] The fifth gate electrode GE5 may be connected to the emission control wiring Ei. The fifth gate electrode GE5 may be provided as a part of the emission control wiring Ei, or may protrude from the emission control wiring Ei. The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 may be made of a semiconductor layer doped or undoped with impurities. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 may be made of a semiconductor layer doped with impurities, and the fifth active pattern ACT5 may be made of a semiconductor layer undoped with impurities. The fifth active pattern ACT5 overlaps the fifth gate electrode GE5. One end of the fifth source electrode SE5 may be connected to the fifth active pattern ACT5. The other end of the fifth source electrode SE5 may be connected to the driving voltage wiring PL through the fifth contact hole CH5. One end of the fifth drain electrode DE5 may be connected to the fifth active pattern ACT5. The other end of the fifth drain electrode DE5 may be connected to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0133] The sixth transistor T6 may include a sixth gate electrode GE6 , a sixth active pattern ACT6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0134] The sixth gate electrode GE6 may be connected to the emission control wiring Ei. The sixth gate electrode GE6 may be provided as a part of the emission control wiring Ei, or may protrude from the emission control wiring Ei. The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 may be made of a semiconductor layer doped or not doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 may be made of a semiconductor layer doped with impurities, and the sixth active pattern ACT6 may be made of a semiconductor layer not doped with impurities. The sixth active pattern ACT6 overlaps the sixth gate electrode GE6. One end of the sixth source electrode SE6 may be connected to the sixth active pattern ACT6. The other end of the sixth source electrode SE6 may be connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 may be connected to the sixth active pattern ACT6. The other end of the sixth drain electrode DE6 may be connected to the seventh source electrode SE7 of the seventh transistor T7.

[0135] The seventh transistor T7 may include a seventh gate electrode GE7 , a seventh active pattern ACT7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 .

[0136] The seventh gate electrode GE7 may be connected to the (i+1)th scan line Si+1. The seventh gate electrode GE7 may be provided as a part of the (i+1)th scan line Si+1, or may protrude from the (i+1)th scan line Si+1. The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be made of a semiconductor layer doped or not doped with impurities. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 may be made of a semiconductor layer doped with impurities, and the seventh active pattern ACT7 may be made of a semiconductor layer not doped with impurities. The seventh active pattern ACT7 overlaps with the seventh gate electrode GE7. One end of the seventh source electrode SE7 may be connected to the seventh active pattern ACT7. The other end of the seventh source electrode SE7 may be connected to the sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 may be connected to the seventh active pattern ACT7. The other end of the seventh drain electrode DE7 may be connected to the initialization drive voltage wiring IPL. In addition, the seventh drain electrode DE7 may be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PX disposed in the (i+1)th row. The seventh drain electrode DE7 and the fourth source electrode SE4 of the fourth transistor T4 of the pixel PX disposed in the (i+1)th row may be connected through the auxiliary connection wiring AUX, the eighth contact hole CH8, and the ninth contact hole CH9.

[0137] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be made of the first gate electrode GE1 of the first transistor T1.

[0138] When viewed from above, the upper electrode UE may overlap with the lower electrode LE and cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by widening the overlapping area between the upper electrode UE and the lower electrode LE. The upper electrode UE may extend in the first direction y. In an embodiment, a voltage having the same level as the driving voltage ELVDD may be applied to the upper electrode UE. The upper electrode UE may have an opening OPN in a region in which the first contact hole CH1 is provided. The first gate electrode GE1 and the first connection electrode CNL1 are connected through the first contact hole CH1.

[0139] The organic light emitting diode OLED, which is a self-luminous element, may include an anode AD, a cathode CD, and a light emitting layer EML disposed between the anode AD and the cathode CD.

[0140] The anode AD may be disposed in a light emitting region corresponding to each pixel PX. The anode AD may be connected to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7 and the tenth contact hole CH10. The second connection electrode CNL2 and the bridge pattern BRP may be disposed in the seventh contact hole CH7 and the tenth contact hole CH10, respectively, to connect the sixth drain electrode DE6 and the seventh source electrode SE7 to the anode AD.

[0141] Here, we will refer to Figures 5 to 7 The structure of the display device according to the embodiment is described in a stacking order.

[0142] Active patterns ACT1 to ACT7 (herein, represented by "ACT") may be disposed on the base substrate 110. The active patterns ACT may include first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 may be made of a semiconductor material.

[0143] The buffer layer 111 may be disposed between the base substrate 110 and the active pattern ACT. The buffer layer 111 may be a layer including an inorganic material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) and / or an inorganic insulating layer of silicon oxynitride (SiON)).

[0144] The gate insulating layer 130 may be located on the base substrate 110 having the active pattern ACT. The gate insulating layer 130 may be a layer including an inorganic material such as silicon oxynitride (SiON), silicon oxide (SiO x ) and / or silicon nitride (SiN x )) of inorganic insulating layer.

[0145] The scan lines Si-1, Si and Si+1, the emission control wiring Ei and the first gate electrode GE1 to the seventh gate electrode GE7 may be disposed on the gate insulating layer 130. The first gate electrode GE1 may be the lower electrode LE of the storage capacitor Cst. The second gate electrode GE2 and the third gate electrode GE3 may be formed integrally with the i-th scan line Si. The fourth gate electrode GE4 may be formed integrally with the (i-1)th scan line Si-1. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be formed integrally with the emission control wiring Ei. The seventh gate electrode GE7 may be formed integrally with the (i+1)th scan line Si+1.

[0146] In an embodiment, the scan lines Si-1, Si and Si+1, the emission control wiring Ei, the first gate electrode GE1 and the seventh gate electrode GE7 may be made of the same material (e.g., a first conductive material) and may be disposed on the same layer. For example, the scan lines Si-1, Si and Si+1, the emission control wiring Ei, the first gate electrode GE1 and the seventh gate electrode GE7 may be made of a first conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti), and may all have a multilayer structure or a single-layer structure.

[0147] When elements are disposed on the same layer, they are located at the same level. In addition, when elements are disposed on the same layer, it means that they are stacked in the same order on the base substrate 110 and formed concurrently (eg, simultaneously) in the same process.

[0148] The first lower insulating layer 150 may be disposed on the base substrate 110 having the scan lines Si-1, Si, and Si+1, etc.

[0149] The upper electrode UE of the storage capacitor Cst and the initialization driving voltage wiring IPL may be disposed on the first lower insulating layer 150. The upper electrode UE may cover the lower electrode LE. The upper electrode UE and the lower electrode LE may form the storage capacitor Cst with the first lower insulating layer 150 interposed therebetween.

[0150] The upper electrode UE and the initialization driving voltage wiring IPL may be made of the same material and may be disposed on the same layer. For example, the upper electrode UE and the initialization driving voltage wiring IPL may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed in multiple layers or a single layer.

[0151] The second lower insulating layer 170 may be disposed on the base substrate 110 having the upper electrode UE and the initialization driving voltage wiring IPL.

[0152] Each of the first lower insulating layer 150 and the second lower insulating layer 170 may be a layer including an inorganic material such as silicon oxynitride (SiON), silicon oxide (SiO x ) and / or silicon nitride (SiN x )) of inorganic insulating layer.

[0153] The data line Dj, the additional driving voltage line PLa of the driving voltage wiring PL, the first connection electrode CNL1 , the second connection electrode CNL2 , and the auxiliary connection wiring AUX may be disposed on the second lower insulating layer 170 .

[0154] The data line Dj may be connected to the second source electrode SE2 through a sixth contact hole CH6 sequentially passing through the gate insulating layer 130 , the first lower insulating layer 150 , and the second lower insulating layer 170 .

[0155] The additional driving voltage line PLa of the driving voltage wiring PL may be connected to the upper electrode UE of the storage capacitor Cst by passing through the third contact hole CH3 and the fourth contact hole CH4 of the second lower insulating layer 170. In addition, the additional driving voltage line PLa of the driving voltage wiring PL may be connected to the fifth source electrode SE5 by passing through the fifth contact hole CH5 sequentially passing through the gate insulating layer 130, the first lower insulating layer 150, and the second lower insulating layer 170.

[0156] The first connection electrode CNL1 may be connected to the first gate electrode GE1 through a first contact hole CH1 sequentially passing through the first lower insulating layer 150 and the second lower insulating layer 170. In addition, the first connection electrode CNL1 may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2 sequentially passing through the gate insulating layer 130, the first lower insulating layer 150, and the second lower insulating layer 170.

[0157] The second connection electrode CNL2 may be a pattern provided as a medium provided between the sixth drain electrode DE6 and the anode AD to connect the sixth drain electrode DE6 and the anode AD. The second connection electrode CNL2 may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 sequentially passing through the gate insulating layer 130, the first lower insulating layer 150, and the second lower insulating layer 170.

[0158] The auxiliary connection wiring AUX may be connected to the initialization driving voltage wiring IPL by passing through the eighth contact hole CH8 of the second lower insulating layer 170. In addition, the auxiliary connection wiring AUX may be connected to the fourth source electrode SE4 and the seventh drain electrode DE7 of the pixel PX disposed in the (i-1)th row by passing through the ninth contact hole CH9 sequentially passing through the gate insulating layer 130, the first lower insulating layer 150, and the second lower insulating layer 170.

[0159] In an embodiment, the data line Dj, the additional driving voltage line PLa, the first connection electrode CNL1, the second connection electrode CNL2 and the auxiliary connection wiring AUX may be made of the same material (e.g., a second conductive material) and may be arranged on the same layer. For example, the data line Dj, the additional driving voltage line PLa, the first connection electrode CNL1, the second connection electrode CNL2 and the auxiliary connection wiring AUX may be made of a second conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti), and may be formed into a multilayer or a single layer. In some optional embodiments, the data line Dj, the additional driving voltage line PLa, the first connection electrode CNL1, the second connection electrode CNL2 and the auxiliary connection wiring AUX may have a multilayer structure of Ti / Al / Ti.

[0160] The first upper insulating layer 210 may be disposed on the base substrate 110 having the data line Dj and the like.

[0161] The bridge pattern BRP and the driving voltage line PLb of the driving voltage wiring PL may be disposed on the first upper insulating layer 210 .

[0162] The bridge pattern BRP may be connected to the second connection electrode CNL2 through the tenth contact hole CH10 passing through the first upper insulating layer 210 .

[0163] The driving voltage line PLb of the driving voltage wiring PL may be connected to the additional driving voltage line PLa through a twelfth contact hole CH12 passing through the first upper insulating layer 210 .

[0164] In an embodiment, the bridge pattern BRP and the driving voltage line PLb may be made of the same material (e.g., a third conductive material) and may be disposed on the same layer. For example, the bridge pattern BRP and the driving voltage line PLb may be made of a third conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed into a multilayer or a single layer. In some optional embodiments, the bridge pattern BRP and the driving voltage line PLb may have a multilayer structure of Ti / Al / Ti.

[0165] The second upper insulating layer 230 may be disposed on the base substrate 110 having the bridge pattern BRP or the like.

[0166] Each of the first upper insulating layer 210 and the second upper insulating layer 230 may be an organic insulating layer including an organic material. In an embodiment, the organic material may be an imide polymer, a generally common polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture of these materials.

[0167] The anode AD may be located on the second upper insulating layer 230. The anode AD may be connected to the bridge pattern BRP through the eleventh contact hole CH11 passing through the second upper insulating layer 230. Since the bridge pattern BRP is connected to the second connection electrode CNL2 through the tenth contact hole CH10, the anode AD may be finally connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the bridge pattern BRP and the second connection electrode CNL2.

[0168] The pixel defining layer 250 may be located on the base substrate 110 having the anode AD to define a light emitting region corresponding to each pixel PX. The pixel defining layer 250 may expose the upper surface of the anode AD and protrude from the base substrate 110 along the periphery of each pixel PX. The pixel defining layer 250 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0169] The light emitting layer EML may be disposed in a region surrounded by the pixel defining layer 250 , and the cathode CD may be disposed on the light emitting layer EML.

[0170] The encapsulation layer 300 may be located on the cathode CD to cover the cathode CD. The encapsulation layer 300 may include a first inorganic layer 310 located on the cathode CD, an organic layer 330 located on the first inorganic layer 310, and a second inorganic layer 350 located on the organic layer 330.

[0171] Figure 8 yes Figure 1 An enlarged plan view of area “Q1”. Fig. 9 is along Figure 8 A cross-sectional view taken along line X5-X6. Fig.10 yes Figure 1 An enlarged plan view of area “Q2”. Fig.11 is along Fig.10 A cross-sectional view taken along line X7-X8. Fig.12 is along Fig.10 A cross-sectional view taken along line X9-X10. Fig.13 is along Fig.10 A cross-sectional view taken along line X11-X12.

[0172] Reference Figure 1 and Figures 8 to 13 , the additional driving voltage line PLa extends upward along the second direction x to the peripheral area NDA to be connected to the driving voltage supply wiring ELVDDL. In some embodiments, the driving voltage supply wiring ELVDDL may be located on the same layer as the additional driving voltage line PLa. For example, the driving voltage supply wiring ELVDDL may be located on the second lower insulating layer 170.

[0173] If data lines sequentially arranged along the first direction y among the plurality of data lines are referred to as first, second, and third data lines D1, D2, and D3, the first, second, and third data lines D1, D2, and D3 may extend upward along the second direction x to the peripheral area NDA and may be separated or spaced apart from the driving voltage supply wiring ELVDDL.

[0174] The first connection wiring portion CL1 (see Figure 1 ) electrically connects the first data line D1 and the first connection pad CN1 among the connection pads CN located on the peripheral area NDA. The second connection wiring portion CL2 (see Figure 1 ) electrically connects the second data line D2 and the second connection pad CN2 located on the peripheral area NDA, and the third connection wiring portion CL3 (see Figure 1 ) electrically connects the third data line D3 and the third connection pad CN3 located on the peripheral area NDA.

[0175] The first connection wiring portion CL1 (see Figure 1 ) includes a first connection wiring CL1a, a second connection wiring CL1b, a first connection pattern CNP1a, a second connection pattern CNP1b, and a first bridge wiring BL1. The second connection wiring portion CL2 (see Figure 1 ) includes a third connection wiring CL2a, a fourth connection wiring CL2b, and a second bridge wiring BL2. In addition, the third connection wiring portion CL3 (see Figure 1 ) includes a fifth connection wiring CL3a, a sixth connection wiring CL3b, a third connection pattern CNP3a, a fourth connection pattern CNP3b and a third bridge wiring BL3.

[0176] The buffer layer 111 and the gate insulating layer 130 are located on the peripheral area NDA of the base substrate 110, and the first connection wiring CL1a, the third connection wiring CL2a, and the fifth connection wiring CL3a are arranged on the gate insulating layer 130 to be separated or spaced apart from each other. The first connection wiring CL1a, the third connection wiring CL2a, and the fifth connection wiring CL3a are insulated from the driving voltage supply wiring ELVDDL and intersect with the driving voltage supply wiring ELVDDL. The first connection wiring CL1a, the third connection wiring CL2a, and the fifth connection wiring CL3a may be located on the peripheral area NDA of the base substrate 110, but may not overlap with the bending area BA. In addition, when viewed from above, both sides of each of the first connection wiring CL1a, the third connection wiring CL2a, and the fifth connection wiring CL3a may be arranged to be outside the edge of the driving voltage supply wiring ELVDDL and not overlap with the driving voltage supply wiring ELVDDL.

[0177] The second connection wiring CL1b, the fourth connection wiring CL2b, and the sixth connection wiring CL3b are located on the gate insulating layer 130 to be separated or spaced apart from each other. The second connection wiring CL1b may be separated or spaced apart from the first connection wiring CL1a by a bending area BA disposed between the second connection wiring CL1b and the first connection wiring CL1a, and may be connected to the first connection pad CN1. In some embodiments, a portion of the second connection wiring CL1b may constitute the first connection pad CN1. Like the second connection wiring CL1b, the fourth connection wiring CL2b may be separated or spaced apart from the third connection wiring CL2a by a bending area BA disposed between the fourth connection wiring CL2b and the third connection wiring CL2a, and may be connected to the second connection pad CN2. In some embodiments, a portion of the fourth connection wiring CL2b may constitute the second connection pad CN2. In addition, the sixth connection wiring CL3b may be separated or spaced apart from the fifth connection wiring CL3a by a bending area BA disposed between the sixth connection wiring CL3b and the fifth connection wiring CL3a, and may be connected to the third connection pad CN3. In some embodiments, a portion of the sixth connection wiring CL3b may constitute the third connection pad CN3.

[0178] In an embodiment, the first connection wiring CL1a, the second connection wiring CL1b, the third connection wiring CL2a, the fourth connection wiring CL2b, the fifth connection wiring CL3a and the sixth connection wiring CL3b may be made of the same first conductive material as the scan lines Si-1, Si and Si+1, and may be arranged on the same layer as the scan lines Si-1, Si and Si+1. In an embodiment, the first conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti) as described above.

[0179] The first and second lower insulating layers 150 and 170 may be located on the first, second, third, fourth, fifth, and sixth connection wirings CL1a, CL1b, CL2a, CL2b, CL3a, and CL3b.

[0180] The first data line D1, the second data line D2, the third data line D3, and the driving voltage supply wiring ELVDDL may be located on the second lower insulating layer 170. The first data line D1 is connected to one side of the first connection wiring CL1a through a thirteenth contact hole CH13 passing through the first lower insulating layer 150 and the second lower insulating layer 170. The second data line D2 is connected to one side of the third connection wiring CL2a through a fourteenth contact hole CH14 passing through the first lower insulating layer 150 and the second lower insulating layer 170. The third data line D3 is connected to one side of the third connection wiring CL2a through a fifteenth contact hole CH15 passing through the first lower insulating layer 150 and the second lower insulating layer 170.

[0181] The first connection pattern CNP1 a , the second connection pattern CNP1 b , the third connection pattern CNP3 a , the fourth connection pattern CNP3 b , and the second bridge wiring BL2 , which are separated from each other, are positioned on the second lower insulating layer 170 .

[0182] The first connection pattern CNP1a is connected to the other side of the first connection wiring CL1a through the sixteenth contact hole CH16 passing through the first and second lower insulating layers 150 and 170. The third connection pattern CNP3a is connected to the other side of the fifth connection wiring CL3a through the twenty-second contact hole CH22 passing through the first and second lower insulating layers 150 and 170.

[0183] The second connection pattern CNP1b is connected to the second connection wiring CL1b through the nineteenth contact hole CH19 passing through the first and second lower insulating layers 150 and 170. The fourth connection pattern CNP3b is connected to the sixth connection wiring CL3b through the twenty-fifth contact hole CH25 passing through the first and second lower insulating layers 150 and 170.

[0184] Referring to the peripheral area NDA surrounding the bending area BA, each of the buffer layer 111 , the gate insulating layer 130 , the first lower insulating layer 150 , and the second lower insulating layer 170 disposed on the base substrate 110 may be made of the inorganic insulating layer described above.

[0185] In some embodiments, the inorganic insulating layer, such as the buffer layer 111 , the gate insulating layer 130 , the first lower insulating layer 150 , and the second lower insulating layer 170 , may have an opening OPB corresponding to the bending area BA.

[0186] The inorganic insulating layers 111, 130, 150, and 170 have significantly low flexibility and may be damaged by external forces due to their brittleness. Therefore, the inorganic insulating layers 111, 130, 150, and 170 of the bending area BA may be damaged by tension generated by bending, and the generated cracks may propagate to other portions. Cracks generated in the inorganic insulating layers 111, 130, 150, and 170 may cause breakage of wiring, which may cause malfunction of the display device.

[0187] According to an embodiment, the inorganic insulating layers 111, 130, 150, and 170 include openings OPB corresponding to the bending areas BA to prevent cracks from occurring due to stress or reduce the possibility of cracks occurring. In some embodiments, the openings OPB may extend in a direction parallel to the bending axis (eg, a first direction y).

[0188] The stress release layer 220 may be disposed in the opening OPB corresponding to the bending area BA. The stress release layer 220 is made of a material having lower brittleness than the inorganic insulating layers 111, 130, 150, and 170 and higher flexibility than the inorganic insulating layers 111, 130, 150, and 170. For example, the stress release layer 220 may be made of an organic insulating material and may include at least one of polyimide, acrylate, and epoxy resin. The stress release layer 220 may fill the entire opening OPB and may be in close contact with the sidewall of the opening OPB to prevent or substantially prevent a gap from being formed between the stress release layer 220 and the inorganic insulating layers 111, 130, 150, and 170.

[0189] The second bridge wiring BL2 crosses the bending area BA and is connected to the third connection wiring CL2a and the fourth connection wiring CL2b.

[0190] The second bridge wiring BL2 is connected to one side of the third connection wiring CL2a through the twentieth contact hole CH20 passing through the first and second lower insulating layers 150 and 170 , and is connected to the fourth connection wiring CL2b through the twenty-first contact hole CH21 passing through the first and second lower insulating layers 150 and 170 .

[0191] A portion of the second bridge wiring BL2 overlapping the bending area BA may be located on the stress release layer 220 .

[0192] In an embodiment, the first connection pattern CNP1a, the second connection pattern CNP1b, the third connection pattern CNP3a, the fourth connection pattern CNP3b, and the second bridge wiring BL2 may be made of the same second conductive material as the first to third data lines D1 to D3, and may be disposed at the same level as the first to third data lines D1 to D3. In an embodiment, the second conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multi-layer or a single layer.

[0193] The first upper insulating layer 210 is positioned on the first connection pattern CNP1 a , the second connection pattern CNP1 b , the third connection pattern CNP3 a , the fourth connection pattern CNP3 b , the second bridge wiring BL2 , and the stress release layer 220 .

[0194] The first and third bridge wirings BL1 and BL3 are located on the first upper insulating layer 210 .

[0195] The first bridge wiring BL1 crosses the bending area BA and is connected to the first connection pattern CNP1a and the second connection pattern CNP1b. In addition, the third bridge wiring BL3 crosses the bending area BA and is connected to the third connection pattern CNP3a and the fourth connection pattern CNP3b.

[0196] One side of the first bridge wiring BL1 is connected to the first connection pattern CNP1a through a seventeenth contact hole CH17 passing through the first upper insulating layer 210 , and the other side of the first bridge wiring BL1 is connected to the second connection pattern CNP1b through an eighteenth contact hole CH18 passing through the first upper insulating layer 210 .

[0197] One side of the third bridge wiring BL3 is connected to the third connection pattern CNP3 a through a twenty-third contact hole CH23 passing through the first upper insulating layer 210 , and the other side of the third bridge wiring BL3 is connected to the fourth connection pattern CNP3 b through a twenty-fourth contact hole CH24 passing through the first upper insulating layer 210 .

[0198] In some embodiments, the first bridge wiring BL1 and the third bridge wiring BL3 are made of the same third conductive material as the driving voltage line PLb and can be disposed on the same layer as the driving voltage line PLb. The third conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or a single layer.

[0199] The first bridge wiring BL1 and the second bridge wiring BL2 adjacent to each other in the first direction y on the bending area BA are located on different layers, and the first upper insulating layer 210 is interposed between the first bridge wiring BL1 and the second bridge wiring BL2. In addition, the second bridge wiring BL2 and the third bridge wiring BL3 adjacent to each other in the first direction y are located on different layers, and the first upper insulating layer 210 is interposed between the second bridge wiring BL2 and the third bridge wiring BL3. Therefore, a short circuit between adjacent bridge wirings located on the bending area BA can be prevented or substantially prevented, and the bridge wirings can be separated or spaced apart by a small gap when viewed from above.

[0200] The contact holes adjacent to each other along the first direction y may not be located on the same straight line, but may be arranged in a zigzag form. For example, assuming that the imaginary line extends along the first direction y, the seventeenth contact hole CH17 for connecting the first bridge wiring BL1 and the first connection pattern CNP1a and / or the sixteenth contact hole CH16 for connecting the first connection pattern CNP1a and the first connection wiring CL1a and the twentieth contact hole CH20 for connecting the second bridge wiring BL2 and the third connection wiring CL2a may not be located on the imaginary line.

[0201] Alternatively, assuming that the shortest distance between the bending area BA and the seventeenth contact hole CH17 measured along the second direction x is W1, the shortest distance between the bending area BA and the sixteenth contact hole CH16 is W2, and the shortest distance between the bending area BA and the twentieth contact hole CH20 is W3, W3 may be different from W1 and W2. Therefore, it is possible to prevent or substantially prevent accidental short circuits between elements adjacent to each other along the first direction y near the contact holes, and improve the reliability of the display device.

[0202] Fig.14 yes Figure 1 An enlarged plan view of area “Q3”. Fig.15 is along Fig.14 A cross-sectional view taken along line X13-X14. Fig.16 is along Fig.14 A cross-sectional view taken along line X15-X16.

[0203] Reference Figure 1 and Figures 14 to 16 , the buffer layer 111 and the gate insulating layer 130 are located on the peripheral area NDA of the base substrate 110, and the first test signal line TL1 and the second test signal line TL2 are disposed on the gate insulating layer 130 to be separated or spaced apart from each other. The first test signal line TL1 is connected to the first test pad TP1, and the second test signal line TL2 is connected to the second test pad TP2.

[0204] In some embodiments, the first test pad TP1 may be a part of the first test signal line TL1 , and the second test pad TP2 may be a part of the second test signal line TL2 .

[0205] The first test signal line TL1 and the second test signal line TL2 may not overlap the bending area BA of the base substrate 110. If the first test signal line TL1 and the second test signal line TL2 overlap the bending area BA of the base substrate 110, it may be difficult to determine whether a crack has occurred in the first crack detection line RL1 or in the first test signal line TL1 and the second test signal line TL2. Therefore, the first test signal line TL1 and the second test signal line TL2 may not overlap the bending area BA of the base substrate 110 to prevent or substantially prevent the first test signal line TL1 and the second test signal line TL2 from being damaged by bending of the display device.

[0206] In some embodiments, the first test signal line TL1 may include a first sub-test signal line TL1a and a second sub-test signal line TL1b. The first sub-test signal line TL1a and the second sub-test signal line TL1b may be separated or spaced apart from each other as shown in the figure. However, the inventive concept is not limited to this case. In an embodiment, the first sub-test signal line TL1a and the second sub-test signal line TL1b may be partially connected to each other.

[0207] The second test signal line TL2 may include a third sub test signal line TL2a and a fourth sub test signal line TL2b. The third sub test signal line TL2a and the fourth sub test signal line TL2b may be separated or spaced apart from each other as shown in the figure. However, the inventive concept is not limited to this case.

[0208] The first test pad TP1 may include a first sub test pad TP1 a connected to the first sub test signal line TL1 a and a second sub test pad TP1 b connected to the second sub test signal line TL1 b .

[0209] The second test pad TP2 may include a third sub test pad TP2a connected to the third sub test signal line TL2a and a fourth sub test pad TP2b connected to the fourth sub test signal line TL2b. In some embodiments, the first sub test pad TP1a, the second sub test pad TP1b, the third sub test pad TP2a, and the fourth sub test pad TP2b may be separated or spaced apart from each other.

[0210] In an embodiment, like the first connection wiring CL1a, the second connection wiring CL1b, the third connection wiring CL2a, the fourth connection wiring CL2b, the fifth connection wiring CL3a, and the sixth connection wiring CL3b, the first test signal line TL1 and the second test signal line TL2 may be made of the same first conductive material as the scan lines Si-1, Si, and Si+1, and may be disposed on the same layer as the scan lines Si-1, Si, and Si+1. In an embodiment, the first conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti) as described above.

[0211] The first and second lower insulating layers 150 and 170 may be located on the first and second test signal lines TL1 and TL2 .

[0212] The first and second test connection patterns TCP1 and TCP2 may be located on the second lower insulating layer 170 to be separated or spaced apart from each other.

[0213] The first test connection pattern TCP1 and the second test connection pattern TCP2 are elements for improving connection reliability. The first test connection pattern TCP1 may be connected to the second sub-test signal line TL1b through the twenty-sixth contact hole CH26 passing through the first lower insulating layer 150 and the second lower insulating layer 170, and may be connected to the first sub-test signal line TL1a through the twenty-seventh contact hole CH27 passing through the first lower insulating layer 150 and the second lower insulating layer 170. The second test connection pattern TCP2 may be connected to the fourth sub-test signal line TL2b through the twenty-ninth contact hole CH29 passing through the first lower insulating layer 150 and the second lower insulating layer 170, and may be connected to the third sub-test signal line TL2a through the thirtieth contact hole CH30 passing through the first lower insulating layer 150 and the second lower insulating layer 170.

[0214] In an embodiment, like the first connection pattern CNP1a, the second connection pattern CNP1b, the third connection pattern CNP3a, the fourth connection pattern CNP3b and the second bridge wiring BL2, the first test connection pattern TCP1 and the second test connection pattern TCP2 can be made of the same second conductive material as the first data line D1 to the third data line D3, and can be located at the same level as the first data line D1 to the third data line D3.

[0215] The first upper insulating layer 210 may be located on the first test connection pattern TCP1 , the second test connection pattern TCP2 , and the stress relief layer 220 .

[0216] The first crack detection line RL1 may be located on the first upper insulating layer 210 .

[0217] The first crack detection line RL1 includes a portion overlapping the bending area BA, and is connected to the first and second test connection patterns TCP1 and TCP2.

[0218] One side of the first crack detection line RL1 is connected to the first test connection pattern TCP1 through a twenty-eighth contact hole CH28 passing through the first upper insulating layer 210 , and the other side of the first crack detection line RL1 is connected to the second test connection pattern TCP2 through a thirty-first contact hole CH31 passing through the first upper insulating layer 210 .

[0219] A portion of the first crack detection line RL1 overlapping the bending area BA may include a plurality of bending portions.

[0220] In some embodiments, like the first bridge wiring BL1 and the third bridge wiring BL3, the first crack detection line RL1 may be made of the same third conductive material as the driving voltage line PLb and may be disposed on the same layer as the driving voltage line PLb. In an embodiment, the third conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multi-layer or a single layer.

[0221] Fig.17 It is used to explain the use Fig.14 FIG. 5 is a diagram showing a structure for detecting cracks in a process.

[0222] Reference Fig.17 Before the display device is bent, a pair of test signal probes are brought into contact with the first sub-test pad TP1a and the third sub-test pad TP2a to provide a test signal to the first crack detection line RL1. In addition, a pair of output signal probes are brought into contact with the second sub-test pad TP1b and the fourth sub-test pad TP2b to measure an output signal generated in response to the test signal. In an example, a current It may be provided to the first crack detection line RL1 as a test signal, a voltage Vt may be measured as an output signal, and the current It (i.e., the test signal) and the voltage Vt (i.e., the output signal) may be compared to obtain a resistance value.

[0223] After the display device is bent, the current It may be provided to the first crack detection line RL1 as a test signal, and the voltage Vt may be measured as an output signal to obtain a resistance value. Then, whether the first crack detection line RL1 has been broken may be detected by comparing the resistance value before the display device is bent with the resistance value after the display device is bent.

[0224] Among the wirings located on the bending area BA, elements disposed relatively further outward or disposed away from the base substrate 110 are relatively more likely to break. For example, since the first bridge wiring BL1 and the third bridge wiring BL3 are disposed relatively higher than the second bridge wiring BL2 on the base substrate 110, the first bridge wiring BL1 and the third bridge wiring BL3 are relatively more likely to break than the second bridge wiring BL2.

[0225] According to the current embodiment, when a crack is detected in the first crack detection line RL1, the possibility that the elements located on the bending area BA (specifically, the first and third bridge wirings BL1 and BL3 located at the same level as the first crack detection line RL1) will be broken can be estimated based on the crack generated in the first crack detection line RL1. Therefore, it is possible to easily detect a malfunction due to a crack that may potentially occur in the display device by using the first crack detection line RL1 during a process of manufacturing the display device.

[0226] In addition, according to the current embodiment, the first sub-test pad TP1a and the third sub-test pad TP2a are set as test signal input pads, and the second sub-test pad TP1b and the fourth sub-test pad TP2b separated or separated from the first sub-test pad TP1a and the third sub-test pad TP2a are set as output signal measurement pads. Therefore, a total of four probes can be used to easily perform a test. Specifically, since the test signal input process and the output signal acquisition process can be performed concurrently (e.g., simultaneously), the test can be performed more easily and faster.

[0227] Fig.18 yes Fig.14 A plan view of a modified example of the structure shown in FIG. Fig.19 is along Fig.18 The present modification example is similar to the present modification example except that a second crack detection line RL2 is also provided. Fig.14 Therefore, the following will mainly describe Fig.14 differences in structure.

[0228] Reference Fig.18 and Fig.19 The second crack detection line RL2 is located on the second lower insulating layer 170 so that at least a portion of the second crack detection line RL2 overlaps the bending area BA. One side of the second crack detection line RL2 is connected to the first test connection pattern TCP1, and the other side of the second crack detection line RL2 is connected to the second test connection pattern TCP2.

[0229] In an embodiment, like the first and second test connection patterns TCP1 and TCP2, the second crack detection line RL2 may be made of the same second conductive material as the first to third data lines D1 to D3 and may be located at the same level as the first to third data lines D1 to D3.

[0230] A portion of the second crack detection line RL2 overlapping the bending area BA may include a plurality of bending portions, and the second crack detection line RL2 overlapping the bending area BA may be located on the stress release layer 220 .

[0231] The test process of the current embodiment can be compared with the above reference Fig.17 The methods described are essentially the same.

[0232] According to the current embodiment, the possibility that the first and third bridge wirings BL1 and BL3 located at the same level as the first crack detection line RL1 will break can be estimated. In addition, the possibility that the element located at the same level as the second crack detection line RL2 (for example, the second bridge wiring BL2) will break can be estimated.

[0233] Fig. 20 yes Fig.14 A plan view of a modified example of the structure shown in FIG. Fig.21 is along Fig. 20 The present modification example is similar to the present modification example except that a third test signal line TL3, a fourth test signal line TL4, a third test pad TP3, a fourth test pad TP4 and a second crack detection line RL2 are also provided. Fig.14 Therefore, the following will mainly describe Fig.14 differences in structure.

[0234] Reference Figure 1 , Fig. 20 and Fig.21 , the buffer layer 111 and the gate insulating layer 130 are disposed on the peripheral area NDA of the base substrate 110, and the third test signal line TL3 and the fourth test signal line TL4 separated or spaced apart from each other are located on the gate insulating layer 130. The third test signal line TL3 and the fourth test signal line TL4 are separated or spaced apart from the first test signal line TL1 and the second test signal line TL2.

[0235] The third test signal line TL3 is connected to the third test pad TP3, and the fourth test signal line TL4 is connected to the fourth test pad TP4. In some embodiments, the third test pad TP3 may be a part of the third test signal line TL3, and the fourth test pad TP4 may be a part of the fourth test signal line TL4.

[0236] In some embodiments, the third test signal line TL3 may include a fifth sub-test signal line TL3a and a sixth sub-test signal line TL3b. The fifth sub-test signal line TL3a and the sixth sub-test signal line TL3b may be separated or spaced apart from each other as shown in the figure. However, the inventive concept is not limited to this case. In an embodiment, the fifth sub-test signal line TL3a and the sixth sub-test signal line TL3b may be partially connected to each other.

[0237] The fourth test signal line TL4 may include a seventh sub-test signal line TL4a and an eighth sub-test signal line TL4b. The seventh sub-test signal line TL4a and the eighth sub-test signal line TL4b may be, but need not be, separated or spaced apart from each other as shown in the figure.

[0238] The third test pad TP3 may include a fifth sub test pad TP3 a connected to the fifth sub test signal line TL3 a and a sixth sub test pad TP3 b connected to the sixth sub test signal line TL3 b .

[0239] The fourth test pad TP4 may include a seventh sub test pad TP4 a connected to the seventh sub test signal line TL4 a and an eighth sub test pad TP4 b connected to the eighth sub test signal line TL4 b .

[0240] In some embodiments, the fifth and sixth sub test pads TP3 a and TP3 b may be separated or spaced apart from the seventh and eighth sub test pads TP4 a and TP4 b .

[0241] In an embodiment, like the first test signal line TL1 and the second test signal line TL2, the third test signal line TL3 and the fourth test signal line TL4 may be made of the same first conductive material as the scan lines Si-1, Si, and Si+1, and may be disposed on the same layer as the scan lines Si-1, Si, and Si+1. In an embodiment, the first conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti) as described above.

[0242] The first lower insulating layer 150 and the second lower insulating layer 170 may be located on the first, second, third, and fourth test signal lines TL1, TL2, TL3, and TL4.

[0243] The second crack detection line RL2 is located on the second lower insulating layer 170 such that at least a portion of the second crack detection line RL2 overlaps the bending area BA. One side of the second crack detection line RL2 is connected to the fifth sub-test signal line TL3a and the sixth sub-test signal line TL3b, and the other side of the second crack detection line RL2 is connected to the seventh sub-test signal line TL4a and the eighth sub-test signal line TL4b.

[0244] One side of the second crack detection line RL2 may be connected to the sixth sub test signal line TL3 b through a thirty-second contact hole CH32 passing through the first lower insulating layer 150 and the second lower insulating layer 170 , and may be connected to the fifth sub test signal line TL3 a through a thirty-third contact hole CH33 passing through the first lower insulating layer 150 and the second lower insulating layer 170 .

[0245] The other side of the second crack detection line RL2 may be connected to the eighth sub-test signal line TL4 b through a thirty-fourth contact hole CH34 passing through the first lower insulating layer 150 and the second lower insulating layer 170 , and may be connected to the seventh sub-test signal line TL4 a through a thirty-fifth contact hole CH35 passing through the first lower insulating layer 150 and the second lower insulating layer 170 .

[0246] A portion of the second crack detection line RL2 overlapping the bending area BA may include a plurality of bending portions, and the second crack detection line RL2 overlapping the bending area BA may be located on the stress release layer 220 .

[0247] In an embodiment, like the first and second test connection patterns TCP1 and TCP2, the second crack detection line RL2 may be made of the same second conductive material as the first to third data lines D1 to D3 and may be located at the same level as the first to third data lines D1 to D3.

[0248] Fig. 22 It is used to explain the use Fig. 20 FIG. 5 is a diagram showing a structure for detecting cracks in a process.

[0249] Reference Fig. 22 Before the display device is bent, a pair of test signal probes are brought into contact with the first sub-test pad TP1a and the third sub-test pad TP2a to provide a test signal to the first crack detection line RL1. In addition, a pair of output signal probes are brought into contact with the second sub-test pad TP1b and the fourth sub-test pad TP2b to measure an output signal generated in response to the test signal. In an example, a current It may be provided to the first crack detection line RL1 as a test signal, a voltage Vt may be measured as an output signal, and the current It (i.e., the test signal) and the voltage Vt (i.e., the output signal) may be compared to obtain a resistance value.

[0250] After the display device is bent, the current It may be provided to the first crack detection line RL1 as a test signal, and the voltage Vt may be measured as an output signal to obtain a resistance value. Then, whether the first crack detection line RL1 has been broken may be detected by comparing the resistance value before the display device is bent with the resistance value after the display device is bent.

[0251] In addition, before the display device is bent, another pair of test signal probes is brought into contact with the fifth sub-test pad TP3a ​​and the seventh sub-test pad TP4a to provide a test signal to the second crack detection line RL2. In addition, another pair of output signal probes is brought into contact with the sixth sub-test pad TP3b and the eighth sub-test pad TP4b to measure an output signal generated in response to the test signal. In an example, a current Ita may be provided to the second crack detection line RL2 as a test signal, a voltage Vta may be measured as an output signal, and the current Ita (i.e., the test signal) and the voltage Vta (i.e., the output signal) may be compared to obtain a resistance value.

[0252] After the display device is bent, the current Ita may be provided as a test signal to the second crack detection line RL2, and the voltage Vta may be measured as an output signal to obtain a resistance value. Then, whether the second crack detection line RL2 has been broken may be detected by comparing the resistance value before the display device is bent with the resistance value after the display device is bent.

[0253] According to the current embodiment, the output signal of the first crack detection line RL1 and the output signal of the second crack detection line RL2 can be measured independently. Therefore, when a crack is detected in the first crack detection line RL1, it can be judged that the elements located on the bending area BA (specifically, the first bridge wiring BL1 and the third bridge wiring BL3 located at the same level as the first crack detection line RL1) have been broken.

[0254] That is, according to the present embodiment, it is possible to determine at which level a wiring among wirings located on the bending area BA has been broken.

[0255] Fig.23 is along with Fig.10 A cross-sectional view of the display device according to the embodiment is taken along a line corresponding to line X7 - X8 . Fig.24 is along with Fig.10 The line X9-X10 corresponding to the line intercepted Fig.23 A cross-sectional view of a display device. Fig.25 is along with Fig.10 The line X11-X12 corresponding to the line interception is based on Fig.23 The display device according to the present embodiment is similar to the display device according to the present embodiment except that the stress release layer 220 is not provided and the opening OPB is filled with the first upper insulating layer 210. Figures 11 to 13 Therefore, the following will mainly describe the embodiment shown in Figures 11 to 13 differences in structure.

[0256] Reference Fig.10 and Figure 23 to Figure 25 , the opening OPB formed in the inorganic insulating layers 111 , 130 , 150 , and 170 to correspond to the bending area BA is filled with the first upper insulating layer 210 .

[0257] A portion of the second bridge wiring BL2 that does not overlap the bending area BA is located on the second lower insulating layer 170. The second bridge wiring BL2 is connected to one side of the third connection wiring CL2a through a twentieth contact hole CH20 passing through the first and second lower insulating layers 150 and 170, and is connected to the fourth connection wiring CL2b through a twenty-first contact hole CH21 passing through the first and second lower insulating layers 150 and 170.

[0258] A portion of the second bridge wiring BL2 overlapping the bending area BA is located on the base substrate 110. The second bridge wiring BL2 may contact sides of the inorganic insulating layers 111, 130, 150, and 170 surrounding the opening OPB.

[0259] Other elements may be the same as those described above, and thus description of these elements will be omitted.

[0260] Fig.26 is along with Fig.14 A cross-sectional view of a display device according to an embodiment is taken along a line corresponding to line X13-X14. Fig.15 and Fig.16 The difference of the embodiment shown in FIG. 1 is that the stress release layer 220 is not provided, and the opening OPB is filled with the first upper insulating layer 210. Since other elements can be the same as those described above with reference to FIG. Figures 14 to 16 Those described are substantially the same, so description of these elements will be omitted.

[0261] Fig. 27 is along with Fig.18 A cross-sectional view of a display device according to an embodiment is taken along a line corresponding to line X17-X18. Fig.19 The embodiment shown in FIG. 1 is different in that the stress release layer 220 is not provided, the opening OPB is filled with the first upper insulating layer 210, and a portion of the second crack detection line RL2 overlapping the bending area BA is located on the base substrate 110. Fig.18 and Fig.19 Those described are substantially the same, so description of these elements will be omitted.

[0262] Fig.28 is along with Fig. 20 A cross-sectional view of a display device according to an embodiment is taken along a line corresponding to line X19-X20. Fig.21 The embodiment shown in FIG. 1 is different in that the stress release layer 220 is not provided, the opening OPB is filled with the first upper insulating layer 210, and a portion of the second crack detection line RL2 overlapping the bending area BA is located on the base substrate 110. Fig. 20 and Fig.21 Those described are substantially the same, so description of these elements will be omitted.

[0263] According to the embodiment, it is possible to provide a display device in which at least a portion of a non-display area is bent.

[0264] In addition, according to the embodiment, it is possible to provide a display device capable of detecting a crack generated in a bent portion.

[0265] However, the effects of the inventive concept are not limited to those set forth herein. The above and other effects of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept pertains by referring to the claims.

[0266] Although some exemplary embodiments have been disclosed for the purpose of illustration, these embodiments are presented only as examples and do not limit the inventive concept. It will be appreciated by those skilled in the art that various modifications and applications can be made without departing from the scope and spirit of the embodiments disclosed in the claims. For example, each element described in the embodiments can be modified and implemented differently. In addition, the differences associated with such modifications and applications should be interpreted as being included within the scope of the embodiments as defined by the claims.

Claims

1. A display device, comprising: a base substrate, comprising a display area and a peripheral area except the display area, wherein the peripheral area comprises a bending area; a first test signal line and a second test signal line, located on the peripheral area of ​​the base substrate and at least partially separated from each other; a test connection pattern, located on the first test signal line and the second test signal line; a crack detection line including at least a portion located on the bent region of the base substrate, located on the test connection pattern, and electrically connected to the first test signal line and the second test signal line; and Data lines and driving voltage lines are located on the display area of ​​the base substrate, wherein the data line and the driving voltage line are located on different layers, the data line and the crack detection line are located on different layers, the crack detection line and the first test signal line and the second test signal line are located on different layers, and The data line and the test connection pattern are located on the same layer and are made of the same material.

2. The display device according to claim 1, wherein: The crack detection line and the driving voltage line are located on the same layer and are made of the same material.

3. The display device according to claim 1, wherein: The test connection pattern comprises: a first test connection pattern, located on the first test signal line and connected to the first test signal line and the crack detection line; and The second test connection pattern is located on the second test signal line, is separated from the first test connection pattern, and is connected to the second test signal line and the crack detection line.

4. A display device, comprising: a base substrate, comprising a display area and a peripheral area except the display area, wherein the peripheral area comprises a bending area; a first test signal line and a second test signal line, located on the peripheral area of ​​the base substrate and at least partially separated from each other; a test connection pattern, located on the first test signal line and the second test signal line; a crack detection line, including at least a portion located on the bent region of the base substrate, located on the test connection pattern, and electrically connected to the first test signal line and the second test signal line; A data line, located on the display area of ​​the base substrate; connection pads located on the peripheral region of the base substrate; and a bridge wiring electrically connecting the data line and the connection pad, wherein the data line and some bridge wirings are located on different layers, the crack detection line and some of the bridge wirings are located on different layers, the crack detection line and the first test signal line and the second test signal line are located on different layers, and The data line and the test connection pattern are located on the same layer and are made of the same material.

5. The display device according to claim 4, wherein: The crack detection line and the remaining bridge wirings among the bridge wirings are made of the same material and are located on the same layer.

6. The display device according to claim 4, wherein: The test connection pattern comprises: a first test connection pattern, located on the first test signal line and connected to the first test signal line and the crack detection line; and The second test connection pattern is located on the second test signal line, is separated from the first test connection pattern, and is connected to the second test signal line and the crack detection line.

7. The display device according to claim 6, further comprising: a first connection wiring connecting the data line and the bridge wiring; as well as a second connection wiring connecting the connection pad and the bridge wiring, The first connection wiring, the second connection wiring, the first test signal line and the second test signal line are located on the same layer and are made of the same material.

8. The display device according to claim 7, further comprising: a first connection pattern located on the first connection wiring and connected to the first connection wiring and the bridge wiring; as well as a second connection pattern located on the second connection wiring, spaced apart from the first connection pattern, and connected to the second connection wiring and the bridge wiring, The first test connection pattern, the second test connection pattern, the first connection pattern and the second connection pattern are located on the same layer and are made of the same material.

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