Photoelectric conversion device and camera

Abstract

Provided is a photoelectric conversion device and a camera. The photoelectric conversion device includes an element isolation portion and a pixel isolation portion. The element isolation portion is provided on a front surface side of a semiconductor layer and is composed of an insulator. The pixel isolation portion includes a portion that overlaps an isolation region in a normal line direction. The semiconductor layer is continuous across semiconductor regions in an intermediate plane. The portion is located between one semiconductor region and another semiconductor region.

Description

[0001] This application is a divisional application of the invention patent application filed on March 29, 2017, with application number 201710197850.9 and entitled "Photoelectric Conversion Device and Camera". Technical Field

[0002] This disclosure relates to a photoelectric conversion device. Background Technology

[0003] The arrangement of trenches in semiconductor layers of photoelectric conversion devices used in cameras (e.g., complementary metal-oxide-semiconductor (CMOS) image sensors) has been studied. Since the isolation portion formed by the trenches acts as a barrier for light, charge, etc., sensitivity is improved and color mixing is suppressed. Therefore, photoelectric conversion performance can be improved.

[0004] Japanese Patent Application Publication No. 2014-204047 discloses an element isolation consisting of a space and an insulator. The space and the insulator are disposed in a trench.

[0005] Studies of the trenches disclosed in Japanese Patent Application Publication No. 2014-204047 show that the sensitivity of the photoelectric conversion unit decreases due to the arrangement of the trenches. Summary of the Invention

[0006] One aspect of the embodiments aims to provide a photoelectric conversion device with improved photoelectric conversion performance. One embodiment provides a photoelectric conversion device comprising: a semiconductor layer having a first surface and a second surface, the second surface opposite to the first surface; a first isolation portion disposed on the first surface side, the first isolation portion being composed of an insulator; and a second isolation portion configured to pass through a plane extending along the second surface, the plane being located closer to the second surface than the first isolation portion, the second isolation portion being composed of trenches disposed in the semiconductor layer. The semiconductor layer includes: a first element region disposed as an element region defined by the first isolation portion, a first element region disposed of a first photoelectric conversion element, a second element region disposed of a second photoelectric conversion element, and a third element region disposed between the first element region and the second element region, the third element region having a different shape from the first element region and the second element region. The first isolation portion includes: a first isolation region located between the first element region and the third element region, and a second isolation region located between the second element region and the third element region. The semiconductor layer includes: a first semiconductor region located between the first element region and the second surface in a normal direction about the first surface; a second semiconductor region located between the second element region and the second surface in the normal direction; a third semiconductor region located between the third element region and the second surface in the normal direction; and a fourth semiconductor region located between the first isolation region and the second surface in the normal direction. The second isolation portion includes a portion overlapping the second isolation region in the normal direction. In the plane, the first semiconductor region and the third semiconductor region are continuous via the fourth semiconductor region, and the portion is located between the second semiconductor region and the third semiconductor region. The first photoelectric conversion element includes a first impurity region of a first conductivity type where the signal charge is a majority carrier and a second impurity region of a second conductivity type where the signal charge is a minority carrier, and the distance between the first impurity region and the portion is greater than the distance between the first impurity region and the first isolation region.

[0007] Other features of the embodiments will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1A and Figure 1B These are schematic diagrams illustrating, respectively, back-side and front-side illumination type camera devices as examples of photoelectric conversion devices.

[0009] Figure 2 This is a schematic diagram illustrating a semiconductor layer in a photoelectric conversion device.

[0010] Figure 3A , Figure 3B , Figure 3C and Figure 3D Variations illustrating the shape and / or positional relationship between the element isolation portion and the pixel isolation portion are shown. Figure 3E , Figure 3F and Figure 3G This is a schematic diagram used to illustrate a variation in the construction of the impurity region.

[0011] Figure 4 This is a schematic diagram of the first example of a layout used to illustrate pixels.

[0012] Figure 5 This is a schematic diagram of a second example of a layout used to illustrate pixels.

[0013] Figure 6 This is a schematic diagram of a third example of a layout used to illustrate pixels.

[0014] Figure 7 This is a schematic diagram of the fourth example of a layout used to illustrate pixels.

[0015] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F , Figure 8G and Figure 8H This is a schematic diagram illustrating a method for manufacturing a photoelectric conversion device.

[0016] Figure 9 This is a diagram of a camera. Detailed Implementation

[0017] In the following description, exemplary embodiments for implementing this disclosure will be described with reference to the accompanying drawings. According to these exemplary embodiments, a photoelectric conversion device with improved photoelectric conversion performance can be provided. In the following description and drawings, components common across multiple drawings are given common reference numerals. Therefore, such common components are described by cross-referencing multiple drawings, and descriptions of components given common reference numerals will be appropriately omitted.

[0018] Figure 1A This is a cross-sectional view illustrating an exemplary embodiment of a back-illuminated camera device used as an example of a photoelectric conversion device. Figure 1B This is a cross-sectional view illustrating an exemplary embodiment of a front-side illumination type camera device, another example used as a photoelectric conversion device. First, the common features of both the back-side illumination type and the front-side illumination type will be described.

[0019] The photoelectric conversion device 1000 includes a semiconductor layer 100 having a front side 1 and a back side 2 opposite to the front side 1. The semiconductor layer 100 is, for example, a single-crystal silicon layer, but is not limited to single-crystal silicon and can be any semiconductor layer capable of photoelectric conversion. The photoelectric conversion device 1000 also includes a device isolation portion 10 disposed on the front side 1 to the semiconductor layer 100, and the device isolation portion 10 is formed by a trench 11 in the semiconductor layer 100 and an insulator 12 in the trench 11. The device isolation portion 10 may have a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. The insulator 12, which partially constitutes the device isolation portion 10, is made of, for example, silicon oxide. The photoelectric conversion device 1000 also includes a pixel isolation portion 20, which is formed by a trench 21 disposed in the semiconductor layer 100. The pixel isolation portion 20 is configured to pass through an intermediate plane 3. The intermediate plane 3 is a virtual plane located closer to the back surface 2 than the element isolation portion 10 and extending along the front surface 1 and / or the back surface 2. The intermediate plane 3 may be parallel to the back surface 2. The direction perpendicular to the intermediate plane 3 is called the normal direction N, and the direction parallel to the intermediate plane 3 is called the in-plane direction P. In the normal direction N, the pixel isolation portion 20 extends from the intermediate plane 3 toward both the front surface 1 and the back surface 2. Within the intermediate plane 3, the semiconductor layer 100 is discontinuous with the pixel isolation portion 20 disposed therein. A solid 22 may exist in the trench 21 of the pixel isolation portion 20. The space within the trench 21 may be a vacuum, a gas may exist in the trench 21, or both a gas and a solid 22 may exist in the trench 21. The solid 22 that can exist in the trench 21 may be an insulator, a conductor, or a semiconductor. A typical insulator that can be used as the solid 22 that exists in the trench 21 is silicon oxide, but silicon nitride, silicon oxynitride, tantalum oxide, hafnium oxide, titanium oxide, etc., may also be used. Typical conductors that can be used as the solid 22 present in the trench 21 are metals or polycrystalline silicon, but aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, metal silicides, etc., can also be used. Typical semiconductors that can be used as the solid 22 present in the trench 21 are monocrystalline silicon, but amorphous silicon can also be used. The conductivity type of the semiconductor used as the solid 22 present in the trench 21 can be the opposite of the conductivity type of the signal charge accumulated in the photoelectric conversion element, which will be described later.

[0020] A photoelectric conversion element 30 is disposed between the front side 1 and the back side 2 of the semiconductor layer 100. The photoelectric conversion element 30 is a photodiode. The photoelectric conversion element 30 used as a photodiode includes an n-type impurity region 40 serving as an accumulation region for accumulating signal charge (electrons) and a p-type impurity region 50 forming a pn junction with the impurity region 40. Electrons generated by photoelectric conversion in the p-type impurity region 50 are accumulated in the impurity region 40. The impurity region 40 may be located within the intermediate plane 3. The impurity region 50 is located between the intermediate plane 3 and the back side 2. Although an electron accumulation photodiode has been illustrated as an example, a hole accumulation photodiode can also be used. In this case, the conductivity type of the impurity region can be reversed with that of the electron accumulation type. The conductivity type where the signal charge is the majority carrier is set to the first conductivity type, and the conductivity type where the signal charge is the minority carrier is set to the second conductivity type. When the signal charge is electrons, the n-type where electrons are the majority carriers is the first conductivity type. It should be noted that the portion of the semiconductor layer 100 considered as a photoelectric conversion element 30 is generated by subjecting the charge read out as a signal charge to photoelectric conversion. Strictly speaking, the portion considered as a photoelectric conversion element 30 is determined by the impurity concentration distribution in the semiconductor layer 100 and a potential curve based on the applied voltage.

[0021] Pixel transistor 90 is disposed in the front side 1 of semiconductor layer 100. Figure 1A and Figure 1B In this design, pixel transistor 90 includes a channel region 70 and a gate electrode 80. Pixel transistor 90 includes a transfer transistor, an amplification transistor, a reset transistor, a selection transistor, etc. (not illustrated). The transfer transistor transfers the signal charge of photoelectric conversion element 30 to a charge detection region. The charge detection region is composed of a floating diffusion region (floating diffusion). The amplification transistor generates a signal based on charge using a source follower circuit and includes a gate connected to the charge detection region. The reset transistor includes a drain connected to the charge detection region and resets the charge of photoelectric conversion element 30. The selection transistor selects between connecting and disconnecting the amplification transistor and the output line.

[0022] The portion of the semiconductor layer 100 located outside the photoelectric conversion element 30 is composed of a p-type impurity region 60. The p-type impurity region 60 has a higher impurity concentration than the impurity region 50 (which is also p-type). A portion of the impurity region 60 can serve as a barrier to suppress charge mixing between pixels. Additionally, a portion of the impurity region 60 can serve as a barrier to prevent noise charges generated at the interface between the semiconductor layer 100 and the insulator 12 from being carried into the photoelectric conversion element 30. The impurity region 60 includes a dense p-type well contact, to which a conductive member supplying a fixed potential, such as ground potential, is connected. A potential is supplied from the well contact to the impurity region 40 of the photoelectric conversion element 30 via the impurity region 60.

[0023] Pixel isolation sections 20 are disposed around the photoelectric conversion element 30. Pixel isolation sections 20 have a structure that enables suppression of color mixing between adjacent pixels. In the semiconductor region surrounded by the pixel isolation sections 20 disposed around the photoelectric conversion element 30, in addition to the impurity region 40, pixel transistors 90 isolated by the element isolation sections 10 are also included. In other words, not only the photoelectric conversion element 30, but also the semiconductor region under the element isolation sections 10 is included between the pixel isolation sections 20 that are adjacent to and face each other in the intermediate plane 3. Furthermore, the semiconductor region under the pixel transistors 90 isolated from the photoelectric conversion element 30 by the element isolation sections 10 is also included between the pixel isolation sections 20 that are adjacent to and face each other in the intermediate plane 3. Figure 1A and Figure 1B In the example shown, the photoelectric conversion element 30 is configured to extend into the semiconductor regions below the element isolation portion 10 and the pixel transistor 90.

[0024] An insulating film 300, consisting of multiple wiring layers 310, 320, and 330 and multiple interlayer insulating layers surrounding the wiring layers 310, 320, and 330, is disposed on the front side 1. The output lines consisting of the wiring layers 310, 320, and 330 are configured to output the signal charge generated by the photoelectric conversion element 30 to the next stage in the form of an electrical signal via the pixel transistor 90.

[0025] exist Figure 1A In the back-illuminated imaging device shown, a dielectric film 410, a light-shielding member 420, a color filter array 430, and a microlens array 440 are disposed on the back side 2. The dielectric film 410 serves as a protective film (passivation film), a planarization film, and / or an anti-reflective film. A support substrate 400 is disposed on an insulating film 300 on the front side 1. Integrated circuits, such as signal processing circuits, can be disposed on the support substrate 400. The semiconductor layer 100 has a thickness of approximately 1 μm to 10 μm. The support substrate 400 has a thickness of approximately 50 μm to 800 μm.

[0026] exist Figure 1B In the front-side illumination type imaging device shown, a dielectric film 410, a color filter array 430, and a microlens array 440 are disposed on an insulating film 300 on the front side 1. The dielectric film 410 serves as a protective film (passivation film), a planarization film, and / or an anti-reflection film. The semiconductor layer 100 has a thickness of approximately 50 μm to 800 μm.

[0027] The color filter array 430 is configured to selectively transmit only light of specific wavelengths. For example, color filters that transmit red, green, and blue wavelengths can be arrayed. Additionally, pixels that transmit white light can be mixed within it. Each microlens in the microlens array 440, which is configured to correspond to each pixel, is configured to converge incident light onto the photoelectric conversion element 30.

[0028] Next, we will refer to Figure 2 Describe in detail the semiconductor layer 100 and the structure in its vicinity.

[0029] The semiconductor layer 100 includes device regions defined by the device isolation portion 10. The device regions are distinguished by their positions relative to the device isolation portion 10. The lower end of each device region in the depth direction coincides with the depth of the bottom surface of the device isolation portion 10. Figure 2 In the diagram, element regions 111, 112, 113, and 114 are illustrated as element regions included in the semiconductor layer 100. A photoelectric conversion element 41 is disposed in element region 111, and a photoelectric conversion element 42 is disposed in element region 112. Element region 113 is disposed between element regions 111 and 112, and semiconductor elements such as transistors, capacitive elements (not shown), and resistive elements (not shown) are disposed in element region 113. The shape of element region 113 differs from the shape of element region 111 or element region 112. This is because semiconductor elements such as transistors, other than the photoelectric conversion element 30, are disposed in element region 113. Typically, the area of ​​element region 113 is smaller than the area of ​​element region 111 or element region 112.

[0030] In this example, a pixel transistor is provided as a semiconductor element in the aforementioned element region 113. Although the channel region 71 is illustrated as... Figure 2 The pixel transistor has an impurity region, but a source region and a drain region (not shown) are also provided in element region 113. The gate electrode 81 of the pixel transistor is disposed on the channel region 71. The photoelectric conversion element 43 is disposed in element region 114. It should be noted that the part shown is... Figure 2The regions of photoelectric conversion elements 41, 42, and 43 in FIG. 1 correspond to the n-type impurity region 40 (used as the accumulation region of photoelectric conversion element 30). The impurity region corresponding to the p-type impurity region 50 forming photoelectric conversion elements 41, 42, and 43 exists outside the regions represented as photoelectric conversion elements 41, 42, and 43.

[0031] The component isolation section 10 includes isolation regions 101, 102, and 103. Isolation region 101 is located between component region 111 and component region 113. Isolation region 102 is located between component region 112 and component region 113. Isolation region 103 is located between component region 111 and component region 114.

[0032] From the component isolation portion 10 toward the back surface 2, the semiconductor layer 100 includes semiconductor regions corresponding to the distribution of component regions and isolation regions on the front surface 1. The semiconductor regions toward the back surface 2 are distinguished by their positions relative to the isolation regions or component regions of the component isolation portion 10. Each semiconductor region is located in the normal direction N between one of the isolation regions of the component isolation portion 10 or one of the component regions of the semiconductor layer 100 and the back surface 2. As such semiconductor regions, the semiconductor layer 100 includes semiconductor regions 121, 122, 123, 124, 125, 126, and 127. Semiconductor region 121 is located between component region 111 and the back surface 2, semiconductor region 122 is located between component region 112 and the back surface 2, and semiconductor region 123 is located between component region 113 and the back surface 2. Semiconductor region 127 is located between component region 114 and the back surface 2. Semiconductor region 124 is located between isolation region 101 and back surface 2, semiconductor region 125 is located between isolation region 102 and back surface 2, and semiconductor region 126 is located between isolation region 103 and back surface 2.

[0033] The pixel isolation portion 20 includes a first portion 201 that overlaps with the isolation region 102 in the normal direction N. As used herein, "overlap" means that one entity extends in a manner that partially or entirely covers another entity. The first portion 201 is formed by trenches 211 of the semiconductor layer 100. In the in-plane direction P, the first portion 201 is located between semiconductor regions 122 and 123. Semiconductor region 125 is divided into multiple portions by the first portion 201. As a result, semiconductor region 125 includes a portion 1251 located between the first portion 201 and semiconductor region 123, and a portion 1252 located between the first portion 201 and semiconductor region 122. In this example, the first portion 201 is connected to the isolation region 102. Additionally, in this example, the first portion 201 is continuous with the back surface 2. In other words, the trenches 21 constituting the first portion 201 are continuous with the back surface 2. When the first portion 201 and the isolation region 102 are to be spaced apart from each other, a portion of the semiconductor region 125 is disposed between the first portion 201 and the isolation region 102. When the first portion 201 and the back surface 2 are to be spaced apart from each other, a portion of the semiconductor region 125 is disposed between the first portion 201 and the back surface 2.

[0034] The pixel isolation portion 20 includes a second portion 202 overlapping the isolation region 103 in the normal direction N. The second portion 202 is formed by trenches 212 of the semiconductor layer 100. In the in-plane direction P, the second portion 202 is located between semiconductor region 121 and semiconductor region 127. Semiconductor region 126 is divided into multiple portions by the second portion 202. As a result, semiconductor region 126 includes a portion 1261 located between the second portion 202 and semiconductor region 121 and a portion 1262 located between the second portion 202 and semiconductor region 127. In this example, the second portion 202 is connected to the isolation region 103. In addition, in this example, the second portion 202 is continuous with the back surface 2. In other words, the trenches 212 constituting the second portion 202 are continuous with the back surface 2. When the second portion 202 and the isolation region 103 are to be spaced apart from each other, a portion of the semiconductor region 126 is disposed between the second portion 202 and the isolation region 103. When the second portion 202 and the back surface 2 are to be spaced apart from each other, a portion of the semiconductor region 126 is disposed between the second portion 202 and the back surface 2.

[0035] In this way, semiconductor regions 122 and 123 are discontinuous due to the first portion 201. Furthermore, semiconductor regions 121 and 127 are discontinuous due to the second portion 202. This configuration reduces light mixing between pixels and improves the optical characteristics of the photoelectric conversion device. Additionally, it reduces charge mixing between pixels and improves the electrical characteristics of the photoelectric conversion device.

[0036] Meanwhile, no pixel isolation portion 20 is disposed between the isolation region 101 and the back surface 2. Therefore, within the intermediate plane 3, semiconductor regions 121 and 123 are continuous with each other, with semiconductor region 124 placed between them. In other words, element regions 111, 113, and the semiconductor layer 100 below the isolation region 101 are continuous with each other. In this way, since no pixel isolation portion 20 is disposed, the semiconductor layer 100 is continuous below the isolation region 101. Therefore, light scattering caused by the trench 21 of the pixel isolation portion 20 is suppressed. Therefore, the amount of light incident on the photoelectric conversion element 30 can be increased, and thus the sensitivity is improved. In addition, as Figure 1A , Figure 1B and Figure 2 As shown, the distance between the photoelectric conversion element 41 (impurity region 40) and the first portion 201 is greater than the distance between the photoelectric conversion element 41 (impurity region 40) and the isolation region 101. Furthermore, the distance between the photoelectric conversion element 41 (impurity region 40) and the second portion 202 is greater than the distance between the photoelectric conversion element 41 (impurity region 40) and the isolation region 103. Since the pixel isolation portion 20, which can be a noise source, is positioned away from the impurity region 40, which serves as an accumulation region for the photoelectric conversion element 30, noise generated near the pixel isolation portion 20 can be prevented from being introduced into the photoelectric conversion element 30. Furthermore, not only the element region 111 and the semiconductor region 121, but also the semiconductor region 124 can be used for the photoelectric conversion element 30. If the pixel isolation portion 20 is disposed in the semiconductor region 124, the volume of the photoelectric conversion element 30 is reduced by an amount corresponding to the volume of the pixel isolation portion 20, thus reducing sensitivity.

[0037] Furthermore, the semiconductor region 123 adjacent to the semiconductor region 124 can also be used as a photoelectric conversion element. If the pixel isolation portion 20 is provided in the semiconductor region 124, the pixel isolation portion 20 prevents the movement of charge between the semiconductor region 123 and the semiconductor region 121. Therefore, it becomes difficult to effectively use the semiconductor region 123 as a photoelectric conversion element. By avoiding the arrangement of the pixel isolation portion 20 and by extending the photoelectric conversion element from the semiconductor region 121 to the semiconductor region 124 and further to the semiconductor region 123, sensitivity can be improved.

[0038] exist Figure 1A and Figure 1BIn the example shown, the photoelectric conversion element 30 is configured to extend into the regions corresponding to semiconductor regions 123 and 124. This configuration makes it easier to align the center of the photoelectric conversion element 30 with or closer to the focusing position of the microlens (typically the optical axis of the microlens). To bring the focusing position of the microlens closer to the center of the photodiode, the distance between the optical axis of the microlens and the isolation region 101 can be smaller than the distance between the optical axis of the microlens and the isolation region 103. This configuration allows light to be focused using a microlens located approximately equidistant from the first portion 201 and the second portion 202.

[0039] As described above, by positioning the pixel isolation portion 20 away from the semiconductor region 124, photoelectric conversion performance can be improved in both optical and electrical aspects.

[0040] Figures 3A to 3D Variations in the shape and / or positional relationship between the element isolation portion 10 and the pixel isolation portion 20 are illustrated. For example... Figure 3A As shown, the component isolation portion 10 can have a tapered shape with its width decreasing towards the back surface 2. Additionally, as... Figure 3A As shown, the pixel isolation portion 20 can have a tapered shape with its width decreasing towards the front side 1. A p-type impurity region (not shown), which serves as a channel stop and is denser than the p-type impurity region 50 of the photoelectric conversion element 30, can be provided around the element isolation portion 10. It is desirable that the pixel isolation portion 20 is configured such that its bottom (on the front side 1) contacts the impurity region serving as the channel stop. This configuration allows dark current to be suppressed in a manner similar to that of the bottom of the pixel isolation portion 20.

[0041] exist Figure 3B In the example shown, the pixel isolation portion 20 is configured to span multiple isolation regions spaced apart from each other in the element isolation portion 10. The portions between the multiple isolation regions are element regions. In this way, the pixel isolation portion 20 may include a portion facing the element regions.

[0042] For example Figure 3C As shown, a portion of the pixel isolation portion 20 may be located closer to the front side 1 (not shown) than the bottommost part of the element isolation portion 10 (towards the back side 2). Figure 3C In this configuration, the side of the pixel isolation portion 20 is located closer to the inside than the side of the element isolation portion 10, and the end of the pixel isolation portion 20 facing the front side is held by the element isolation portion 10. In other words, the pixel isolation portion 20 can be configured to penetrate into the element isolation portion 10 or extend further into the central region of the element isolation portion 10. This configuration allows for the reduction of noise generated around the bottom of the pixel isolation portion 20. The element isolation portion 10 can be configured such that its side overlaps with the pixel isolation portion 20.

[0043] like Figure 3D As shown, the pixel isolation portion 20 can have a tapered shape with its width decreasing towards the rear side 2. Furthermore, the pixel isolation portion 20 can be exposed in the front side 1. Additionally, as... Figure 3D As shown, the side of the element isolation portion 10 can be located closer to the inside than the side of the pixel isolation portion 20, and the element isolation portion 10 can be clamped by the end of the front side 1 of the pixel isolation portion 20. In the side view, the element isolation portion 10 can be completely covered by the pixel isolation portion 20.

[0044] Figures 3E to 3G Variations in the construction of impurity regions 40, 50, and 60 are illustrated.

[0045] exist Figure 3E In the example shown, the impurity region 60 includes a well 61 of the pixel transistor 90. The well 61 is made asymmetrical with respect to the center of the pixel transistor 90. More specifically, the area of ​​the well 61 overlapping with the isolation region 101 of the element isolation portion 10 is smaller than the area of ​​the well 61 overlapping with the isolation region 102 of the element isolation portion 10. With this configuration, the volume of the photoelectric conversion element 30 disposed below the isolation region 101 can be increased, thereby improving sensitivity.

[0046] exist Figure 3F In the example shown, the depths of impurity regions 62 and 63, which serve as concentrated p-type regions acting as potential barriers, are different with respect to the front side 1. Impurity region 62 is positioned relative to the reference. Figure 2 The semiconductor region corresponding to the semiconductor region 124 surrounding the pixel isolation section 20 is described. Impurity region 63 is provided in the semiconductor region corresponding to the reference region. Figure 2 The semiconductor region 125 described corresponds to the semiconductor region. Impurity region 63 is set at a greater depth with respect to the front side 1 than impurity region 62. By setting impurity region 63 at a greater depth, noise generated at the interface between pixel isolation portion 20 and semiconductor layer 100 is less likely to be introduced into photoelectric conversion element 30. By setting impurity region 63 at a greater depth, noise generated at the interface between pixel isolation portion 20 and semiconductor layer 100 is less likely to be introduced into photoelectric conversion element 30. Figure 2 The impurity region 63 in the semiconductor region 125 described is formed at a greater depth with respect to the front side 1, which can suppress the generation of noise from the pixel isolation section 20.

[0047] exist Figure 3G In the example shown, the n-type impurity region 40 of the photoelectric conversion element 30 is configured to extend into the semiconductor region 124 and further into the reference region. Figure 2 In the semiconductor region 123 described. By increasing the volume of the impurity region 40 in this way while effectively utilizing the semiconductor regions 124 and 123, the sensitivity or saturation of the photoelectric conversion element 30 can be improved.

[0048] In the following text, reference will be made to Figures 4 to 7 An example describing the layout of pixels. In the following example, the in-plane direction P described above is divided into X and Y directions that intersect (orthogonal) each other. Additionally, the normal direction N is referred to as the Z direction, which intersects (orthogonally) the X and Y directions.

[0049] Reference Figure 4 A first example describing the layout of pixels. Figure 4 In the example shown, the pixel isolation section 20 defines multiple semiconductor region groups in the intermediate plane 3. Each semiconductor region group surrounded by the pixel isolation section 20 includes multiple consecutive semiconductor regions that are not isolated by the pixel isolation section 20. The multiple semiconductor region groups that are isolated from each other are classified into a first type of semiconductor region group Gs and a second type of semiconductor region group Gt.

[0050] Three element regions are set in the respective semiconductor groups Gs of the first type. In the following text, index m is a number of 1 or 3, and index n is a number of 2 or 4. The meaning of these indices will be explained later.

[0051] The photodiode PDm, which serves as a photoelectric conversion element, and the floating diffuser FDm are disposed in the first element region of the three element regions in each semiconductor region group Gs.

[0052] The reset transistor RSm is located in the second element region of the three element regions in each semiconductor region group Gs.

[0053] The well contact WCm is located in the third element region of the three element regions in each semiconductor region group Gs. Here, m is a number of 1 or 3 determined for each semiconductor region group, and... Figure 4 Each semiconductor region group is further equipped with PD1, PD3, RS1, RS3, etc. The component region equipped with photodiode PD3 corresponds to the reference. Figure 2 The described component area is 114.

[0054] Three element regions are arranged in each semiconductor region group Gt of the second type. A photodiode PDn, serving as a photoelectric conversion element, and a floating diffuser FDn are arranged in the first element region of the three element regions in each semiconductor region group Gt. An amplifying transistor SFn and a selecting transistor SLn are arranged in the second element region of the three element regions in each semiconductor region group Gt. A well contact WCn is arranged in the third element region of the three element regions in each semiconductor region group Gt. Here, n is a number of 2 or 4 determined for each semiconductor region group, and... Figure 4PD2, PD4, SF2, SF4, etc., are added to each semiconductor region group. The component region with photodiode PD2 corresponds to the reference. Figure 2 The described component region 112, and the component region where the photodiode PD4 is disposed, corresponds to the reference. Figure 2 The described component region 111. Additionally, the component region where the amplifying transistor SF4 is located corresponds to the reference region. Figure 2 The described component area is 113. (Referencing) Figure 2 In a similar manner to the described element region 113, the semiconductor region below the element region where the well contacts WCn and WCm are located is continuous with the semiconductor region below the element region where the photodiode PD1 is located.

[0055] Well contacts WCm and WCn are connected to conductive members for supplying potential to the impurity region 40 of the photoelectric conversion element 30 via the impurity region 60. By setting well contacts WCn and WCm for each semiconductor region group Gs and Gt as in this example, the controllability of the potential in the semiconductor regions included in the semiconductor region groups Gs and Gt, as well as the controllability of the potential in the element regions within the semiconductor regions, can be increased, and a stable image can be obtained.

[0056] Next, we will refer to Figure 5 A second example describing the layout of pixels. Figure 5 In the example shown, the pixel isolation section 20 defines multiple semiconductor region groups in the intermediate plane 3. Each semiconductor region group surrounded by the pixel isolation section 20 includes multiple consecutive semiconductor regions that are not isolated by the pixel isolation section 20. Four element regions are disposed in each semiconductor region group Gr. In the following text, the index p is a number selected from 1, 3, 5, and 7; and the index q is a number selected from 2, 4, 6, and 8. The meaning of these indices will be explained later.

[0057] Photodiodes PDAp and PDBp, as photoelectric conversion elements, transmission gates TXAp and TXBp, and floating diffusers FDAp and FDBp are disposed in the first element region of the four element regions in each semiconductor region group Gr. The signal charge of photodiode PDAp is transferred to floating diffuser FDAp via transmission gate TXAp. The signal charge of photodiode PDBp is transferred to floating diffuser FDBp via transmission gate TXBp. A common microlens is provided for photodiodes PDAp and PDBp. In other words, photodiodes PDAp and PDBp are provided for a single microlens. Light obtained by photodiodes PDAp and PDBp through pupil division is detected separately, and ranging or focus detection by phase difference detection method can be performed. In addition, by combining the signal obtained with the sensitivity of photodiode PDAp, which is different from the sensitivity of photodiode PDBp, the dynamic range can be widened. In this example, by extending photodiode PDBp into the portion below the pixel transistor, the sensitivity of photodiode PDBp can be made higher than that of photodiode PDAp.

[0058] Photodiodes PDAq and PDBq, as photoelectric conversion elements, transmission gates TXAq and TXBq, and floating diffusers FDAq and FDBq are disposed in the second element region of the four element regions in each semiconductor region group Gr. The signal charge of photodiode PDAq is transferred to floating diffuser FDAq via transmission gate TXAq. The signal charge of photodiode PDBq is transferred to floating diffuser FDBq via transmission gate TXBq. A common microlens is provided for photodiodes PDAq and PDBq. Photodiodes PDAq and PDBq are provided for individual microlenses. Light obtained by photodiodes PDAq and PDBq through pupil segmentation is detected separately, and ranging or focus detection by phase difference detection method can be performed. In addition, by combining the signal obtained with the sensitivity of photodiode PDAq, which is different from the sensitivity of photodiode PDBq, the dynamic range can be widened. In this example, by extending photodiode PDBq into the portion below the pixel transistor, the sensitivity of photodiode PDBq can be made higher than that of photodiode PDAq.

[0059] Here, p is a number selected from 1, 3, 5, and 7, determined for each semiconductor region group Gr. Figure 5 In this context, PDA1, PDB3, FDA1, FDB3, etc., are added to each semiconductor region Gr. The component region with photodiodes PDA3 and PDB3 corresponds to the reference. Figure 2 The described component area is 114.

[0060] Here, q is a number selected from 2, 4, 6, and 8, determined for each semiconductor region group Gr. Figure 5 In this context, PDA2, PDB4, FDA2, FDB4, etc., are added to each semiconductor region Gr. The component region with photodiodes PDA2 and PDB2 corresponds to the reference. Figure 2 The described component region 111. Additionally, the component region where photodiodes PDA6 and PDB6 are located corresponds to the reference region. Figure 2 The described component area is 112.

[0061] The reset transistor RSm, the amplification transistor SFm, and the selection transistor SLm are located in the third element region of the four element regions in each semiconductor region group Gr. The well contact WCm is located in the fourth element region of the four element regions in each semiconductor region group Gr.

[0062] Here, m is a number selected from 1, 2, 3, and 4, determined for each semiconductor region group Gr. Figure 5 In this context, RS1, RS3, WC2, WC4, etc., are added to each semiconductor region Gr. Here, the relationships p = 2 × m – 1 and q = 2 × m hold. The component region equipped with the selection transistor SL1 corresponds to the reference region. Figure 2 The described component area is 113.

[0063] In the first example, by setting a trap contact WCm for each semiconductor region group Gr, the controllability of the potential in the semiconductor regions included in the semiconductor region group Gr and the controllability of the potential in the component regions of the semiconductor regions can be increased, and a stable image can be obtained.

[0064] Furthermore, in this example, photodiodes PDAp and PDBp disposed in the first element region and photodiodes PDAq and PDBq disposed in the second element region share transistors RSm, SFm, and SLm disposed in the third element region. The semiconductor region below the element region, where photodiodes sharing transistors in the above manner are disposed, is not isolated by the pixel isolation portion 20 and is included in a single semiconductor region group. This configuration makes it possible to reduce the difference between the signals of photodiodes PDAp and PDBp disposed in the first element region and the signals of photodiodes PDAq and PDBq disposed in the second element region.

[0065] Furthermore, the pixel isolation section 20 is configured to surround a plurality of photodiodes that are adjacent to each other. Pixel transistors are disposed at the intersections defining the regions of the pixels. Pixel isolation sections 20 are not disposed in such intersections. The pixel isolation section 20 surrounds photodiodes that share a reset transistor RS, an amplification transistor SF, a selection transistor SL, or a well contact WC. According to this example, color mixing can be suppressed, and the influence of the pixel isolation section 20 on the transistors can be reduced.

[0066] Next, we will refer to Figure 6 A third example describing the layout of pixels. Figure 6 In the example shown, within the intermediate plane 3, the first portion 201 and the second portion 202 of the pixel isolation portion 20 define multiple groups of semiconductor regions in the X direction. Each group of semiconductor regions sandwiched by the pixel isolation portion 20 in the X direction includes multiple consecutive semiconductor regions that are not isolated by the pixel isolation portion 20 in the X direction. This feature is similar to that of the second example. Even the same portion of the pixel isolation portion 20 can be referenced based on its positional relationship relative to the photoelectric conversion element of interest. Figure 2 Either the first part 201 or the second part 202 described, therefore in Figure 6 In this context, a given portion of the pixel isolation section 20 is referred to as portion 201 / 202.

[0067] Meanwhile, in this example, the semiconductor region groups sandwiched by the pixel isolation portion 20 in the X direction are isolated in the Y direction by the third portion 203 of the pixel isolation portion 20. This configuration allows for increased isolation performance between pixels in the Y direction. It should be noted that the third portion 203 is discontinuous with the first portion 201 and the second portion 202. Therefore, the semiconductor region groups sandwiched by the pixel isolation portion 20 in the X direction include semiconductor regions that are continuous between semiconductor region groups in the Y direction.

[0068] Photodiodes PDAp and PDBp are disposed in the element region of the first semiconductor region of one semiconductor region group. Photodiodes PDAq and PDBq are disposed in the element region of the first semiconductor region of another semiconductor region group. Transistors RSm, SFm, and SLm are shared by photodiodes PDAp and PDBp, as well as photodiodes PDAq and PDBq.

[0069] The semiconductor regions beneath transistors RSm, SFm, and SLm are not isolated by the pixel isolation section 20, and these semiconductor regions are continuous between semiconductor region groups. In addition to the above, the intersections of semiconductor region groups are not isolated by the pixel isolation section 20, and portions where semiconductor regions are continuous between semiconductor region groups are provided. This is because, in the pixel isolation section 20, the third portion 203 disposed between adjacent photodiodes is discontinuous with the first portion 201 and the second portion 202.

[0070] By providing portions between semiconductor region groups where pixel isolation sections 20 are not located, the range of potentials supplied by a single well is widened. In other words, by making the pixel isolation sections 20 discontinuous, the wells of adjacent pixels can be connected to each other, making the potentials of the wells the same. Furthermore, compared to the first or second example, the number of well contacts can be reduced. As a result, the occurrence of noise caused by well contacts can be suppressed.

[0071] Reference Figure 7 The fourth example describing the layout of pixels. Figure 6 In the example shown, the element isolation portion 10 is provided between the photodiode and the transistor disposed around the photodiode. On the other hand, the element isolation portion 10 is not disposed between adjacent photodiodes. Although not shown, a diffused isolation portion with pn junction isolation is formed between adjacent photodiodes. Therefore, the pixel isolation portion 20 is formed to correspond to the element isolation portion 10 extending along the photodiodes arrayed in a manner that sandwiches the diffused isolation portion.

[0072] According to this example, it is possible to suppress color mixing in the column or row direction in the pixel area and to reduce the influence of the pixel isolation section 20 on the photodiode.

[0073] Next, refer to Figures 8A to 8H The following describes a method for manufacturing a solid-state camera device according to this exemplary embodiment.

[0074] First of all, Figure 8A In step a shown, a trench 11 for the device isolation portion 10 is formed in the front side F of the semiconductor substrate SUB. A channel stop layer (not shown) is formed around the trench 11 by ion implantation.

[0075] Next, in Figure 8B In step b shown, the insulator 12 for the component isolation section 10 is embedded in the trench 11. Silicon oxide is suitable for the insulator 12. Excess insulator outside the trench 11 is removed by chemical mechanical polishing (CMP) or the like. Thus, the component isolation section 10 with an STI (shallow trench isolation) structure is formed.

[0076] Next, in Figure 8C In step c shown, a gate insulating film (not shown) and a gate electrode 80 are laminated onto the front side F of the semiconductor substrate SUB, thereby forming a pixel transistor (not shown). Furthermore, the source-drain region of the photoelectric conversion element 30 and the pixel transistor is formed by ion implantation performed from the front side F of the semiconductor substrate SUB.

[0077] Next, in Figure 8D In step d shown, an insulating layer covering the gate electrode 80 is laminated, and then contact holes are formed in the insulating layer. Furthermore, a wiring layer and an interlayer insulating layer are laminated onto the insulating layer where the contact holes are formed, thus forming a multilayer wiring structure. In this example, three wiring layers 310, 320, and 330 are formed. For example, copper or aluminum wires can be used for the wiring structure.

[0078] Next, in Figure 8E In step e shown, the support substrate 400 is attached to the insulating film 300 from above. The support substrate 400 can be attached by adhesive bonding or other known methods. However, it is preferred that the attachment be performed at a temperature not exceeding 400°C so that the wiring structure is not affected.

[0079] Next, in Figure 8F In step f shown, a thinning process is performed from the back side B1 of the semiconductor substrate SUB until the semiconductor substrate SUB has the desired thickness. The thinning of the semiconductor substrate SUB creates a new back side B2 that replaces the back side B1. The back side B2 can be bounded by the photoelectric conversion element 30. For example, chemical mechanical polishing (CMP), dry etching, wet etching, etc., can be used. Alternatively, these techniques can be combined. For example, the film thickness of the thinned semiconductor substrate SUB can be in the range of 1 μm to 10 μm, and from the perspective of improving the light-receiving sensitivity of the photodiode or the mechanical strength of the semiconductor substrate, a film thickness in the range of 2 μm to 5 μm is preferred.

[0080] Next, in Figure 8GIn step g shown, a trench 21 for the pixel isolation portion 20 is formed in the back side B2 of the semiconductor substrate SUB at a position opposite to where the element isolation portion 10 is formed in the front side F of the semiconductor substrate SUB. At this point, the depth of the trench 21 for the pixel isolation portion 20 relative to the back side B2 can be the depth from the bottom of the pixel isolation portion 20 to the element isolation portion 10. For example, if the thickness of the semiconductor substrate SUB after thinning is approximately 2 μm and the depth of the element isolation portion 10 is approximately 0.3 μm, then the trench 21, which is to be positioned opposite the element isolation portion 10, is formed to have a depth of approximately 1.7 μm. This pixel isolation portion 20 is formed by the following process. Here, the width of the bottom of the pixel isolation portion 20 can be made smaller than the width of the bottom of the element isolation portion 10. With this configuration, it becomes easier to make the bottom of the pixel isolation portion 20 contact the bottom of the element isolation portion 10 even when alignment shift occurs.

[0081] The trench 21 of the pixel isolation portion 20 is not provided under the isolation region 101 adjacent to the photoelectric conversion element 30, which is part of the element isolation portion 10. This structure enables the aforementioned photoelectric conversion performance to be improved.

[0082] The method for forming the pixel isolation portion 20 will be described in further detail. First, in order to form the trench 21 of the pixel isolation portion 20 in the semiconductor substrate SUB, anisotropic dry etching is used, for example, to form the trench 21 with a desired width. When the trench 21 of the pixel isolation portion 20 is processed by dry etching, the terminal of the semiconductor substrate SUB during etching can be detected using the element isolation portion 10. Alternatively, etching can be performed using an etching time specified according to the film thickness of the semiconductor substrate SUB. In addition, a portion of the bottom of the element isolation portion 10 can be etched.

[0083] Next, in Figure 8G In step g shown, a solid 22 is formed in the trench 21. First, a fixed charge film (not shown) is formed to suppress dark current generated in the back surface 2 of the semiconductor layer 100. Therefore, the fixed charge film (not shown) is formed according to the shape of the back surface B2 of the semiconductor substrate SUB. This fixed charge film is formed at least on the back surface B2 of the semiconductor substrate SUB, and may also be formed to cover the sidewalls or bottom surface of the trench 21 of the pixel isolation portion 20. By covering the sidewalls and bottom surface of the pixel isolation portion 20 with a fixed charge film in this way, dark current that may be generated on the front surface of the trench 21 can also be suppressed. For example, a hafnium oxide film formed by atomic layer deposition (ALD) can be used for the fixed charge film.

[0084] Next, a solid 22 made of a dielectric material, a metallic material, a light-shielding material, or a combination of these materials is formed inside the pixel isolation portion 20 of the semiconductor substrate SUB. For example, a film of a material having a lower refractive index than the silicon forming the semiconductor substrate SUB (e.g., a silicon oxide film or a titanium oxide film) is formed on a fixed charge film. Subsequently, the conductive material is buried by chemical vapor deposition (CVD) or atomic layer deposition (ALD), thereby forming the pixel isolation portion 20. Alternatively, a silicon oxide film is formed on the fixed charge film by atomic layer deposition (ALD), and then another silicon oxide film is deposited thereon by high-density plasma (HDP) CVD. In this way, the pixel isolation portion 20 can be formed by burying it with a double-layer insulating film. In particular, materials that can be formed at a low temperature of no more than 400°C are preferred, and it is desirable to deposit amorphous silicon doped with P-type impurities, copper, tungsten, etc., by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Here, the aforementioned fixed charge film can be used as the solid 22.

[0085] Although an example of embedding the solid 22 into the pixel isolation portion 20 has been described above, the internal structure of the trench 21 is not limited to this, and any known structure and manufacturing method capable of suppressing color mixing can be used. Furthermore, part or all of the trench 21 of the pixel isolation portion 20 may, for example, be hollow.

[0086] Although the formation of the pixel isolation portion 20 from the back side B2 of the semiconductor substrate has been described in this example, the method of forming the pixel isolation portion 20 is not limited to the method described herein. For example, a trench 21 may be formed from the front side F of the semiconductor substrate SUB before forming the element isolation portion 10 as described in steps a and b.

[0087] After that, it formed Figure 1A The structure shown is as follows. A dielectric film 410 is formed on the back side B2 of the semiconductor substrate SUB, and light-shielding members 420 are patterned between pixels on the dielectric film 410. After film deposition by sputtering or chemical vapor deposition (CVD), the light-shielding members 420 are formed by removing the portion except for the portion requiring the light-shielding structure (including the portion between pixels). As materials for the light-shielding members 420, for example, a laminate of titanium and tungsten, a laminate of titanium nitride and tungsten, etc., can be used.

[0088] Next, a planarization film (not shown) is formed, and a color filter array 430, corresponding to each pixel (e.g., red, green, and blue), is formed on the planarization film. A microlens array 440 is then formed on the color filter array 430. The color filters and microlenses are formed to correspond to each pixel in the pixel array. Using the method described above, a photoelectric conversion device is completed. A semiconductor substrate SUB is used as the semiconductor layer 100 described above.

[0089] According to the example above, by extending the pixel isolation portion 20 into the element isolation portion 10 in the depth direction, color mixing between adjacent pixels can be effectively suppressed. The pixel isolation portion 20 can be configured to surround not only the photoelectric conversion element but also the semiconductor region beneath the element region where transistors are disposed. This configuration allows for a wider range of photoelectric conversion performed by the photoelectric conversion element.

[0090] The photoelectric conversion device 1000 described herein can be applied to Figure 9 The camera 2000 shown has an image sensor 1001.

[0091] In addition to the imaging device 1001, the camera 2000 may also include at least one of the following: a signal processing device 1002 for processing signals obtained from the imaging device, a storage device 1003 for storing signals obtained from the imaging device, and a display device 1004 for displaying information obtained from the imaging device. Besides dedicated camera devices such as still cameras, video cameras, and surveillance cameras, the camera 2000 used herein also includes an information terminal equipped with imaging capabilities and a mobile body (vehicle, aircraft, etc.) equipped with imaging capabilities.

[0092] Even if not explicitly stated in this specification, features that can be obtained from the accompanying drawings and common general technical knowledge constitute a part of this disclosure. This disclosure can be appropriately modified without departing from its technical spirit.

[0093] While this disclosure has been described with reference to exemplary embodiments, it should be understood that this disclosure is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be interpreted in the broadest possible sense to cover all such variations and equivalent structures and functions.

Claims

1. A photoelectric conversion device, the photoelectric conversion device comprising: The semiconductor layer has a first surface and a second surface, wherein the second surface is opposite to the first surface. The semiconductor layer includes a first isolation portion, a first region where a first photoelectric conversion element is disposed, a second region adjacent to the first region where a second photoelectric conversion element is disposed, and a transistor configured to transfer the signal charge of the first photoelectric conversion element to a charge detection region. The first isolation portion is formed by a first trench and includes a first insulator disposed in the first trench. The first trench is disposed in the semiconductor layer and passes through a virtual plane. The virtual plane is closer to the second surface than the first surface and is disposed along the second surface. In this configuration, at least a portion of the first photoelectric conversion element, the gate electrode of the transistor, the first isolation portion, and at least a portion of the second photoelectric conversion element are arranged in this order along a first direction. In the plan view, the longitudinal direction of the first isolation portion extends along a virtual straight line intersecting the first direction, and The semiconductor layer includes a well contact region for supplying potential to the wells in the first region and the second region, the well contact region being located on the virtual straight line in the plan view.

2. The photoelectric conversion device according to claim 1, wherein The trap contact area is surrounded by a second insulating portion, which includes a second insulator disposed on the first side in a plan view.

3. The photoelectric conversion device according to claim 1, wherein The traps in the first region and the second region are interconnected.

4. The photoelectric conversion device according to claim 1, wherein, The first region includes a first transistor, the first transistor including a first gate electrode disposed on the first surface and configured to read signals from the first photoelectric conversion element, and the second region includes a second transistor, the second transistor including a second gate electrode disposed on the first surface and configured to read signals from the second photoelectric conversion element.

5. The photoelectric conversion device according to claim 4, further comprising a second isolation portion, the second isolation portion comprising a second insulator disposed on the first surface side. wherein The first gate electrode is disposed on the second isolation portion.

6. The photoelectric conversion device according to claim 1, wherein The semiconductor layer includes a third isolation portion, a third region for providing a third photoelectric conversion element, and a fourth region for providing a fourth photoelectric conversion element. The third isolation portion is formed by a third trench and includes a third insulator disposed in the third trench. The third trench is disposed in the semiconductor layer and passes through the virtual plane. The third photoelectric conversion element, the third isolation section, and the fourth photoelectric conversion element are arranged in this order along the second direction, and The third isolation section extends longitudinally along the virtual straight line.

7. The photoelectric conversion device according to claim 1, wherein The first region includes a third photoelectric conversion element, and the second region includes a fourth photoelectric conversion element.

8. The photoelectric conversion device according to claim 7, further comprising a microlens. wherein, The first photoelectric conversion element and the third photoelectric conversion element are arranged between the microlens and the first surface.

9. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device further comprises a microlens array and a light-shielding component.

10. The photoelectric conversion device according to claim 1, wherein The first isolation portion includes at least one of a hollow portion, a metallic material, and a light-shielding material.

11. The photoelectric conversion device according to claim 1, wherein A fixed charge film is provided in the first groove of the first isolation section.

12. The photoelectric conversion device according to claim 1, wherein The first groove of the first isolation section is at least partially hollow.

13. The photoelectric conversion device according to claim 1, wherein The semiconductor layer includes a first transistor and a second transistor, each transistor being configured to read out a signal based on the signal charge of the first photoelectric conversion element. The first transistor and the second transistor are arranged along a third direction, and the well contact region is located in the third direction.

14. The photoelectric conversion device according to claim 1, wherein The semiconductor layer includes a first transistor configured to read out a signal based on the signal charge of the first photoelectric conversion element, and a second transistor configured to read out a signal based on the signal charge of the second photoelectric conversion element. The well contact region is located between the first transistor and the second transistor.

15. The photoelectric conversion device according to claim 1, wherein, The gate electrode of the transistor is disposed on the second surface.

16. The photoelectric conversion device according to claim 1, wherein The semiconductor layer includes a transistor region and another well contact region for supplying potential to the wells in the semiconductor layer. The well contact region, the transistor region, and the other well contact region are arranged in this order along the first direction.

17. The photoelectric conversion device according to claim 16, wherein The transistor region does not include photoelectric conversion elements.

18. A camera, the camera comprising: The photoelectric conversion device according to any one of claims 1-17; and A signal processing device configured to process signals obtained from the photoelectric conversion device.

19. A camera, the camera comprising: The photoelectric conversion device according to any one of claims 1-17; and At least one of the following: a signal processing device configured to process signals obtained from the photoelectric conversion device; a storage device configured to store signals obtained from the photoelectric conversion device; and a display device configured to display information obtained from the photoelectric conversion device.

Images