A circuit for generating a reference clock in a PCIE fixture

Abstract

The present invention discloses a circuit for generating a reference clock in a PCIE fixture. The circuit includes a switch module, a control module, and a crystal oscillator module. The switch module and the crystal oscillator module are both connected to the control module. The crystal oscillator module continuously outputs an initial clock signal with a constant frequency and sends the initial clock signal to the control module. The switch module generates a trigger signal of constant duration through a trigger circuit. The switch module sends the trigger signal to a timing module. The timing module generates a control signal of constant duration. The timing module sends the control signal to the control module. The control module combines the initial clock signal and the control signal to generate a reference clock signal of constant duration and constant frequency. The control module integrates the initial timing module that continuously outputs a constant frequency and the control signal of constant duration, thereby generating a reference clock signal of constant duration and constant frequency. This circuit meets the requirements of PCIE consistency testing and has a simple circuit structure, low cost, and is easy to promote.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board testing, and more particularly to a circuit for generating a reference clock in a PCIE fixture. Background Art

[0002] Printed circuit boards (PCBs), also known as printed circuit boards or printed circuit boards, are a crucial component of electronic products' physical support and signal transmission. For PCI Express (PCIe) conformance testing of PCBs, a CLB (Compliance Load Board) fixture is required to test the performance of PCIe motherboards, or a CBB (Compliance Base Board) fixture is required to test the performance of PCIe gold finger cards.

[0003] During this process, a set of reference clock signals needs to be generated on the CLB fixture or CBB fixture and transmitted to the DUT through the RX0 differential line of the fixture board to control the chip of the DUT to send code patterns of different rates. Then, an oscilloscope is connected to the CLB fixture or CBB fixture to perform eye diagram testing. This is stipulated by the PCIE test protocol.

[0004] There are strict requirements for the generated reference clock signal. The frequency of the general reference clock signal is 100MHz and the duration period is 1ms. Only in this way can the reference clock signal be input into the chip under test to make the chip under test generate a switching code pattern.

[0005] Therefore, a method is needed to generate a reference clock signal that meets the above requirements in a PCIE fixture. Summary of the Invention

[0006] In order to generate a reference clock signal with a frequency of 100 MHz and a duration of 1 ms in a PCIE, the present invention provides a circuit for generating a reference clock in a PCIE fixture.

[0007] The technical solution of the present invention is as follows:

[0008] A circuit for generating a reference clock in a PCIE fixture includes a switch module, a control module, and a crystal oscillator module. The switch module and the crystal oscillator module are both connected to the control module. The crystal oscillator module continuously outputs an initial clock signal of a constant frequency and sends the initial clock signal to the control module. The switch module generates a trigger signal of a constant duration through a trigger circuit. The switch module sends the trigger signal to a timing module. The timing module generates a control signal of a constant duration. The timing module sends the control signal to the control module. The control module combines the initial clock signal and the control signal to generate a reference clock signal of a constant duration and a constant frequency.

[0009] The above-mentioned circuit for generating a reference clock in a PCIE fixture, the switch module includes a push button switch, the push button switch is connected to the timing chip of the timing module through two universal logic gate chips, the push button switch outputs a low-level trigger signal, the low-level trigger signal is sent to the timing chip through the universal logic gate chip, and the timing chip generates the high-level control signal.

[0010] Furthermore, the button switch includes an eighth control SW8 and a ninth control SW9, the first pin of the eighth control SW8 is respectively connected to the first pin of the ninth control SW9 and the fifth pin of one of the universal logic gate chips, the second pin of the eighth control SW8 is connected to the third pin of the ninth control SW9, the third pin of the eighth control SW8 is connected to the first pin of one of the universal logic gate chips, the first pin of the ninth control SW9 is respectively connected to the first pin of the eighth control SW8 and the fifth pin of one of the universal logic gate chips, and the third pin of the ninth control SW9 is connected to the second pin of the eighth control SW8.

[0011] Furthermore, the timing chip is respectively connected to two parallel resistors and a grounded capacitor, and the period of the control signal generated by the timing chip is T=C×(RA×RA1) / (RA+RA1).

[0012] Furthermore, the universal logic gate chip includes a third chip U3 and a fifth chip U5, the button switch connects the first pin of the third chip U3 and the fifth pin of the third chip U3, the third pin of the third chip U3 and the fourth pin of the third chip U3 are connected to the first pin of the fifth chip U5, the second pin of the fifth chip U5, the tenth pin of the fifth chip U5 and the thirteenth pin of the fifth chip U5 through a connector.

[0013] In the above-mentioned circuit for generating a reference clock in a PCIE fixture, the control signal sent by the timing module is connected to the control module via a reverse chip.

[0014] Furthermore, the third pin of the timing chip of the timing module outputs a high-level first control signal, the first control signal is sent to the first pin of the reverse chip through the 110th connector J110, the second pin of the reverse chip outputs a low-level second control signal with the same frequency as the first control signal, and the reverse chip outputs the second control signal to the control module.

[0015] In the above-mentioned circuit for generating a reference clock in a PCIE fixture, the crystal oscillator module is provided with a differential clock circuit, and the differential clock circuit outputs the initial clock signal with a frequency of 100 MHz.

[0016] Furthermore, the first output end of the differential time difference circuit is connected to the second pin of the control chip of the control module, and the second output end of the differential time difference circuit is connected to the fifth pin of the control chip.

[0017] The above-mentioned circuit for generating a reference clock in a PCIE fixture, the control signal is input into the first pin of the control chip of the control module and the fourth pin of the control chip, the output end of the differential clock circuit of the crystal oscillator module is respectively connected to the second pin of the control chip and the fifth pin of the control chip, and the third pin of the control chip and the sixth pin of the control chip output the reference clock signal.

[0018] Furthermore, the sixth pin of the control chip is connected to a radio frequency connector, and the control module sends the reference clock signal through the radio frequency connector.

[0019] The beneficial effect of the present invention according to the above scheme is that the present invention integrates the initial timing module with continuous output of constant frequency and the control signal of constant duration through the control module, thereby generating a reference clock signal with constant duration and constant frequency, meeting the requirements of PCIE consistency test, having a simple circuit structure and low cost, and being conducive to promotion.

[0020] The present invention uses a push button switch to generate a trigger signal, which serves as a trigger for a control signal. By combining these two signals through a control chip, the generation timing, signal duration, and output period of the resulting reference clock signal are independently controlled: the push button switch controls the generation timing of the reference clock signal, the frequency of the initial clock signal output by the crystal oscillator module controls the frequency of the reference clock signal, and the control signal output by the timing module controls the duration of the reference clock signal. This system has strong overall controllability and is easily incorporated into various intelligent systems, improving circuit board production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 Schematic diagram of the circuit structure of the button switch and the third chip U3.

[0023] Figure 2 Schematic diagram of the circuit structure of the fifth chip U5.

[0024] Figure 3 FIG. 2 is a schematic diagram of the circuit structure of the second chip U2 .

[0025] Figure 4 FIG. 4 is a schematic diagram of the circuit structure of the fourth chip U4.

[0026] Figure 5 Schematic diagram of the circuit structure of the first chip U1 and the RF connector. DETAILED DESCRIPTION

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] A circuit for generating a reference clock in a PCIE fixture includes a switch module, a control module, and a crystal oscillator module. The switch module and the crystal oscillator module are both connected to the control module. The crystal oscillator module continuously outputs an initial clock signal with a constant frequency and sends the initial clock signal to the control module. The switch module generates a trigger signal of constant duration through a trigger circuit. The switch module sends the trigger signal to a timing module. The timing module generates a control signal of constant duration. The timing module sends the control signal to the control module. The control module combines the initial clock signal and the control signal to generate a reference clock signal of constant duration and constant frequency.

[0029] The circuit includes a crystal oscillator module, which continuously outputs a constant initial clock signal with a frequency of 100Mhz after being connected to the circuit. Since the initial clock signal is a continuously output signal, its waveform remains unchanged and is continuous, and it is impossible to generate a signal waveform with a period of only 1 millisecond. The switch module provides a control signal of constant duration, and the push button switch generates a trigger signal of 1 millisecond. The low-level trigger signal outputs a high-level control signal of 1 millisecond after passing through the timing module. The control module simultaneously integrates the output high-level control signal with the initial clock signal output by the crystal oscillator module, and reversely processes the high-level control signal to form a low-level intermediate control signal of 1 millisecond. The other end of the control module inputs the 100MHz differential initial clock signal generated by the crystal oscillator module, and forms a reference clock signal with a frequency of 100MHz that lasts for 1 millisecond after the operation of the control chip.

[0030] In this embodiment, the specific circuit is as follows:

[0031] like Figure 1 As shown, the button switch includes an eighth control SW8 and a ninth control SW9.

[0032] The first pin of the eighth control SW8 is respectively connected to the first pin of the ninth control SW9, the other end of the ninety-fourth resistor R94 and the fifth pin of the third chip U3; the second pin of the eighth control SW8 is connected to the third pin of the ninth control SW9; the third pin of the eighth control SW8 is respectively connected to the other end of the ninety-third resistor R93 and the first pin of the third chip U3; the fourth pin of the eighth control SW8 and the fifth pin of the eighth control SW8 are both grounded.

[0033] The first pin of the ninth control SW9 is respectively connected to the first pin of the eighth control SW8, the other end of the ninety-fourth resistor R94 and the fifth pin of the third chip U3, the second pin of the ninth control SW9 is grounded, the third pin of the ninth control SW9 is connected to the second pin of the eighth control SW8, and the fourth pin of the ninth control SW9 and the fifth pin of the ninth control SW9 are both grounded.

[0034] One end of the ninety-third resistor R93 is connected to the 3.3V power supply, and the other end is respectively connected to the third pin of the eighth control SW8 and the first pin of the third chip U3.

[0035] One end of the ninety-fourth resistor R94 is connected to the 3.3V power supply, and the other end is respectively connected to the first pin of the eighth control SW8, the first pin of the ninth control SW9, and the fifth pin of the third chip U3.

[0036] The first pin of the third chip U3 is connected to the other end of the ninety-third resistor R93 and the third pin of the eighth control SW8 respectively, the second pin of the third chip U3 is connected to the sixth pin of the third chip U3, the third pin of the third chip U3 and the fourth pin of the third chip U3 are both connected to the output circuit and the thirteenth pin of the third chip U3, the fifth pin of the third chip U3 is connected to the other end of the ninety-fourth resistor R94, the first pin of the eighth control SW8 and the first pin of the ninth control SW9 respectively, the sixth pin of the third chip U3 is connected to the second pin of the third chip U3, the seventh pin of the third chip U3 is grounded, the eighth pin of the third chip U3 is connected to the push-pull output circuit, and the ninth pin of the third chip U3 is connected to the push-pull output circuit. The tenth pin of the third chip U3 and the eleventh pin of the third chip U3 are respectively connected, the tenth pin of the third chip U3 is respectively connected to the ninth pin of the third chip U3 and the eleventh pin of the third chip U3, the eleventh pin of the third chip U3 is respectively connected to the ninth pin of the third chip U3 and the tenth pin of the third chip U3, the twelfth pin of the third chip U3 is respectively connected to the other end of the twenty-sixth resistor R216 and the fourth pin of the transmission line pulse generator, the thirteenth pin of the third chip U3 is respectively connected to the output circuit, the third pin of the third chip U3 and the fourth pin of the third chip U3, and the fourteenth pin of the third chip U3 is respectively connected to the 3.3V power supply and one end of the fifty-first capacitor C151.

[0037] One end of the 151st capacitor C151 is respectively connected to the fourteenth pin of the third chip U3 and the 3.3V power supply, and the other end is grounded.

[0038] One end of the 216th resistor R216 is connected to the 3.3V power supply, and the other end is respectively connected to the fourth pin of the transmission line pulse generator and the twelfth pin of the third chip U3.

[0039] The first pin of the transmission line pulse generator is connected to the first pin of the 124th connector J124, the second pin of the transmission line pulse generator is connected to the second pin of the 124th connector J124, the third pin of the transmission line pulse generator is grounded, and the fourth pin of the transmission line pulse generator is respectively connected to one end of the 216th and the twelfth pin of the third chip U3.

[0040] The output circuit is connected to the fifth chip U5 via the 147th connector J147.

[0041] like Figure 2As shown, the first pin of the fifth chip U5, the second pin of the fifth chip U5, and the thirteenth pin of the fifth chip U5 are all connected to the third pin of the third chip U3 and the fourth pin of the third chip U3, the third pin of the fifth chip U5 and the fourth pin of the fifth chip U5 are all connected to the other end of the 153rd capacitor C153, the fifth pin of the fifth chip U5 is respectively connected to the eighth pin of the fifth chip U5 and the twelfth pin of the fifth chip U5, the sixth pin of the fifth chip U5 is connected to the ninth pin of the fifth chip U5, the seventh pin of the fifth chip U5 is grounded, and the eighth pin of the fifth chip U5 is grounded. The fifth pin of the fifth chip U5 is connected to the twelfth pin of the fifth chip U5, the ninth pin of the fifth chip U5 is connected to the sixth pin of the fifth chip U5, the tenth pin of the fifth chip U5 is connected to the third pin of the third chip U3 and the fourth pin of the third chip U3, the eleventh pin of the fifth chip U5 is connected to the second pin of the one hundred and fourth connector J104, the thirteenth pin of the fifth chip U5 is connected to the third pin of the third chip U3 and the fourth pin of the third chip U3, and the fourteenth pin of the fifth chip U5 is respectively connected to the 3.3V power supply and one end of the two hundred and thirty-eighth capacitor C238.

[0042] One end of the 153rd capacitor C153 is grounded, and the other end is connected to the third pin of the fifth chip U5 and the fourth pin of the fifth chip U5.

[0043] One end of the 238th capacitor C238 is respectively connected to the fourteenth pin of the fifth chip U5 and the 3.3V power supply, and the other end is grounded.

[0044] A first pin of the one hundred and fourth connector J104 is grounded, and a second pin of the one hundred and fourth connector J104 is connected to an eleventh pin of the fifth chip U5.

[0045] The one hundred and fourth connector J104 is connected to the second chip U2.

[0046] The eleventh pin of the fifth chip U5 is connected to the second pin of the second chip U2 via the one hundred and fourth connector J104.

[0047] like Figure 3As shown, the first pin of the second chip U2 is grounded, the second pin of the second chip U2 is connected to the eleventh pin of the fifth chip U5, the third pin of the second chip U2 is connected to the second pin of the one-hundredth connector J110, the fourth pin of the second chip U2 is respectively connected to the 3.3V power supply, one end of the one-hundredth resistor R100, one end of the one-hundredth resistor R103 and the eighth pin of the second chip U2, the fifth pin of the second chip U2 is left floating, the sixth pin of the second chip U2 and the seventh pin of the second chip U2 are both connected to the other end of the one-hundredth resistor R100, the other end of the one-hundredth resistor R103 and one end of the one-hundredth capacitor C144, and the eighth pin of the second chip U2 is connected to the fourth pin of the second chip U2, the 3.3V power supply, one end of the one-hundredth resistor R100 and one end of the one-hundredth resistor R103.

[0048] One end of the 100th resistor R100 is respectively connected to the 3.3V power supply, one end of the 103rd resistor R103, the fourth pin of the second chip U2 and the eighth pin of the second chip U2, and the other end is respectively connected to the sixth pin of the second chip U2, the seventh pin of the second chip U2, one end of the 144th capacitor C144 and the other end of the 103rd resistor R103.

[0049] One end of the 103rd resistor R103 is respectively connected to the 3.3V power supply, one end of the 100th resistor R100, the fourth pin of the second chip U2 and the eighth pin of the second chip U2, and the other end is respectively connected to the sixth pin of the second chip U2, the seventh pin of the second chip U2, one end of the 144th capacitor C144 and the other end of the 100th resistor R100.

[0050] One end of the 144th capacitor C144 is respectively connected to the sixth pin of the second chip U2, the seventh pin of the second chip U2, the other end of the 100th resistor R100 and the other end of the 103rd resistor R103, and the other end is grounded.

[0051] A first pin of the one-hundred-tenth connector J110 is grounded, and a second pin of the one-hundred-tenth connector J110 is connected to a third pin of the fifth chip U5.

[0052] like Figure 4As shown, the first pin of the fourth chip U4 is connected to the third pin of the second chip U2, the second pin of the fourth chip U4 is connected to the second pin of the 101st connector J101, the first pin of the first chip U1 and the fourth pin of the first chip U1, the third pin of the fourth chip U4, the fifth pin of the fourth chip U4, the seventh pin of the fourth chip U4, the ninth pin of the fourth chip U4, the eleventh pin of the fourth chip U4 and the thirteenth pin of the fourth chip U4 are all grounded, the fourth pin of the fourth chip U4, the sixth pin of the fourth chip U4, the eighth pin of the fourth chip U4, the tenth pin of the fourth chip U4 and the twelfth pin of the fourth chip U4 are all floating, and the fourteenth pin of the fourth chip U4 is respectively connected to the 3.3V power supply and one end of the 237th capacitor.

[0053] The first pin of the 101st connector J101 is grounded, and the second pin of the 101st connector J101 is respectively connected to the second pin of the fourth chip U4, the first pin of the first chip U1, and the fourth pin of the first chip U1.

[0054] like Figure 5 As shown, the first pin of the first chip U1 is connected to the second pin of the 101st connector J101, the second pin of the fourth chip U4 and the fourth pin of the first chip U1, the second pin of the first chip U1 is connected to the first output end of the differential clock circuit, the third pin of the first chip U1 is connected to one end of the 120th capacitor C120, the fourth pin of the first chip U1 is connected to the second pin of the 101st connector J101, the first pin of the first chip U1 and the second pin of the fourth chip U4, the fifth pin of the first chip U1 is connected to the second output end of the differential clock circuit, the sixth pin of the first chip U1 is connected to the 119th capacitor C119, the seventh pin of the first chip U1 is grounded, the eighth pin of the first chip U1, the ninth pin of the first chip U1, the eleventh pin of the first chip U1 and the twelfth pin of the first chip U1 are left floating, the tenth pin of the first chip U1 and the thirteenth pin of the first chip U1 are both connected to the 104th resistor.

[0055] One end of the 119th capacitor C119 is connected to the sixth pin of the first chip U1 , and the other end is connected to one end of the 95th resistor R95 .

[0056] One end of the ninety-fifth resistor R95 is connected to the other end of the one hundred and nineteenth capacitor C119 , and the other end is respectively connected to the first pin of the ninety-third RF connector S93 and one end of the two hundred and twenty-second resistor R212 .

[0057] The first pin A of the ninety-third RF connector S93 is respectively connected to the other end of the ninety-fifth resistor R95 and one end of the two-hundred-twelfth resistor R212, and the second pin of the ninety-third RF connector S93, the third pin of the ninety-third RF connector S93, the fourth pin of the ninety-third RF connector S93 and the fifth pin of the ninety-third RF connector S93 are grounded.

[0058] One end of the 212th resistor R212 is respectively connected to the other end of the 95th resistor R95 and the first pin of the 93rd RF connector S93 , and the other end thereof is grounded.

[0059] One end of the 120th capacitor C120 is connected to the third pin of the first chip U1 , and the other end is connected to one end of the 96th resistor R96 .

[0060] One end of the ninety-sixth resistor R96 is connected to the other end of the one hundred and twentieth capacitor C120 , and the other end is connected to the first pin of the ninety-fourth RF connector S94 and one end of the two hundred and thirteenth resistor R213 .

[0061] One end of the 213th resistor R213 is respectively connected to the first pin of the 94th RF connector S94 and the other end of the 96th resistor R96 , and the other end of the 213th resistor R213 is grounded.

[0062] The first pin of the ninety-fourth RF connector S94 is respectively connected to the other end of the ninety-sixth resistor R96 and one end of the two-hundred-thirteenth resistor R213, and the second pin of the ninety-fourth RF connector S94, the third pin of the ninety-fourth RF connector S94, the fourth pin of the ninety-fourth RF connector S94 and the fifth pin of the ninety-fourth RF connector S94 are all grounded.

[0063] According to the above circuit structure, the first pin of the push button switch outputs a trigger signal, which is sent along the circuit to the first and fifth pins of the third chip U3. The trigger signal is then output from the third and fourth pins of the third chip U3 via the 147th connector J147 to the first, second, and tenth and thirteenth pins of the fifth chip U5. The trigger signal is then output from the eleventh pin of the fifth chip U5 via the 104th connector J104 to the second pin of the second chip U2. In the control chip of the push button switch, the second and first pins are connected when the push button switch is pressed. When the push button switch is released, the second and third pins of the two controls of the push button switch are connected. Therefore, in this embodiment, the circuit connection is configured such that the first pin is grounded and the third pin is left floating. This allows a low-level trigger signal to be generated when the push button switch is pressed. This low-level trigger signal then passes through two universal logic gate chips (the third chip U3 and the fifth chip U5). The universal logic gate chips are used to establish a timing chip that can work normally under all trigger pulse conditions, provide the timing chip with a latching function of the trigger signal, and ensure that the timing chip is only triggered once after the button switch is pressed, so that the control signal finally generated is a constant signal of 1 millisecond.

[0064] Pin 11 of chip U5 outputs a signal via connector J104 to pin 2 of chip U2 (the timing chip). This signal is then passed through resistor R100 (the 100th resistor), resistor R103 (the 103rd resistor), and capacitor C144 (the 144th capacitor). According to the timing chip's operating principle, the clock signal's period is T = C × (RA × RA1) / (RA + RA1). For example, RA = 22k ohms, RA1 = 1k ohm, and C = 1uF. Substituting this into the above formula yields: T = C × (RA × RA1) / (RA + RA1) = 1uF × (22k ​​× 1k) / (22k ​​+ 1k), which is approximately 1ms, meeting the specified requirements. Substituting the above calculation results into the 100th resistor R100, the 103rd resistor R103 and the 144th capacitor C144, the resistance of the 100th resistor R100 is 22K ohms, the resistance of the 103rd resistor R103 is 1K ohm, and the capacitance of the 144th capacitor C144 is 1uF.

[0065] The resulting high-level control signal, which lasts for 1 millisecond, is output from pin 3 of the second chip U2 and sent via connector J110 to pin 1 of the fourth chip U4. The fourth chip U4 is a reverse chip. After the reverse chip's calculations, the high-level control signal undergoes a reverse transformation, becoming a low-level control signal with a duration of 1 millisecond.

[0066] A low-level control signal is output from the second pin of the fourth chip U4 to the first pin of the first chip U1 and the fourth pin of the first chip U1. The first chip U1 is the control chip. At the same time, the crystal oscillator module sends the initial differential clock signal (frequency is 100MHz) to the second pin of the first chip U1 and the fifth pin of the first chip U1 through the two output ends of the differential clock circuit. According to the operation of the first chip U1 (control chip), the third pin of the first chip U1 and the sixth pin of the third chip U3 output a reference clock signal with a duration of 1 millisecond and 100MHz, which is sent out through the RF connector.

[0067] In this embodiment, the model of the first chip U1 (control chip) is QS3VH125S1G.

[0068] In this embodiment, the model of the fourth chip U4 (reverse chip) is SN74LVC04ADR.

[0069] In this embodiment, the model of the second chip U2 (timing chip) is LMC555CMX.

[0070] In this embodiment, the model of the third chip U3 (universal logic gate chip) is SN74AC00DR.

[0071] In this embodiment, the signal of the fifth chip U5 (universal logic gate chip) is SN74AC00DR

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit for generating a reference clock in a PCIE fixture, characterized in that: It includes a switch module, a control module and a crystal oscillator module, the switch module and the crystal oscillator module are both connected to the control module, the crystal oscillator module continuously outputs an initial clock signal of a constant frequency and sends the initial clock signal to the control module, the switch module generates a trigger signal of a constant duration through a trigger circuit, the switch module sends the trigger signal to a timing module, the timing module generates a control signal of a constant duration, the timing module sends the control signal to the control module, and the control module combines the initial clock signal and the control signal to generate a reference clock signal of a constant duration and a constant frequency; the switch module includes a button switch, the button switch is connected to the timing chip of the timing module through two universal logic gate chips, the button switch outputs a low-level trigger signal, the low-level trigger signal is sent to the timing chip through the universal logic gate chip, and the timing chip generates a high-level control signal.

2. The circuit for generating a reference clock in a PCIE fixture according to claim 1, wherein: The button switch includes an eighth control SW8 and a ninth control SW9, the first pin of the eighth control SW8 is respectively connected to the first pin of the ninth control SW9 and the fifth pin of one of the universal logic gate chips, the second pin of the eighth control SW8 is connected to the third pin of the ninth control SW9, the third pin of the eighth control SW8 is connected to the first pin of one of the universal logic gate chips, the first pin of the ninth control SW9 is respectively connected to the first pin of the eighth control SW8 and the fifth pin of one of the universal logic gate chips, and the third pin of the ninth control SW9 is connected to the second pin of the eighth control SW8.

3. The circuit for generating a reference clock in a PCIE fixture according to claim 1, wherein: The timing chip is respectively connected to two parallel resistors and a grounded capacitor. The period of the control signal generated by the timing chip is T=C×(RA×RA1) / (RA+RA1).

4. The circuit for generating a reference clock in a PCIE fixture according to claim 1, wherein: The universal logic gate chip includes a third chip U3 and a fifth chip U5. The button switch connects the first pin of the third chip U3 and the fifth pin of the third chip U3. The third pin of the third chip U3 and the fourth pin of the third chip U3 are connected to the first pin of the fifth chip U5, the second pin of the fifth chip U5, the tenth pin of the fifth chip U5 and the thirteenth pin of the fifth chip U5 through a connector.

5. The circuit for generating a reference clock in a PCIE fixture according to claim 1, wherein: The control signal sent by the timing module is connected to the control module via the reverse chip.

6. The circuit for generating a reference clock in a PCIE fixture according to claim 5, wherein: The third pin of the timing chip of the timing module outputs a high-level first control signal, the first control signal is sent to the first pin of the reverse chip through the 110th connector J110, the second pin of the reverse chip outputs a low-level second control signal with the same frequency as the first control signal, and the reverse chip outputs the second control signal to the control module.

7. The circuit for generating a reference clock in a PCIE fixture according to claim 1, wherein: The crystal oscillator module is provided with a differential clock circuit, and the differential clock circuit outputs the initial clock signal with a frequency of 100 MHz.

8. The circuit for generating a reference clock in a PCIE fixture according to claim 1, wherein: The control signal is input to the first pin of the control chip of the control module and the fourth pin of the control chip, the output end of the differential clock circuit of the crystal oscillator module is connected to the second pin of the control chip and the fifth pin of the control chip respectively, and the third pin of the control chip and the sixth pin of the control chip output the reference clock signal.

9. The circuit for generating a reference clock in a PCIE fixture according to claim 8, wherein: The sixth pin of the control chip is connected to a radio frequency connector, and the control module sends the reference clock signal through the radio frequency connector.

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