Correlation between emission sites using CAD data and emission microscopy images

Abstract

One method includes capturing a photon emission microscopy (PEM) image of an integrated circuit (IC) and identifying emission sites in the PEM image, where emission sites are associated with leakage current. A set of common networks connecting multiple emission sites is located using layout data and / or netlist data from computer-aided design (CAD) data. A critical network connecting a threshold number of emission sites is identified from this set of common networks based on the layout data and / or netlist data. The critical network is cross-mapped by a processor to netlist data in the CAD data. A specific device with output pins connected to the critical network is identified based on the netlist data. The specific device identified based on the netlist data is cross-mapped by the processor to layout data, where the critical network connects at least two devices, including the specific device, at the identified emission sites.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 17 / 135,240 (Attorney's File No. SYNP 3456-2), filed December 28, 2020, entitled "Correlation between Emission Spots Utilizing CAD Data in Combination with Emission Microscope Images," filed by Ankush Bharati Oberai and Rupa Sunil Kamoji, and U.S. Provisional Application No. 62 / 955,652 (Attorney's File No. SYNP 3456-1), filed December 31, 2019, entitled "Correlation between Emission Spots Utilizing CAD Data in Combination with Emission Microscope Images." Both the non-provisional and provisional applications are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to fault analysis of manufactured integrated circuits. Background Technology

[0004] As technology nodes shrink, the need for improved methods for analyzing integrated circuit (IC) faults increases and becomes more urgent. A technology node refers to a specific semiconductor manufacturing process and its design rules. Different technology nodes typically represent different circuit generations and architectures. Generally, the smaller the technology node, the smaller the feature size, requiring smaller transistors that are faster and more energy-efficient. For example, the 7-nanometer (nm) lithography process is a semiconductor manufacturing process following the 10-nm process node. Due to the small feature size of transistors within ICs, fault analysis methods need surgical accuracy. For instance, fault analysis can be performed using emission microscopy images (EMMI) generated by photon emission microscopy (PEM) to detect leakage currents caused by device defects (e.g., gate oxide defects / leakage, latch-up, electrostatic discharge (ESD) faults, junction leakage, etc.).

[0005] Specifically, EMMI (also known as emission microscopy) is an optical analysis technique used to detect and locate certain IC faults. Emission microscopy is non-invasive and can be performed from either the front or back of the device. Many device defects cause weak light emission in the visible and near-infrared (IR) spectra. This emission is captured as emission sites / hot spots on an image of the IC captured using EMMI. EMMI is performed using photon emission microscopy to obtain the image. Typically, the image will show a series of photon emission sites caused by one or more physical defects. However, by observing the emission alone, it is impossible to distinguish between emission caused by device defects and secondary emission caused by actual transistor faults on the IC.

[0006] In recent IC designs, there can be more than 7-8 transmission gates between the two photon emission sites connecting them. In photon emission microscopy (PEM) systems with a resolution of approximately 0.5 micrometers (μm) and transistor sizes smaller than 1 μm, it is impossible to associate a photon emission site with exactly one transistor. For any fault isolation method, it is desirable to associate these emission sites via a common network connecting them. Summary of the Invention

[0007] A method is provided for finding the correlation between emission sites identified using photon emission microscopy on an integrated circuit and computer-aided design (CAD) data. A photon emission microscopy (PEM) image of the integrated circuit (IC) is captured. Emission sites in the PEM image are identified, where each emission site is associated with leakage current. A set of common networks connecting multiple emission sites is found using layout data and / or netlist data from the CAD data. Critical networks connecting a threshold number of emission sites are identified from this set of common networks based on the layout data and / or netlist data. In one embodiment, the threshold number of emission sites is the maximum number of emission sites in the set of common networks. The critical networks identified according to the layout data are cross-mapped by a processor to netlist data in the CAD data. Specific devices having output pins connected to the critical networks can be identified based on the netlist data. The specific devices identified according to the netlist data are cross-mapped by the processor to the layout data. The critical networks connect at least two devices at the identified emission sites, including the specific devices.

[0008] The search for a common network may include finding networks that overlap with each transmit point, finding devices connected to each of the found networks, and adding the found devices to the connected device list. Input or output pins of devices in the connected device list can be identified, networks connected to identified input or output pins can be identified, and additional devices connected to identified networks can be found. It can be determined whether the number of devices connected to identified networks is below a limit. In response to determining that the number of devices connected to identified networks is below a limit, it can be determined whether any additional devices connected to identified networks are in the connected device list. In response to determining that additional devices connected to identified networks are in the connected device list, the identified network can be added to the valid network list and classified as a common network.

[0009] Cross-mapping of critical networks to netlist data in CAD data, and cross-mapping of specific devices to layout data, can be achieved using layout data to schematic diagram data in CAD data.

[0010] Identifying a specific device can include searching for netlist data in CAD data in either the forward direction from the device's input to its output or the reverse direction from the device's output to its input.

[0011] The first device of at least two devices at the identified emission site may have a defect that causes light emission on the PEM image, the second device of at least two devices at the identified emission site may emit light on the PEM image due to the defect in the first device, and the identified device is the first device.

[0012] At least two devices at identified transmission points can be connected via a direct wired connection. At least two devices at identified transmission points can be connected via one or more transmission gates.

[0013] The method may also include selecting emitter sites identified in layout data, using netlist data to find devices that overlap with emitter sites, and finding interconnection paths between devices that overlap with emitter sites.

[0014] The method may further include selecting a pair of elements in netlist data that are cross-mapped from emitter sites in layout data, wherein the first element in the pair is one of a first device and a first network, and the second element in the pair is one of a second device and a second network; and finding interconnection paths between the elements in the pair.

[0015] The method can also use one of the layout data and netlist data in the CAD data to select an interconnect path between devices that overlap with the emitter sites in the first graphics viewer; and use the other of the layout data and netlist data in the CAD data to cross-map the interconnect path to the second graphics viewer.

[0016] A system and a non-transitory computer-readable medium are also provided for finding the correlation between emission sites identified using photon emission microscopy (PEM) on an integrated circuit (IC) and computer-aided design (CAD) data corresponding to that IC, as described herein.

[0017] As used herein, a schematic viewer can display schematic data generated from netlist data, including devices such as transistors, transmission gates, full adders, half adders, and gates (e.g., AND, NAND, OR, NOR), as well as interconnections between devices. A layout viewer can display layout data, including geometric representations of circuit components such as transistors or capacitors, and wiring such as connections between circuit components through multiple conductors. A mask viewer can display photolithographic masks used to produce finished integrated circuits. Attached Figure Description

[0018] The patent or application documents contain at least one color drawing. The Patent Office will provide a copy of the patent or patent application publication, along with several color drawings, upon request and payment of necessary fees. The color drawings are also available in PAIR via the Supplemental Contents tab.

[0019] This disclosure will be more fully understood from the following detailed description and the accompanying drawings illustrating embodiments of the present disclosure. The drawings are provided to give knowledge and understanding of embodiments of the present disclosure and are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0020] Figure 1 Example emitter sites on layout data of an IC design in a layout viewer using PEM images, according to some embodiments, are shown.

[0021] Figure 2 Example schematic data from a simplified schematic viewer according to some embodiments is shown, which corresponds to Figure 1 The layout data shown.

[0022] Figure 3 A flowchart is shown, according to some embodiments, for finding the correlation between emission sites identified on an integrated circuit (IC) using a photon emission microscope and the corresponding computer-aided design (CAD) data of the IC.

[0023] Figure 4An example circuit diagram according to some embodiments is shown, which illustrates multiple emission sites identified by EMMI generated by PEM.

[0024] Figure 5 Computer-aided design (CAD) data for connectivity analysis is shown according to some embodiments.

[0025] Figure 6 A flowchart is shown illustrating the process of extracting a public network of emitter sites in an integrated circuit (IC) using computer-aided design (CAD) data, according to some embodiments.

[0026] Figure 7A and Figure 7B An example case is shown in which an emission point is associated with a device below the emission point according to some embodiments, wherein the emission point is connected by direct and indirect connections.

[0027] Figure 8A , Figure 8B and Figure 8C An example case is shown where emission sites on an integrated circuit are identified using a laser scanning microscope (LSM) via laser-assisted device alteration (LADA) according to some embodiments.

[0028] Figure 9A and Figure 9B An example graphical user interface (GUI) according to some embodiments is shown, which is used to select inputs for a process of finding interconnection paths between emission sites and also shows the found interconnection paths.

[0029] Figure 10A and Figure 10B A cross-mapping of the interconnection path between a first graphics viewer using one of the layout data and netlist data in CAD data, according to some embodiments, and a second graphics viewer using the other of the layout data and netlist data in CAD data.

[0030] Figure 11 The figures illustrate flowcharts of various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure.

[0031] Figure 12 The figure illustrates an abstract diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0032] This disclosure relates to a method for finding the correlation between emission sites identified using photon emission microscopy (PEM) on an integrated circuit and computer-aided design (CAD) data. Photon emission microscopy generates emission microscopy images (EMMIs) that include emission sites for semiconductor component fault analysis. Emission microscopy images (EMMIs) can also be referred to as PEM images. Photon emission microscopy uses a high-sensitivity charge-coupled device (CCD) capable of detecting photons emitted when electron / hole pairs recombine in the device. An emission site refers to the location on the EMMI where emitted photons are detected, and can also be referred to as a PEM site. For example, the emitted photons can be weak light with wavelengths between 350 nm and 1100 nm. EMMIs can be widely used to detect leakage currents caused by device defects, such as gate oxide defects / leakage, latch-up, electrostatic discharge (ESD) faults, junction leakage, etc. However, in recent IC designs, components are becoming increasingly smaller, and a first emission site with physical defects leading to the emission of raw photons can be connected to a second emission site via more than 7-8 transmission gates.

[0033] Sometimes, a failure in one transistor on an IC can make it appear as if other transistors are also faulty, even if they are not actually faulty. Using analytical methods that can identify networks connecting multiple emitter sites, it's impossible to pinpoint which emitter site has a transistor with a physical defect that causes photon emission at other emitter sites. There is a strong need to distinguish between one or more transistors that have actually failed and one or more transistors that appear to have failed simply because they have actually failed.

[0034] Methods can identify networks directly connected to transistors below emission sites, known as common networks. In an IC, a network or common network can include one or more metal or polysilicon conductors. These methods can be used to locate faulty devices emitting light due to direct defects on the device, such as open or short circuits in the metal or polysilicon interconnects. However, devices can also be connected via transmission gates, and some fault location methods cannot correlate multiple emission sites and identify faulty devices, especially when devices below emission sites are connected via transmission gates. Therefore, the aforementioned methods for identifying devices below photon emission sites reported by optical and laser emission technologies are insufficient to accurately identify faulty transistors in nanoscale technology nodes.

[0035] The disclosed technology utilizes a database for integrated circuit (IC) design. This database is generated using IC design data, including netlist data, layout data, and layout pair schematic (LVS) data. The layout data corresponds to the IC's layout. Based on the location of emitter sites on the IC layout, critical networks can be located in the layout data and cross-mapped to the schematic data. A critical network is a network connecting a threshold number of emitter sites. For example, layout data and / or netlist data from CAD data can be used to find a set of common networks connecting multiple emitter sites in an IC. This set of common networks can be ordered according to the number of emitter sites connected to each common network, and a critical network can be identified that connects to a greater number of emitter sites than any other common network in this set. In the schematic data, driving devices on the critical networks can be located and cross-mapped back to the layout data to pinpoint faulty devices, such as transistors, that cause photon emission at the faulty device and other emitter sites connected to the critical networks.

[0036] As depicted in the CAD data, an IC design comprises devices connected via a network through their input and output pins. Devices with output pins connected to the network are called drivers on the network. For example, drivers can be transistors, gates (AND, NAND, OR, NOR, XOR, NOR), flip-flops, etc. Devices with input pins connected to the network are called receivers on the network. Depending on how the network is connected to the devices, a device can be a driver for a first network and a receiver for a second network.

[0037] The advantages of this disclosure include, but are not limited to, identifying devices below the emission point as reported by optical and laser emission technologies, and identifying connectivity between devices directly connected by wires or indirectly connected by transmission gates. The disclosed techniques can help fault analysis engineers focus on the most critical networks and / or devices connected to the emission point for faster fault location and analysis. The disclosed techniques can be applied to analog, digital, and / or mixed-signal integrated circuits.

[0038] Figure 1An example emission site is shown in a layout viewer using PEM images of an IC design, according to some embodiments. In this example, multiple emission sites (e.g., 101-107) from a PEM image of the IC are selected in the layout data of the IC design, with these multiple emission sites connected to network 121. A faulty device may be located at one of these multiple emission sites and may cause photon emission at the faulty device and other emission sites connected to network 121. In the layout data of the IC design, the network can be implemented as one or more connections and interconnections using conductive material. Correlating these emission sites detected by photon emission microscopy (which indicates potential faulty transistors in the integrated circuit) can be used for IC fault analysis.

[0039] A set of common networks connecting multiple transmitter sites of an IC can be identified. These common networks can be ordered according to the number of transmitter sites connected to each common network. A key network 121 can be identified as the common network that connects to a greater number of transmitter sites than any other common network in the set.

[0040] Figure 2 Example schematic data from a simplified schematic viewer according to some embodiments is shown, which corresponds to Figure 1 The layout data is shown. Using the layout data to illustrate the diagram, the layout data ( Figure 1 The critical network 121 found in the diagram is cross-mapped to schematic data, as shown in schematic viewer 200. In this example, OR gate 201 is found as the driving device for critical network 121, and OR gate 201 is cross-mapped back to emitter site 101 in the layout data using layout pair schematic data to perform physical fault analysis of the IC.

[0041] As used herein, a cross-mapped network or device refers to identifying a network or device represented by a first data type and its corresponding device or network represented by a second data type. The first and second data types include layouts, netlists, schematics, and layout-to-schematic data in CAD data. Schematic data is the logical representation of an IC design and can be viewed in a schematic viewer. Layout data is the physical representation of an IC design and can be viewed in a layout viewer. Cross-mapping helps identify the same network or the same device in both representations of the same IC design.

[0042] For example, mapping networks represented in schematic data to layout data means using schematic data to identify logical networks in a schematic viewer and using layout data to identify corresponding networks in a layout viewer. The corresponding network in the layout viewer can be represented by multiple polygons, and can be highlighted by highlighting those polygons representing the network.

[0043] For example, mapping network crosses represented in layout data to schematic data means identifying the network by selecting one of the polygons representing the network in the layout viewer and highlighting the corresponding network in the schematic viewer using the schematic data.

[0044] Figure 3 A flowchart is shown, according to some embodiments, for finding the correlation between emission sites identified on an integrated circuit (IC) using photon emission microscopy (PEM) and the corresponding computer-aided design (CAD) data of the IC.

[0045] Photon emission microscopy uses a type of electron microscope that utilizes localized variations in electron emission originating from layers of material to generate image contrast in PEM images. Within a PEM image, the Physical Fault Analysis (PFA) region can be reduced to a few micrometers. When an IC under test generates leakage current due to certain physical anomalies, this leakage current can be observed through the PEM of the IC's gate region. The gate region is located within a polysilicon layer, thus the emission sites are visible within the polysilicon layer.

[0046] In step 310, a photon emission microscopy (PEM) image of the fabricated integrated circuit (IC) is captured. For ICs tested by PEM, only the polysilicon layer is selected to capture photon emission; that is, photon emission can only originate from the polysilicon layer. In step 320, emission sites in the PEM image can be identified in the IC's layout data, such as in a layout viewer. Figure 1 As shown in the figure, the emitter site is associated with the leakage current, and the PEM image of the IC corresponds to the layout data of the IC.

[0047] In step 330, layout data and / or netlist data from the CAD data are used to locate a common network connecting multiple emitter sites of the IC. If LVS data is available, it can be used to locate a common network. If LVS data is unavailable, layout data can be used. (See reference) Figure 6 Further description of extracting public networks.

[0048] In step 340, based on the layout data and / or netlist data, a key network with a threshold number of transmitter sites can be identified from the set of public networks. In one embodiment, the threshold number of transmitter sites is the maximum number of transmitter sites in the set of public networks. For example, a set of extracted public networks can be sorted in order of the number of transmitter sites connected to each public network. A key network can be identified that connects the maximum number of transmitter sites in the set of public networks. In other words, a key network can be identified that connects more transmitter sites than any other public network in the set, or that connects the maximum number of transmitter sites in the set of public networks.

[0049] In step 350, the processor can use the layout to cross-map the key networks identified by the layout data to netlist data in the CAD data, such as in a schematic viewer. Figure 2 As shown in the figure.

[0050] In step 360, based on the netlist data, a specific device with an output pin connected to a critical network can be identified. This specific device can be referred to as a driver for the critical network. By tracing networks and devices by their input and output pins connected to the network, the IC design can be traced to find driver devices with output pins connected to the critical network. A critical network may connect at least two devices, including the specific device, at identified emitter sites.

[0051] In step 370, based on the specific device identified by the netlist data for the critical network, the processor can use layout data to cross-map schematic data back to layout data to limit the Physical Fault Analysis (PFA) region for performing Physical Fault Analysis (PFA) on the critical network and the emitter sites connected to the network. For example, schematic data as an example of a specific device ( Figure 2 The driving device 201 in ) can be cross-mapped to layout data ( Figure 1 The emission point 101 in )

[0052] The critical network connects at least two devices at the identified emission points, where the specific device can be one of the at least two devices. The at least two devices at the identified emission points can be connected via a direct wired connection, or via one or more transmission gates, or via one or more buffers and / or inverters. The first device among the at least two devices at the identified emission points may have a defect that causes light emission on the PEM image, and the second device among the at least two devices at the identified emission points may emit light due to a defect in the first device. The identified specific device is the first device among the at least two devices at the identified emission points.

[0053] Figure 4An example circuit schematic 400 according to some embodiments is shown, illustrating multiple emitter sites identified by an EMMI generated by PEM. In the schematic, multiple emitter sites are marked with STAR. Multiple emitter sites may be due to a single defect on transistor MP1 causing multiple device saturation. In this example, the root cause of multiple emitter sites is a gate oxide via, which causes leakage in transistor MP1. Network A is connected to the gates of transistors MP1 and MN1. When network A is at a logic high level (= 1), light emission on transistors MP1 and MN1 is turned on, as shown by STAR.

[0054] Network B is connected to the outputs of transistors MP1 and MN1 and to the gates of transistors MP2 and MN2. Due to leakage at transistor MP1, network B is neither logic high (=1) nor logic low (=0), and transistors MP2 and MN2 are saturated and emit light, as shown in STAR. In this example, network B has two driving devices, MP1 and MN1. When searching for the driving device as the root cause, the disclosed techniques can present the two driving devices of the network for troubleshooting engineers to explore.

[0055] Network C is connected to the outputs of transistors MP2 and MN2 and to the input of the transmission gate formed by transistors MP3 and MN3. Because network B is neither logic high (=1) nor logic low (=0), and network C is neither logic high (=1) nor logic low (=0), transistors MP3 and MN3 in the transmission gate copy the voltage level at network C to network D.

[0056] Network D is connected to the output of the transmission gate and to the gates of transistors MP4 and MN4. Because the voltage level of network C is replicated to network D, network D is neither at logic high (=1) nor logic low (=0). Therefore, transistors MP4 and MN4 saturate and emit light, as shown in STAR.

[0057] For reference Figure 6 The process described above can use layout data from computer-aided design (CAD) data to extract the common network (networks A, B, C, D) and transmission gates (MP3, MN3) connecting all transmission sites (MP1, MN1, MP2, MN2, MN4, MP4). (See reference.) Figure 5 Further description of the CAD data. Transmission points can be connected via direct wired connections (networks B, C, D) or via single- or multi-level transmission gates (MP3, MN3). Based on this extracted schematic diagram and representation of the physical layout connections, fault analysis engineers can quickly determine the most probable and reasonable transmission point closest to the physical defect, thus facilitating faster fault localization.

[0058] Figure 5Computer-aided design (CAD) data for connectivity analysis is illustrated according to some embodiments. Various data types in the CAD data are used to associate emitter sites with physical locations in the IC design and to identify devices below the emitter sites. The CAD data is converted to a database format to optimize storage and enable efficient region-based searches. The CAD data may include netlist data 501, layout data 502, and layout pair schematic data 503.

[0059] The netlist data 501 in the CAD data may include devices such as transistors, buffers, inverters, and gates (e.g., AND, NAND, OR, NOR, XOR, XNONR), as well as the connections between these devices. The netlist data can be used to find connections between various devices and extract schematic diagrams of all connected devices. The layout data 502 in the CAD data may include geometric representations of the devices and connections from the netlist data. The layout-to-schematic (LVS) data 503 in the CAD data may include the correspondence between devices and connections in the layout data and devices and connections in the netlist data.

[0060] like Figure 11 As shown in the example process, netlist data can be generated by process 1118 for synthesis, and layout data can be generated by process 1124 for physical implementation. Schematic data can be generated from the netlist data, including devices such as transistors, transmission gates and gates (e.g., AND, NAND, OR, NOR), and connections between devices. Layout-to-Schematic (LVS) data can be generated as a result of comparing the layout data and the schematic data.

[0061] Figure 6 A flowchart illustrating the process of extracting a common network connecting emitter sites in an integrated circuit (IC) using computer-aided design (CAD) data, according to some embodiments, is shown. As shown in the CAD data, devices in the IC design have input and output pins that are connected to the network. A device may have one or more input pins and one or more output pins, and can be connected to one or more networks via these input and output pins. Multiple networks can connect multiple devices via the input and output pins of multiple devices. Multiple networks may overlap with a single emitter site.

[0062] For example, this process can be implemented using graphs to construct devices and networks in an IC design. Graphs consist of nodes and edges connecting the nodes. A network in CAD data can be represented as a node in the graph, while a device in the CAD data that has connections to the network can be represented as an edge in the graph. The search for networks and devices can be performed by traversing the edges and nodes in the graph representing the CAD data of the IC design.

[0063] In step 610, emission points from the PEM image of the IC can be selected in the IC's layout data, such as using a layout viewer. Figure 1 As shown in the figure, the PEM image of the IC corresponds to the layout data of the IC.

[0064] In step 611, the layout data of the IC design can be used to find the network that overlaps with each emitter site.

[0065] In step 612, the layout data of the IC design can be used to locate all devices connected to each network. For example, devices can be located by following the network's input or output pins connected to the network and the device.

[0066] In step 613, the device found in step 612 can be added to the connected device list. The devices added to the connected device list are further explored until a device already in the connected device list is found, as described in the following steps.

[0067] In step 614, the layout data of the IC design can be searched in the positive direction from the input pins to the output pins of the devices to identify the output pins of the devices in the list of connected devices. For example, the output pins of the devices can be the source and drain pins of transistors.

[0068] In step 615, the layout data of the IC design can be searched in the reverse direction from the output pin to the input pin to identify the input pin of the device in the list of connected devices. For example, the input pin of the device may be the gate of a transistor.

[0069] In step 616, the network connected to the input pin and / or output pin identified in step 615 can be identified.

[0070] In step 617, additional devices connected to the identified network identified in step 616 can be located.

[0071] In step 618, it is determined whether the number of devices connected to the identified network is below a limit, such as 512. If not, the identified network is a global network, and in step 619, the identified network and devices connected to it are ignored to extract the network of devices below the connection point. In response to determining that the number of devices connected to the identified network is below the limit, in step 620, it is determined whether any additional devices connected to the identified network found in step 617 are already in the list of connected devices. If not, the process continues to step 612.

[0072] In response to determining that an additional device connected to the identified network is in the list of connected devices, in step 621, the identified network is added to the list of valid networks and the identified network is classified as a public network for the purpose of extracting the public network of the device below the connection point.

[0073] Figure 7A and Figure 7B Examples of how emitter sites are associated with devices below them, according to some embodiments, are illustrated, where the emitter sites are connected by direct and indirect connections. A direct connection refers to a network implemented using a conductive material as one or more connections and interconnections. An indirect connection refers to a device that does not overlap with the emitter site but is connected between emitter sites. Figure 7A A layout viewer 700 is shown, which displays the emission points (701, 702, 703) marked in the layout. (See diagram below.) Figure 7B A schematic viewer 710 is shown, which displays a diagram related to... Figure 7A The image shows the corresponding devices at the emission sites, with STAR markings indicating the emission sites. The image overlaid on the layout has three emission sites 701, 702, and 703. Figure 7A Diagram Viewer Figure 7B ) showed with Figure 7A The three emission sites correspond to three devices 711, 712, and 713. Based on the device connection analysis diagram, indirect connection 714 is located, corresponding to indirect connection 704 shown in the layout viewer 700. Here, indirect connection 714 does not overlap with the emission sites but connects to the emission sites (702, 703, ...). Figure 7A Two overlapping devices (712, 713) Figure 7B Devices between ).

[0074] This technology identifies devices beneath emission sites reported by photon emission and laser emission technologies by finding correlations between emission sites marked on integrated circuits using photon emission microscopy and computer-aided design (CAD) data. It can also identify connectivity between these devices, whether directly connected via networks, indirectly connected via one or more stages of transmission gates, or indirectly connected via one or more stages of buffers and / or inverters. Mapping the layout to a schematic and extracting logic connections further enhances the capabilities of PEM technology.

[0075] This technology helps fault analysis engineers focus on the most critical networks and components, enabling faster fault location and analysis. Using this method, fault analysis engineers can complete a fault analysis task in approximately 30 minutes to an hour, compared to several months using other methods.

[0076] This technology can be applied to analog, digital, or mixed-signal products.

[0077] Figure 8A , Figure 8B and Figure 8C An example is shown illustrating the use of a laser scanning microscope (LSM) to identify emission sites on an integrated circuit via laser-assisted device alteration (LADA) according to some embodiments. LSM is an optical imaging technique used to improve the optical resolution and contrast of photomicrographs by using a spatial pinhole to block out-of-focus light in the imaging. LSM can be used to collect images of IC devices emitting light due to leakage. Marginal faults are common in fault analysis, where the fault is voltage-dependent or time-dependent. Figure 8A Example series emission images 810 of an integrated circuit at different times from dynamic LADA technology are shown. Instead of using top-of-chip microprobes to isolate fault locations, laser-assisted device alteration (LADA) and modified test modes can be used to isolate fault locations. Depending on the wavelength of the laser used for LADA, the laser can sense current or heat, thereby temporarily altering device characteristics. Identifying device characteristics can help fault analysis engineers debug circuits on semiconductor devices. The numbers 1, 2, 3, 4, and 5 in the images represent the sequence of emission sites captured using LSM, and fault analysis engineers can use them to isolate fault locations among multiple emission sites.

[0078] Figure 8B A layout view 820 is shown, illustrating the multiple devices beneath which LADA technology is applied at different times via emission points 821 and 822. A critical path 823 connecting the multiple devices is also shown.

[0079] Figure 8C A schematic viewer 830 is shown, illustrating a top-level design L1 including a logic design hierarchy. The logic design hierarchy in L1 includes a lower-level design L2, which in turn includes a lower-level design L3, which in turn includes a lower-level design L4. L4 includes lower-level designs L5 and L6. L5 includes a lower-level design L5A, and L6 includes a lower-level design L6A. Devices 831 within design L5A and 832 within design L6A are shown in... Figure 8B The emission sites 821 and 822 are marked below them. Devices 831 and 832 are connected by a critical path 833 in the schematic diagram, which corresponds to... Figure 8B The critical path 823 in the layout view shown. (Reference) Figure 6 The interconnectivity of devices below multiple emitter sites is further described by identifying them through networks or transmission gates.

[0080] Figure 9A and Figure 9BAn example graphical user interface (GUI) 900 according to some embodiments is shown. This GUI 900 is used to select inputs for a process of finding interconnect paths between emitter sites and also shows the found interconnect paths. The GUI has two processes. In a first process, an interconnect path between emitter sites can be found by selecting emitter sites identified in layout data. In a second process, an interconnect path between emitter sites can be found by selecting a pair of elements in netlist data, wherein the pair of elements has been cross-mapped from emitter sites in the layout data. The first element in the pair is one of a first device and a first network, and the second element in the pair is one of a second device and a second network. In the GUI, emitter sites are referred to as hotspots.

[0081] A similar diagram in the lower right corner of the GUI shows devices at a hotspot connected to each other via different paths. These paths can be direct connections, such as conductors or wires, or indirect connections. Indirect connections are also known as jumps. As used herein, jumps can include transmission gates, inverters, and buffers.

[0082] Figure 9A The first flow in the GUI is illustrated, which is used to locate interconnect paths by selecting emitter sites identified in the layout data. In this first flow, emitter sites or hotspots identified in the layout data are selected, devices overlapping with the emitter sites are located using netlist data, and interconnect paths are found between the devices overlapping the emitter sites. The interconnect paths and the devices overlapping the emitter sites can be displayed in the GUI.

[0083] In the top left corner of the GUI, the first process "Hotspot" is selected, while the second process "Cross Mapping" is crossed out, indicating that the second process is not selected.

[0084] The "Hotspots" table in the upper left corner of the GUI in the first process lists the hotspots selected by the user in the layout data, and the number of device (e.g., transistor) instances in each hotspot. For example, the first hotspot HS-1 has two instances, the second hotspot HS-2 has one instance, and the third hotspot HS-3 has one instance. The GUI provides hotspot editing functions, including adding, deleting, clearing, and filtering hotspots. Hotspots can be filtered using checkboxes. Edited hotspots can be saved to a file on the computer or loaded from a file.

[0085] The "Instances in Hotspots" table in the lower left corner of the GUI lists the leaf-level instances present in the selected hotspot. CAD data for an IC design can include a device hierarchy from the top level down to the leaf-level instances. Some instances in the hierarchy may have lower-level devices below them. Leaf-level instances do not have lower levels below them. In this example, devices .. / M10_14 and .. / M11_14 are in the first hotspot HS-1, device .. / M4_14 is in the second hotspot HS-2, and device .. / M6_14 is in the third hotspot HS-3. Devices can be filtered using checkboxes. This table updates dynamically as hotspots are added, deleted, cleared, and filtered.

[0086] The "Path Results" table in the upper right corner of the GUI lists the paths between the driving device and the receiving device, as well as the number of hops and hotspots encountered along the paths. Paths can start at the source device and end at the target device, and include hops between the source and target devices. For example, the first path P1 is between the driving device .. / M10_14 and the receiving device .. / M6_14, with one hop H1, and encounters two hotspots HS-1 and HS-3. The second path P2 is between the driving device .. / M11_14 and the receiving device .. / M4_14, with no hops, and encounters two hotspots HS-1 and HS-2. The third path P3 is between the driving device .. / M6_14 and the receiving device .. / M4_14, with one hop H2, and encounters two hotspots HS-2 and HS-3. The fourth path P4 is between the driving device .. / M10_14 and the receiving device .. / M4_14, with two jumps H1 and H2, and contacts two hot spots HS-1 and HS-3.

[0087] Figure 9B The second process in the GUI is illustrated. This second process is used to find interconnect paths between emitter sites by selecting a pair of elements in netlist data, where the pair of elements has been cross-mapped from emitter sites in layout data. The first element in the pair is one of a first device and a first network, and the second element in the pair is one of a second device and a second network. The interconnect paths between the elements in the pair can be found in the netlist data. The interconnect paths and the elements in the pair can be displayed in the GUI.

[0088] In the top left corner of the GUI, the first process "Hotspot" is crossed out, indicating that the first process is not selected, while the second process "Cross Mapping" is selected.

[0089] In the "Cross-Mapping" table in the upper left corner of the GUI for the second process, devices ".. / M10_14", ".. / M11_14", and ".. / M4_14" are selected. Networks ".. / N6_1" and ".. / N6_2" are also selected. Devices and networks in the "Cross-Mapping" table can be filtered using checkboxes. Selected and filtered devices and networks can be saved to a file on the computer or loaded from a file on the computer.

[0090] The "Path Results" table in the upper right corner of the GUI lists the paths between the driving device and the receiving device, as well as the number of hops along the paths. Paths can start at the source device and end at the target device, and include hops between the source and target devices. For example, the first path P1 is between the driving device .. / M10_14 and the network .. / N6_2, and has one hop H1. The second path P2 is between the driving device .. / M11_14 and the network .. / N6_1, and has no hops. The third path P3 is between the network .. / N6_2 and the receiving device .. / M4_14, and has one hop H2. The fourth path P4 is between the driving device .. / M10_14 and the receiving device .. / M4_14, and has two hops, H1 and H2.

[0091] Figure 10A and Figure 10B A cross-mapping of interconnect paths is illustrated between a first graphics viewer using one of layout data and netlist data from CAD data, and a second graphics viewer using the other of layout data and netlist data from CAD data, according to some embodiments. The interconnect paths lie between devices overlapping with emitter sites and may include direct wired connections or indirect devices such as transmission gates, buffers, and inverters. For example, the first graphics viewer may be a mask viewer using layout data, the second graphics viewer may be a schematic viewer using netlist data, and the cross-mapping between the mask viewer and the schematic viewer may use layout-to-schematic data (LVS). Figure 10A and Figure 10B In the example, the emission site is referred to as a hotspot.

[0092] Interconnection paths between devices that overlap with emission sites can be achieved using either layout data or netlist data from the CAD data in a first graphics viewer. Figure 10A The interconnection path can be cross-mapped to a second graphics viewer using layout data from the CAD data and another from the netlist data. Figure 10B The interconnection path can then be displayed in a second graphical viewer.

[0093] Figure 10AAn example first graphical viewer 1011 and a first legend 1010 for the first graphical viewer are shown. In the first graphical viewer, hotspots HS$1 and HS$2 on the IC design layout are selected. The first legend lists the driving device “... / XCMP3_14 / MA” corresponding to one of the hotspots HS$1 and HS$2, and the receiving device “... / XOBY4_1 / M10_14” corresponding to the other of the hotspots HS$1 and HS$2. The interconnect paths in the legend include groups of all devices and networks for the corresponding paths. In this example, the paths in the legend list the networks (“... / XOBY4_1 / N3_14”, “... / XOBY4_1 / N1_14”) and devices (“... / XOBY4_2 / XCMP18_14”) between the driving device and the receiving device. Those devices and networks in the interconnect paths are cross-mapped to Figure 10B The second graphics viewer shown.

[0094] Figure 10B This includes an exemplary second graph viewer 1021 and a second legend 1020 for the second graph viewer. The second legend lists devices and networks cross-mapped from the first graph viewer, such as... Figure 10A As shown. The second graphical viewer displays the device hierarchy from higher to lower levels, such as "7C9116", "XBIO_0", and "XOBY4_1". Device "XOBY4_1" includes leaf-level devices "MA", "XCMP18_14", and "M10_14". Figure 10A The driver device “... / XCMP3_14 / MA” and the receiver device “... / XOBY4_1 / M10_14” listed in the first legend of the first graphics viewer are cross-mapped to Figure 10B In the second graphics viewer shown. Figure 10A The networks “... / XOBY4_1 / N3_14” and “... / XOBY4_1 / N1_14” and the device “... / XOBY4_2 / XCMP18_14” listed in the first legend of the first graph viewer are cross-mapped to, as shown below. Figure 10B The second graphics viewer in the device “XOBY4_1” shown.

[0095] Figure 11An exemplary set of processes 1100 used during the design, verification, and manufacturing of an article of manufacture, such as an integrated circuit, is illustrated for converting and verifying design data and instructions representing the integrated circuit. Each of these processes can be constructed and implemented as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These steps begin with the creation of a product concept 1110 using information provided by the designer, which is converted to create information for an article of manufacture using a set of EDA processes 1112. When the design is complete, the design is tape-out 1134, where tape-out refers to the original pattern (e.g., geometric pattern) of the integrated circuit being sent to a manufacturing apparatus to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is manufactured 1136 and a packaging and assembly process 1138 is performed to produce a finished integrated circuit 1140. According to the present technology as described herein, for fault location in fault analysis, photon emission analysis 1142 is performed on the finished integrated circuit 1140, and correlation with CAD data (layout) 1144 is performed.

[0096] Device failure can occur when a device does not meet its electrical and / or mechanical specifications. Device failure may be due to IC design issues or process and / or manufacturing problems. Based on the results of failure analysis, device failure can be corrected in the IC design or process and / or manufacturing. Using this technique, failure analysis engineers can complete a failure analysis task in approximately 30 minutes to 1 hour, compared to several months required using other methods. This technique significantly accelerates turnaround time in the device failure analysis and corrective action cycle.

[0097] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High levels of abstraction can be used to design circuits and systems using hardware description languages ​​(“HDLs”) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer-level (“RTL”) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction, which is a less abstract description, adds more useful details to the design description; for example, more details for modules include descriptions. Lower levels of abstraction, which are less abstract descriptions, can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify a lower level of abstraction with more detailed descriptions is SPICE, used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is enabled to be used by the corresponding tools at that layer (e.g., formal verification tools). The design process can use... Figure 11 The sequence described herein. A process that can be described by an EDA product (or tool).

[0098] During system design phase 1114, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0099] During logic design and functional verification 1116, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that conform to the requirements of the specifications of the circuit or system being designed. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as a “simulator” or “prototype system” is used to accelerate functional verification.

[0100] During synthesis and design 1118 for testing, HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, where edges of the graph structure represent components of the circuit, and nodes of the graph structure represent how the components are interconnected. Both HDL code and netlist are hierarchical artifacts that can be used by EDA products to verify whether the integrated circuit functions according to a specified design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that it meets specifications.

[0101] During netlist verification 1120, the consistency between the netlist and timing constraints, as well as the correspondence between the netlist and HDL code, are checked. During design planning 1122, the overall layout of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0102] During layout or physical implementation 1124, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connecting circuit components through multiple conductors) are performed, and cells can be selected from a library to implement a specific logic function. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and in simulations. Parameters, such as dimensions, are specified for the selected cells (based on "standard cells"), and these parameters are made accessible in a database for use in EDA products.

[0103] During the analysis and extraction phase 1126, circuit functionality is verified at the layout level, allowing for finer-grained layout design. During physical verification 1128, the layout design is checked to ensure manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and to ensure circuit functionality conforms to the HDL design specifications. During resolution enhancement 1130, the geometry of the layout is transformed to improve the fabrication of the circuit design.

[0104] During the tape-out process, data is created for the production of a photomask (after applying lithographic enhancement where appropriate). During mask data preparation 1132, the "tape-out" data is used to generate a photomask, which is used to produce the finished integrated circuit.

[0105] Computer systems (such as) Figure 12 The storage subsystem of the computer system 1200 can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and products for using the physical and logical designs of the libraries.

[0106] Figure 12 An example machine of computer system 1200 is shown, within which a set of instructions can be executed to cause the machine to perform any or one of the methods discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment. The photon emission microscope (PEM) 1201 of the emission microscope system can be coupled to computer system 1200 via network 1220 to obtain PEM images of integrated circuits for use in this technology.

[0107] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) to perform the actions to be taken by the specified machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0108] Example computer system 1200 includes processing device 1202, main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.) and data storage device 1218, which communicate with each other via bus 1230.

[0109] Processing device 1202 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1202 may be configured to execute instructions 1226 for performing the operations and steps described herein.

[0110] The computer system 1200 may also include a network interface device 1208 for communication via a network 1220. The computer system 1200 may also include a video display unit 1210 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), a graphics processing unit 1222, a signal generation device 1216 (e.g., a speaker), a video processing unit 1228, and an audio processing unit 1232.

[0111] Data storage device 1218 may include machine-readable storage medium 1224 (also referred to as non-transitory computer-readable medium) on which one or more sets of instructions 1226 or software embodying any one or more of the methods or functions described herein are stored. Instructions 1226 may also reside wholly or at least partially in main memory 1204 and / or processing device 1202 during execution by computer system 1200, which also constitute machine-readable storage media.

[0112] In some implementations, instruction 1226 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 1224 is shown as a single medium in the example implementations, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine and processing device 1202 to perform any one or more methods of the methods of this disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0113] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. These operations are operations that require physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0114] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, it is apparent from this disclosure that, throughout the specification, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data, represented as physical (electronic) quantities within the registers and memories of the computer system, into other data, similarly represented as physical quantities within the computer system's memory or registers or other such information storage devices.

[0115] This disclosure also relates to means for performing the operations described herein. Such means may be specifically constructed for the intended purpose, or may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0116] The algorithms and displays presented herein are not substantially related to any particular computer or other device. Various other systems may be used in conjunction with the programs taught herein, or it may be demonstrated that it is convenient to construct more specialized devices to perform the methods. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described herein.

[0117] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium storing instructions that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0118] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific example implementations. It will be apparent that various modifications can be made to these implementations without departing from the broader spirit and scope of the embodiments of this disclosure as set forth in the appended claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements are labeled with the same numerals. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method comprising: Photon emission microscopy (PEM) images of integrated circuits (ICs); Identify emission sites in the PEM image, which are associated with leakage current; Using at least one or more of layout data obtained from computer-aided design (CAD) data and netlist data obtained from said CAD data, find a set of common networks connecting multiple emission sites. Based on at least one or more of the layout data and the netlist data, identify a network from the set of public networks connected to a plurality of transmission sites that meet a threshold number. The processor cross-maps the identifier network identified by the layout data to the netlist data in the CAD data; A specific device is identified based on the netlist data, and the specific device has an output pin that is connected to the identified network. as well as The processor cross-maps the specific device identified by the netlist data to the layout data. The identification network connection therein identifies at least two devices at the emission site, including the specific device.

2. The method according to claim 1, wherein the search of the public network includes: Find the network that overlaps with each emission point; Locate the devices that are connected to each of the found networks; Add the found device to the list of connected devices; Identify the input or output pins of the devices in the list of connected devices; The identifier is connected to a network that has an identified input or output pin; Locate the additional devices connected to the identified network; Determine whether the number of devices connected to the identified network is below the limit; In response to determining that the number of devices connected to the identified network is below the limit, it is determined whether any of the additional devices connected to the identified network are in the list of connected devices; as well as In response to determining that the additional device connected to the identified network is in the list of connected devices, the identified network is added to the list of valid networks and the identified network is classified as a public network.

3. The method according to claim 1, wherein the cross-mapping of the identifier network to netlist data in the CAD data and the cross-mapping of the specific device to the layout data use layout pair schematic data in the CAD data, the layout pair schematic data including the correspondence between devices and connections in the layout data and devices and connections in the netlist data.

4. The method of claim 1, wherein identifying the specific device comprises searching the netlist data in the CAD data in a forward direction from the device's input to its output or in a reverse direction from the device's output to its input.

5. The method of claim 1, wherein a first device of the at least two devices at the identified emission site has a defect that causes light emission on the PEM image, a second device of the at least two devices at the identified emission site emits light on the PEM image due to the defect in the first device, and the identified device is the first device.

6. The method of claim 1, further comprising identifying the network based on the public network connected to the maximum number of transmission sites.

7. The method of claim 1, wherein the at least two devices at the identified transmission sites are connected via one or more transmission gates.

8. The method according to claim 1, further comprising: Select the emission point identified in the layout data; Use the netlist data to find devices that overlap with the emission site; as well as Locate the interconnection paths between the devices that overlap with the emission site.

9. The method according to claim 1, further comprising: Select a pair of elements from the netlist data, the pair of elements being cross-mapped from the emitter sites in the layout data, wherein the first element of the pair of elements is one of a first device and a first network, and the second element of the pair of elements is one of a second device and a second network; and Find the interconnection path between the elements in the pair.

10. The method of claim 1, further comprising: Using one of the layout data and the netlist data from the CAD data, select the interconnect path between devices that overlap with the emission site and are displayed in the first graphics viewer; as well as The interconnection paths are cross-mapped to a second graphics viewer using the layout data from the CAD data and another data from the netlist data.

11. A system comprising: Memory, storing instructions; as well as A processor, coupled to the memory, executes the instructions, which, when executed, cause the processor to perform operations including: Photon emission microscopy (PEM) images of integrated circuits (ICs); Identify emission sites in the PEM image, which are associated with leakage current; Using at least one or more of layout data obtained from computer-aided design (CAD) data and netlist data obtained from said CAD data, find a set of common networks connecting multiple emission sites. Based on at least one or more of the layout data and the netlist data, identify a network from the set of public networks connected to a plurality of transmission sites that meet a threshold number. The processor cross-maps the identifier network identified by the layout data to the netlist data in the CAD data; A specific device is identified based on the netlist data; the specific device has an output pin connected to the identified network; and The processor cross-maps the specific device identified by the netlist data to the layout data. The identification network connection therein identifies at least two devices at the emission site, including the specific device.

12. The system according to claim 11, wherein the search for the public network includes: Find the network that overlaps with each emission point; Locate the devices that are connected to each of the found networks; Add the found device to the list of connected devices; Identify the input or output pins of the devices in the list of connected devices; The identifier is connected to a network that has an identified input or output pin; Locate the additional devices connected to the identified network; Determine whether the number of devices connected to the identified network is below the limit; In response to determining that the number of devices connected to the identified network is below the limit, it is determined whether any of the additional devices connected to the identified network are in the list of connected devices; as well as In response to determining that the additional device connected to the identified network is in the list of connected devices, the identified network is added to the list of valid networks and the identified network is classified as a public network.

13. The system of claim 11, wherein identifying the particular device includes searching the netlist data in the CAD data in a forward direction from the device's input to its output or in a reverse direction from the device's output to its input.

14. The system of claim 11, wherein a first device of the at least two devices at the identified emission site has a defect that causes light emission on the PEM image, a second device of the at least two devices at the identified emission site emits light on the PEM image due to the defect in the first device, and the identified device is the first device.

15. The system of claim 11, wherein the at least two devices at the identified transmission sites are connected via one or more transmission gates.

16. A non-transitory computer-readable medium including stored instructions, said instructions causing the processor to perform operations when executed by a processor, said operations including: Photon emission microscopy (PEM) images of integrated circuits (ICs); Identify emission sites in the PEM image, which are associated with leakage current; Using layout data obtained from computer-aided design (CAD) data and from the CA... Obtained from D data Find at least one or more of the data in the netlist to find a set of common networks that connect multiple emission sites; Based on at least one or more of the layout data and the netlist data, identify a network from the set of public networks connected to a plurality of transmission sites that meet a threshold number. The processor cross-maps the identifier network identified by the layout data to the netlist data in the CAD data; A specific device is identified based on the netlist data, and the specific device has an output pin that is connected to the identified network. as well as The processor cross-maps the specific device identified by the netlist data to the layout data. The identification network connection therein identifies at least two devices at the emission site, including the specific device.

17. The non-transitory computer-readable medium of claim 16, wherein the search of the public network comprises: Find the network that overlaps with each emission point; Locate the devices that are connected to each of the found networks; Add the found device to the list of connected devices; Identify the input or output pins of the devices in the list of connected devices; The identifier is connected to a network that has an identified input or output pin; Locate the additional devices connected to the identified network; Determine whether the number of devices connected to the identified network is below the limit; In response to determining that the number of devices connected to the identified network is below the limit, it is determined whether any of the additional devices connected to the identified network are in the list of connected devices; as well as In response to determining that the additional device connected to the identified network is in the list of connected devices, the identified network is added to the list of valid networks and the identified network is classified as a public network.

18. The non-transitory computer-readable medium of claim 16, wherein the identification of the particular device includes searching the netlist data in the CAD data in a forward direction from the device's input to its output or in a reverse direction from the device's output to its input.

19. The non-transitory computer-readable medium of claim 16, wherein a first device of the at least two devices at the identified emission site has a defect that causes light emission on the PEM image, a second device of the at least two devices at the identified emission site emits light on the PEM image due to the defect in the first device, and the identified device is the first device.

20. The non-transitory computer-readable medium of claim 16, wherein the at least two devices at the identified transmission sites are connected via one or more transmission gates.

Images