Electronic device and method for controlling timing signals

Abstract

According to an embodiment, an electronic device may include: at least one processor; a display; a memory configured to store image frames; and a display controller configured to output image frames. The at least one processor may be configured to: transmit a first image frame to be output through the display based on a first timing signal received from the display controller; identify a state of the electronic device; transmit first control information for changing the timing of the first timing signal; receive a second timing signal from the display controller in response to transmitting the first control information for changing the timing of the first timing signal; and transmit a second image frame to be output through the display to the memory based on the received second timing signal. The timing of the second timing signal may be different from the timing of the first timing signal.

Description

Technical Field

[0001] One or more embodiments of the present disclosure generally relate to electronic devices capable of controlling timing signals and methods therefor. Background Art

[0002] Electronic devices such as smartphones and other portable electronic devices are providing an increasing number of services and functions. To meet the needs of various users and improve the efficiency of electronic device usage, communication service providers and equipment manufacturers are competing to develop electronic devices with differentiated and diversified functions. As a result, the various functions provided by electronic devices are increasingly evolving. Summary of the Invention

[0003] Technical issues

[0004] A display device using command driving can read data (e.g., an image frame) from a memory (e.g., a graphics random access memory (GRAM)) and output an image via a display panel in synchronization with a synchronization signal (e.g., a vertical synchronization (VSYNC) signal) generated by a display driver integrated circuit (IC) (DDI). In this case, the display driver IC can read the data (e.g., an image frame) during a scan-on time of each cycle (e.g., each interval) of the synchronization signal (e.g., VSYNC signal) and transmit the data to the display (e.g., panel).

[0005] A processor (e.g., a display processing unit (DPU)) may send each item of data (e.g., an image frame) to a memory (e.g., a GRAM) and store the data in the GRAM in response to a timing signal received in response to a synchronization signal (e.g., a VSYNC signal) generated by a display driver IC. The processor may be configured to send each item of data (e.g., an image frame) to the GRAM within a scan-on time of the display driver IC (e.g., before the scan-on time expires) so that no tearing effect occurs.

[0006] The interval of the synchronization signal (e.g., VSYNC signal) described above can correspond to the refresh rate of the display. Depending on whether high responsiveness is required or whether a longer battery life is required (e.g., whether low power consumption is required), the processor can dynamically change the interval of the synchronization signal (e.g., VSYNC signal) to dynamically change the refresh rate of the display. The shorter the interval of the synchronization signal (e.g., VSYNC signal), the less time it takes for the data (e.g., image frame) sent from the processor to be output through the panel of the display (in other words, high responsiveness is guaranteed). However, because the scan-on time of the display driver IC is shortened, the processor may need to run at a high operating speed in order to send data (e.g., image frame) to the memory (e.g., GRAM) within the scan-on time of the display driver IC. As a result, the power consumption of the processor can be further increased. Conversely, the longer the interval of the timing signal (e.g., VSYNC signal), the longer it takes for the data (e.g., image frame) sent from the processor to be output through the panel of the display (in other words, low responsiveness is provided). Furthermore, because the scan-on time of the display driver IC has been increased, the processor can send data (e.g., image frames) to the memory (e.g., GRAM) within the scan-on time of the display driver IC even when the processor is operating at a low operating speed. Thus, the power consumption of the processor can be further reduced.

[0007] As described above, depending on whether high responsiveness or long battery life is required, the processor can dynamically change the refresh rate of the display by dynamically changing the interval of the synchronization signal (e.g., the VSYNC signal). However, when the scan-on time of the display driver IC is changed, the user may notice a difference in brightness in the image output through the display panel when the change is made. When the refresh rate of the display is dynamically changed, this may cause inconvenience to the user.

[0008] According to an embodiment, the electronic device can maintain the scan-on time of the display driver IC even if the interval of a synchronization signal (eg, a VSYNC signal) is changed according to whether high responsiveness is required or whether a longer battery life is required.

[0009] According to an embodiment, the electronic device can change the timing of the timing signal received in response to the synchronization signal (e.g., VSYNC signal) according to whether high responsiveness is required or whether longer battery life is required, thereby adjusting the time period in which data (e.g., image frames) can be sent to the memory (e.g., GRAM).

[0010] Solutions to the Problem

[0011] According to an embodiment, an electronic device includes: at least one processor; a display; a memory configured to store image frames received from the at least one processor; and a display controller configured to output the image frames stored in the memory through the display. The at least one processor is configured to: send a first image frame to be output through the display to the memory based on a first timing signal received from the display controller; identify a state of the electronic device; send first control information for changing the timing of the first timing signal to the display controller in response to the identified state of the electronic device; receive a second timing signal from the display controller based on the sending of the first control information for changing the timing of the first timing signal; and send a second image frame to be output through the display to the memory based on the received second timing signal, wherein the timing of the second timing signal is different from the timing of the first timing signal.

[0012] According to an embodiment, a method for controlling an electronic device includes: sending a first image frame to be output through the display of the electronic device to a memory of the electronic device based on a first timing signal received from a display controller of the electronic device; identifying a state of the electronic device; sending first control information for changing the timing of the first timing signal to the display controller of the electronic device based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to the sending of the first control information for changing the timing of the first timing signal; and sending a second image frame to be output through the display to the memory based on the received second timing signal, wherein the timing of the second timing signal is different from the timing of the first timing signal.

[0013] According to an embodiment, a computer-readable non-volatile recording medium is provided, which stores instructions that are executed to enable at least one processor of an electronic device to execute the following: sending a first image frame to be output through the display of the electronic device to the memory of the electronic device based on a first timing signal received from the display controller of the electronic device; identifying the state of the electronic device; sending first control information for changing the timing of the first timing signal to the display controller of the electronic device based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to the sending of the first control information for changing the timing of the first timing signal; and sending a second image frame to be output through the display to the memory based on the received second timing signal, and wherein the timing of the second timing signal is different from the timing of the first timing signal.

[0014] Other aspects, advantages, and salient features of the disclosure will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the disclosure.

[0015] Beneficial effects of the present invention

[0016] According to certain embodiments, an electronic device may provide seamless refresh rate switching of a display by maintaining a scan-on time of a display driver IC even if an interval of a synchronization signal (eg, a VSYNC signal) is changed.

[0017] According to certain embodiments, the electronic device can adjust the time at which data (e.g., image frames) can be sent to a display driver IC (or GRAM) by changing the timing of a timing signal received in response to a synchronization signal (e.g., a VSYNC signal), thereby adjusting the operating speed of the processor and / or the power consumption of the processor.

[0018] Various effects and advantages that can be achieved according to the present disclosure are not limited to the above description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] A more complete appreciation of the present disclosure and its many attendant aspects will be readily obtained as the present disclosure is better understood by reference to the following detailed description considered in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a diagram illustrating an electronic device in a network environment according to various embodiments;

[0021] Figure 2 is a block diagram illustrating components of an electronic device according to an embodiment;

[0022] Figure 3 is a diagram illustrating transmission of a timing signal and an image frame of an electronic device according to an embodiment;

[0023] Figure 4A is a view showing a first mode of an electronic device according to an embodiment;

[0024] Figure 4B is a view showing a second mode of the electronic device according to an embodiment;

[0025] Figure 5 is a view showing a third mode of the electronic device according to an embodiment;

[0026] Figure 6A is a flowchart illustrating an operation of changing a rising timing of a timing signal by an electronic device according to an embodiment;

[0027] Figure 6Bis a flow chart illustrating the operation of a processor, a display controller, and / or a display according to an embodiment;

[0028] Figure 7 is a diagram illustrating an operation of changing a rising timing of a timing signal by an electronic device according to an embodiment;

[0029] Figure 8A is a diagram showing an example in which the rising timing of a timing signal is changed according to an embodiment;

[0030] Figure 8B is a view showing an example in which a transmittable time of an image frame is changed according to an embodiment;

[0031] Figure 9 is a flowchart illustrating an operation of changing a rising timing of a timing signal by an electronic device according to an embodiment;

[0032] Figure 10A is a flowchart illustrating an operation of changing a rising timing of a timing signal by an electronic device according to an embodiment;

[0033] Figure 10B is a flowchart illustrating driving mode switching of an electronic device according to an embodiment;

[0034] Figure 10C is a flowchart illustrating driving mode switching of an electronic device according to an embodiment;

[0035] Figure 11A is a view showing a screen for setting a refresh rate of an electronic device according to an embodiment;

[0036] Figure 11B is a view showing preset applications according to an embodiment;

[0037] Figure 11C is a view showing another preset application according to an embodiment;

[0038] Figure 12A is a diagram illustrating an operation of changing a timing signal in response to a user input by an electronic device according to an embodiment;

[0039] Figure 12B is a diagram illustrating an operation of determining a timing signal when a plurality of execution screens are displayed by an electronic device according to an embodiment; and

[0040] Figure 13 is a view illustrating an operation of determining a timing signal based on a stylus pen by an electronic device according to an embodiment.

[0041] Throughout the drawings, like reference numerals will be understood to refer to like parts, components and structures. DETAILED DESCRIPTION

[0042] Figure 1 1 is a block diagram illustrating an electronic device 101 in a network environment 100 according to various embodiments. Figure 1 , the electronic device 101 in the network environment 100 can communicate with the electronic device 102 via the first network 198 (e.g., a short-range wireless communication network), or communicate with the electronic device 104 or the server 108 via the second network 199 (e.g., a long-range wireless communication network). According to an embodiment, the electronic device 101 can communicate with the electronic device 104 via the server 108. According to an embodiment, the electronic device 101 may include a processor 120, a memory 130, an input device 150, a sound output device 155, a display device 160, an audio module 170, a sensor module 176, an interface 177, a haptic module 179, a camera module 180, a power management module 188, a battery 189, a communication module 190, a subscriber identification module (SIM) 196, or an antenna module 197. In some embodiments, at least one of the components (e.g., the display device 160 or the camera module 180) may be omitted from the electronic device 101, or one or more other components may be added to the electronic device 101. In some embodiments, some of the components may be implemented as a single integrated circuit. For example, the sensor module 176 (eg, a fingerprint sensor, an iris sensor, or an illumination sensor) may be implemented to be embedded in the display device 160 (eg, a display).

[0043] The processor 120 may run, for example, software (e.g., program 140) to control at least one other component of the electronic device 101 coupled to the processor 120 (e.g., a hardware component or a software component), and may perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculation, the processor 620 may load commands or data received from another component (e.g., sensor module 176 or communication module 190) into the volatile memory 132, process the commands or data stored in the volatile memory 132, and store the resulting data in the non-volatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 123 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operationally independent of or in conjunction with the main processor 121. Additionally or alternatively, the auxiliary processor 123 may be configured to consume less power than the main processor 121 or to be specifically configured for a designated function. The auxiliary processor 123 may be implemented separately from the main processor 121 or as part of the main processor 21 .

[0044] When the main processor 121 is in an inactive state (e.g., a sleep state), the auxiliary processor 123 may control at least some of the functions or states related to at least one component (e.g., the display device 160, the sensor module 176, or the communication module 190) among the components of the electronic device 101 that is not the main processor 121, or when the main processor 121 is in an active state (e.g., running an application), the auxiliary processor 123 may control at least some of the functions or states related to at least one component (e.g., the display device 160, the sensor module 176, or the communication module 190) among the components of the electronic device 101 that is not the main processor 121 together with the main processor 121. Depending on the embodiment, the auxiliary processor 123 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 180 or the communication module 190) that is functionally related to the auxiliary processor 123.

[0045] The memory 130 may store various data used by at least one component of the electronic device 101 (e.g., the processor 120 or the sensor module 176). The various data may include, for example, software (e.g., the program 140) and input data or output data for commands related thereto. The memory 130 may include a volatile memory 132 or a non-volatile memory 134.

[0046] The program 140 may be stored as software in the memory 130 , and may include, for example, an operating system (OS) 142 , middleware 144 , or applications 146 .

[0047] The input device 150 may receive commands or data from outside the electronic device 101 (e.g., a user) to be used by other components of the electronic device 101 (e.g., the processor 120). The input device 150 may include, for example, a microphone, a mouse, a keyboard, or a digital pen (e.g., a stylus).

[0048] The sound output device 155 can output sound signals to the outside of the electronic device 101. The sound output device 155 can include, for example, a speaker or a receiver. The speaker can be used for general purposes such as playing multimedia or playing records, and the receiver can be used for incoming calls. Depending on the embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0049] The display device 160 can visually provide information to the outside of the electronic device 101 (e.g., a user). The display device 160 may include, for example, a display, a holographic device, or a projector, and a control circuit for controlling a corresponding one of the display, the holographic device, and the projector. Depending on the embodiment, the display device 160 may include a touch circuit adapted to detect a touch or a sensor circuit adapted to measure the strength of the force caused by the touch (e.g., a pressure sensor).

[0050] The audio module 170 can convert sound into an electrical signal, and vice versa. According to an embodiment, the audio module 170 can obtain sound via the input device 150, or output sound via the sound output device 155 or an earphone of an external electronic device (e.g., electronic device 102) directly (e.g., wired) coupled to the electronic device 101 or wirelessly coupled.

[0051] The sensor module 176 can detect the operating state (e.g., power or temperature) of the electronic device 101 or the environmental state (e.g., the state of the user) outside the electronic device 101, and then generate an electrical signal or data value corresponding to the detected state. Depending on the embodiment, the sensor module 176 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0052] The interface 177 may support one or more specific protocols for directly (e.g., wired) or wirelessly coupling the electronic device 101 to an external electronic device (e.g., the electronic device 102). Depending on the embodiment, the interface 177 may include, for example, a High-Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface.

[0053] The connection end 178 may include a connector, wherein the electronic device 101 can be physically connected to an external electronic device (e.g., the electronic device 102) via the connector. Depending on the embodiment, the connection end 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0054] The haptic module 179 may convert the electrical signal into mechanical stimulation (eg, vibration or motion) or electrical stimulation that can be recognized by the user via his sense of touch or kinesthetic sense. According to an embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0055] The camera module 180 can capture still images or moving images. According to an embodiment, the camera module 180 may include one or more lenses, image sensors, image signal processors, or flashes.

[0056] The power management module 188 may manage power supply to the electronic device 101. According to an embodiment, the power management module 188 may be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0057] The battery 189 may power at least one component of the electronic device 101. According to an embodiment, the battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0058] The communication module 190 can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 101 and an external electronic device (e.g., electronic device 102, electronic device 104, or server 108), and perform communication via the established communication channel. The communication module 190 may include one or more communication processors capable of operating independently from the processor 120 (e.g., an application processor (AP)) and support direct (e.g., wired) communication or wireless communication. Depending on the embodiment, the communication module 190 may include a wireless communication module 192 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules can communicate with an external electronic device via a first network 198 (e.g., a short-range communication network such as Bluetooth, Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA)) or a second network 199 (e.g., a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or a Wide Area Network (WAN))). These various types of communication modules may be implemented as a single component (e.g., a single chip), or may be implemented as a plurality of components (e.g., a plurality of chips) separated from each other. The wireless communication module 192 may identify and authenticate the electronic device 101 in a communication network (such as the first network 198 or the second network 199) using user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the user identification module 196.

[0059] The antenna module 197 can send signals or power to the outside (e.g., an external electronic device) or receive signals or power from the outside (e.g., an external electronic device). According to an embodiment, the antenna module may include an antenna including a radiator formed by a conductor or conductive pattern formed on a substrate (e.g., a printed circuit board (PCB)). According to an embodiment, the antenna module 197 may include a plurality of antennas. In this case, at least one antenna suitable for a communication scheme used in a communication network such as the first network 198 or the second network 199 can be selected from the plurality of antennas by the communication module 190, for example. Signals or power can then be sent or received between the communication module 190 and the external electronic device via the selected at least one antenna. According to an embodiment, other components other than the radiator (e.g., a radio frequency integrated circuit (RFIC)) may further be formed as part of the antenna module 197.

[0060] At least some of the above components can be connected to each other via an inter-peripheral communication scheme (e.g., a bus, general-purpose input output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) and communicatively send signals (e.g., commands or data) therebetween.

[0061] According to an embodiment, commands or data may be transmitted or received between the electronic device 101 and the external electronic device 104 via the server 108 coupled to the second network 199. The external electronic device 102 and the external electronic device 104 may each be a device of the same type as the electronic device 101 or a device of a different type than the electronic device 101. According to an embodiment, all or some operations to be executed on the electronic device 101 may be executed at one or more of the external electronic device 102, the external electronic device 104, or the external electronic device 108. For example, if the electronic device 101 should automatically execute a function or service or should execute a function or service in response to a request from a user or another device, the electronic device 101 may request the one or more external electronic devices to execute at least a portion of the function or service instead of executing the function or service, or the electronic device 101 may request the one or more external electronic devices to execute at least a portion of the function or service in addition to executing the function or service. The one or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or execute another function or service related to the request, and send the result of the execution to the electronic device 101. The electronic device 101 may provide the result as at least a partial response to the request, with or without further processing the result. To this end, for example, cloud computing technology, distributed computing technology, or client-server computing technology may be used.

[0062] Figure 2 is a block diagram illustrating components of the electronic device 101 according to an embodiment.

[0063] According to an embodiment, the electronic device 101 may include a processor 120, a display controller 201, and a display 203 (eg, Figure 1 At least one of the display devices 160).

[0064] According to an embodiment, the processor 120 may perform the overall operation of the electronic device 101 and may control the overall operation of other components of the electronic device 101. According to an embodiment, the processor 120 may include a display controller 201 and / or a display processing unit (DPU) that controls the display 203. According to an embodiment, the processor 120 may include an application processor (AP) of the electronic device 101 and may exist as a separate module within the application processor. The processor 120 may include a microprocessor or any suitable type of processing circuit, such as one or more general-purpose processors (e.g., ARM-based processors), digital signal processors (DSPs), programmable logic devices (PLDs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), graphics processing units (GPUs), graphics card controllers, and the like. In addition, it will be appreciated that when a general-purpose computer accesses code for implementing the processes shown herein, the execution of the code transforms the general-purpose computer into a special-purpose computer for performing the processes shown herein. Certain functions and steps provided in the figures may be implemented in hardware, software, or a combination of both and may be executed in whole or in part within the programming instructions of a computer. In addition, the skilled person understands and appreciates that a "processor" or "microprocessor" may be hardware in the claimed disclosure.

[0065] According to an embodiment, the processor 120 may transmit data to the memory 130 and store the data in the memory 130. For example, the data may include an image frame to be output through the display 203.

[0066] According to an embodiment, the processor 120 may receive a timing signal from the display controller 201. For example, the timing signal received from the display controller 201 may include a tearing effect synchronization (TE-SYNC) signal. It will be apparent to those skilled in the art that the TE-SYNC signal may be referred to as a tearing effect (TE) signal, a timing signal, a tearing signal, or a tearing effect synchronization signal, or various other terms. In the present disclosure, the timing signal received from the display controller 201 may be referred to as a TE-SYNC signal, a first timing signal, or a second timing signal. According to an embodiment, the TE-SYNC signal may be a signal corresponding to a synchronization signal (e.g., a VSYNC signal) generated by the display controller 201, which will be described later. According to an embodiment, the timing signal (e.g., a TE-SYNC signal) received from the display controller 201 may include an electrical signal whose voltage value rises and / or falls at a predetermined period or interval. For example, the timing signal (e.g., a TE-SYNC signal) received from the display controller 201 may include a signal whose voltage value rises and / or falls at the same period (e.g., the same interval) as the synchronization signal (e.g., a VSYNC signal).

[0067] According to an embodiment, the processor 120 may transmit data (e.g., image frames) to the display controller 201 or the memory 130 in response to a timing signal (e.g., a TE-SYNC signal) received from the display controller 201. According to an embodiment, the processor 120 may transmit data (e.g., image frames) to the display controller 201 or the memory 130 in response to a rise in the voltage value of the timing signal (e.g., a TE-SYNC signal). According to an embodiment, the transmission of data (e.g., image frames) by the processor 120 may be performed via a wired manner and / or a wireless manner. According to an embodiment, the wired transmission of data (e.g., image frames) may be performed via a display port that connects the processor 120 and the display controller 201 and / or the memory 130 via a wire. According to an embodiment, the wireless transmission of data (e.g., image frames) may include long-range wireless communication such as cellular communication and / or short-range wireless communication such as Bluetooth (BL) communication, near field communication (NFC) communication, or wireless fidelity (Wi-Fi) communication. In addition to the wired transmission and / or wireless transmission described above, data (eg, image frames) may be transmitted to the display controller 201 and / or the memory 130 according to various other transmission methods.

[0068] According to an embodiment, the processor 120 may change the rising timing (e.g., the timing when the voltage value of the TE-SYNC signal rises) of the timing signal (e.g., the TE-SYNC signal) received from the display controller 201. According to an embodiment, the processor 120 may send control information (e.g., first control information) to the display controller 201 and control the display controller 201 to send the timing signal (e.g., the TE-SYNC signal) whose rising timing has been changed. According to an embodiment, the processor 120 may change the rising timing of the timing signal (e.g., the TE-SYNC signal) based on the state of the electronic device 101, which is described in detail below. For example, the state of the electronic device 101 may include at least one of the type of (one or more) applications executed on the electronic device 101, the content of the screen displayed on the display 203 of the electronic device 101 (e.g., the execution screen of the application), the type of user input received, and the temperature of the electronic device 101.

[0069] According to an embodiment, the processor 120 may change the interval of the synchronization signal (e.g., VSYNC signal) generated by the display controller 201. According to an embodiment, the processor 120 may send control information (e.g., second control information) to the display controller 201 and control the display controller 201 to change the interval of the synchronization signal (e.g., VSYNC signal). According to an embodiment, when it is recognized that a predetermined application is executed or the temperature of the electronic device 101 exceeds a predetermined temperature, the processor 120 may change the interval of the synchronization signal (e.g., VSYNC signal), which is described in detail below.

[0070] According to an embodiment, the display controller 201 may control the overall operation of the display 203. For example, the display controller 201 may include a display driver IC (DDI) that controls the display 203.

[0071] According to an embodiment, the display controller 201 may generate a synchronization signal. For example, the synchronization signal may include a VSYNC signal. It will be apparent to those skilled in the art that the VSYNC signal may be referred to as a timing signal or a vertical synchronization signal or various other terms. In the present disclosure, the synchronization signal is referred to as a VSYNC signal. According to an embodiment, the synchronization signal (e.g., the VSYNC signal) may include an electrical signal whose voltage value rises and / or falls at a predetermined period (e.g., interval).

[0072] According to an embodiment, the display controller 201 may transmit data (e.g., image frames) stored in the memory 130 to the display 203 based on a synchronization signal (e.g., a VSYNC signal). According to an embodiment, the display controller 201 may transmit data (e.g., image frames) to the display 203 based on a rise in the voltage value of the synchronization signal (e.g., a VSYNC signal). According to an embodiment, the operation of transmitting data (e.g., image frames) to the display 203 by the display controller 201 may be referred to as an operation of reading (or scanning) data (e.g., image frames) by the display controller 201 or an operation of reading (or scanning) data and transmitting the data to the display 203. According to an embodiment, the interval of the synchronization signal (e.g., a VSYNC signal) may be the inverse of the refresh rate of the display 203.

[0073] According to an embodiment, the display controller 201 may generate a timing signal (e.g., a TE-SYNC signal) corresponding to a synchronization signal (e.g., a VSYNC signal) and transmit the timing signal (e.g., a TE-SYNC signal) to the processor 120. According to an embodiment, the display controller 201 may transmit the timing signal (e.g., a TE-SYNC signal) corresponding to the synchronization signal (e.g., a VSYNC signal) to the processor 120, thereby providing the processor 120 with an interval of the synchronization signal (e.g., a VSYNC signal) and / or a timing for reading data (e.g., an image frame) and transmitting the data (e.g., an image frame) to the display 203. According to an embodiment, the timing signal (e.g., a TE-SYNC signal) may have its voltage value rise and / or fall at a timing corresponding to the synchronization signal (e.g., a VSYNC signal), or may have its voltage value rise and / or fall at a timing different from the timing of the synchronization signal (e.g., a VSYNC signal).

[0074] According to an embodiment, the memory 130 may include a graphics random access memory (GRAM) (e.g., Figure 1 The volatile memory 132 is used to temporarily store data (eg, image frames) received from the processor 120. According to an embodiment, the memory 130 may be included in the display controller 201 or may be included in the display 203.

[0075] According to an embodiment, the display 203 may visually output data (e.g., image frames) received from the display controller 201. According to an embodiment, the display 203 may be used interchangeably with the term "display panel." According to an embodiment, the display 203 may include a touch screen for receiving a touch input.

[0076] For convenience of description, the timing signal and the synchronization signal are referred to herein as a TE-SYNC signal and a VSYNC signal, respectively.

[0077] Figure 3 is a diagram showing an electronic device (eg, Figure 1 A view of the sending of a timing signal of the electronic device 101) and an image frame.

[0078] like Figure 3 As shown in , "AP" may refer to a processor (e.g., Figure 1 A “DDI” (display driver IC) may refer to a display controller (e.g., a processor 120). Figure 2 display controller 201), GRAM may refer to graphics random access memory (e.g., Figure 2 Memory 130), and "display" may refer to a display (e.g., Figure 2 display 203).

[0079] According to an embodiment, the timing signal of the electronic device 101 includes a VSYNC signal 301 (eg, Figure 2 Sync signal) and TE-SYNC signal 303 (e.g., first timing signal and second timing signal). Depending on the embodiment, the vertical axes of VSYNC signal 301 and TE-SYNC signal 303 may indicate the relative magnitude of the voltage value of each signal. Depending on the embodiment, the rising voltage values of VSYNC signal 301 and TE-SYNC signal 303 may not necessarily be the same.

[0080] According to an embodiment, the VSYNC signal 301 may determine whether the Figure 1 The image frame is read from the memory 130 of the display controller (e.g., Figure 2 The display controller 201) sends a signal to a display (e.g., Figure 2 The time period (or timing) for sending image frames to the display 203).

[0081] refer to Figure 3 301 and 307, the display controller 201 can read the voltage value of the VSYNC signal 301 from the memory (for example, Figure 1 Memory 130) reads the image frame and displays it to a display (e.g., Figure 2 Display 203) sends image frames.

[0082] According to an embodiment, the operation cycle 307 of the display controller 201 may include a VBP cycle 309, a VACTIVE cycle 311, and a VFP cycle 313. According to an embodiment, the VBP cycle 309 may be a vertical back porch (VBP) cycle. According to an embodiment, the VFP cycle 313 may be a vertical front porch (VFP) cycle. According to an embodiment, the VACTIVE cycle 311 may be a scan cycle of the display controller 201. It will be apparent to those skilled in the art that the VACTIVE cycle 311 may be referred to as a read cycle or a scan cycle or various other terms. According to an embodiment, the display controller 201 may read data from a memory (e.g., a memory device) in the VACTIVE cycle 311 (e.g., within the VACTIVE cycle 311). Figure 1 Memory 130) reads the image frame and displays it to a display (e.g., Figure 2 According to an embodiment, the length (time) of the VBP period 309 and / or the length (time) of the VFP period 313 may be proportional to the interval of the VSYNC signal 301 corresponding to the operation cycle 307 of the display controller 201. For example, the length (time) of the VBP period 309 and / or the length (time) of the VFP period 313 may occupy a certain proportion of the operation cycle 307 of the display controller 201 and may be extended as the interval of the VSYNC signal 301 increases.

[0083] According to an embodiment, the TE-SYNC signal 303 may determine when a processor (e.g., Figure 1 processor 120) to the memory 130 (e.g., Figure 2 The time period (or timing) when the image frame is sent to the memory 130 of the display.

[0084] refer to Figure 3 In response to the rise in the voltage value of the TE-SYNC signal 303, the processor 120 may start sending image frames (e.g., the Nth frame, the (N+1)th frame, ...) to the memory 130 at each rising timing. According to an embodiment, the processor 120 may be configured to send each image frame within the VACTIVE period 311 (e.g., before each VACTIVE period 311 expires) when the display controller 201 reads the image frame to prevent the tearing effect from occurring.

[0085] According to an embodiment, the time period during which the processor 120 can transmit each image frame (hereinafter, referred to as "transmittable time") may be within a range from the rising timing ① of the voltage value of the TE-SYNC signal 303 to the timing ② at the end of the VACTIVE period 311. According to an embodiment, since the length of the VACTIVE period 311 within one cycle is proportional to the interval of the VSYNC signal 301, the transmittable time of the processor 120 may be determined based on the rising timing of the voltage value of the TE-SYNC signal 303, the length of the VACTIVE period 311, and / or the period of the VSYNC signal 301.

[0086] refer to Figure 3 301 and 303, the VSYNC signal 301 and the TE-SYNC signal 303 may be set so that their voltage values rise and / or fall correspondingly (for example, the signals have the same interval). According to an embodiment, the rising timing of the VSYNC signal 301 and the rising timing of the TE-SYNC signal 303 may be the same, or the rising timing of the VSYNC signal 301 may be set to be different from the rising timing of the VSYNC signal 301. According to an embodiment, when the rising timing of the VSYNC signal 301 and the rising timing of the TE-SYNC signal 303 are synchronized (for example, coincident), the transmittable time of the processor 120 may be determined based on the rising timing of the voltage value of the VSYNC signal 301, the length of the VACTIVE period 311, and / or the period of the VSYNC signal 301.

[0087] According to an embodiment, since the image frame generated by and sent from the processor 120 is sent to the display 203 in the VACTIVE period 311 (for example, within the VACTIVE period 311), the time taken for the image generated by the processor 120 to be output through the display 203 can be determined based on the rising timing of the voltage value of the TE-SYNC signal 303, the length of the VACTIVE period 311 and / or the interval of the VSYNC signal 301.

[0088] For convenience of description, the description mainly focuses on the VACTIVE cycle 311 , wherein the VBP cycle 309 and the VFP cycle 313 are omitted from the following figures.

[0089] Figure 4A is a diagram showing an electronic device (eg, Figure 1 A view of the first mode of the electronic device 101). Figure 4B is a view illustrating a second mode of the electronic device 101 according to an embodiment.

[0090] According to an embodiment, the first mode may be referred to as a normal driving mode. According to an embodiment, the second mode may be referred to as a high-speed driving mode. According to an embodiment, it will be apparent to those skilled in the art that the first mode and the second mode may be referred to as various other terms.

[0091] According to an embodiment, Figure 4A and Figure 4B The VSYNC signal 301 and TE-SYNC signal 303 can be connected with Figure 3 The VSYNC signal 301 and TE-SYNC signal 303 are identical unless otherwise noted. Figure 4A and Figure 4B The case where the rising timing of the voltage value of the VSYNC signal 301 and the rising timing of the voltage value of the TE-SYNC signal 303 are synchronized (for example, coincident) is shown.

[0092] The following is based on Figure 4A and Figure 4B According to the embodiment, compared with Figure 4A In the case of Figure 4B In the case of Figure 2 The refresh rate of the display 203) can be higher. For example, Figure 4A The refresh rate of the display 203 may be 60 Hz, and Figure 4B The refresh rate of the display 203 may be 120 Hz. For example, Figure 4A The interval of the VSYNC signal 301 may be approximately 16.67 ms (= 1 / (60 Hz) * 1000), and Figure 4B The interval of the VSYNC signal 301 may be about 8.33 ms (=1 / (120 Hz)*1000).

[0093] According to an embodiment, the processor 120 may be configured to send the image frames within the VACTIVE period 311 when the display controller 201 reads (or scans) the image frames to prevent the tearing effect from occurring.

[0094] According to an embodiment, AP-FREQ (Application Processor Frequency) 401 may refer to the operating frequency of the processor 120 and may be related to the operating speed of the processor 120. According to an embodiment, the operating speed may be the speed at which the processor 120 is required to transmit frames within the VACTIVE period 311 of the display controller 201, and as the available transmission time of the processor 120 decreases, the required operating speed of the processor 120 may increase. According to an embodiment, the operating frequency may be the operating frequency required for the processor 120 to transmit image frames at a specific operating speed, and the operating frequency may refer to, for example, the oscillator clock frequency of the processor 120.

[0095] According to an embodiment, the operation speed and operation frequency of the processor 120 may be determined based on the interval of the VSYNC signal 301. According to an embodiment, because the processor 120 can transmit image frames within the transmittable time T1 and the transmittable time T2, as the interval of the VSYNC signal 301 decreases, the transmittable time may be reduced (for example, T1>T2). Therefore, the shorter the interval of the VSYNC signal 301 (for example, the higher the refresh rate of the display 203), the higher the operation speed and operation frequency required by the processor 120 may be. For example, because Figure 4A The interval of the VSYNC signal 301 is approximately 16.67ms and Figure 4B The interval of the VSYNC signal 301 is about 8.33ms, so in Figure 4B In the case of the processor 120, the required operating speed and operating frequency may be higher than in the case of Figure 4A The computing speed and frequency under the circumstances.

[0096] Shown below Figure 4A and Figure 4B Comparison between.

[0097] [Table 1]

[0098]

[0099] when Figure 4A The interval of the VSYNC signal 301 is approximately 16.67ms and Figure 4B When the interval of the VSYNC signal 301 is approximately 8.33 ms, the values in Table 1 may be as follows.

[0100] Referring to Table 1, OSC may be an operating frequency (eg, an oscillator frequency) of the display controller 201. For example, OSC_NM may be 48.25 MHz and OSC_HS may be 96.5 MHz.

[0101] Frames per second (FPS) may be a refresh rate of the display 203. The refresh rate of the display 203 may be the inverse of an interval of the VSYNC signal 301.

[0102] (VACTIVE / VTOTAL_NM) and (VACTIVE / VTOTAL_HS) may refer to the ratio between the VACTIVE period 311 and the total period (e.g., VBP period + VACTIVE period + VFP period) of the VSYNC signal 301. The VACTIVE period may be the VBP period (e.g., Figure 3 VBP cycle 309) and VFP cycle (e.g., Figure 3 Cycles other than VFP cycle 313).

[0103] when Figure 4A and Figure 4B The intervals of the VSYNC signal 301 are approximately 16.67ms and approximately 8.33ms, respectively. Figure 4A The length of the VACTIVE period 311 may be approximately 16.5 ms (= (1 / 60 Hz) * (3200 H) / 3232 H) * 1000), and Figure 4B The length of the VACTIVE period 311 may be approximately 8.25 ms (=(1 / 120 Hz)*(3200 H / 3232 H)*1000).

[0104] According to the embodiment, because Figure 4B The length of the VACTIVE period 311 (e.g., approximately 8.25 ms) is greater than Figure 4A The length of the VACTIVE cycle 311 is short, so with the Figure 4A Compared with the case of VACTIVE, the computing speed and computing frequency required for the processor 120 to send the image frame to the memory 130 in the VACTIVE period 311a or 311b can be higher.

[0105] According to an embodiment, as the operation speed and operation frequency of the processor 120 and / or the display controller 201 of the electronic device 101 increase, the power consumption (or current consumption) of the electronic device 101 may increase. Figure 4A Compared with the case Figure 4B In the case of the processor 120 and / or the display controller 201, the operation speed and operation frequency are higher, so Figure 4A Compared with the situation in Figure 4B In this case, the power consumption of the electronic device 101 can be higher.

[0106] Figure 5 is a diagram showing an electronic device (eg, Figure 1 FIG. 1 is a diagram illustrating a third mode of an electronic device 101. According to an embodiment, the third mode may be referred to as an adaptive high-speed driving mode.

[0107] According to an embodiment, Figure 5 The VSYNC signal 301 and TE-SYNC signal 303 can be connected with Figure 3 The VSYNC signal 301 and TE-SYNC signal 303 are identical unless otherwise noted. Figure 5The case where the rising timing of the voltage value of the VSYNC signal 301 is synchronized with (e.g., coincident with) the rising timing of the voltage value of the TE-SYNC signal 303 is shown. Depending on the embodiment, in the third mode of the present disclosure, the rising timing of the voltage value of the VSYNC signal 301 may not necessarily be synchronized with (e.g., coincident with) the rising timing of the voltage value of the TE-SYNC signal 303.

[0108] Figure 5 The following is shown: the operation frequency of the display controller 201 is Figure 4B The operating frequency of the display controller 201 in the second mode is the same as that of the display controller 201, and the refresh rate of the display 203 (or the interval of the VSYNC signal 301) is the same as that of the display controller 201. Figure 4A The refresh rate of the display 203 (or the interval of the VSYNC signal 301) in the first mode is the same. According to an embodiment, because Figure 5 The operating frequency of the display controller 201 is Figure 4B The same, so Figure 5 The third mode and Figure 4B Seamless switching between the second modes may be possible.

[0109] According to the embodiment, because Figure 5 The operating frequency of the display controller 201 is Figure 4B , so the display controller 201 reads the data from the memory (e.g. Figure 1 The length of the VACTIVE period 311 for reading an image frame from the memory 130 and sending the image frame to the display 203 can be Figure 4B The length of the VACTIVE period 311 is the same as that of the VACTIVE period 311. For example, referring to the length of the VACTIVE period in Table 1, Figure 5 The length of the VACTIVE period 311 may be approximately 8.25 ms (=(1 / 60 Hz)*(3200 H / 6464 H)*1000).

[0110] According to an embodiment, AP-FREQ 401 may refer to the operation speed and operation frequency of the processor 120. According to an embodiment, because Figure 5 The length of the VACTIVE cycle 311 is Figure 4B The length of the VACTIVE cycle 311 is the same as that of the VACTIVE cycle 311, so the time T3 that the processor 120 can send can be the same as that of the VACTIVE cycle 311. Figure 4B According to the embodiment, since the processor 120 can send the image frame within the transmittable time T3, it is as if Figure 4B In such cases, high operating speed and high operating frequency may be required for the processor 120.

[0111] Shown below Figure 4A 、 Figure 4B and Figure 5 Comparison between.

[0112] [Table 2]

[0113]

[0114] Figure 4B and Figure 5 The comparison between Figure 5 In the case of , a blank period 501 occurs from the timing (②) when the VACTIVE period 311 corresponding to the first image frame (e.g., frame 0) expires to the timing (③) when the VACTIVE period 311 corresponding to the next image frame (e.g., frame 1) starts. According to an embodiment, the occurrence of the blank period 501 may refer to a VFP period (e.g., Figure 3 According to an embodiment, the processor 120 may be configured to transmit one image frame at a given interval corresponding to one cycle (e.g., one interval) of the VACTIVE period 311 so that no tearing effect occurs. According to an embodiment, although the processor 120 starts transmitting the second image frame (e.g., frame 1) that is transmitted next in sequence after the blank period 501 after transmitting the first image frame (e.g., frame 0), no tearing effect may occur. For example, in Figure 5 In the case of , since one operation cycle 307 is 6464H, the blank period 501 can be 3232H. Figure 5 The refresh rate is described as Figure 4A The refresh rate is the same (for example, 60Hz), but Figure 5 The refresh rate is not necessarily the same as Figure 4A The refresh rate is the same. For example, according to an embodiment, Figure 5 The refresh rate can be in the range from 60 Hz to 120 Hz and can be dynamically changed in the range from 60 Hz to 120 Hz.

[0115] Figure 6A is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) changes the timing signal (eg, Figure 3 600a of the operation of the rising timing of the TE-SYNC signal 303). Figures 3 to 5 Describe this.

[0116] According to an embodiment, in operation 610a, the electronic device 101 may generate a timing signal based on a first timing signal (eg, Figure 3 TE-SYNC signal 303) sends the first frame (for example, Figure 3According to an embodiment, a processor (e.g., Figure 1 The processor 120) may respond to a first timing signal (eg, Figure 3 The voltage value of the TE-SYNC signal 303) rises and the memory (for example, Figure 2 Memory 130) sends the first frame (eg, Figure 3 According to an embodiment, the processor 120 can send a first image frame (eg, Figure 3 The time of the image frame) may be in the range from the first timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 ①) to VACTIVE cycle (for example, Figure 3 The timing at the end of the VACTIVE cycle 311) (for example, Figure 5 According to an embodiment, the first timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303 in Figure 5 ① in), VACTIVE cycle (for example, Figure 3 The length of the VACTIVE cycle 311) and / or the synchronization signal (e.g., Figure 3 The sending time of the processor 120 is determined by the interval of the VSYNC signal 301).

[0117] According to an embodiment, in operation 630a, the electronic device 101 may identify the state of the electronic device 101. For example, the state of the electronic device 101 may include the type of (one or more) applications executed on the electronic device 101, the type of the display of the electronic device 101 (e.g., Figure 2 At least one of the content of a screen displayed on the display 203 (eg, an execution screen of an application), the type of user input received, and the temperature of the electronic device 101.

[0118] According to an embodiment, in operation 650a, the electronic device 101 may send first control information to change the first timing signal (eg, Figure 3 According to an embodiment, the processor 120 may send first control information to the display controller 201 based on the state of the electronic device 101 to change the first timing signal (for example, Figure 3 According to an embodiment, the first control information may include a timing for the synchronization signal (eg, Figure 3 Each cycle of the VSYNC signal 301 changes the first timing signal (eg, Figure 3The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 For example, refer to Figure 5 , when the operation cycle of the display controller 201 (for example, Figure 3 When the operation cycle 307) is 6464H, the first control information may include information about the first timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 For example, the information about the change time may include information about the change value (unit: H or ms) corresponding to the change time and / or the relationship between the change time and the blank period (e.g., Figure 5 According to an embodiment, the processor 120 may determine the time for transmitting the first timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 ①) Push the change time back or forward.

[0119] According to an embodiment, the processor 120 may determine whether the state of the identified electronic device 101 is a state in which high responsiveness is required (or allowed) or a state in which low power consumption is required (or allowed). According to an embodiment, responsiveness may refer to the time taken for data (e.g., image frames) generated by the processor 120 in response to the reception of user input or the execution of an application to be output through the display 203. For example, as the time taken for data (e.g., image frames) generated by the processor 120 to be output through the display 203 decreases, it can be said that the responsiveness of the electronic device 101 is higher. According to an embodiment, power consumption may refer to the power consumption of the processor 120 and / or the display controller 201. According to an embodiment, a state in which low power consumption is required (or allowed) may correspond to a state in which high responsiveness is not required (or allowed).

[0120] According to an embodiment, the processor 120 may identify the type of application executed on the electronic device 101 and determine whether the state of the identified electronic device 101 is a state in which high responsiveness is required (or allowed) or a state in which low power consumption is required (or allowed). According to an embodiment, the electronic device 101 may determine that as the data (e.g., image frames) generated per unit time according to the operation of the executed application increases (e.g., as the frame rate increases), the generated data (e.g., image frames) need to be output via the display 203 in a shorter time and require high responsiveness. According to an embodiment, whether the executed application is an application requiring high responsiveness may be preset. For example, when an application software package (package) released by an application developer includes information indicating whether the application requires high responsiveness or information about the operating speed and / or operating frequency of the processor 120 required for the operation of the application, the processor may determine whether the executed application is an application requiring high responsiveness based on the information.

[0121] According to an embodiment, the processor 120 can determine whether the state of the identified electronic device 101 is a state in which high responsiveness is required (or allowed) or a state in which low power consumption is required (or allowed) based on the content of the screen displayed on the display 203 of the electronic device 101 (e.g., an application execution screen). For example, when a video with a high frame rate is output through the display 203, the processor 120 can determine that it is in a state in which high responsiveness is required. For example, when a rotation of the display mode of the display 203 (e.g., switching between landscape mode and portrait mode) is detected, the processor 120 can determine that it is in a state in which high responsiveness is required. For example, if the screen displayed on the display 203 does not change for a preset time or longer, the processor 120 can determine that it is in a state in which low power consumption is required (or allowed).

[0122] According to an embodiment, the processor 120 may determine whether the state of the identified electronic device 101 is a state in which high responsiveness is required (or allowed) or a state in which low power consumption is required (or allowed) based on the type of user input received. For example, when the received user input is an input received using a stylus, the processor 120 may determine that it is in a state in which high responsiveness is required. For example, once the stylus is detected to be removed from the housing of the electronic device 101, the processor 120 may determine that it is in a state in which high responsiveness is required. For example, when a short-range wireless communication signal (e.g., a signal received via Bluetooth communication) is detected from the stylus, the processor 120 may determine that high responsiveness is required. For example, once a user input of scrolling a screen is received, the processor 120 may determine that it is in a state in which high responsiveness is required. For example, once a predetermined number (or more) of inputs are received from the user within a predetermined time, the processor 120 may determine that it is in a state in which high responsiveness is required. For example, when no input is received from the user within a predetermined time, the processor 120 may determine that it is in a state in which low power consumption is required (or allowed).

[0123] According to an embodiment, the processor 120 may determine whether the state of the identified electronic device 101 is a state in which high responsiveness is required (or allowed) or a state in which low power consumption is required (or allowed) based on the temperature of the electronic device 101. For example, the temperature of the electronic device 101 may be a temperature sensed for at least one component of the electronic device 101 (e.g., the processor 120 or the display 203). In one example, upon detecting that the temperature of the electronic device 101 exceeds a predetermined temperature (e.g., 50°C), the processor 120 may determine that it is in a state requiring low power consumption. In another example, upon detecting that the temperature of the electronic device 101 is less than a predetermined temperature (e.g., 20°C), the processor 120 may determine that it is in a state allowing high responsiveness or allowing high power consumption.

[0124] According to an embodiment, based on whether the identified state of the electronic device 101 requires (or allows) high responsiveness or requires (or allows) low power consumption, the processor 120 may determine the timer to be used compared to the initial timing signal (e.g., Figure 3 TE-SYNC signal 303) and the timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 According to an embodiment, when it is determined that the state of the identified electronic device 101 is a state that requires (or allows) high responsiveness or requires (or allows) high power consumption, the processor 120 may determine to change the timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5According to an embodiment, when it is determined that the state of the identified electronic device 101 is a state that requires (or allows) low responsiveness or requires (or allows) low power consumption, the processor 120 may determine to set the timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 ①) Push the change time forward.

[0125] According to an embodiment, the processor 120 may generate first control information including the determined change time and transmit the generated first control information to the display controller 201 .

[0126] According to an embodiment, in operation 670a, the electronic device 101 may receive a second timing signal after transmitting the first control information. According to an embodiment, the processor 120 may receive the second timing signal from the display controller 201. According to an embodiment, the second timing signal may be synchronized with the first timing signal (e.g., Figure 3 The TE-SYNC signal 303 of FIG. 1 is different in the rising timing of the voltage value. For example, compared with the first timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303 in Figure 5 Compared with ①), the rising timing of the voltage value of the second timing signal can be earlier or later. For example, when the first timing signal is Figure 8A TE-SYNC signal 303-1, the second timing signal may be Figure 8A In this example, the rising timing of the second timing signal may be Figure 8A In another example, when the first timing signal is Figure 8A TE-SYNC signal 303-2, the second timing signal may be Figure 8A In this example, the rising timing of the second timing signal may be Figure 8A The first rising timing (①-1).

[0127] According to an embodiment, in operation 690a, the electronic device 101 may transmit a second frame (eg, Figure 3 According to an embodiment, a processor (e.g., Figure 1 The processor 120) may send a signal to the memory (eg, Figure 2 Memory 130) sends a second frame (eg, Figure 3 image frames).

[0128] Figure 6Bis a flow chart 600b illustrating the operation of the processor 120, the display controller 201, and / or the display 203, according to an embodiment.

[0129] According to an embodiment, in operation 601b, the processor 120 may receive a first timing signal (eg, Figure 3 TE-SYNC signal 303).

[0130] According to an embodiment, in operation 603b, the processor 120 may send a first frame (eg, Figure 3 According to an embodiment, the image frame may be displayed in response to a first timing signal (eg, Figure 3 The first frame (eg, Figure 3 The sending of image frames).

[0131] According to an embodiment, in operation 605b, the display controller 201 may scan a first frame (eg, Figure 3 According to an embodiment, the image frame may be displayed in response to a VSYNC signal (eg, Figure 3 The voltage value of the VSYNC signal 301) rises to execute the first frame (for example, Figure 3 Scanning of image frames).

[0132] According to an embodiment, in operation 607b, the display controller 201 may send a first frame (eg, Figure 3 image frames).

[0133] According to an embodiment, in operation 609b, the display 203 may output a first frame (eg, Figure 3 According to an embodiment, the first frame (eg, Figure 3 The image frame) can be visually output as an image through the display 203 (e.g., displayed).

[0134] According to an embodiment, in operation 611b, the processor 120 may identify the state of the electronic device 101. According to an embodiment, operation 609b is not necessarily performed after the above operations are performed, but operation 609 may be performed before or when any of the above operations are performed.

[0135] According to an embodiment, in operation 613 b , the processor 120 may transmit first control information to the display controller 201 .

[0136] According to an embodiment, in operation 615b, the display controller 201 may change the timing signal (eg, Figure 3According to an embodiment, the display controller 201 may identify information included in the received first control information (eg, information for changing (or adjusting) the first timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) (for example, Figure 5 According to an embodiment, the display controller 201 may generate a signal having the same timing as the first timing signal (eg, Figure 3 The TE-SYNC signal 303) is a second timing signal having a rising timing of a voltage value different from the rising timing of a voltage value.

[0137] According to an embodiment, in operation 617b, the processor 120 may receive a second timing signal from the display controller 201. According to an embodiment, the processor 120 may receive a second timing signal generated to have the same timing as the first timing signal (eg, Figure 3 The TE-SYNC signal 303) is a second timing signal having a rising timing of a voltage value different from the rising timing of a voltage value.

[0138] According to an embodiment, in operation 619b, the processor 120 may send the second frame (eg, Figure 3 According to an embodiment, the second frame (eg, Figure 3 The sending of image frames).

[0139] According to an embodiment, in operation 621b, the display controller 201 may scan the second frame (eg, Figure 3 According to an embodiment, the image frame may be displayed in response to a VSYNC signal (eg, Figure 3 The voltage value of the VSYNC signal 301) rises to execute the second frame (for example, Figure 3 Scanning (or reading) of an image frame).

[0140] According to an embodiment, in operation 623b, the display controller 201 may send a second frame (eg, Figure 3 image frames).

[0141] According to an embodiment, in operation 625b, the display 203 may output a second frame (eg, Figure 3 According to an embodiment, the second frame (eg, Figure 3 The image frame) can be visually output as an image through the display 203 (e.g., displayed).

[0142] According to an embodiment, the processor 120 may perform operations 603b and 619b at different operation speeds. The first timing signal (eg, Figure 3 The voltage values of the TE-SYNC signal 303 in the TE-SYNC signal and the second timing signal rise at different times, so the required operating speed and / or operating frequency of the processor 120 can be different. This will be described in more detail below.

[0143] Figure 7 is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) changes the timing signal (eg, Figure 3 FIG. 3 is a view of the operation of the rising timing of the TE-SYNC signal 303).

[0144] refer to Figure 7 , timing signals (e.g., Figure 3 The voltage value of the TE-SYNC signal 303) may rise (703a) at the first rising timing (①-1) or may rise (703b) at the second rising timing (①-2). Figure 2 The display controller 201) sends the timing signal (eg, Figure 3 The rising timing of the TE-SYNC signal 303) is changed from the first rising timing (①-1) to the second rising timing (①-2) (for example, Figure 7 Direction ) or change from the second rising timing (①-2) to the first rising timing (①-1) (for example, Figure 7 Direction changes in the Figure 7 shows the VSYNC signal (e.g., Figure 3 The timing when the voltage value of the VSYNC signal 301 rises (707) is consistent with the timing signal (for example, Figure 3 The timing (①-1) of the voltage value when the TE-SYNC signal 303) rises (703a) is the same, but the rising timing of the VSYNC signal can be between ①-1 and ①-2.

[0145] According to an embodiment, the processor (e.g. Figure 1 The processor 120 of FIG. 1 sends a signal to the memory (eg, Figure 2 Memory 130) sends image frame ("frame a") 701a (eg, Figure 3 According to an embodiment, the image frame ("frame b") 701b may be sent by the processor 120 to the memory 130 during the second sending time Tb (eg, Figure 3 As will be Figure 8A and Figure 8B Described in more detail, with the timing signal (e.g., Figure 3 The processor 120 may send an image frame (eg, Figure 3 The time period (hereinafter, “transmittable time”) of the image frame (of the image frame) can be changed. Therefore, the operation speed and / or operation frequency required by the processor 120 can be changed, and the power consumed by the processor 120 can be changed.

[0146] According to an embodiment, the electronic device 101 may identify the state of the electronic device 101, and based on the identified state of the electronic device 101, the rising timing may be changed from the first rising timing (①-1) to the second rising timing (①-2) (for example, Figure 7 Direction ) or change from the second rising timing (①-2) to the first rising timing (①-1) (for example, Figure 7 Direction For example, once it is determined that the state of the identified electronic device 101 is a state that requires (or allows) high responsiveness or requires (or allows) high power consumption, the electronic device 101 may (for example, Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) is changed from the first rising timing (①-1) to the second rising timing (①-2). For example, once it is determined that the state of the identified electronic device 101 is a state that requires (or allows) low responsiveness or requires (or allows) low power consumption, the electronic device 101 can (for example, at Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) is changed from the second rising timing (①-2) to the first rising timing (①-1).

[0147] According to the embodiment, regardless of whether the rising timing is at the first rising timing (①-1) or at the second rising timing (①-2), the timing signal (eg, Figure 3 The timing when the TE-SYNC signal 303 of the TE-SYNC signal falls (705) can remain unchanged. For example, the timing signal (e.g., Figure 3 The falling timing of the TE-SYNC signal 303) may correspond to the VSYNC signal (eg, Figure 3 The falling timing of the VSYNC signal 301).

[0148] According to an embodiment, Figure 7 Unlike the situation shown in , the timing signal (e.g. Figure 3 The falling timing of the TE-SYNC signal 303) may be different depending on whether the rising timing is at the first rising timing (①-1) or at the second rising timing (①-2). For example, in the case where the timing signal rises (703a) at the first rising timing (①-1) and in the case where the timing signal rises (703b) at the second rising timing (①-2), the timing signal (e.g., Figure 3 The duration time interval of the relatively high voltage value of the TE-SYNC signal 303) may remain unchanged, but the timing signal (eg, Figure 3 The falling timing of the TE-SYNC signal 303) may be different between a case where the timing signal rises (703a) at the first rising timing (①-1) and a case where the timing signal rises (703b) at the second rising timing (①-2).

[0149] Table 3 shows the timing signals (e.g., Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) does not coincide with the timing of the rise of the synchronization signal (for example, Figure 3 The case where the rising timing of the voltage value of the VSYNC signal 301) is synchronized ("asynchronous TE") with the timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) is consistent with the synchronization signal (for example, Figure 3 For example, the timing signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) does not coincide with the timing of the rise of the synchronization signal (for example, Figure 3 In the case of synchronization of the rising timing of the voltage value of the VSYNC signal 301) ("asynchronous TE"), for example, the timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) is the second rising timing (①-2). For example, the timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) is consistent with the synchronization signal (for example, Figure 3 In the case of synchronization of the rising timing of the voltage value of the VSYNC signal 301) ("synchronization TE"), for example, the timing signal (for example, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) is the first rising timing (①-1).

[0150] [Table 3]

[0151]

[0152] Referring to Table 3, AP-FREQ may refer to the operating frequency of the processor 120. The value of AP-FREQ may refer to the relative magnitude of the operating frequency of the processor 120. "Layer" may refer to the number of layers of images displayed on the display 203 in each "scene". "Camera preview" may refer to a situation where a camera application is being executed. "Video player" may refer to a situation where a video application is running. "Youtube" may refer to a situation where a YouTube application is running. "Landscape" and "Portrait" may refer to a situation where the display mode of the display 203 is landscape mode or portrait mode, respectively.

[0153] Referring back to Table 3, it can be shown that the operating frequency of the processor 120 is relatively small in the case of "asynchronous TE" compared to "synchronous TE". This may mean that as the timing signal (e.g., Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) is changed, and the operating frequency of the processor 120 can be reduced, as described above. Figure 7 As described above, the power consumption of the processor 120 can be reduced.

[0154] Figure 8A 3 is a diagram showing an example in which the rising timing of a timing signal (eg, TE-SYNC signal 303) is changed according to an embodiment. Figure 8A and Figure 5 and / or Figure 7 To describe the embodiment.

[0155] According to an embodiment, the first timing signal (eg, TE-SYNC signal 303-1) may be a signal whose voltage value periodically rises at each first rising timing (①-1), and the rising state is maintained during the first duration D1. Figure 5 , the first timing signal (eg, TE-SYNC signal 303-1) may be Figure 5 Timing signal (for example, Figure 5 The TE-SYNC signal 303 is the same.

[0156] According to an embodiment, the second timing signal (e.g., TE-SYNC signal 303-2) may be a signal whose voltage value periodically rises at every second rising timing (①-2), and the rising state is maintained for a second duration D2. Compared to the first timing signal (e.g., TE-SYNC signal 303-1), the second timing signal (e.g., TE-SYNC signal 303-2) may have a different voltage value rising timing than the first timing signal (e.g., TE-SYNC signal 303-1).

[0157] According to an embodiment, a processor (e.g., Figure 1 The processor 120 of the electronic device (eg, Figure 1 electronic device 101) to control the display controller (eg, Figure 2 Display controller 201) with (for example, in Figure 7 Direction ) changes the timing signal (e.g., TE-SYNC signal 303) from a first timing signal (e.g., TE-SYNC signal 303-1) to a second timing signal (e.g., TE-SYNC signal 303-2) or (e.g., Figure 7 Direction (above) changes the timing signal (eg, TE-SYNC signal 303) from the second timing signal (eg, TE-SYNC signal 303-2) to the first timing signal (eg, TE-SYNC signal 303-1).

[0158] Although the following describes a processor (e.g., Figure 1 The processor 120 of the electronic device (eg, Figure 1 electronic device 101) to control the display controller (eg, Figure 2 Display controller 201) with (for example, in Figure 7 Direction In the example of changing the timing signal (e.g., TE-SYNC signal 303) from the first timing signal (e.g., TE-SYNC signal 303-1) to the second timing signal (e.g., TE-SYNC signal 303-2), even when the processor controls the display controller 201 to (e.g., Figure 7 Direction The same description may also apply when the timing signal (eg, TE-SYNC signal 303) is changed from the second timing signal (eg, TE-SYNC signal 303-2) to the first timing signal (eg, TE-SYNC signal 303-2).

[0159] According to an embodiment, the processor 120 may send an image frame (eg, a timing signal) to the memory 130 based on the timing signal (eg, the TE-SYNC signal 303). Figure 3 image frames).

[0160] According to an embodiment, the processor 120 can send an image frame (e.g., Figure 3 The transmittable time of the image frame of the image frame may be at a rising timing (eg, Figure 5 ①) to the timing at the end of the VACTIVE cycle 311 (for example, Figure 5For example, when the timing signal (e.g., TE-SYNC signal 303) is the first timing signal (e.g., TE-SYNC signal 303-1), the time during which the processor 120 can transmit may be less than or equal to time T3 from the rising timing (①-1) of the voltage value of the first timing signal (e.g., TE-SYNC signal 303-1) to timing ② at the end of the VACTIVE cycle 311. For example, when the timing signal (e.g., TE-SYNC signal 303) is the second timing signal (e.g., TE-SYNC signal 303-2), the time during which the processor 120 can transmit may be less than or equal to time T3' from the rising timing (①-2) of the voltage value of the first timing signal (e.g., TE-SYNC signal 303-2) to timing ② at the end of the VACTIVE cycle 311.

[0161] According to an embodiment, the processor 120 may transmit the image frame (eg, Figure 3 For example, when the timing signal (eg, TE-SYNC signal 303) is the first timing signal (eg, TE-SYNC signal 303-1), the processor 120 may transmit the image frame (eg, Figure 3 For example, when the timing signal (eg, TE-SYNC signal 303) is the second timing signal (eg, TE-SYNC signal 303-2), the processor 120 may transmit the image frame (eg, Figure 3 According to an embodiment, the first transmission time Ta and the second transmission time Tb may be less than or equal to T3 and T3', respectively.

[0162] According to an embodiment, as the timing signal (e.g., TE-SYNC signal 303) changes from a first timing signal (e.g., TE-SYNC signal 303-1) to a second timing signal (e.g., TE-SYNC signal 303-2), the sending time of the image frame sent by the processor 120 can be changed from the first sending time Ta to the second sending time Tb.

[0163] According to an embodiment, AP-FREQ 401 may refer to the operating speed and operating frequency of the processor 120. According to an embodiment, as the transmission time changes (e.g., increases) from the first transmission time Ta to the second transmission time Tb, the required operating speed and / or operating frequency of the processor 120 may decrease.

[0164] According to an embodiment, as the operating speed and / or operating frequency required by the processor 120 changes (e.g., decreases), the power consumed by the processor 120 may decrease. Similarly, as the timing signal (e.g., TE-SYNC signal 303) changes from the second timing signal (e.g., TE-SYNC signal 303-2) to the first timing signal (e.g., TE-SYNC signal 303-1), the transmission time of the processor 120 may decrease, the operating speed and / or operating frequency required by the processor 120 may increase, and the power consumption of the processor 120 may increase.

[0165] According to an embodiment, the second rising timing (①-2) of the second timing signal (e.g., TE-SYNC signal 303-2) may occur earlier than the first rising timing (①-1) of the first timing signal (e.g., TE-SYNC signal 303-1) by a change time B (=Tb-Ta). As will be described below, Figure 9 As described in more detail in , the change time B may be less than or equal to the length of the blank period 501. According to an embodiment, the length of the blank period 501 may correspond to a VFP period (e.g., Figure 3 The length of the VFP period 313 of the blank period 501 may be increased. For example, the length of the blank period 501 may be 3232H. According to an embodiment, the length of the change time B may be determined based on the first control information. According to an embodiment, the first control information may include information about a change value (unit: H or ms) corresponding to the change time B and / or a ratio of the change time to the length of the blank period 501. For example, the first control information may include information about a change time B (e.g., 4ms) that is less than or equal to the time length of the blank period 501 (e.g., 8.25ms). For example, the first control information may include information about a length ratio (e.g., 50%) of the change time B to the length of the blank period 501 (e.g., 3232H).

[0166] According to an embodiment, as the rising timing of the timing signal (e.g., TE-SYNC signal 303) changes from the first rising timing (①-1) to the second rising timing (①-2), the operating speed and / or operating frequency required by the processor 120 can be reduced, and the power consumption of the processor 120 can be reduced in proportion to the change time B.

[0167] Figure 8B is a diagram showing an image frame (eg, Figure 3 A view of an example in which the transmittable time of an image frame) is changed.

[0168] Figure 8B (a) shows that when the display (e.g., Figure 2 When the refresh rate of the display 203) is the first refresh rate, the display controller (eg, Figure 2For example, the first refresh rate may be 120 Hz.

[0169] Figure 8B (b) shows the operation cycle of the display controller 201 when the refresh rate of the display 203 is the second refresh rate (for example, 60 Hz). The second refresh rate can be a value less than the first refresh rate. For example, the second refresh rate can be a frequency between 60 Hz and 120 Hz. Figure 8B An example in which the second refresh rate is half the first refresh rate (eg, 60 Hz) is described.

[0170] According to an embodiment, when the refresh rate of the display 203 changes from the first refresh rate to the second refresh rate, the length of the VFP period 313 may change from L1 to L2 (increase ΔL). According to an embodiment, the period ΔVFP of the VFP period 313 may be the blank period 501.

[0171] According to an embodiment, as the length of the VFP period 313 increases (eg, the blank period 501 appears), the electronic device 101 may increase the TE-SYNC signal (eg, Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303 of the electronic device 101 is adjusted (eg, changed) to be within the range of the increased length ΔL of the period ΔVFP. Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303) is adjusted (e.g., changed) from the first rising timing (①-1) to the second rising timing (①-2) by as much as B. According to an embodiment, the length of the change time B may be less than or equal to the increased length ΔL of the period ΔVFP. For example, the increased length ΔL of the period ΔVFP may be the synchronization signal (e.g., Figure 3 The period of the VSYNC signal 301).

[0172] refer to Figure 8B (c) and (d), with the TE-SYNC signal (e.g., Figure 3 The rising timing of the voltage value of the TE-SYNC signal 303 of the TE-SYNC signal 303 is changed by B, and the transmittable time at which the electronic device 101 can transmit the image frame ("Nth frame") can be changed (increased) from T3 to T3'. According to an embodiment, as the transmittable time is changed (increased) from T3 to T3', the electronic device 101 can transmit the image frame ("Nth frame") at a time that has been increased by B. Thus, the processor (for example, Figure 2The operating speed and / or operating frequency required for the processor 120 to send image frames to the memory 130 within the VACTIVE cycle 311 of the display controller 201 (for example, before the end of the VACTIVE cycle 311) can be reduced, and the power consumption of the processor 120 can be reduced.

[0173] According to an embodiment, the TE-SYNC signal (eg, Figure 3 The first control information of the TE-SYNC signal 303 may include information about the ratio of the length of the change time B to the length of the blank period 501. For example, the first control information may include information about B / ΔL or a corresponding value thereof (e.g., B / ΔL*100(%)). Depending on the embodiment, the first control information may include information about the change value corresponding to the change time B. For example, the first control information may include information indicating that the length of the change time (B) is 4 ms and / or 300 H.

[0174] Figure 9 is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) changes the timing signal (eg, Figure 3 900 of the operation of timing the rise of the TE-SYNC signal 303).

[0175] According to an embodiment, in operation 910, the electronic device 101 may identify a state of the electronic device 101. For example, the state of the electronic device 101 may include the type of (one or more) applications executed on the electronic device 101, the type of the display of the electronic device 101 (e.g., Figure 2 At least one of the content of a screen displayed on the display 203 (eg, an execution screen of an application), the type of user input received, and the temperature of the electronic device 101.

[0176] According to an embodiment, the processor 101 may determine whether the state of the electronic device 101 is a state requiring high responsiveness or a state requiring low power consumption. According to an embodiment, the electronic device 101 may determine whether the identified state of the electronic device 101 is a state in which high responsiveness is required (or allowed) or a state in which low power consumption is required (or allowed).

[0177] According to an embodiment, when it is determined that the identified state of the electronic device 101 is a state requiring low power consumption, in operation 950, the electronic device 101 may send a timing signal (eg, Figure 3 According to an embodiment, the state in which low power consumption is required (or allowed) may refer to a state in which low responsiveness is required and / or low responsiveness is allowed. Figure 7 , the electronic device 101 may (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the first rising timing (for example, Figure 7 ①-1) is changed to the second rising timing (for example, Figure 7 ①-2). Figure 7 Direction can be relative to a display controller (e.g. Figure 2 The display controller 201) of the synchronization signal (for example, Figure 3 The VSYNC signal 301) rises (for example, Figure 7 707) when the timing a-direction.

[0178] According to an embodiment, when it is determined that the identified state of the electronic device 101 is a state requiring high responsiveness, in operation 970, the electronic device 101 may transmit a timing signal (eg, Figure 3 The rising timing of the TE-SYNC signal 303) is changed to be pushed back. According to an embodiment, the state in which high responsiveness is required may refer to a state in which high power consumption is required and / or high power consumption is allowed. Figure 7 , the electronic device 101 may (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the second rising timing (for example, Figure 7 ①-2) is changed to the first rising timing (for example, Figure 7 ①-1). Figure 7 Direction can be relative to a display controller (e.g. Figure 2 The display controller 201) of the synchronization signal (for example, Figure 3 The VSYNC signal 301) rises (for example, Figure 7 707) when the timing a+ direction.

[0179] According to an embodiment, the electronic device 101 may perform operation 910 again after performing the above-described operation 950 or operation 970 .

[0180] Figure 10A is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) changes the timing signal (eg, Figure 31000a of the operation of timing the rise of the TE-SYNC signal 303). Figure 9 Repeated description of those described above.

[0181] According to an embodiment, in operation 1010a, the electronic device 101 may determine an adaptive high-speed driving mode (eg, Figure 5 According to an embodiment, when the adaptive high-speed driving mode is activated, the blank period (eg, Figure 5 501) exists so that the timing signal (eg, Figure 3 The rising timing of the TE-SYNC signal 303) can be as follows Figure 5 , but it should not be understood as being limited to a specific operating mode (e.g., adaptive high-speed driving mode or the third mode) in the present disclosure. Figure 1 processor 120) and / or a display controller (e.g., Figure 2 display controller 201) to perform operation 1010a.

[0182] According to an embodiment, upon determining that the adaptive high-speed driving mode is not activated, the electronic device 101 may maintain the timing signal (eg, Figure 3 According to an embodiment, when the adaptive high-speed driving mode is not activated, it may refer to, for example, when Figure 4A or Figure 4B There are no blank periods shown in Figure 5 501) exists, but it should not be understood as being limited to a specific operating mode in the present disclosure (e.g., normal driving mode, high-speed driving mode, first mode or second mode).

[0183] According to an embodiment, when it is determined that the adaptive high-speed driving mode is activated, the electronic device 101 may perform operations 1030a to 1060a. Figure 9 The same description given of operations 910 to 970 of FIG. 10 may be applied to operations 1030 a to 1060 a , and thus, descriptions of operations 1030 a to 1060 a are not given below.

[0184] Figure 10B is a diagram showing an electronic device (eg, Figure 1 Flowchart 1000b of driving mode switching of the electronic device 101).

[0185] According to an embodiment, in operation 1010b, the electronic device 101 may operate in a high-speed driving mode. According to an embodiment, the electronic device 101 may operate a display (eg, Figure 2 The refresh rate of the display 203) is set to a higher value (e.g., 120 Hz), and the processor (e.g., Figure 1 According to an embodiment, the operation speed and / or operation frequency of the processor 120 of the display controller (e.g., Figure 2 The display controller 201) generates a synchronization signal (eg, Figure 3 The interval of the VSYNC signal 301 is the inverse of the refresh rate of the display (e.g., 120 Hz) (e.g., approximately 8.33 ms (= 1 / 120*1000)). For example, the high-speed drive mode may be Figure 4B The second mode corresponds to the driving mode.

[0186] According to an embodiment, in operation 1030b, the electronic device 101 may identify the execution of a predetermined application on the electronic device 101. For example, the predetermined application may include at least one of a camera application and a navigation application. According to an embodiment, the predetermined application is not limited to the examples described above. According to an embodiment, operation 1030b may be performed by the processor 120.

[0187] According to an embodiment, in operation 1050b, the electronic device 101 may switch to an adaptive high-speed driving mode. For example, the adaptive high-speed driving mode may refer to a mode in which a blank period (eg, Figure 5 The blank period 501 in the timing signal (eg, Figure 3 The rising timing of the TE-SYNC signal 303) can be as follows Figure 5 , but it should not be understood as being limited to the specific operation mode in the present disclosure (e.g., adaptive high-speed driving mode or the third mode). According to an embodiment, when it is recognized that a predetermined application is executed, the processor 120 may send a synchronization signal (e.g., Figure 3The processor 120 may include second control information for changing the interval of the synchronization signal (e.g., VSYNC signal 301) and / or the refresh rate of the display 203. For example, the second control information may include a specific setting value indicating the refresh rate to be set and / or the interval of the synchronization signal (e.g., VSYNC signal 301). For example, the second control information may include a specific setting value indicating the ratio for changing the interval of the synchronization signal (e.g., VSYNC signal 301) and / or the refresh rate to be set. According to an embodiment, when it is recognized that a predetermined application is executed, the processor 120 may send to the display controller 201 the second control information for changing the refresh rate of the display 203 to a refresh rate (e.g., 60 Hz) lower than the refresh rate (e.g., 120 Hz) of operation 1010b, thereby controlling the display controller 201 to change the refresh rate of the display 203 to a refresh rate corresponding to the setting value included in the second control information. According to an embodiment, when it is recognized that a predetermined application is executed, the processor 120 may transmit second control information to the display controller 201 to change the interval of the synchronization signal (e.g., the VSYNC signal 301) to an interval (e.g., 16.67 ms (=1 / 60)) longer than the interval (e.g., 8.33 ms) of the synchronization signal (e.g., the VSYNC signal 301) of operation 1010b, thereby controlling the display controller 201 to generate the synchronization signal (e.g., the VSYNC signal 301) having the changed interval (e.g., 16.67 ms). According to an embodiment, as Figure 5 As shown in FIG, the scan-on time of the display controller 201 (eg, Figure 3 The length of the VACTIVE period 311 in the display 203 may be the same as when a high refresh rate (e.g., 120 Hz) is set in the display 203. Therefore, after the refresh rate of the display 203 and / or the interval of the synchronization signal (e.g., the VSYNC signal 301) is changed, the blank period (e.g., Figure 5 A blank period 501) may occur so that a timing signal (eg, Figure 3 The rising timing of the TE-SYNC signal 303 in is changed.

[0188] Figure 10C is a diagram showing an electronic device (eg, Figure 1 Flowchart 1000c of driving mode switching of the electronic device 101).

[0189] According to an embodiment, in operation 1010c, the electronic device 101 may operate in a high-speed driving mode. According to an embodiment, the electronic device 101 may turn on the display (eg, Figure 2 The refresh rate of the display 203) is set to a higher value (e.g., 120 Hz), and the processor (e.g., Figure 1According to an embodiment, the operation speed and / or operation frequency of the processor 120 of the display controller (e.g., Figure 2 The display controller 201) generates a synchronization signal (eg, Figure 3 The interval of the VSYNC signal 301 is the inverse of the refresh rate of the display (for example, 120 Hz) (for example, 8.33 ms (= 1 / 120*1000)). For example, the high-speed driving mode can be the same as Figure 4B The second mode corresponds to the driving mode.

[0190] According to an embodiment, in operation 1030c, the electronic device 101 may recognize that the temperature of the electronic device 101 exceeds a predetermined temperature. For example, the temperature of the electronic device 101 may be a temperature sensed by a component of the electronic device 101 (e.g., the processor 120 or the display 203). For example, the predetermined temperature may be 50°C. According to an embodiment, the temperature may be sensed by the processor 120 and / or the temperature sensor (e.g., Figure 1 sensor module 176) to perform operation 1030b.

[0191] According to an embodiment, in operation 1050c, the electronic device 101 may switch to an adaptive high-speed driving mode. For example, the adaptive high-speed driving mode may refer to a mode in which a blank period (eg, Figure 5 501) exists so that the timing signal (eg, Figure 3 The rising timing of the TE-SYNC signal 303) can be as follows Figure 5 , but it should not be understood as being limited to the specific operation mode in the present disclosure (e.g., adaptive high-speed driving mode or the third mode). According to an embodiment, when it is recognized that the temperature of the electronic device 101 exceeds a predetermined temperature, the processor 120 may send a synchronization signal to the display controller 201 to change the display controller 201 (e.g., Figure 3 The second control information of the interval of the VSYNC signal 301) and / or the refresh rate of the display 203. According to an embodiment, Figure 10B The description of the second control information in operation 1050b may be applied to the second control information, and thus a detailed description thereof is not given.

[0192] Figure 11A is a view illustrating a screen for setting a refresh rate of the electronic device 101 according to an embodiment.

[0193] refer to Figure 11A , a setting screen 1101a for setting a refresh rate of the display 203 may be displayed on the display 203 of the electronic device 101. According to an embodiment, the display 203 may include a touch screen for receiving a touch input.

[0194] According to an embodiment, the settings screen 1101a may include a first entry 1103a ("High refresh rate") corresponding to a high refresh rate and a second entry 1105a ("Stand refresh rate") corresponding to a standard refresh rate. According to an embodiment, the standard refresh rate may be a relatively lower refresh rate than the high refresh rate. For example, the high refresh rate may be 120 Hz, and the standard refresh rate may be 60 Hz. According to an embodiment, the settings screen 1101a may further include an apply button ("Apply") 1107a.

[0195] According to an embodiment, the first entry 1103a may correspond to Figure 4B The second mode or Figure 5 According to an embodiment, the second entry 1105a may correspond to Figure 4A The first mode.

[0196] According to an embodiment, a processor (e.g., Figure 1 The processor 120 may receive an input for selecting one of the first item 1103a or the second item 1105a from the user. Depending on an embodiment, the processor 120 may receive an input (e.g., a touch input) for selecting one of the first item 1103a or the second item 1105a using a touch screen, and receive an input (e.g., a touch input) for selecting the apply button 1107a.

[0197] According to an embodiment, when the first entry 1103a is selected, the processor 120 may control the electronic device 101 to Figure 4B The second mode or Figure 5 The system operates in one of the third modes.

[0198] According to an embodiment, when the first entry 1103a corresponds to Figure 4B In the second mode, the display 203 may be set to a high refresh rate (e.g., 120 Hz), and the display controller (e.g., Figure 2 The display controller 201) may be set to a synchronization signal (eg, Figure 3For example, the processor 120 may operate at a relatively high operating speed and / or a high operating frequency. According to an embodiment, upon recognizing that a predetermined application (e.g., a camera application or a navigation application) is executed or upon recognizing that the temperature of the electronic device 101 exceeds a predetermined temperature (e.g., 50°C), the processor 120 may reduce the refresh rate of the display 203. For example, the refresh rate of the display 203 may be changed from a high refresh rate (e.g., 120 Hz) to a relatively low refresh rate (e.g., a value included in the range from 60 Hz to 120 Hz). According to an embodiment, the electronic device 101 may be changed from a high refresh rate (e.g., 120 Hz) to a relatively low refresh rate (e.g., a value included in the range from 60 Hz to 120 Hz). Figure 4B Switch to the second mode Figure 5 Therefore, the operation speed and / or operation frequency of the processor 120 can be reduced.

[0199] According to an embodiment, when the first entry 1103a corresponds to Figure 5 In the third mode, the display 203 can be set as follows Figure 5 , and a display controller (e.g., a relatively low refresh rate as shown in Figure 2 The display controller 201) may be set to a synchronization signal (eg, Figure 3 According to an embodiment, the electronic device 101 may Figure 5 Run in the third mode.

[0200] According to an embodiment, when the electronic device 101 switches to the third mode or operates in the third mode, the processor 120 may change the timing signal (eg, Figure 3 Therefore, the operation speed and / or operation frequency of the processor 120 can be changed.

[0201] Figure 11B is a view illustrating preset applications according to an embodiment.

[0202] According to an embodiment, a predetermined application (e.g., Figure 10B The predetermined application) may be a camera application.

[0203] refer to Figure 11B , the execution screen 1101 b of the camera application can be displayed on the display 203 of the electronic device 101.

[0204] According to an embodiment, upon recognizing that the camera application is executed or the execution screen of the camera application is displayed, the processor 120 may switch to the third mode (eg, Figure 5), or from the second mode (e.g. Figure 4B The second mode) switches to the third mode (for example, Figure 5 The third mode).

[0205] According to an embodiment, the camera application may be configured to generate image frames (e.g., Figure 3 According to an embodiment, the processor 120 may identify a refresh rate set for the display 203 and identify that the identified refresh rate is higher than the frame rate of the camera application. According to an embodiment, when identifying that the identified refresh rate is higher than the frame rate of the camera application, the processor 120 may determine that the refresh rate of the display 203 can be reduced, and in order to reduce power consumption of the display 203 and / or the display controller 201, the processor 120 may control the display 203 and / or the display controller 201 to reduce the refresh rate of the display 203. According to an embodiment, the processor 120 may change the timing signal based on the state of the electronic device 101 (for example, Figure 3 Therefore, the operation speed and / or operation frequency of the processor 120 can be changed.

[0206] According to an embodiment, when recognizing that a predetermined application (eg, a camera application) is terminated or switched to another execution screen of the predetermined application, the processor 120 may control the display 203 and / or the display controller 201 to increase the refresh rate of the display 203 .

[0207] Figure 11C is a view illustrating another preset application according to an embodiment.

[0208] According to an embodiment, a predetermined application (e.g., Figure 10B The predetermined application) may be a navigation application.

[0209] refer to Figure 11C , the execution screen 1101c of the navigation application can be displayed on the display 203 of the electronic device 101.

[0210] According to an embodiment, upon recognizing that the navigation application is executed or the execution screen of the navigation application is displayed, the processor 120 may switch to the third mode (eg, Figure 5 ) or from the second mode (e.g. Figure 4B The second mode) switches to the third mode (for example, Figure 5 The third mode).

[0211] According to an embodiment, the navigation application may be configured to generate image frames (eg, Figure 3According to an embodiment, the processor 120 may identify a refresh rate set for the display 203 and identify that the identified refresh rate is higher than the frame rate of the camera application. According to an embodiment, when identifying that the identified refresh rate is higher than the frame rate of the camera application, the processor 120 may determine that the refresh rate of the display 203 can be reduced, and in order to reduce power consumption of the display 203 and / or the display controller 201, the processor 120 may control the display 203 and / or the display controller 201 to reduce the refresh rate of the display 203. According to an embodiment, the processor 120 may change the timing signal based on the state of the electronic device 101 (for example, Figure 3 Therefore, the operation speed and / or operation frequency of the processor 120 can be changed.

[0212] According to an embodiment, a navigation application may be an application configured to consume high power. For example, because a signal of a wireless communication scheme (e.g., a global positioning system (GPS)) may be sent and / or received according to the operation of the navigation application, the navigation application may be an application that consumes high power. According to an embodiment, the electronic device 101 may recognize that the executed navigation application is an application that consumes high power, and in order to reduce the power consumption of the display controller 201, the electronic device 101 may control the display 203 and / or the display controller 201 to reduce the refresh rate of the display 203. According to an embodiment, the processor 120 may change the timing signal (e.g., Figure 3 Therefore, the operation speed and / or operation frequency of the processor 120 can be changed.

[0213] Figure 12A is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) changes the timing signal (eg, Figure 3 TE-SYNC signal 303) is displayed.

[0214] refer to Figure 12A , an execution screen 1201 a of an application (eg, an Internet application) may be displayed on the display 203 of the electronic device 101 .

[0215] According to an embodiment, a processor (e.g., Figure 1 The processor 120 of the embodiment may receive a drag input for scrolling the execution screen 1201a from the user 1203a using the display 203 (eg, a touch screen). Figure 12A , an input of dragging from the first point 1205a to the second point 1207a may be received. According to an embodiment, the processor 120 may control the display controller (eg, Figure 2 display controller 201) to change the timing signal (e.g., Figure 3 According to an embodiment, the electronic device 101 may be in a state where Figure 5 According to an embodiment, upon receiving a drag input on the execution screen 1201a, the processor 120 may control the display controller 201 to (for example, Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the second rising timing (for example, Figure 7 ①-2) is changed to the first rising timing (for example, Figure 7 ①-1).

[0216] According to an embodiment, upon recognizing that the received drag input for scrolling the execution screen 1201a is released, the processor 120 may control the display controller 201 to (for example, Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the first rising timing (for example, Figure 7 ①-1) is changed to the second rising timing (for example, Figure 7 ①-2).

[0217] Figure 12B is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) determines a timing signal (eg, Figure 3 TE-SYNC signal 303) is displayed.

[0218] refer to Figure 12B , respective execution screens 1201b and 1203b of a plurality of applications (eg, an Internet application and a camera application) may be displayed on the display 203 of the electronic device 101. According to an embodiment, the plurality of applications may be applications of the same type or applications of different types.

[0219] According to an embodiment, a processor (e.g., Figure 1 The processor 120) can identify the types of multiple executed applications and / or the contents of the displayed execution screens of the applications.

[0220] According to an embodiment, the processor 120 may generate a timing signal (eg, Figure 3 TE-SYNC signal 303).

[0221] According to an embodiment, the processor 120 may identify whether at least one of the plurality of executed applications is an application corresponding to high responsiveness. For example, when a game application and an Internet application are executed, the processor 120 may determine that the game application is an application requiring high responsiveness. According to an embodiment, upon identifying that at least one of the plurality of executed applications is an application corresponding to high responsiveness, the processor 120 may control the display controller (e.g., Figure 2 201) with (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the second rising timing (for example, Figure 7 ①-2) is changed to the first rising timing (for example, Figure 7 ①-1).

[0222] According to an embodiment, upon recognizing that a plurality of executed applications are all applications corresponding to low power consumption (eg, applications for which low responsiveness is allowed), the processor 120 may control the display controller (eg, Figure 2 201) with (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the first rising timing (for example, Figure 7 ①-1) is changed to the second rising timing (for example, Figure 7 According to an embodiment, upon identifying that at least one of the plurality of executed applications is an application corresponding to low power consumption (eg, one for which low responsiveness is allowed), the processor 120 may control the display controller (eg, Figure 2 201) with (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the first rising timing (for example, Figure 7 ①-1) is changed to the second rising timing (for example, Figure 7 ①-2).

[0223] According to an embodiment, when a video with a high FPS is being output via at least one of the displayed execution screens of a plurality of applications, the processor 120 may control the display controller (eg, Figure 2 201) with (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the second rising timing (for example, Figure 7 ①-2) is changed to the first rising timing (for example, Figure 7 ①-1).

[0224] According to an embodiment, when a video with a low FPS is being output via all displayed execution screens of a plurality of applications, the processor 120 may control the display controller (eg, Figure 2 201) with (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the first rising timing (for example, Figure 7 ①-1) is changed to the second rising timing (for example, Figure 7 ①-2).

[0225] According to an embodiment, the above-described contents are merely examples. When a user input (eg, a scroll gesture) requiring high responsiveness is received through any one of the plurality of execution screens 1201b and 1203b, the processor 120 may control the display controller (eg, Figure 2 Display controller 201) (e.g., in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) from the second rising timing (for example, Figure 7 ①-2) is changed to the first rising timing (for example, Figure 7 ①-1).

[0226] Figure 13 is a diagram showing an electronic device (eg, Figure 1 The electronic device 101) determines a timing signal (eg, Figure 3 TE-SYNC signal 303) is displayed.

[0227] According to an embodiment, a processor (e.g., Figure 1The processor 120 of the electronic device 101 may recognize that the stylus 1303 is removed 1305 (eg, popped-up) from the housing 1301 of the electronic device 101. According to an embodiment, the processor 120 may use a sensor included in the housing (eg, Figure 1 The sensor module 176 of the stylus 1303 may be used to recognize the removal of the stylus 1303. According to an embodiment, when a short-range wireless communication signal (eg, a signal received through Bluetooth communication) is detected from the stylus 1303, the processor 120 may recognize that the stylus 1303 is removed.

[0228] According to an embodiment, the processor 120 may receive an input from the stylus 1303. For example, the input from the stylus 1303 may include at least one of touching, tapping, hovering, or dragging using the stylus 1303. For example, the input from the stylus 1303 may include a short-range wireless communication signal from the stylus 1303 (for example, a signal received through Bluetooth communication).

[0229] According to an embodiment, when the removal 1305 of the stylus pen 1303 is recognized or when an input of the stylus pen 1303 is received, the processor 120 may determine that it is in a state requiring high responsiveness. According to an embodiment, when the removal 1305 of the stylus pen 1303 is recognized or when an input of the stylus pen 1303 is received, the processor 120 may control the display controller (e.g., Figure 2 Display controller 201) with (for example, in Figure 7 Direction The timing signal (for example, Figure 3 The rising timing of the TE-SYNC signal 303) (for example, Figure 5 ①) is changed from the second rising timing (①-2) to the first rising timing (①-1).

[0230] According to an embodiment, an electronic device (e.g., Figure 1 The electronic device 101 includes at least one processor (eg, Figure 1 processor 120); a display (e.g., Figure 2 display 203); memory (e.g., Figure 1 130 ) configured to store image frames received from at least one processor; and a display controller (e.g., Figure 2 The display controller 201 is configured to output the image frame stored in the memory through the display, wherein the at least one processor is configured to: based on a first timing signal (e.g., Figure 3 The TE-SYNC signal 303) sends a first image frame (eg, Figure 3The present invention also provides a method for displaying an image frame to be outputted through a display by a memory, wherein the image frame is displayed on the display screen; identifying a state of the electronic device; sending first control information for changing the timing of a first timing signal to a display controller based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to sending the first control information for changing the timing of the first timing signal; and sending a second image frame to be outputted through the display to a memory based on the received second timing signal. The timing of the second timing signal may be different from the timing of the first timing signal.

[0231] According to an embodiment, at least one processor may be configured to: transmit the first image frame to the memory during a first transmission time in response to a rise of a first timing signal, and transmit the second image frame to the memory during a second transmission time in response to a rise of a second timing signal. The second transmission time may be different from the first transmission time.

[0232] According to an embodiment, at least one processor may be configured to: send the first image frame to the memory at a first operating speed during a first sending time, and send the second image frame to the memory at a second operating speed during a second sending time. The second operating speed may be different from the first operating speed.

[0233] According to an embodiment, the at least one processor may be configured to transmit first control information for changing a rising timing of the first timing signal to the display controller based on the identified state of the electronic device.

[0234] According to an embodiment, the first control information may include information about a change time for changing a rising timing of the first timing signal.

[0235] According to an embodiment, the display controller may be configured to: Figure 3 VSYNC signal 301) sends at least one of the first image frame or the second image frame stored in the memory to the display.

[0236] According to an embodiment, the display controller can be configured to: based on the rise of the synchronization signal, read at least one of the first image frame or the second image frame received from at least one processor and stored from the memory, and send at least one of the first image frame or the second image frame to the display.

[0237] According to an embodiment, the at least one processor may be configured to transmit second control information for changing an interval of the synchronization signal to the display controller.

[0238] According to an embodiment, the display controller may be configured to change a rising timing of the first timing signal relative to the synchronization signal based on the first control information, and transmit a second timing signal having the changed rising timing to the at least one processor.

[0239] According to an embodiment, the display controller may be configured to change the rising timing of the first timing signal within a period range of the synchronization signal.

[0240] According to an embodiment, the state of the electronic device may include at least one of the type of executed application, the content of the displayed execution screen, the type of received user input, or the temperature of the electronic device.

[0241] According to an embodiment, a method for controlling an electronic device includes: transmitting a first image frame to be output through a display of the electronic device to a memory of the electronic device based on a first timing signal received from a display controller of the electronic device; identifying a state of the electronic device; transmitting first control information for changing the timing of the first timing signal to the display controller of the electronic device based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to transmitting the first control information for changing the timing of the first timing signal; and transmitting a second image frame to be output through the display to the memory based on the received second timing signal. The timing of the second timing signal may be different from the timing of the first timing signal.

[0242] According to an embodiment, transmitting the first image frame based on the first timing signal may include transmitting the first image frame to the memory during a first transmission time in response to a rising edge of the first timing signal, and transmitting the second image frame based on the second timing signal may include transmitting the second image frame to the memory during a second transmission time in response to a rising edge of the second timing signal. The second transmission time may be different from the first transmission time.

[0243] According to an embodiment, transmitting the first image frame during the first transmission time may include transmitting the first image frame to the memory at a first operating speed during the first transmission time. Transmitting the second image frame during the second transmission time may include transmitting the second image frame to the memory at a second operating speed during the second transmission time. The second operating speed may be different from the first operating speed.

[0244] According to an embodiment, transmitting the first control information for changing the timing of the first timing signal based on the identified state of the electronic device may include transmitting the first control information for changing the rising timing of the first timing signal to the display controller based on the identified state of the electronic device.

[0245] According to an embodiment, the first control information may include information about a change time for changing a rising timing of the first timing signal.

[0246] According to an embodiment, the method may further include transmitting, by the display controller, at least one of the first image frame or the second image frame stored in the memory to the display based on the synchronization signal.

[0247] According to an embodiment, the method may further include transmitting second control information for changing an interval of the synchronization signal to the display controller.

[0248] According to an embodiment, the method may further include: changing, by the display controller, a rising timing of the first timing signal relative to the synchronization signal based on the received first control information; and sending, by the display controller, a second timing signal having the changed rising timing to at least one processor.

[0249] According to an embodiment, a computer-readable non-volatile recording medium is provided, which stores instructions configured to, when executed, cause at least one processor of an electronic device to execute the following: transmitting a first image frame to be output through a display of the electronic device to a memory of the electronic device based on a first timing signal received from a display controller of the electronic device; identifying a state of the electronic device; transmitting first control information for changing the timing of the first timing signal to the display controller of the electronic device based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to transmitting the first control information for changing the timing of the first timing signal; and transmitting a second image frame to be output through the display to the memory based on the received second timing signal. The timing of the second timing signal may be different from the timing of the first timing signal.

[0250] The electronic device according to various embodiments may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a household appliance. According to an embodiment of the present disclosure, the electronic device is not limited to those described above.

[0251] It should be understood that the various embodiments of the present disclosure and the terms used therein are not intended to limit the technical features set forth herein to specific embodiments, but include various changes, equivalents or replacement forms for corresponding embodiments. For the description of the accompanying drawings, similar figure numerals can be used to refer to similar or related elements. It will be understood that the noun in the singular form corresponding to the term can include one or more things, unless the relevant context clearly indicates otherwise. As used herein, each phrase in the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" can include all possible combinations of the items listed together with the corresponding phrases in the multiple phrases. As used herein, terms such as "the 1st" and "the 2nd" or "first" and "second" can be used to simply distinguish corresponding parts from another part, and do not limit the parts in other aspects (for example, importance or order). It will be understood that if an element (e.g., a first element) is referred to as being “coupled with another element (e.g., a second element)”, “coupled to another element (e.g., a second element)”, “connected with another element (e.g., a second element)”, or “connected to another element (e.g., a second element)”, whether or not the terms “operably” or “communicatively” are used, it means that the element can be directly (e.g., wired) connected to the other element, wirelessly connected to the other element, or connected to the other element via a third element.

[0252] As used herein, the term "module" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms (e.g., "logic," "logic block," "part," or "circuit"). A module may be a single integrated component adapted to perform one or more functions or the smallest unit or part of the single integrated component. For example, depending on an embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0253] The various embodiments described herein can be implemented as software (e.g., program 140) comprising one or more instructions stored in a storage medium (e.g., internal memory 136 or external memory 138) that can be read by a machine (e.g., electronic device 101). For example, a processor (e.g., processor 120) of a machine (e.g., electronic device 101) can call at least one of the one or more instructions stored in the storage medium and execute the at least one instruction under the control of the processor with or without the use of one or more other components. This enables the machine to be operable to perform at least one function according to the called at least one instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The machine-readable storage medium can be provided in the form of a non-transitory storage medium. The term "non-transitory" only means that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but the term does not distinguish between data being semi-permanently stored in the storage medium and data being temporarily stored in the storage medium.

[0254] According to an embodiment, the method according to various embodiments of the present disclosure may be included and provided in a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be released in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or may be downloaded via an application store (e.g., the Play Store). TM ) The computer program product may be published online (e.g., downloaded or uploaded) or may be published (e.g., downloaded or uploaded) directly between two user devices (e.g., smartphones). If published online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium (e.g., a memory of a manufacturer's server, an application store's server, or a relay server).

[0255] According to an embodiment, each component (for example, module or program) in the above-mentioned components can include single entity or multiple entities. According to an embodiment, one or more components in the above-mentioned components can be omitted, or one or more other components can be added. Alternatively or additionally, multiple components (for example, module or program) can be integrated into a single component. In this case, according to various embodiments, the integrated component can still perform the one or more functions of each component in the multiple components in the same or similar manner as a corresponding component in the multiple components before integration. According to an embodiment, the operation performed by module, program or another component can be performed sequentially, in parallel, repeatedly or in a heuristic manner, or one or more operations in the operation can be performed or omitted in different orders, or one or more other operations can be added.

[0256] Certain aspects of the above-described embodiments of the present disclosure can be implemented in hardware, firmware, or via software or computer code that can be stored in a recording medium such as a CD-ROM, a digital versatile disk (DVD), a magnetic tape, a RAM, a floppy disk, a hard disk, or a magneto-optical disk, or by the execution of computer code that is initially stored on a remote recording medium or a non-transitory machine-readable medium and downloaded via a network and to be stored on a local recording medium, so that the methods described herein can be presented using a general-purpose computer or a special processor via such software stored on a recording medium or in programmable or dedicated hardware such as an ASIC or FPGA. As will be understood in the prior art, a computer, processor, microprocessor controller, or programmable hardware includes memory components such as RAM, ROM, flash memory, etc., which can store or receive software or computer code that implements the processing methods described herein when accessed and executed by the computer, processor, or hardware.

[0257] While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. An electronic device, comprising: at least one processor; monitor; a memory configured to store image frames received from the at least one processor; as well as a display controller configured to output the image frames stored in the memory through the display, Wherein, the at least one processor is configured to: transmitting a first image frame to be output through the display to the memory based on a first timing signal received from the display controller, wherein the display controller is configured to transmit the image frame data stored in the memory to the display based on a synchronization signal, wherein the first timing signal is synchronized with the synchronization signal; identifying a status of the electronic device; transmitting first control information for changing a rising timing of the first timing signal to the display controller based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to transmitting the first control information for changing the rising timing of the first timing signal; and sending a second image frame to be output through the display to the memory based on the received second timing signal, The second timing signal is asynchronous with the synchronization signal.

2. The electronic device according to claim 1, wherein The at least one processor is further configured to: transmitting the first image frame to the memory during a first transmission time in response to a rising edge of the first timing signal; and transmitting the second image frame to the memory during a second transmission time in response to a rise of the second timing signal, The second sending time is different from the first sending time.

3. The electronic device according to claim 2, wherein The at least one processor is further configured to: sending the first image frame to the memory at a first operating speed during the first sending time; as well as sending the second image frame to the memory at a second operating speed during the second sending time, The second operating speed is different from the first operating speed.

4. The electronic device according to claim 1, wherein The first control information includes information on a change time for changing a rising timing of the first timing signal.

5. The electronic device according to claim 1, wherein The display controller is further configured to transmit the first image frame and / or the second image frame stored in the memory to the display based on the synchronization signal. The electronic device according to claim 5 , wherein: The display controller is further configured to: read the first image frame and / or the second image frame received and stored from the at least one processor from the memory and send the first image frame and / or the second image frame received and stored from the at least one processor to the display based on the rising timing of the synchronization signal.

7. The electronic device according to claim 5, wherein: The at least one processor is further configured to send second control information for changing an interval of the synchronization signal to the display controller.

8. The electronic device according to claim 1, wherein The display controller is further configured to change the rising timing of the first timing signal within a period range of the synchronization signal.

9. The electronic device according to claim 1, wherein: The state of the electronic device includes a type of executed application, content of a displayed execution screen, a type of received user input, and / or a temperature of the electronic device.

10. A method for controlling an electronic device by using at least one processor of the electronic device, the method comprising: transmitting, to a memory of the electronic device, a first image frame to be output through a display of the electronic device based on a first timing signal received from a display controller of the electronic device, wherein the display controller is configured to transmit image frame data stored in the memory to the display based on a synchronization signal, wherein the first timing signal is synchronized with the synchronization signal; identifying a status of the electronic device; transmitting first control information for changing a rising timing of the first timing signal to a display controller of the electronic device based on the identified state of the electronic device; receiving a second timing signal from the display controller in response to transmitting the first control information for changing the rising timing of the first timing signal; and sending a second image frame to be output through the display to the memory based on the received second timing signal, The second timing signal is asynchronous with the synchronization signal.

11. The method according to claim 10, in, Sending the first image frame based on the first timing signal further comprises: transmitting the first image frame to the memory during a first transmission time in response to a rising edge of the first timing signal, The sending of the second image frame based on the second timing signal further includes: transmitting the second image frame to the memory during a second transmission time in response to a rising edge of the second timing signal, and The second sending time is different from the first sending time.

12. The method according to claim 11, in, Transmitting the first image frame during the first transmission time further comprises: sending the first image frame to the memory at a first operating speed during the first sending time, The sending of the second image frame during the second sending time further comprises: sending the second image frame to the memory at a second operating speed during the second sending time, and The second operating speed is different from the first operating speed.

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