Scan chain circuits and their corresponding implementation methods

Abstract

Embodiments of this disclosure relate to scan chain circuits and corresponding implementation methods. The present invention relates to a scan chain circuit including cascaded flip-flops having functional input nodes and test input nodes, the test input nodes being configured to selectively couple to logic circuitry at clock edge times. A clock line is provided, configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have an active clock edge applied to them at a corresponding clock edge time. The flip-flop chain includes a set of flip-flops configured to receive an edge-inverted signal and selectively invert their active clock edges in response to an assertion of the edge-inverted signal.

Description

Technical Field

[0001] This document relates to screening techniques used in semiconductor devices.

[0002] One or more embodiments can be advantageously (but not limited to) applied to semiconductor devices intended for use in the automotive industry, where automotive system manufacturers want component suppliers to ship components at 0 ppm, i.e., devices with zero failures per million units. Background Technology

[0003] Aging and high-voltage dynamic voltage stress (HVST) are commonly used to screen for “infant” mortality in semiconductor devices.

[0004] A common approach is based on a scanning architecture, which helps to apply stress to various internal nodes of the device.

[0005] Scan chains may face issues related to high-pressure operation, as such architectures can be sensitive to violations of "hold" timing.

[0006] These violations may not be easily identified or corrected. This can lead to potentially high area penalties: these violations may actually correspond to stress conditions outside the functional scope specified by the standard. If this occurs, the corresponding library cannot be characterized, which affects accurate analysis. Summary of the Invention

[0007] According to one or more embodiments, a circuit is provided.

[0008] A scan chain architecture can be an example of such a circuit.

[0009] One or more embodiments may involve corresponding methods.

[0010] The scanning method, where the sampling edge of a continuous flip-flop (FF) can be set according to the logic value, can be an example of this approach.

[0011] One or more embodiments may include clock inversion logic applied to the FF.

[0012] One or more embodiments may include a trigger having pins configured to hold or invert the sampling edge.

[0013] This facilitates a solution that eliminates the need for custom flip-flops by simply adding (external) clock inversion logic to the flip-flop.

[0014] For example, one or more embodiments may involve adding a pin (e.g., "CKT") on each flip-flop, each flip-flop being configured to hold or invert the sampling edge of a successive flip-flop based on the logic value present at that pin. Attached Figure Description

[0015] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0016] Figure 1 This is an exemplary block diagram of a conventional scan chain architecture;

[0017] Figure 2 These are examples of time-plotted representations of the possible temporal behavior of a specific signal, which may occur in situations such as... Figure 1 In the scan chain architecture shown;

[0018] Figure 3 This is an exemplary block diagram of a scan chain architecture according to an embodiment of the present description;

[0019] Figure 4 Is it like this? Figure 3 Exemplary circuit diagrams showing possible details of the scan unit architecture; and

[0020] Figure 5 yes Figure 4 An exemplary transistor-level representation of certain details. Detailed Implementation

[0021] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more of these specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in order not to obscure certain aspects of the embodiments.

[0022] Within the framework of this description, references to "embodiment" or "one embodiment" are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0023] Furthermore, specific conformations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0024] As mentioned earlier, while representing a method often used to screen for “infant” mortality in semiconductor devices, stress testing at high supply voltages is affected by the fact that the device being tested is not designed to operate under such extreme conditions.

[0025] Therefore, when the device under test exceeds its functional specifications, aging under high voltage (HVST) and dynamic voltage stress (DVS) become crucial.

[0026] In fact, the basic principle behind this approach is that when a stress voltage higher than the specification is applied, the increased applied voltage leads to a shorter duration (and a reduction in test costs). However, operating the circuitry under such "out-of-range" conditions can have undesirable effects on design complexity (e.g., timing angles may not be achievable) and area overhead.

[0027] like Figure 1 The scan chain indicated as 10 is typically used to detect potential faults / defects in the logic chain (CL) of electronic circuits (combinatorial) (not visible for simplicity).

[0028] Automated Test Pattern Generation (ATPG) helps generate stimulus test patterns by (actually) using techniques such as aging under high voltage and dynamic voltage stress (HVST) stimulation (in short, HVST) to stimulate and verify all manufacturing defects / faults present in the logic CL.

[0029] Automated Test Pattern Generation (ATPG) helps generate stimulus test patterns by (in effect) using techniques (e.g., among the various techniques used to facilitate the achievement of desired ppm performance) to stimulate and verify manufacturing defects / faults, aging under high voltage, and dynamic voltage stress (in short, HVST) at all nodes present in the logic CL.

[0030] As is commonly understood by those skilled in the art, such as Figure 1 The basic purpose of the architecture of scan chain 10 shown is to detect faults in the logic CL, including both combinational and sequential (flip-flops), as well as faults in the clock tree. Flip-flops are implicitly overridden (they can be detected implicitly unless the scan chain cannot be shifted), and combinational logic is tested due to the generated patterns.

[0031] like Figure 1 The scan chain 10 shown includes a set of cascaded scan triggers 101, 102, 103, 104, 105 and 106, which are clocked by a clock signal applied to the CK node of the triggers via a line clock.

[0032] This clock signal can be generated via control circuit S in a manner known to those skilled in the art.

[0033] Although six triggers are illustrated here for ease of explanation, scan chain 10 can actually include different numbers, and in fact, any number of triggers.

[0034] Furthermore, for simplicity and ease of understanding, flip-flops belonging to the same clock domain (i.e., sharing a single clock signal) will always be considered; in fact, the discussion in this paper can be applied to scan chains that operate using different clock signals / operating in different clock domains.

[0035] In the current implementation, as shown in this paper, the scan trigger has a multiplexer M at its internal input.

[0036] The test enable signal applied to the test enable node TE of the flip-flop (generated in a manner known to those skilled in the art, for example via control circuit S—the relevant connections are not visible for simplicity) determines whether the D (function) input or TI (test) input reaches the output Q of the flip-flop when the activation clock edge reaches CK.

[0037] In a full scan arrangement, all flip-flops in the logic CL are replaced with scan flip-flops.

[0038] They are connected together in the form of a scan chain, which acts as a shift register when the design is in shift test mode (i.e., the test enable signal TE is asserted). The first flip-flop in the scan chain is connected to the scan input, and the last flip-flop in the scan chain is connected to the scan output.

[0039] The scan chain operation can be viewed as involving three phases: scan input (this is the scan_in shift mode phase, where the FFs in the chain are serially loaded via the scan input pin), capture (the design remains in functional timing mode, and the test mode response is captured), and scan output (this is the scan-out shift mode phase, where the FFs in the chain are unloaded via the scan output pin; the scan input phase can occur simultaneously).

[0040] Note that in a so-called "partial scan" arrangement, some triggers may not be configured to act as scan triggers. A full scan arrangement helps improve test results for increased complexity.

[0041] The structure and operation of scan chains, as discussed above, are otherwise standard practice in the field. For further details, see S. Sharma's "Scan Chains: PnR Outlook" (see design-reuse.com), which is merely an example. This makes a more detailed description unnecessary here.

[0042] like Figure 1As shown, a problem related to the operation of scan chain 10 is that, for example, due to the different physical locations of flip-flops 101 to 106 in the chain, the activation clock edge in the clock signal from the control circuit S may arrive at the clock node CK of each flip-flop 101, 102, 103, 104, 105 with different delays. See, for example, [link to relevant documentation]. Figure 1 The purely exemplary values ​​shown for triggers 102 to 106 are 0ns, 1ns, 3.0ns, 3.1ns, and 4.6ns. In this purely exemplary representation, it is assumed that trigger 101 has a delay of 0ns.

[0043] Similarly, for the same reason, during test mode, signals at the TI (test) input can be received with different delays at D1, D2, D3, D4, and D5 (see, for example, see...). Figure 1 The values ​​indicated by the TI inputs for triggers 102, 103, 104, 105, and 106 are 0.5ns, 1.3ns, 2.1ns, 0.2ns, and 1.2ns, respectively (purely exemplary).

[0044] like Figure 2 As shown, when t setup Interval and t hold The input signals during the interval, when there is no level change before and after reaching the activation clock edge of CK, contribute to the correct operation of the scan chain.

[0045] Figure 2 (This is just an example; see t for reference only.) hold (Possible value equal to 0.2ns) Three possible time behaviors of this signal relative to the time of arrival at the active clock edge of CK.

[0046] Of these three possible temporal behaviors (collectively referred to as data):

[0047] The first action is marked as OK, corresponding to t setup and t hold The expected time behavior is that there is no level transition during the interval;

[0048] The second behavior flag is a setting violation, corresponding to the t of the clock signal. setup Level transitions during the interval; and

[0049] The third behavior is marked as a hold violation, corresponding to the clock signal t. hold Level transitions during the interval.

[0050] Generally speaking (for example, referring to) Figure 1 In a cascaded arrangement, the correct operation of a scan chain for a pair of adjacent flip-flops (10j and 10j+1) can be achieved as follows:

[0051] Ckdel10 j -Ckdel10 j+1 +Dj>t hold

[0052] in:

[0053] Ckdel10j and Ckdel10j+1 indicate the clock delays at flip-flops 10j and 10j+1, respectively.

[0054] Dj is related to Figure 1 The time delay associated with block Dj (j = 1, ..., 5) in the data.

[0055] Figure 1 The reported - purely exemplary - values ​​are examples of situations where a violation could affect triggers 104 and 105, which would affect the correct shift operation of scan chain 10.

[0056] use Figure 1 The reported values ​​are purely exemplary, namely Ckdel104 = 3.0 ns, Ckdel105 = 3.1 ns, and D4 = 0.2 ns, and assume (for example only) t hold =0.2ns, which fails to satisfy the desired relationship, where undesirable hold violations will lead to unsatisfactory operations ( Figure 1 (The thumb is pointing downwards).

[0057] It should be noted that the correlation timing of the signals, as described above, depends on the circuit layout and manufacturing technology and cannot be changed as the pattern is generated.

[0058] A possible solution to correct the (hold) time problem discussed above could involve adding more buffers, such as D1, ..., D5, between the Q node and TI node of the trigger, in addition to adding a node in the Design Rule Check (DRC) to prevent violations, i.e., increasing the delay Dj to satisfy the aforementioned rules.

[0059] The drawback of this solution may be related to its inherent instability.

[0060] In addition, retention analysis may be involved to provide sufficient functionality in predicting voltage and temperature turns (VT turns) used under aging / dynamic voltage stress conditions.

[0061] In most cases, library representation models for these VT corner conditions are unavailable because they exceed the functional specifications.

[0062] Furthermore, if different threshold cell types are used on the data and clock paths, namely Standard Vt (SVT), Low Vt (LVT), and Ultra-Low Vt (ULVT), the corresponding derating factors may differ, which undesirably involves specific analyses.

[0063] Another possible solution to mitigate "hold" violations would involve providing separate outputs for certain consecutive cell elements, such as flip-flops. For example, a functional Q node could be connected only to the functional logic CL, and a scan output node could be connected only to the next test input TI node. Such a scan output driver could be designed with low strength to allow for a signal propagation delay (e.g., 3 ns).

[0064] This will create an infrastructure that is more robust to hold-time failures that may be introduced by high-voltage operation.

[0065] However, the solution is not robust by nature and cannot be verified when VT corner information is unavailable, which carries the risk that potential critical issues may only arise at the semiconductor level (“on silicon”).

[0066] In one or more embodiments, possible hold violations between successive flip-flops in a scan chain such as 10 can be offset by changing the sampling edge of adjacent subsequent (sequential) flip-flops in the scan chain.

[0067] Figure 3 Scan chain 10 of such an embodiment is illustrated.

[0068] Unless the context otherwise indicates, it has been combined Figure 1 The parts or components discussed are all indicated by similar reference numerals in the accompanying drawings, so for the sake of brevity, the corresponding descriptions will not be repeated.

[0069] exist Figure 3 In the scan chain 10, which is used for techniques such as dynamic voltage stress under aging and high voltage (in short, HVST), it again includes a set of cascaded triggers 101, 102, 103, 104, 105 and 106, which are applied to the CK node of the triggers by a clock signal via a line clock.

[0070] Similarly, although six triggers are illustrated for ease of explanation, scan chain 10 can actually contain a different number, in fact, any number of triggers.

[0071] In such Figure 3 In one or more embodiments shown, in order to change the sampling edge of adjacent subsequent (sequential) flip-flops in the scan chain, a node (pin) CKT is added to each flip-flop 101 to 106 in the scan chain 10. The node CKT is configured as follows:

[0072] When in a "0" logic value (user mode), maintain the original clock edge, and

[0073] Invert the edges of triggers such as 101, 103, and 105 when the value is "1" (test mode).

[0074] The latter arrangement is in Figure 3 For example, the figure shows that triggers 101, 103 and 105 have a falling edge at CK, while triggers 102, 104 and 106 maintain a rising edge at CK.

[0075] like Figure 3 As shown, edge inversion occurs in an alternating sequence, for example, starting from the first flip-flop 101 in the chain.

[0076] It is worth noting that:

[0077] In some (otherwise rare) cases, the triggers in scan chain 10 may already have mixed rising / falling edges; and

[0078] In some cases, the triggers in scan chain 10 can be "native" falling edges so that the edge inversion can change from falling to rising when activated.

[0079] For simplicity, the immediate example will involve triggers 101 to 106:

[0080] (All) Rising edge types—generally more common than falling edge types—can therefore be assumed that edge inversion occurs from rising to falling (see triggers 101, 103, and 105), and

[0081] They belong to the same clock domain (i.e., share a single clock signal), while one or more embodiments may involve different clock signals / domains.

[0082] It should be understood that the embodiments are not limited to this exemplary representation and / or any type of trigger, as long as they depend on the possible inversion of the original edge (whether rising or falling).

[0083] like Figure 3 As shown, triggers 101 to 106 can be considered as arranged in pairs, that is:

[0084] 101, 102;

[0085] 102, 103;

[0086] 103, 104;

[0087] 104, 105; and

[0088] 105, 106

[0089] Each pair includes an "upstream" trigger and a "downstream" trigger, wherein one of the triggers in the pair (e.g., the upstream triggers in the pair, here the odd-numbered triggers 101, 103, 105 in the chain) undergoes edge inversion (e.g., rising to falling), while the other trigger in the pair (e.g., the downstream triggers in the pair, here the even-numbered triggers 102, 104, 106 in the chain) does not undergo edge inversion and retains (e.g.) the rising edge at CK.

[0090] Therefore, in edge inversion, adjacent flip-flops in the chain (here 101 and 102, 102 and 103, 103 and 104, 104 and 105, 105 and 106) will have mutually opposite (inverted) sampling edges.

[0091] In such Figure 3 In one or more embodiments shown, the CKT pins of flip-flops 101 to 106 in the scan chain are coupled to line TM, which applies a test mode signal (e.g., generated in control circuit S) to enable (enable only) during high-voltage manufacturing testing. It should be noted that such a signal can be both static and dynamic (i.e., always active during capture or non-capture, and during shift).

[0092] It is important to note that the line TM is typically different from the test enable (TE) input of a flip-flop, which goes high in capture mode when a shift is performed.

[0093] This helps to set the line TM to a stable active mode during aging HVST, activates the test enable (TE) input of the trigger during shift (high), and deactivates it during capture (low).

[0094] Additionally, it should be noted that under certain conditions, line TM can remain low during capture during the aging process.

[0095] Figure 3 The representation shows the input CKT of the odd-numbered flip-flops 101, 103, and 105 (edge-inverted) coupled to line TM and the input CKT of the even-numbered flip-flops 102, 104, and 106 (no-edge-inverted) coupled to ground.

[0096] It should be understood that this representation is merely for ease of description, provided that all flip-flops 101 to 106 (as discussed below) can be coupled to line TM and configured to provide or not provide edge inversion based on logic signal processing.

[0097] like Figure 3As shown, not all flip-flops in scan chain 10 are connected to line TM to allow for alternating clock edges (e.g., falling, rising, falling, rising, falling, rising). As the example shows, this can be achieved simply by connecting every other flip-flop in the chain (e.g., one flip-flop out of every two flip-flops or by alternating between flip-flops) to TM or GND.

[0098] Otherwise, it will be understood that in the presence of a trigger of the "native" falling edge type (e.g., 103), the node CKT at that trigger can be considered connected to GND, provided that the edge out-of-phase rule between adjacent triggers (in the exemplary case under consideration, with respect to triggers 102 and 104) has been observed even when not connected to CKT.

[0099] Therefore, one or more embodiments rely on the understanding that, as discussed above, an inverted edge provides a half-clock cycle margin.

[0100] exist Figure 1 In the conventional solution shown, the clock signals to flip-flops 101 through 106 are all "aligned" (see...). Figure 1 The rising edge at CK (in the middle) leads to the relationship described above.

[0101] Ckdel10 j -Ckdel10 j+1 +Dj>t hold .

[0102] In contrast, due to the combination of the above... Figure 3 As mentioned above, the edges are out of phase, therefore a new rule applies, namely:

[0103] Ckdel10 j +D j <Ckhalfperiod+Ckdel10 j+1 +t setup

[0104] Among them, again:

[0105] Ckdel10j and Ckdel10j+1 indicate the clock delay of a pair of adjacent flip-flops 10j and 10j+1, respectively.

[0106] Dj is the relevant time delay (j = 1, ..., 5), and

[0107] Ckhalfperiod represents half a cycle of a clock signal.

[0108] This relationship indicates that, as described above, the inverting edge provides a margin of half a clock cycle, by potentially reducing thold The problem (at most) transforms into a setup issue that is less detrimental to normal operation, which helps to avoid maintaining violations (for example, see...). Figure 2 (The third figure in the text).

[0109] In fact, to accommodate the two values ​​of Dj and / or Ckdel10j and Ckdel10j+1 to (further) facilitate correct shift operations, CKhalfperiod (clock frequency reduction) can be increased.

[0110] As mentioned earlier, this edge inversion can be integrated into flip-flops such as 101 to 106 (e.g. Figure 3 As shown, the input CKT of the trigger is alternately coupled to line TM and ground, or added as an external function.

[0111] Figure 4 Here are examples of possible implementations of a library of trigger cells for general-purpose triggers 10j (j = 0, 1, ..., 6), such as... Figure 3 As shown, EX-OR logic 20 is used on the clock input to invert the clock edge with a small area overhead.

[0112] exist Figure 4 In the circuit diagram, LM and LS represent (conventionally) latch master circuit devices and latch slave circuit devices that provide Q outputs for each flip-flop (e.g., via logic inverters).

[0113] Similarly, Figure 4 The diagram shows a conventional arrangement for providing signals derived from the TE, D, and TI inputs of flip-flop 10j to the latch main circuit device LM.

[0114] exist Figure 4 In one possible implementation, the EX-OR gate 20 receives signals on its input clock (CK) and TM (CKT) lines and provides an output signal CK1, which (after logic inversion of the logic inverter 30) provides the clock signal CK2. Signal CK2 can be applied together with CK1 to both the latch master circuit device LM and the latch slave circuit device LS to provide the desired Q output for each flip-flop.

[0115] Figure 5 This is a transistor-level representation of a possible implementation of the EX-OR circuit device 20, including three pairs of electronic switches, such as MOSFET transistors 31, 32; 41, 42; and 51, 52.

[0116] like Figure 5 As shown, transistors 31 and 32 in the first pair:

[0117] Including complementary (p- and n-type) MOSFET transistors, through which the current path (source and drain in the case of field-effect transistors such as MOSFETs) passes via resistor R SS (referred to as V+) are cascaded together in the current flow line between power node V+ and ground, with an intermediate node A between transistors 31 and 32; and

[0118] Its control node (the gate in the case of a field-effect transistor such as a MOSFET) is coupled to the input node CKT to alternately turn on (conduct) and off (not conduct) according to the signal at node CKT.

[0119] like Figure 5 As shown, transistors 41 and 42 in the second pair:

[0120] This includes complementary (p- and n-) MOSFET transistors cascaded together via current paths (source and drain in the case of field-effect transistors, such as MOSFETs) in the current flow lines between the input node CKT and node A between transistors 31 and 32, wherein the intermediate node B between transistors 41 and 42 (and also between transistors 51 and 52) provides the signal CK1; and

[0121] Its control node (the gate in the case of a field-effect transistor such as a MOSFET) is coupled to the input node CK to turn on (make it conduct) and off (make it deconduct) according to the signals at nodes CK and CKT: for example, when CKT=1, CK can enable (make it conduct) one of the two transistors 41 and 42; when CKT=0, neither of the two transistors can be enabled, regardless of the logic value of CK.

[0122] like Figure 5 As shown, transistors 51 and 52 in the third pair:

[0123] This includes complementary (p- and n-) MOSFET transistors, through which current paths are arranged in parallel between node CK and node B between transistors 41 and 42 (source and drain in the case of field-effect transistors such as MOSFET transistors); and

[0124] Its control node (the gate in the case of a field-effect transistor such as a MOSFET transistor) is coupled to the input node CKT (transistor 51) and node A between transistors 31 and 32 (transistor 52).

[0125] Figure 4 and Figure 5The schematic diagrams are examples of possible implementations of reduced area overhead advantageously associated with the EXOR structure. Otherwise, those skilled in the art will readily understand that these implementations are merely exemplary and not limiting of the embodiments.

[0126] One or more embodiments illustrated herein can advantageously provide a flexible solution that helps to:

[0127] Prevent potential holding violations (primarily by simply reducing the frequency of gear shifts);

[0128] Optimize area overhead and reduce timing impact on specific flip-flop clock designs; and

[0129] By simply adding clock inversion logic (potentially outside of the flip-flop architecture), a solution is provided that also applies to designs without a custom flip-flop structure.

[0130] In the latter aspect, optimize the trigger structure that embeds EXOR logic (such as...). Figure 4 and Figure 5 As shown (by way of possible examples only), or adding EXOR logic outside the trigger (thus avoiding the use of a custom trigger), are both viable options.

[0131] Furthermore, one or more embodiments illustrated herein may advantageously provide fault coverage of the added CKT signal during ATPG manufacturing testing.

[0132] One or more embodiments illustrated herein can effectively address the problem associated with the fact that voltage stress can present a challenge whenever the circuit (logic) being screened is forced to operate (well) above its functional specifications.

[0133] It is worth noting that conventional scanning methods currently used to stress devices under such extreme conditions may have drawbacks related to the fact that the scanning architecture relies on maintaining timing to facilitate proper shifting operations (which is critical) and consumes area.

[0134] One or more embodiments help to overcome this limitation under these extreme conditions by appropriate shifting operations, thereby reducing area overhead.

[0135] In short, a circuit as illustrated herein (e.g., 10) may include:

[0136] A scan chain of cascaded flip-flops (e.g., 101, 102, 103, 104, 105, 106), wherein the flip-flops in the chain have functional input nodes (D) and test input nodes (TI), configured to operate at clock edge time (e.g., see [link]). Figure 2 t in setup, t hold Selectively coupled (e.g., via a multiplexer M driven by a test enable signal applied to the test enable node TE) to a logic circuit device (e.g., CL) (flip-flops in this chain are configured to selectively couple the functional input node (D) and the test input node (TI) to the logic circuit (CL) at clock edge time (t) setup , t hold (triggered by the clock edge); and

[0137] A clock circuit device (e.g., a line designated as a clock in the figure) is configured to distribute at least one clock signal (as described, one or more embodiments may include different clocks) to a flip-flop in a chain, wherein the flip-flop in the chain has an active clock edge (CK) applied to the flip-flop at the corresponding clock edge time.

[0138] In the circuit shown herein, the flip-flops in the chain may include a set of flip-flops (e.g., 101, 103, 105) configured to receive an edge-inverted signal (e.g., TM) and selectively invert the active clock edge in response to the edge-inverted signal being asserted.

[0139] In the circuit shown herein, the set of flip-flops may consist of non-adjacent flip-flops in a chain (e.g., 101, 103, and 105).

[0140] In the circuit shown herein, the set of flip-flops may consist of alternating flip-flops (e.g., flip-flops 101, 103, and 105) in a chain, wherein each flip-flop in the set has one or two adjacent flip-flops in the chain, the chain being configured to maintain the active clock edge regardless of whether the edge inverted signal is asserted.

[0141] For example, as shown in this article:

[0142] The edge-inverting flip-flop 101 has an edge-holding flip-flop 102 adjacent to it;

[0143] The edge-inverting flip-flop 103 has adjacent edge-holding flip-flops 102 and 104; and

[0144] The edge-inverting flip-flop 105 has adjacent edge-sustaining flip-flops 104 and 106.

[0145] In the circuits shown herein, the flip-flops in the group (e.g., 101, 103, 105) include logic circuitry configured to receive the edge-inverted signal and invert the sampled edge in response to an assertion of the edge-inverted signal.

[0146] In the circuits shown herein, the logic circuit device may include an EX-OR logic circuit device.

[0147] In a "normal" trigger, this EX-OR circuit can be replaced by an inverter.

[0148] The methods described herein may include:

[0149] At the clock edge time (see, for example, Figure 2 t in setup , t hold The input node selected from the functional input nodes (e.g., D) and test input nodes (e.g., TI) of the cascaded flip-flops scan chain (e.g., 101, 102, 103, 104, 105, 106) is coupled to a logic circuit device (e.g., CL) via a test enable signal applied to the test enable node TE, for example, through a multiplexer M; and

[0150] At least one clock signal (as described, one or more embodiments may include different clocks) is assigned to a flip-flop in the chain, wherein the flip-flops in the chain have an activation clock edge applied to the flip-flop at their respective clock edge times.

[0151] Methods illustrated herein may include applying an edge-inverted signal (e.g., TM) to a set of flip-flops (e.g., 101, 103, 105) in the chain to selectively invert the active clock edge applied thereon.

[0152] Advantageously, during high-voltage and / or temperature testing of the logic circuit device (e.g., CL) (e.g., during aging and dynamic voltage stress at high voltage - HVST), the edge-inverting signal can be applied to the set of triggers in the chain.

[0153] The methods illustrated herein may include reducing the frequency of at least one clock signal (e.g., a clock) distributed to flip-flops in a chain, the edge-inverting signal being applied to the group of flip-flops in the chain.

[0154] As mentioned earlier, when an inverted edge signal is applied to these flip-flops, reducing the frequency of the clock signal (i.e., increasing ckhalfperiod) helps to adjust the two values ​​of Ckdel10j and Ckdel10j+1 in Dj and / or the following relationship:

[0155] Ckdel10 j +D j <Ckhalfperiod+Ckdel10 j+1 +t setup

[0156] As mentioned earlier, this will result in the correct shift operation.

[0157] The method illustrated herein may include applying the edge-inverted signal to a set of non-adjacent flip-flops in the chain (101, 103, 105) (e.g., 101, 103, and 105 in 101, 102, 103, 104, 105, 106).

[0158] The method described herein may include applying the edge-inverted signal to a set of alternating flip-flops in a chain, wherein each flip-flop in the set (101, 103, 105) has one or two adjacent flip-flops in the chain, configured to maintain the active clock edge (e.g., Figure 3 (As shown in the diagram, coupled to ground).

[0159] In other words, as shown in this article:

[0160] The edge-inverting flip-flop 101 has an edge-holding flip-flop 102 adjacent to it;

[0161] The edge-inverting flip-flop 103 has adjacent edge-holding flip-flops 102 and 104; and

[0162] The edge-inverting flip-flop 105 has adjacent edge-sustaining flip-flops 104 and 106.

[0163] Without prejudice to the fundamental principles, details and embodiments may vary only as described by way of example, without departing from the scope of protection.

[0164] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An electronic circuit, comprising: A scan chain includes multiple flip-flops cascaded in the chain, each of the multiple flip-flops having a corresponding functional input node and a corresponding test input node, each of the multiple flip-flops being configured to selectively couple the corresponding functional input node or the corresponding test input node to a logic circuit device, and each of the multiple flip-flops being triggered by a clock edge at a clock edge time. as well as A clock circuit arrangement is configured to output at least one clock signal to the plurality of flip-flops, wherein an activation clock edge is applied to the plurality of flip-flops at a corresponding clock edge time. The plurality of triggers includes a trigger set, which is configured as follows: Receive the inverted edge signal; as well as In response to the assertion of the edge inverted signal, the active clock edge is selectively inverted.

2. The electronic circuit of claim 1, wherein the set of triggers comprises triggers that are not adjacent to each other in the chain.

3. The electronic circuit of claim 1, wherein the set of triggers comprises every other trigger in the chain of a plurality of triggers, wherein each trigger in the set of triggers has one or two adjacent triggers in the chain, and wherein the trigger in the one or two adjacent triggers is configured to maintain the active clock edge non-inverted, regardless of whether the edge inverted signal is asserted.

4. The electronic circuit of claim 1, wherein the triggers in the set of triggers include logic circuitry configured to receive the edge-inverted signal and, in response to an assertion of the edge-inverted signal, invert the sampling edge of the active clock edge.

5. The electronic circuit according to claim 4, wherein the logic circuit device includes XOR logic.

6. The electronic circuit of claim 1, wherein the set of triggers is configured to receive the edge-inverted signal during high-voltage and / or temperature testing of the logic circuit device.

7. The electronic circuit of claim 1, wherein the frequency of the at least one clock signal is reduced in response to providing the edge-inverting signal to the set of flip-flops.

8. A method for scanning an electronic device, comprising: At the clock edge time, the logic circuit device is coupled to the corresponding functional input node or corresponding test input node of the flip-flops in a plurality of flip-flops, which are cascaded in a scan chain; At least one clock signal is output to the plurality of flip-flops, wherein an activation clock edge is applied to the plurality of flip-flops at the corresponding clock edge time; as well as An edge-inverting signal is provided to the set of flip-flops in the plurality of flip-flops to selectively invert the active clock edge applied to the set of flip-flops.

9. The method of claim 8, comprising: During high-voltage and / or temperature testing of the logic circuit device, the edge-inverted signal is provided to the set of triggers.

10. The method of claim 8, comprising: In response to providing the edge-inverting signal to the set of triggers, the frequency of the at least one clock signal is reduced.

11. The method of claim 8, wherein the set of triggers is a non-adjacent set of the plurality of triggers in the chain.

12. The method of claim 8, wherein the set of triggers comprises every other trigger among the plurality of triggers in the chain, and wherein each trigger in the set of triggers has one or two adjacent triggers in the chain, the one or two adjacent triggers being configured to maintain the active clock edge from being inverted.

13. The method of claim 8, wherein the logic circuit device comprises XOR logic.

14. An electronic system comprising: Logic circuit devices; A scan chain includes multiple flip-flops cascaded in the chain, each of the multiple flip-flops having a corresponding functional input node and a corresponding test input node, the functional input node and the test input node being configured to be selectively coupled to the logic circuit device at clock edge time; as well as A clock circuit arrangement is configured to output at least one clock signal to the plurality of flip-flops, wherein an activation clock edge is applied to the plurality of flip-flops at a corresponding clock edge time. The plurality of triggers includes a trigger set, which is configured as follows: Receive the inverted edge signal; as well as In response to the assertion of the edge inverted signal, the active clock edge is selectively inverted.

15. The electronic system of claim 14, wherein the set of triggers comprises triggers that are not adjacent to each other in the chain.

16. The electronic system of claim 14, wherein the set of triggers includes every other trigger among the plurality of triggers in the chain, wherein each trigger in the set of triggers has one or two adjacent triggers in the chain, and wherein the trigger among the one or two adjacent triggers is configured to maintain the active clock edge non-inverted regardless of whether the edge inverted signal is asserted.

17. The electronic system of claim 14, wherein the triggers in the set of triggers include logic circuitry configured to receive the edge-inverted signal and, in response to an assertion of the edge-inverted signal, invert the sampling edge of the active clock edge.

18. The electronic system of claim 17, wherein the logic circuit device comprises XOR logic.

19. The electronic system of claim 14, wherein the set of triggers is configured to receive the edge-inverted signal during high-voltage and / or temperature testing of the logic circuit device.

20. The electronic system of claim 14, wherein in response to the inverted edge signal being provided to the set of triggers, the frequency of the at least one clock signal is reduced.

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