Electronic device and method for using its storage space

Abstract

Various embodiments disclose an electronic device and a method of using its storage space. The electronic device includes: a storage device including a non-volatile memory, a storage device controller, and a storage interface, the non-volatile memory including a buffer space and a storage space; and a processor. According to various embodiments, the processor may be configured to perform control to: determine whether the storage device supports a high-speed data storage mode using the buffer space of the non-volatile memory of the storage device; based on the storage device supporting the high-speed data storage mode, activate a function of writing data buffered in the buffer space of the non-volatile memory into the storage space of the non-volatile memory by operating the storage interface in a first state; and based on no request for the storage device being generated during a predetermined period while operating the storage interface in a second state, transition the storage interface of the storage device to the first state.

Description

[0001] This application is a divisional application of a Chinese invention patent with an application date of June 3, 2020, an application number of 202010493211.9, and an invention title of "Electronic Device and Method for Utilizing Its Storage Space". Technical Field

[0002] The present disclosure relates to an electronic device and a method for utilizing its storage space, and for example, relates to an electronic device capable of writing data into its storage device in a high-speed data storage mode and a method for utilizing its storage space. Background Art

[0003] In order to enable a portable terminal to store a large amount of data, it is preferable to use a high-density data storage scheme.

[0004] Although a high-density data storage scheme enables an electronic device to store a larger amount of data in its storage device compared to a low-density data storage scheme, it may have the disadvantage of a relatively slow data storage speed. At the same time, the latest progress in high-speed data transfer technology has promoted the development of technologies for quickly storing transferred data.

[0005] The data writing speed can be improved in a high-speed data storage mode, in which a part of the storage space is allocated as a buffer space so that data is buffered in the buffer space in a low-density data storage mode and then written into the storage space in a high-density data storage mode. In the case where the storage device autonomously performs an operation of writing the data buffered in the buffer space into the storage space, the processor of the electronic device cannot check the progress status of the writing operation and the current consumption caused by the writing operation, which results in deterioration of the performance of the electronic device.

[0006] In the case of performing an operation of writing the data buffered in the buffer space into the storage space in a high-density data storage mode with a buffer space of a specific size, the writing operation is suspended until a specific size of the buffer space is secured, which results in a reduction in the available capacity of the buffer space and the storage space of the storage device.

[0007] If an operation of writing the data buffered in the buffer space into the storage space in a high-density data storage mode is performed in the middle of storing data in response to a new data write input / output request, this may deteriorate the performance of processing the new data write input / output request. Summary of the Invention

[0008] Embodiments of the present disclosure provide an electronic device, including: a memory including a memory device controller, a memory interface, and a non-volatile memory including a buffer space and a storage space; and a processor coupled to the memory via the memory interface, the processor being configured to perform control to: use the buffer space of the non-volatile memory of the memory to determine whether the memory supports a high-speed data storage mode, and if the memory supports the high-speed data storage mode, send a first control command to the memory to activate the memory device controller to automatically perform flushing data in the buffer space to the storage space of the non-volatile memory when the memory interface is in a first state, and wherein, if the memory supports the high-speed data storage mode, the processor is further configured to perform control to: whenever a new data write request is generated when the memory interface is in the first state, send a second control command to the memory to provide an instruction for a transition of the memory interface from the first state to a second state; send the data write request to the memory such that the memory device controller performs a function of writing the data to the buffer space of the non-volatile memory; and when a predetermined period during which no data request is sent to the memory expires, send a third control command to the memory to cause the memory interface to transition from the second state to the first state, wherein the first state is a state in which the memory interface operates in a sleep mode, and wherein the second state is a state of the memory interface that allows the memory to receive the data write request from the processor.

[0009] Embodiments of the present disclosure provide a non-transitory computer-readable medium storing instructions executable by a processor of an electronic device, wherein the electronic device includes: a storage including a storage device controller, a storage interface, and a non-volatile memory including a buffer space and a storage space, and the processor coupled to the storage via the storage interface, wherein the instructions, when executed, cause the processor to: determine whether the storage supports a high-speed data storage mode using the buffer space of the non-volatile memory of the storage; if the storage supports the high-speed data storage mode, send a first control command to the storage to activate the storage device controller to automatically perform flushing data in the buffer space to the storage space of the non-volatile memory when the storage interface is in a first state; and wherein, if the storage supports the high-speed data storage mode, the processor is further configured to perform control to: whenever a new data write request is generated when the storage interface is in the first state, send a second control command to the storage to provide an instruction for a transition of the storage interface from the first state to a second state; send the data write request to the storage such that the storage device controller performs a function of writing the data to the buffer space of the non-volatile memory; and when a predetermined time period in which no data request is sent to the storage expires, send a third control command to the storage to cause the storage interface to transition from the second state to the first state, wherein the first state is a state in which the storage interface operates in a sleep mode, and wherein the second state is a state of the storage interface that allows the storage to receive the data write request from the processor.

[0010] Embodiments of the present disclosure provide an electronic device that can prevent performance degradation of the electronic device and increase the available capacity of the buffer space at a time point desired by the processor of the electronic device in the following manner, the manner enabling the processor to set a time point at which data buffered in the buffer space is written to the storage space in a high-density data storage mode, which allows the processor to check information about the progress of the write operation and the current consumption caused by the write operation.

[0011] Embodiments of the present disclosure further provide an electronic device that can increase the available capacity of the buffer space and the storage space for writing data in a high-density data storage mode in the following manner, the manner enabling an operation of writing data buffered in the buffer space to the storage space in a high-density data storage mode to be performed when the storage interface operates in a sleep mode or in the middle of a process of the electronic device entering a power-saving mode.

[0012] Embodiments of the present disclosure also provide an electronic device that can prevent and / or reduce the degradation of the performance of processing new data write input / output requests caused by operations of writing data into a storage space in the following manner, which enables the operation of writing the data buffered in a buffer space into the storage space in a high-density data storage mode when the storage interface operates in a sleep mode or in the middle of the process of the electronic device entering a power-saving mode.

[0013] According to various example embodiments, an electronic device may include: a storage device including a non-volatile memory, a storage device controller, and a storage interface, the non-volatile memory including a buffer space and a storage space; and a processor configured to perform control to: determine whether the storage device supports a high-speed data storage mode using the buffer space of the non-volatile memory of the storage device; based on the storage device supporting the high-speed data storage mode, activate a function of writing the data buffered in the buffer space of the non-volatile memory into the storage space of the non-volatile memory based on the storage interface operating in a first state; and based on no request for the storage device being generated during a predetermined period in which the storage interface operates in a second state, transition the storage interface of the storage device to the first state.

[0014] According to various example embodiments, a storage control method of an electronic device may include: determining whether the storage device supports a high-speed data storage mode using the buffer space of the non-volatile memory of the storage device; based on the storage device supporting the high-speed data storage mode, activating a function of writing the data buffered in the buffer space of the non-volatile memory into the storage space of the non-volatile memory based on the storage interface operating in a first state; and based on no request for the storage device being generated during a predetermined period in which the storage interface operates in a second state, transition the storage interface of the storage device to the first state.

[0015] According to various example embodiments, an electronic device may include: a storage device including a non-volatile memory, a storage device controller, and a storage interface, the non-volatile memory including a buffer space and a storage space; a touch screen; a communication circuit; and a processor configured to perform control to: perform a power-saving operation for components of the electronic device to cause the electronic device to enter a power-saving mode, the components including the touch screen, the communication circuit, and the storage device; determine whether the storage device supports a high-speed data storage mode based on the start of the power-saving operation for the storage device among the power-saving operations for the components of the electronic device; based on the storage device supporting the high-speed data storage mode, identify a high-speed

[0016] The available capacity of the buffer space of the data storage mode; setting, based on the available capacity of the buffer space, a time period during which the memory writes data buffered in the buffer space of the non-volatile memory to the storage space of the non-volatile memory; and writing, during the time period, the data buffered in the buffer space of the non-volatile memory of the storage device to the storage space. Description of the Drawings

[0017] From the following detailed description taken in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent, in which:

[0018] Figure 1 is a block diagram showing an example electronic device in a network environment according to various embodiments;

[0019] Figure 2 is a block diagram showing an example architecture of an electronic device according to various embodiments;

[0020] Figure 3 is a diagram showing an example process for an electronic device to store data in a high-density data storage mode according to various embodiments;

[0021] Figure 4 is a diagram showing an example refresh process of an electronic device operating in a high-speed data storage mode using a low-density data storage scheme and a high-density data storage scheme in a step-by-step manner according to various embodiments;

[0022] Figure 5 is a block diagram showing an example configuration of an electronic device according to various embodiments;

[0023] Figure 6 is a signal flow diagram showing an example signal flow between an application processor and a storage device in an electronic device according to various embodiments;

[0024] Figure 7 is a flowchart showing an example operation of an application processor of an electronic device according to various embodiments;

[0025] Figure 8 is a flowchart showing an example operation of an application processor of an electronic device according to various embodiments;

[0026] Figure 9 is a diagram showing an example power-saving operation for components of an electronic device during a power-saving mode entry process according to various embodiments;

[0027] Figure 10 is a signal flow diagram showing an example signal flow between an application processor and a storage device in an electronic device according to various embodiments;

[0028] Figure 11 is a flowchart illustrating an example operation of an application processor of an electronic device according to various embodiments; and

[0029] Figure 12 is a flowchart illustrating an example operation of an application processor of an electronic device according to various embodiments. DETAILED DESCRIPTION

[0030] Figure 1 is a block diagram of an electronic device 101 in a network environment 100. Referring Figure 1 , the electronic device 101 in the network environment 100 may communicate with an electronic device 102 via a first network 198 (e.g., a short-range wireless communication network) or communicate with an electronic device 104 or a server 108 via a second network 199 (e.g., a long-range wireless communication network). According to an embodiment, the electronic device 101 may communicate with the electronic device 104 via the server 108. According to an embodiment, the electronic device 101 may include a processor 120, a memory 130, an input device 150, a sound output device 155, a display device 160, an audio module 170, a sensor module 176, an interface 177, a haptic module 179, a camera module 180, a power management module 188, a battery 189, a communication module 190, a subscriber identification module (SIM) 196, or an antenna module 197. In some embodiments, at least one of the components (e.g., the display device 160 or the camera module 180) may be omitted from the electronic device 101, or one or more other components may be added to the electronic device 101. In some embodiments, some of the components may be implemented as a single integrated circuit. For example, the sensor module 176 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be implemented as being embedded in the display device 160 (e.g., a display).

[0031] The processor 120 may run software (e.g., program 140) to control at least one other component (e.g., a hardware component or a software component) connected to the electronic device 101 and may perform various data processing or computations. According to one embodiment, as at least part of the data processing or computation, the processor 120 may load commands or data received from another component (e.g., the sensor module 176 or the communication module 190) into the volatile memory 132, process the commands or data stored in the volatile memory 132, and store the resulting data in the non-volatile memory 134. According to an embodiment, the processor 120 may include a main processor 121 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 123 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operationally independent of or combined with the main processor 121. Additionally or alternatively, the auxiliary processor 123 may be adapted to consume less power than the main processor 121 or to be specifically used for a designated function. The auxiliary processor 123 may be implemented separately from the main processor 121 or as part of the main processor 121.

[0032] When the main processor 121 is in an inactive (e.g., sleep) state, the auxiliary processor 123 may control at least some of the functions or states related to at least one of the components of the electronic device 101 (other than the main processor 121) (e.g., the display device 160, the sensor module 176, or the communication module 190), or when the main processor 121 is in an active state (e.g., running an application), the auxiliary processor 123 may control at least some of the functions or states related to at least one of the components of the electronic device 101 (e.g., the display device 160, the sensor module 176, or the communication module 190) together with the main processor 121. According to an embodiment, the auxiliary processor 123 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 180 or the communication module 190) that is functionally related to the auxiliary processor 123.

[0033] The memory 130 may store various data used by at least one component of the electronic device 101 (e.g., the processor 120 or the sensor module 176). The various data may include, for example, software (e.g., program 140) and input data or output data for commands related thereto. The memory 130 may include a volatile memory 132 or a non-volatile memory 134.

[0034] The program 140 may be stored in the memory 130 as software, and the program 140 may include, for example, an operating system (OS) 142, middleware 144, or an application 146.

[0035] The input device 150 may receive commands or data to be used by other components (e.g., the processor 120) of the electronic device 101 from the outside of the electronic device 101 (e.g., a user). The input device 150 may include, for example, a microphone, a mouse, or a keyboard.

[0036] The sound output device 155 may output a sound signal to the outside of the electronic device 101. The sound output device 155 may include, for example, a speaker or a receiver. The speaker may be used for general purposes such as playing multimedia or playing a record, and the receiver may be used for incoming calls. According to an embodiment, the receiver may be implemented separately from the speaker or as part of the speaker.

[0037] The display device 160 may visually provide information to the outside of the electronic device 101 (e.g., a user). The display device 160 may include, for example, a display, a holographic device, or a projector, and a control circuit for controlling a corresponding one of the display, the holographic device, and the projector. According to an embodiment, the display device 160 may include a touch circuit adapted to detect a touch or a sensor circuit (e.g., a pressure sensor) adapted to measure the intensity of a force caused by the touch.

[0038] The audio module 170 may convert sound into an electrical signal and vice versa. According to an embodiment, the audio module 170 may obtain sound via the input device 150, or output sound via the sound output device 155 or headphones of an external electronic device (e.g., the electronic device 102) directly (e.g., wired) or wirelessly connected to the electronic device 101.

[0039] The sensor module 176 may detect an operating state of the electronic device 101 (e.g., power or temperature) or an environmental state outside the electronic device 101 (e.g., a state of a user), and then generate an electrical signal or a data value corresponding to the detected state. According to an embodiment, the sensor module 176 may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0040] The interface 177 may support one or more specific protocols used to directly (e.g., wired) or wirelessly connect the electronic device 101 to an external electronic device (e.g., the electronic device 102). According to an embodiment, the interface 177 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0041] The connection end 178 may include a connector, where the electronic device 101 may be physically connected to an external electronic device (e.g., the electronic device 102) via the connector. According to an embodiment, the connection end 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0042] The haptic module 179 may convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that can be recognized by the user via his sense of touch or kinesthesia. According to an embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0043] The camera module 180 may capture still images or moving images. According to an embodiment, the camera module 180 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0044] The power management module 188 may manage the power supply to the electronic device 101. According to an embodiment, the power management module 188 may be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0045] The battery 189 may supply power to at least one component of the electronic device 101. According to an embodiment, the battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0046] The communication module 190 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 101 and an external electronic device (e.g., the electronic device 102, the electronic device 104, or the server 108), and perform communication via the established communication channel. The communication module 190 may include one or more communication processors capable of operating independently of the processor 120 (e.g., an application processor (AP)), and support direct (e.g., wired) communication or wireless communication. According to an embodiment, the communication module 190 may include a wireless communication module 192 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). Each of these communication modules may communicate with an external electronic device via a first network 198 (e.g., a short-range communication network, such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA)) or a second network 199 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., LAN or wide area network (WAN))). These various types of communication modules may be implemented as a single component (e.g., a single chip), or these various types of communication modules may be implemented as multiple separate components (e.g., multiple chips). The wireless communication module 192 may identify and authenticate the electronic device 101 in a communication network (such as the first network 198 or the second network 199) using user information (e.g., an international mobile subscriber identity (IMSI)) stored in the user identification module 196.

[0047] The antenna module 197 may transmit a signal or power to the outside of the electronic device 101 (e.g., an external electronic device) or receive a signal or power from the outside of the electronic device 101 (e.g., an external electronic device). According to an embodiment, the antenna module 197 may include one or more antennas, and thus, at least one antenna suitable for a communication scheme used in a communication network (such as the first network 198 or the second network 199) may be selected by, for example, the communication module 190 (e.g., the wireless communication module 192). Subsequently, a signal or power may be transmitted or received between the communication module 190 and an external electronic device via the selected at least one antenna.

[0048] At least some of the above components may be interconnected with each other via an inter-peripheral communication scheme (e.g., a bus, a general-purpose input / output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI)) and communicatively transmit signals (e.g., commands or data) therebetween.

[0049] According to an embodiment, commands or data may be transmitted or received between the electronic device 101 and the external electronic device 104 via the server 108 connected to the second network 199. Each of the electronic devices 102 and 104 may be the same type of device as the electronic device 101 or a different type of device from the electronic device 101. According to an embodiment, all or some of the operations running on the electronic device 101 may be run on one or more of the external electronic device 102, the external electronic device 104, or the server 108. For example, if the electronic device 101 is to automatically perform a function or service or is to perform a function or service in response to a request from a user or another device, the electronic device 101 may request at least part of the function or service to be performed by the one or more external electronic devices instead of running the function or service, or in addition to running the function or service, the electronic device 101 may also request at least part of the function or service to be performed by the one or more external electronic devices. The one or more external electronic devices that receive the request may perform the requested at least part of the function or service, or perform additional functions or additional services related to the request, and transmit the result of the execution to the electronic device 101. The electronic device 101 may provide the result as at least part of a reply to the request with or without further processing of the result. For this purpose, for example, cloud computing technology, distributed computing technology, or client-server computing technology may be used.

[0050] Figure 2 is a block diagram showing an example architecture of an electronic device according to various embodiments.

[0051] Referring to Figure 2 , the electronic device 101 may include an application processor (AP) (e.g., including processing circuitry) 200 (e.g., Figure 1 the processor 120 in Figure 1 ), and a storage device 300 (e.g., Figure 2 the memory 130 in Figure 1 ). According to various disclosed embodiments, the electronic device 101 may be configured by omitting or replacing some of the components depicted in Figure 1 . According to various embodiments, the electronic device 101 may further include a battery (not shown) (e.g., Figure 1 the battery 189 in Figure 1a display device 160), a speaker (e.g., Figure 1 a sound output device 155) in, a touch screen (e.g., Figure 1 a display device 160) in, a communication circuit (e.g., Figure 1 a communication module 190) in, a universal serial bus (USB), Figure 1 a connection terminal 178) in, etc.

[0052] According to various embodiments, the application processor 200 may control various components of the electronic device and / or perform communication-related operations or data processing, and it may include Figure 1 at least a part of the configuration and / or functions of the processor 120. For example, the processor may be operably connected to the components of the electronic device 101.

[0053] According to various embodiments, the components of the storage device 300 controlled via the application processor 200 may be referred to as a host. According to various embodiments, the host may include an environment in which software and an operating system including the application processor operate. For example, the host may be a system on chip (SoC) that includes the functions of a chipset responsible for the operation of various applications and graphics processing on the electronic device 101.

[0054] According to various embodiments, the application processor 200 may include an application 210, a storage driver 220, a controller 230, and / or a storage interface 240. Components depicted by dashed lines, such as the application 210 and the storage driver 220, may be software programs.

[0055] According to various embodiments, the controller 230 may include various circuits and control other components of the application processor 200 and / or perform communication-related operations or data processing. According to various embodiments, the controller 230 may include a controller for controlling corresponding components of the electronic device 102. For example, the controller 230 may include a storage host controller 231 for controlling the operation of the storage device 300. For example, the controller 230 may include a PMIC interface controller (e.g., Figure 5 a PMIC interface controller 233) for controlling the operation of the PMIC (e.g., Figure 5 the PMIC 500) in.

[0056] According to various embodiments, the controller 230 may transmit various control commands to the storage device 300 via the storage interface 240 of the application processor 200. For example, the storage host controller 231 of the controller 230 may receive a data storage request generated by the application 210 via the storage driver 220, and in response to the data storage request, send a data write input / output request to the storage device 300 via the storage interface 240. According to various embodiments, the storage interface 240 of the application processor 200 may include various link interfaces for providing a data link function. According to various embodiments, the storage interface 240 of the application processor 200 may include, for example but not limited to, a MIPI M-PHY interface, a MIPI unipro interface defined by the Mobile Industry Processor Interface (MIPI) Alliance, and the like. For example, the application processor 200 may perform high-speed data communication with the storage device 300 via the MIPI M-PHY interface or the MIPI unipro interface.

[0057] According to various embodiments, the storage device 300 may store various data used by at least one of the components of the electronic device 101 (e.g., the application processor 200). According to various embodiments, the storage device 300 may include a flash memory 310, a storage device controller 320, and / or a storage interface 330.

[0058] According to various embodiments, as an example, the flash memory 310 may include a non-volatile memory (e.g., Figure 1 the non-volatile memory 134 in). For example, the flash memory 310 may include a NAND flash memory 310 compliant with the Universal Flash Storage (UFS) standard. According to various embodiments, the storage device controller 320 may control the components of the storage device 300 and / or perform communication-related operations and data processing. According to various embodiments, the storage device controller 320 may receive various control commands from the application processor 200 via the storage interface 330 of the storage device 300. For example, the storage device controller 320 may receive a data request including a data write request (data write I / O), a data read request (data read I / O), or a data delete request (data delete I / O) from the application processor 200 via the storage interface 330 of the storage device 300. According to various embodiments, the storage interface 330 of the storage device 300 may include various link interfaces for providing a data link function. According to various embodiments, the storage interface 330 of the storage device 300 may include, for example but not limited to, a MIPI M-PHY interface, a MIPI unipro interface defined by the MIPI Alliance, and the like.

[0059] According to various embodiments, a storage management unit 321 of a storage device controller 320 may establish and control at least one logical unit 323. For example, the at least one logical unit 323 may correspond to at least one storage cell 311 of the flash memory 310 to store corresponding data.

[0060] Figure 3 is a diagram illustrating an example process for an electronic device to store data in a high-density data storage mode according to various embodiments.

[0061] Referring to Figure 3 , the flash memory 310 of the storage device 300 may operate in data storage modes that differ according to the number of data bits that can be stored in a cell. For example, the flash memory 310 may operate in a single level cell (SLC) mode for storing 1-bit data in a cell, a multi-level cell (MLC) mode for storing 2-bit data in a cell, a triple-level cell (TLC) mode for storing 3-bit data in a cell, or a quad-level cell (QLC) mode for storing 4-bit data in a cell. In the case of operating in the MLC, TLC, or QLC mode, the flash memory 310 may store data at a higher density than in the SLC mode and write data at a lower speed than in the SLC mode. Although for ease of explanation, the following description is directed to the case where the flash memory stores data in the TLC mode, it will be clear to those skilled in the art that the MLC or QLC mode may also be employed in the various disclosed embodiments.

[0062] According to various embodiments, the flash memory 310 may switch between two storage modes. For example, the flash memory 310 operating in the TLC mode in which data is written relatively slowly may temporarily switch the storage mode to the SLC mode to write data at a relatively high speed (hereinafter referred to as the high-speed data storage mode).

[0063] According to various embodiments, by adopting a high-speed data storage mode, the storage speed (or write speed) of the flash memory 310 operating in the TLC mode can be improved. For example, the high-speed data storage mode can be implemented in the following manner, which buffers the data to be stored in the flash memory 310 in the SLC mode in the buffer space 313 of the flash memory 310 and writes the data into the storage space 315 of the flash memory 310 in the TLC mode. The flash memory 310 can allocate a predetermined size of its blank space (e.g., the space not filled with data) as the buffer space 313 to buffer data in the SLC mode and write the data into the storage space 315 of the flash memory 310 in the TLC mode. The data written into the storage space 315 can be deleted from the buffer space 313. For example, first, the data received from the application processor 200 is written into the high-speed writable buffer space 313 with a predetermined size borrowed from the blank space of the flash memory 310 in the SLC mode, and then, secondly, it is rewritten into the storage space 315 of the flash memory 310 in the TLC mode. Since the operation of rewriting data in the TLC mode is an intra-memory operation transparent to the application processor 200, the user may feel that the storage speed has been improved. According to various embodiments, the high-speed data storage mode can include the Universal Flash Storage (UFS) 3.1 Turbo write mode of the joint electron device engineering council (JEDEC) standard. The operation of writing the data buffered in the buffer space 313 of the flash memory 310 can be a flush operation (or migration operation) of the UFS 3.1 Turbo write mode.

[0064] According to various embodiments, the application processor 200 can send a data write input / output (I / O) or a memory write I / O (hereinafter referred to as a "write request") for storing data to the storage device 300 via the storage host controller 231 of the controller 230.

[0065] According to various embodiments, when receiving a data write request from the application processor 200, the storage device controller 320 of the storage device 300 can control the flash memory 310 to buffer the data in the buffer space 313. For example, the storage device controller 320 can write the data into the buffer space 313 of the flash memory 310 in the SLC mode.

[0066] According to various embodiments, the storage device may perform a refresh operation under the control of the storage device controller 320 as an operation of rewriting data buffered in the buffer space 313 of the flash memory 310 to the storage space 315 of the flash memory 310. For example, the storage device 300 may write at least a portion of the data buffered in the buffer space 313 of the flash memory 310 to the storage space 315 of the flash memory 310 in the TLC mode (or MLC or QLC mode), and delete the data written to the storage space 315 from the buffer space 313. Although the buffer space 313 and the storage space 315 are distinguished in the flash memory 310 for ease of explanation, in a physically identical (hybrid) storage space, the buffer space and the storage space are logically distinguished only.

[0067] According to various embodiments, the storage device 300 may send a response signal indicating that the data has been completely stored to the application processor 200.

[0068] In the case where the storage device 300 autonomously performs the refresh operation, the application processor 200 cannot check the progress status of the refresh operation and the current consumption caused by the data rewrite operation, which may lead to deterioration of the performance of the electronic device 101.

[0069] Figure 4 FIG. is a diagram illustrating an example refresh process of an electronic device operating in a high-speed data storage mode using a low-density data storage scheme and a high-density data storage scheme in a step-by-step manner according to various embodiments.

[0070] Referring to Figure 4 , the application processor 200 may send a control command to the storage device 300, and the control command provides an instruction for activating the refresh operation function or performing the refresh operation during a predetermined period. According to various embodiments, the storage device 300 may perform the refresh operation based on the control command.

[0071] According to various embodiments, when the storage interface 240 of the application processor 200 (e.g., see Figure 2 ) is in the sleep mode, the application processor 200 may control the storage device 300 to perform the refresh operation of the flash memory 310. According to various embodiments, the storage interface 240 of the application processor 200 and the storage interface 330 of the storage device 300 may operate in the same operating state under the control of the application processor 200. For example, the application processor 200 may control the storage interface 240 of the application processor 200 and the storage interface 330 of the storage device 300 (e.g., see Figure 2)Operate in a sleep mode. According to various embodiments, the storage interface 330 of the storage device 300 may operate in one of various operating states. According to various embodiments, the storage interface may operate in one of various operating states corresponding to the state of the link interface. For example, the storage interface 330 may operate in one of various unipro states defined by the MIPI Alliance, for example.

[0072] According to various embodiments, if no data requests (such as new data write requests, data read requests, and data delete requests) are generated for the storage device 300 during a predetermined period (e.g., 10 ms), the application processor 200 may send a control command to the storage device, and the control command provides an instruction for entering the first state. Upon receiving the control command, the storage interface 330 may enter the first state. For example, the first state of the storage interface 330 may be, for example, the hibernate state among the unipro states defined by the MIPI Alliance. For example, the hibernate state of the storage interface 330 is a state in which the storage interface 330 operates in a sleep mode.

[0073] According to various embodiments, if a data write request for storing data in the storage device 300 is received from the application processor 200, the storage interface 330 enters a second state, in which a data write operation is performed in response to the data write request received from the application processor 200. For example, the second state of the storage interface 330 may be, for example, the linkup state among the unipro states defined by the MIPI Alliance. The current consumed in the hibernate state (e.g., less than 1 mA) is a few hundredths of the current consumed when processing a data write request in the linkup state (e.g., 300 mA to 500 mA).

[0074] According to various embodiments, when the storage interface 330 operates in the first state, the storage device 300 may perform a refresh operation of the flash memory 310. For example, the refresh operation may be performed in such a manner that the data buffered in the buffer space 313 of the flash memory 310 is written into the storage space 315 of the flash memory 310. For example, the refresh operation may include a data relocation operation that is performed in such a manner that at least a part of the data stored in the buffer space 313 is written into the storage space 315, and the data written into the storage space 315 is deleted from the buffer space 313. In order to cause the flash memory 310 to perform a refresh operation when the storage interface 330 operates in the first state, the flash memory 310 should be powered during the refresh operation.

[0075] According to various embodiments, when the storage interface 330 of the storage device 300 operates in the first state, the application processor 200 may control the storage device 300 to activate the function of performing a refresh operation. When activating this function, whenever the storage interface 330 is in the first state, the storage device 300 may perform a refresh operation of the flash memory 310. For example, the storage device 300 may perform a refresh operation of the flash memory 310 during the period from entering the first state until waking up from the first state. According to various embodiments, during the refresh operation of the flash memory 310 performed when the storage interface 330 is in the first state, the application processor 200 may control the power management module to supply power from the battery to the flash memory 310.

[0076] According to various embodiments, if a new data write request is generated, the application processor 200 may send a control command to the storage device 300, and the control command provides an instruction for transitioning from the first state to the second state. For example, upon receiving the control command, the storage device 300 may stop the refresh operation and control the storage interface to transition from the first state to the second state. For example, the storage device 300 may control the storage interface 330 to enter the second state within a predetermined time (e.g., 5 ms) after receiving the control command to prevent the processing of the new data write request from being delayed.

[0077] According to various embodiments, whenever the storage interface 330 enters the first state, the storage device 300 may determine whether to activate the function of performing a refresh operation of the flash memory 310 when the storage interface 330 operates in the first state. According to various embodiments, when the storage interface 330 operates in the first state, the storage device 300 may perform a refresh operation of the flash memory 310 when the corresponding function is activated.

[0078] According to various embodiments, the application processor 200 may control the storage device 300 such that when a new data write request is generated during the refresh operation of the flash memory 310 of the storage device 300, the flash memory 310 stops the refresh operation and the storage interface enters the second state.

[0079] According to various embodiments, the application processor 200 may determine whether to allocate a part of the storage space 315 of the flash memory 310 as a buffer space 313 for buffering data in the SLC mode to verify whether the storage device 300 supports the high-speed data storage mode.

[0080] According to various embodiments, the application processor 200 may initialize the flash memory 310 of the storage device 300 when power-on of the electronic device is detected, and determine whether the storage device 300 supports a high-speed data storage mode that utilizes (e.g., uses) the buffer space 313 of the flash memory 310 when detection of completion of the initialization of the flash memory 310 is detected. According to various embodiments, the application processor 200 may initialize at least a part of the settings of the storage device 300 when detection of a transition of the electronic device 101 from a power-saving mode to a normal mode (e.g., resume or wake-up) (or exit from the power-saving mode of the electronic device 101) is detected, and determine whether the storage device 300 supports a high-speed data storage mode that utilizes (e.g., uses) the buffer space 313 of the flash memory 310 when detection of completion of the initialization is detected.

[0081] According to various embodiments, in a first state (e.g., a sleep state) where no data write request is generated, in a case where a refresh operation of the flash memory 310 is performed, the refresh operation does not overlap with any data write request processing operation. For example, this may mean that there is no delay in processing a data write request, and the time for performing the refresh operation can be ensured, resulting in an increase in the capacity of the buffer space 313 available for the flash memory 310.

[0082] According to various embodiments, when the electronic device 101 performs a power-saving operation on the storage device during a process of entering a power-saving mode, the application processor 200 may control the storage device 300 to perform a refresh operation of the flash memory 310. The process of entering the power-saving mode of the electronic device 101 may include a process of performing power-saving tasks for respective components (e.g., a touch screen and a communication circuit) of the electronic device 101 in a predetermined order so that the electronic device 101 enters the power-saving mode.

[0083] According to various embodiments, if there is no task to be executed, the electronic device 101 may turn off the display screen to enter a power-saving mode (e.g., a suspend mode or a sleep mode). For example, if there is no input signal or a power-off button is pressed to turn off the touch screen during a predetermined period of time, the electronic device 101 may start a process of entering the power-saving mode. If a new task is created during the process of entering the power-saving mode (e.g., if the power button is pressed to turn on the display or a message is received), the electronic device 101 may stop the process of entering the power-saving mode and wake up.

[0084] According to various embodiments, the process of the electronic device 101 entering the power saving mode may include power saving operations for each component (e.g., camera, storage device 300, touch screen, speaker, and communication module) operably connected to the application processor 200. Examples of the power saving operations for the components may include operations of turning off the power and clock of the corresponding components and other subordinate operations. After completing the power saving operations for all components operably connected to the application processor 200, the application processor 200 may also perform its own power saving operation to complete the process of the electronic device 101 entering the power saving mode. In the case where at least one power saving operation in the process of entering the power saving mode is not completed, the electronic device 101 cannot enter the power saving mode and must resume the process of entering the power saving mode again.

[0085] According to various embodiments, in the process of entering the power saving mode in which the power saving operations for each component (e.g., touch screen and communication circuit) of the electronic device 101 are sequentially performed, when detecting the start of the power saving operation for the storage device 300, the application processor 200 may determine whether the storage device 300 supports the high-speed data storage mode. The power saving operation for the storage device 300 may be performed via the storage driver 220 of the application processor 200.

[0086] According to various embodiments, if it is determined that the storage device 300 supports the high-speed data storage mode, the application processor 200 may check the available capacity of the buffer space 313 of the flash memory 310. For example, the buffer space 313 of the flash memory 310 may be a temporary storage space in which data is stored in the SLC mode.

[0087] According to various embodiments, the application processor 200 may set a time period for performing the refresh operation of the flash memory 310 based on the available capacity of the buffer space 313. According to various embodiments, the application processor 200 may determine whether to terminate the power saving operation for the storage device 300 based on the available capacity of the buffer space 313.

[0088] According to various embodiments, if it is determined that the available capacity of the buffer space 313 of the flash memory 310 is equal to or less than a first threshold (e.g., equal to or lower than 30% of the total amount of the buffer space 313), the application processor 200 may determine to control the storage device 300 to perform a refresh operation during a first time period (e.g., 500 ms). For example, assuming that the electronic device 101 terminates and resumes the process of entering the power-saving mode, the first time period may refer to, for example, the maximum time period for the refresh operation without affecting the operation of resuming the process of entering the power-saving mode. According to various embodiments, the application processor 200 may perform control to stop the power-saving operation for the storage device (uncompleted) and resume the process of entering the power-saving mode of the electronic device 101 after the storage device 300 has performed the refresh operation of the flash memory 310 during the first time period.

[0089] According to various embodiments, if it is determined that the available capacity of the buffer space 313 of the flash memory 310 is greater than the first threshold and equal to or less than a second threshold (e.g., greater than 30% of the total capacity of the buffer space 313 and equal to or lower than 80%), the application processor 200 may determine to control the storage device 300 to perform a refresh operation during a second time period (e.g., 200 ms). The second time period may be shorter than the first time period. According to various embodiments, after the expiration of the second time period, for example, after the storage device 300 performs the refresh operation of the flash memory 310 during the second time period, the application processor 200 may complete the power-saving operation for the storage device 300. The application processor 200 may perform power-saving operations for other components of the electronic device 101 (e.g., the display and the camera) to complete the process of entering the power-saving mode of the electronic device 101.

[0090] According to various embodiments, if it is determined that the available capacity of the buffer space 313 of the flash memory 310 is greater than the second threshold (e.g., greater than 80% of the total capacity of the buffer space 313), the application processor 200 may determine to control the storage device 300 to suspend the refresh operation (set the time period of the refresh operation to 0) and immediately complete the power-saving operation for the storage device 300. The application processor 200 may perform the power-saving operations for other components of the electronic device 101 that have not been performed yet.

[0091] According to various embodiments, when the storage device 300 is performing the refresh operation of the flash memory 310, the application processor 200 may control the power management module to supply power from the battery to the flash memory 310.

[0092] According to various embodiments, the application processor 200 may perform control such that when the storage device 300 is performing the refresh operation of the flash memory 310, no data requests including new data write requests, data read requests, or data delete requests are sent to the storage device 300.

[0093] According to various embodiments, when a new task generated in the electronic device 101 is detected while the storage device 300 is performing a refresh operation of the flash memory 310, the application processor 200 may control the storage device 300 to stop the refresh operation of the flash memory 310 and resume the power-saving mode input process of the electronic device 101 without completing the power-saving operation for the storage device 300.

[0094] According to various embodiments, if it is determined that an additional refresh operation is required after the refresh operation of the flash memory 310 is completed during a predetermined period in the process of performing the power-saving operation for the storage device 300 among the power-saving operations for the components of the electronic device 101 (e.g., a touch screen and a communication circuit) in the power-saving mode, the standby mode entry process may be resumed without completing the power-saving operation, which enables the storage device 300 to repeatedly perform the refresh operation of the flash memory 313. According to various embodiments, the application processor 200 is capable of controlling the storage device 300 to repeatedly perform the refresh operation of the flash memory 310 before the electronic device 101 enters the standby mode, which results in an increase in the available capacity of the buffer space 313 of the flash memory 310.

[0095] Figure 5 It is a block diagram showing an example configuration of an electronic device according to various embodiments.

[0096] Referring to Figure 5 , the electronic device 101 may further include a power management module (power management integrated circuit (PMIC)) 500 (e.g., Figure 1 the power management module 188 in Figure 1 ) and a battery (not shown) (e.g.,

[0097] According to various embodiments, the power management module 500 may manage the power supply to the components of the electronic device 101 under the control of the application processor 200. According to various embodiments, the battery may supply power to the components of the electronic device 101.

[0098] According to various embodiments, the power management module 500 may manage the power (e.g., VCCQ and VCC) supplied to the storage device controller 320 and the flash memory 310 of the storage device 300.

[0099] According to various embodiments, the application processor 200 may send a power control command to the PMIC 500. For example, the storage driver 220 may send a power control command to the PMIC 500 via the PMIC interface controller 233 of the controller 230. According to various embodiments, the PMIC interface controller 233 may beFigure 2 The components included in the controller 230.

[0100] According to various embodiments, when the storage interface 330 of the storage device 300 is in a first state (e.g., a sleep state), the PMIC 500 may supply power to the storage device controller 320 under the control of the application processor 200. According to various embodiments, when the storage interface 330 of the storage device 300 is in the first state, the PMIC 500 may or may not supply power to the flash memory 310.

[0101] According to various embodiments, when the storage device 300 performs a refresh operation on the flash memory 310 while the storage interface 330 is in the first state, the PMIC 500 may supply power to the flash memory 310. For example, when the storage device 300 activates the function of performing a refresh operation on the flash memory 310 while the storage interface 330 is in the first state, the PMIC 500 may continue to supply power to the flash memory 310 even though the storage interface 330 is in the first state.

[0102] Figure 6 is a signal flow diagram showing an example signal flow between an application processor and a storage device in an electronic device according to various embodiments.

[0103] Referring to Figure 6 the signal flow diagram 600, the application processor 200 may confirm in operation 601 whether the storage device 300 supports a high-speed data storage mode. For example, the application processor 200 may confirm whether the flash memory 310 of the storage device 300 has a buffer space 313 allocated for the high-speed data storage mode.

[0104] According to various embodiments, when the electronic device 101 is powered on or transitions from a power-saving mode to a normal mode (e.g., resumes, wakes up, or exits the power-saving mode), the application processor 200 may determine whether the storage device 300 supports a high-speed data storage mode. According to various embodiments, when the electronic device 101 is powered on or exits the power-saving mode, the application processor 200 may initialize at least a part of the settings of the storage device 300, and determine whether the storage device 300 supports a high-speed data storage mode for use of the buffer space 313 of the flash memory when detecting that the initialization of the storage device 300 is completed.

[0105] According to various embodiments, at operation 603, the storage device 300 may send a response signal to the application processor 200 indicating whether the storage device 300 supports the high-speed data storage mode. For example, if some of the storage space 315 of the flash memory 310 of the storage device 300 is allocated as a buffer space 313 for the high-speed data storage mode, the storage device 300 may send a response signal to the application processor 200 including information indicating its support for the high-speed data storage mode.

[0106] According to various embodiments, the application processor 200 may, at operation 605, send a control command to the storage device 300 based on the support for the high-speed data storage mode in the storage device 300, the control command providing an instruction for activating a function for performing a refresh operation of the flash memory of the storage device 300. For example, the refresh operation may be performed in such a manner that at least a part of the data buffered in the buffer space 313 of the flash memory 310 in the SLC mode is written into the storage space 315 of the flash memory 310 in the TLC mode, and the data written into the storage space 315 is deleted from the buffer space 313 of the flash memory 310 in the storage device 300.

[0107] According to various embodiments, when the electronic device 101 is powered on or transitions from a power-saving mode to a normal mode (e.g., resumes, wakes up, or exits the power-saving mode), when the storage interface 330 of the storage device is operating in a first state, the application processor 200 may send a control command for the storage device 300 to perform a refresh operation of the flash memory 310.

[0108] According to various embodiments, upon receiving the control command, the storage device 300 may activate the function for performing a refresh operation of the flash memory 310 at operation 607 when the storage interface 330 is operating in a first state. For example, the first state of the storage interface 330 may be a state in which the storage interface 330 is operating in a sleep mode. For example, the first state may be a dormant state defined by the MIPI Alliance.

[0109] According to various embodiments, at operation 609, the storage device 300 may send a response signal to the application processor 200, the response signal including information indicating activation of the function for performing a refresh operation of the flash memory 310 when the storage interface 330 is operating in a first state. According to various embodiments, operation 609 may be omitted.

[0110] According to various embodiments, at operation 611, the application processor 200 may monitor the occurrence of data requests (e.g., data write requests, data read requests, or data delete requests) to be sent to the storage device 300. For example, the application processor 200 may periodically check for many newly occurring data write requests.

[0111] According to various embodiments, at operation 613, the storage device 300 may cause the memory interface 300 to operate in a second state. For example, the storage space 330 may be in a state that allows the storage device 300 to receive a data write request from the application processor 200 and perform a data write operation. The second state may be an established link state defined by the MIPI Alliance.

[0112] According to various embodiments, at operation 615, the application processor 200 may send a control command to the storage device 300, the control command providing an instruction to transition the storage interface 330 to a first state when a predetermined time period expires while the storage interface 330 of the storage device 300 operates in the second state and no write request to be sent to the storage device 300 occurs during the predetermined time period.

[0113] According to various embodiments, at operation 617, the storage device 300 may control the storage interface 330 to enter the first state in response to receiving the control command.

[0114] According to various embodiments, if the storage space 330 enters the first state, the storage device 300 may determine at operation 619 whether to activate a function of performing a refresh operation of the flash memory 310 during a duration in which the storage interface 330 operates in the first state.

[0115] According to various embodiments, after activating the function of performing a refresh operation of the flash memory 310 during the duration in which the storage interface 330 is in the first state, at operation 621, the storage device 300 may perform a refresh operation of the flash memory 310 while the storage interface 330 is in the first state.

[0116] Figure 7 is a flowchart showing an example operation of the application processor 200 of the electronic device 101 according to various embodiments.

[0117] Referring to Figure 7 to flowchart 700, the application processor 200 may determine at operation 710 whether the storage device 300 supports a high-speed data storage mode that utilizes (e.g., uses) the buffer space 313 of the flash memory 310. For example, the flash memory 310 may be a non-volatile memory (e.g., Figure 1 the non-volatile memory 134 in

[0118] According to various embodiments, the application processor 200 may control the storage device 300 in operation 720 to activate a function of performing a refresh operation of the flash memory 310 when the storage interface 330 operates in a first state. For example, the refresh operation may be performed in such a manner that at least a part of the data buffered in the buffer space 313 of the flash memory 310 in the SLC mode is written into the storage space 315 of the flash memory 310 in the TLC mode, and the data written into the storage space 315 is deleted from the buffer space 313 of the flash memory 310 in the storage device 300.

[0119] According to various embodiments, the application processor 200 may control the storage device 300 in operation 730 such that when the storage interface 330 of the storage device 300 operates in a second state, the storage interface 330 enters the first state when a predetermined time period elapses without a data request (e.g., a data write request, a data read request, or a data delete request) to be sent to the storage device 300 occurring.

[0120] Figure 8 is a flowchart illustrating an example operation of an application processor of an electronic device according to various embodiments. Details overlapping with the detailed description made with reference to Figure 6 and Figure 7 may not be repeated here.

[0121] Referring to Figure 8 the flowchart 800 of, in operation 801, the application processor 200 may power on the electronic device 101.

[0122] According to various embodiments, in operation 803, the application processor 200 may control the storage device 300 to initialize the flash memory 310 when the electronic device 101 is powered on. For example, the flash memory 310 may be a non-volatile memory (e.g., Figure 1 the non-volatile memory 134 in). According to various embodiments, when the electronic device exits the power saving mode, the application processor 200 may initialize at least a part of the settings of the storage device 300.

[0123] According to various embodiments, when the initialization of the flash memory 310 is completed, the application processor 200 may determine in operation 805 whether the storage device 300 supports a high-speed data storage mode that utilizes (e.g., uses) the buffer space 313 of the flash memory 310.

[0124] If it is determined at operation 805 that the storage device 300 supports the high-speed data storage mode (yes at operation 805), the process proceeds to operation 807, in which the application processor 200 controls the storage device 300 to activate the function of performing a refresh operation during the duration of operation of the storage interface 330 in the first state. If it is determined that the storage device 300 does not support the high-speed data storage mode (no in operation 805), the process ends.

[0125] According to various embodiments, at operation 809, the application processor 200 may monitor the occurrence (e.g., generation) of data requests (e.g., data write requests, data read requests, or data delete requests). For example, the application processor 200 may periodically check for many newly occurring data write requests.

[0126] According to various embodiments, the application processor 200 may determine at operation 811 whether a new data request to be sent to the storage device 300 occurs during the period of operation of the storage interface 330 in the second state.

[0127] If it is determined that a new data request occurs during the predetermined period (yes in operation 811), the process returns to operation 809. If it is determined that a new data request occurs, the application processor 200 may send the data request to the storage device 300.

[0128] According to various embodiments, if it is determined at operation 811 that no new data requests (e.g., write requests, read requests, or delete requests) to be sent to the storage device 300 occur during the predetermined period (no in operation 811), then the process proceeds to operation 813, in which the application processor 200 may control the storage device 300 such that the memory interface 330 enters the first state.

[0129] Figure 9 FIG. is a diagram showing an example power-saving operation of components of an electronic device during the power-saving mode entry process according to various embodiments.

[0130] Referring to Figure 9 , the electronic device 101 may include an application processor 200, a storage device 300, a camera 910, an LCD 920, a speaker 930, a touch screen 940, a communication circuit 950, and / or a USB interface 960.

[0131] According to various embodiments, when performing a power saving operation for the storage device 300 during the power saving mode entry process of the electronic device 101, the application processor 200 may control the storage device 300 to perform a refresh operation of the flash memory 310. The power saving mode entry process may be a process in which the electronic device 101 enters the power saving mode by performing power saving operations for the components of the electronic device 101 in a predetermined order.

[0132] According to various embodiments, if there is no task to be executed, the electronic device 101 may turn off the display screen to enter the power saving mode (e.g., suspend mode or sleep mode). For example, if there is no input signal or the power off button is pressed to turn off the touch screen during a predetermined period, the electronic device 101 may start the process of entering the power saving mode. If a new task is created during the process of entering the power saving mode (e.g., if the power button is pressed to turn on the display or a message is received), the electronic device 101 may stop the process of entering the power saving mode and wake up.

[0133] According to various embodiments, the process of the electronic device 101 entering the power saving mode may include power saving operations for each component operably connected to the application processor 200. Examples of the power saving operations for these components may include operations of turning off the power and clock of the corresponding components and other subordinate operations. After completing the power saving operations for all components operably connected to the application processor 200, the application processor 200 may also perform its own power saving operation to complete the power saving mode entry process of the electronic device 101. In the case where at least one power saving operation in the power saving mode entry process is not completed, the electronic device 101 cannot enter the power saving mode and must start the power saving mode entry process again.

[0134] For example, in the case where the power saving mode entry process of the electronic device 101 is configured to sequentially perform power saving operations for the storage device 300, the camera 910, the LCD 920, the speaker 930, the touch screen 940, the communication circuit 950, the USB interface 960, and the application processor 200, if the power saving operation for the storage device 300 is not completed, the power saving operation for the camera 910 cannot be started, which may cause the electronic device 101 to resume the power saving mode entry process again.

[0135] According to various embodiments, during the power saving mode entry process in which power saving operations for each component of the electronic device 101 are sequentially performed, when detecting the start of the power saving operation for the storage device 300, the application processor 200 may determine whether the storage device 300 supports the high-speed data storage mode.

[0136] Figure 10It is a signal flow diagram showing an example signal flow between an application processor and a storage device in an electronic device according to various embodiments.

[0137] Referring to Figure 10 Signal flow diagram 1000, the application processor 200 may initiate the process of entering the power-saving mode of the electronic device 101 at operation 1001. For example, when there is no operation to be performed by the electronic device, the application processor 200 may initiate the process of entering the power-saving mode. According to various embodiments, the process of entering the power-saving mode of the electronic device 101 may include power-saving operations for each component of the electronic device 101 operably connected to the application processor 200.

[0138] According to various embodiments, at operation 1003, the application processor 200 may initiate a power-saving operation for the storage device 300 during the process of entering the power-saving mode in which power-saving operations for each component of the electronic device 101 are performed. Examples of power-saving operations for components may include operations of turning off the power and clock to the storage device 300.

[0139] According to various embodiments, at operation 1005, the application processor 200 may confirm whether the storage device 300 supports the high-speed data storage mode when initiating the power-saving operation for the storage device 300. For example, the application processor 200 may confirm whether a buffer space for the high-speed data storage mode is allocated in the flash memory 310 of the storage device 300. For example, the flash memory 310 may be a non-volatile memory (e.g., Figure 1 the non-volatile memory 134 in

[0140] According to various embodiments, the storage device 300 may send a response signal indicating whether the storage device 300 supports the high-speed data storage mode to the application processor 200 at operation 1007. For example, if some of the storage space 315 of the flash memory 310 of the storage device 300 is allocated as the buffer space 313 for the high-speed data storage mode, the storage device 300 may send a response signal including information indicating that it supports the high-speed data storage mode to the application processor 200.

[0141] According to various embodiments, the application processor 200 may confirm the available capacity of the buffer space 313 for the high-speed data storage mode in the flash memory 310 of the storage device 300 at operation 1009.

[0142] According to various embodiments, the storage device 300 may send a response signal including information indicating the available capacity of the buffer space 313 of the flash memory 310 to the application processor 200 at operation 1011.

[0143] According to various embodiments, the application processor 200 may set, at operation 1013, a time period for the storage device 300 to perform a refresh operation on the flash memory 310 based on the available capacity of the buffer space 313. For example, the refresh operation may be performed in such a manner that at least a portion of the data buffered in the buffer space 313 of the flash memory 310 in the SLC mode is written into the storage space 315 of the flash memory 310 in the TLC mode, and the data written into the storage space 315 is deleted from the buffer space 313 of the flash memory 310 in the storage device 300.

[0144] According to various embodiments, at operation 1015, the application processor 200 may send a control command to the storage device 300, the control command providing an instruction for performing a refresh operation during a preset time period.

[0145] According to various embodiments, at operation 1017, the storage device 300 may perform a refresh operation during a preset time period.

[0146] Figure 11 is a flowchart showing an example operation of an application processor of an electronic device according to various embodiments.

[0147] Referring to Figure 11 flowchart 1100 of, the application processor 200 may perform, at operation 1110, power saving operations for components of the electronic device 101 (e.g., Figure 9 components of the electronic device 101 depicted in

[0148] According to various embodiments, at operation 1120, when detecting the start of a power saving operation for the storage device 300 during the process of entering the power saving mode, the application processor 200 may determine whether the storage device 300 supports a high-speed data storage mode.

[0149] According to various embodiments, when detecting the fact that the storage device 300 supports a high-speed data storage mode, the application processor 200 may, at operation 1130, check the available capacity of the buffer space 313 for the high-speed data storage mode in the flash memory 310. For example, the flash memory 310 may be a non-volatile memory (e.g., Figure 1 non-volatile memory 134 in

[0150] According to various embodiments, at operation 1140, the application processor 200 may set a time period for the storage device 300 to perform a refresh operation on the flash memory 310 based on the available capacity of the buffer space 313.

[0151] According to various embodiments, at operation 1150, the application processor 200 may control the storage device 300 to perform a refresh operation of the flash memory 310 during a preset time period.

[0152] Figure 12 is a flowchart illustrating an example operation of an application processor of an electronic device according to various embodiments. Detailed descriptions overlapping with those made with reference to Figure 9 and Figure 10 will not be repeated here.

[0153] Referring to Figure 12 the flowchart 1200 of, at operation 1201, the application processor 200 may initiate a power saving mode entry process of the electronic device 101.

[0154] According to various embodiments, at operation 1203, the application processor 200 may perform a power saving operation for the storage device 300 during a power saving mode entry process in which power saving operations for respective components of the electronic device 101 are sequentially performed.

[0155] According to various embodiments, the application processor 200 may determine at operation 1205 whether the storage device 300 supports a high-speed data storage mode.

[0156] According to various embodiments, when detecting the fact that the storage device 300 supports the high-speed data storage mode, the application processor 200 may check at operation 1207 the available capacity of the buffer space 313 for the high-speed data storage mode in the flash memory 310.

[0157] According to various embodiments, the application processor 200 may set at operation 1209 a time period for the storage device 300 to perform a refresh operation of the flash memory 310 based on the available capacity of the buffer space 313. For example, if the available capacity of the buffer space 313 is equal to or less than a first threshold, this may determine that the storage device 300 performs a refresh operation of the flash memory 310 during a first time period. For example, if the available capacity of the buffer space 313 is greater than the first threshold and equal to or less than a second threshold, this may determine that the storage device 300 performs a refresh operation of the flash memory 310 during a second time period. For example, if the available capacity of the buffer space 313 is greater than the second threshold, this may determine that the storage device 300 does not perform a refresh operation of the flash memory 310.

[0158] According to various embodiments, at operation 1211, the application processor 200 may control the storage device 300 to perform a refresh operation of the flash memory 310 during a preset time period.

[0159] According to various embodiments, at operation 1213, the application processor 200 may determine whether to complete the power saving operation for the storage device 300 based on the available capacity of the buffer space 313. For example, if it is determined that the available capacity of the buffer space 313 is equal to or greater than the first threshold (in operation 1213, "no"), the application processor 200 may control to stop the power saving operation for the storage device 300 after the flash memory 310 of the storage device 300 completes the refresh operation during the first time period at operation 1217, and resume the power saving mode entry process again. For example, if it is determined that the available capacity of the buffer space 313 is greater than the first threshold and equal to or less than the second threshold (in operation 1213, "yes"), the application processor 200 may control to perform the power saving operation for the storage device 300 after the flash memory 310 of the storage device 300 completes the refresh operation during the second time period, and perform and complete the power saving operation for other remaining components at operation 1215 to put the electronic device 101 into the power saving mode. For example, if it is determined that the available capacity of the buffer space 313 is greater than the second threshold, the application processor 200 may control to immediately complete the power saving operation for the storage device 300 without the refresh operation in the flash memory 310 of the storage device 300, and perform and complete the power saving operation for other remaining components at operation 1215 to put the electronic device 101 into the power saving mode.

[0160] An electronic device in various example embodiments may include: a storage device including a non-volatile memory, a storage device controller, and a storage interface, the non-volatile memory including a buffer space and a storage space; and a processor. The processor may be configured to perform control to: determine whether the storage device supports a high-speed data storage mode using the buffer space of the non-volatile memory of the storage device; based on the storage device supporting the high-speed data storage mode, activate a function of writing data buffered in the buffer space of the non-volatile memory into the storage space of the non-volatile memory based on the storage interface operating in a first state; and based on no request being generated for the storage device 300 during a predetermined time period in which the storage interface operates in a second state, transition the storage interface of the storage device to the first state.

[0161] In the electronic device according to various example embodiments, writing the data buffered in the buffer space into the storage space may include: deleting the data written into the storage space from the buffer space.

[0162] In the electronic device according to various example embodiments, the first state of the storage interface may be a state in which the storage interface operates in a sleep mode, and the second state of the storage interface may be a state in which the storage device performs a data write operation in a high-speed data storage mode based on a write request received by the storage interface.

[0163] In an electronic device according to various example embodiments, a storage device may be configured to determine whether a function is activated based on the storage interface entering a first state, and based on the function being activated, write data buffered in a buffer space of a non-volatile memory to a storage space of the non-volatile memory based on the storage interface operating in the first state.

[0164] The electronic device according to various example embodiments may further include: a battery; and a power management module including various power management circuits. A processor of the electronic device may be configured to control the power management module to supply power from the battery to the non-volatile memory based on the storage interface operating in the first state.

[0165] In an electronic device according to various example embodiments, a processor may be configured to send a control command indicating activation of a function to the storage device based on the storage device supporting a high-speed data storage mode.

[0166] In an electronic device according to various example embodiments, a processor may be configured to: control the storage device to stop writing data buffered in a buffer space of the non-volatile memory to the storage space and transition the storage interface to a second state based on a new write request being generated based on the storage device writing data buffered in the buffer space of the non-volatile memory to the storage space.

[0167] A storage control method of an electronic device according to various example embodiments may include: determining whether the storage device supports a high-speed data storage mode using a buffer space of a non-volatile memory of the storage device; based on the storage device supporting the high-speed data storage mode, activating a function of writing data buffered in the buffer space of the non-volatile memory to the storage space of the non-volatile memory based on the storage interface operating in a first state; and based on no request for the storage device being generated during a predetermined period in which the storage interface operates in a second state, transitioning the storage interface of the storage device to the first state.

[0168] In the storage control method of an electronic device according to various example embodiments, writing data buffered in the buffer space to the storage space may include: deleting the data written to the storage space from the buffer space.

[0169] In the storage control method of an electronic device according to various example embodiments, the first state of the storage interface may be a state in which the storage interface operates in a sleep mode, and the second state of the storage interface may be a state in which the storage device performs a data write operation in a high-speed data storage mode based on a write request received by the storage interface.

[0170] The storage control method of an electronic device according to various example embodiments may further include controlling a power management module to supply power from a battery to a non-volatile memory by operating based on a storage interface of a storage device in a first state.

[0171] The storage control method of an electronic device according to various example embodiments may further include: determining whether a new write request is generated based on writing data buffered in a buffer space of a non-volatile memory to a storage space by a storage device; stopping writing data buffered in the buffer space of the non-volatile memory to the storage space based on the new write request being generated based on writing data buffered in the buffer space of the non-volatile memory to the storage space; and transitioning a storage interface of the storage device to a second state.

[0172] An electronic device according to various example embodiments may include: a storage device including a non-volatile memory, a storage device controller, and a storage interface, the non-volatile memory including a buffer space and a storage space; a touch screen; a communication circuit; and a processor. In the electronic device according to various example embodiments, the processor may be configured to: perform power-saving operations for components of the electronic device in a predetermined order to cause the electronic device to enter a power-saving mode, the components including the touch screen, the communication circuit, and the storage device 300; determine whether the storage device supports a high-speed data storage mode based on the start of the power-saving operation for the storage device among the power-saving operations for the components of the electronic device; identify an available capacity of a buffer space for the high-speed data storage mode in the non-volatile memory based on the storage device supporting the high-speed data storage mode; set a time period during which the memory writes data buffered in the buffer space of the non-volatile memory to the storage space of the non-volatile memory based on the available capacity of the buffer space; and write data buffered in the buffer space of the non-volatile memory of the storage device to the storage space during the time period.

[0173] In the electronic device according to various example embodiments, the processor is configured to determine whether the power-saving operation for the storage device is completed based on the available capacity of the buffer space.

[0174] In the electronic device according to various example embodiments, the processor may be configured to: control the storage device to perform an operation of writing data buffered in the buffer space of the non-volatile memory to the storage space during a first time period based on the available capacity of the buffer space being equal to or less than a first threshold, and stop the power-saving operation for the storage device and resume the power-saving operations for the components of the electronic device to cause the electronic device to enter the power-saving mode based on the expiration of the first time period.

[0175] In an electronic device according to various example embodiments, a processor may be configured to control a storage device to perform an operation of writing data buffered in a buffer space of a non-volatile memory during a second time period based on the available capacity of the buffer space being greater than a first threshold and equal to or less than a second threshold, and based on expiration of the second time period, complete a power saving operation for the storage device.

[0176] In an electronic device according to various example embodiments, a processor may be configured to perform control to complete a power saving operation for a storage device based on the available capacity of a buffer space being greater than a second threshold without writing data buffered in the buffer space of the non-volatile memory of the storage device into a storage space.

[0177] An electronic device according to various example embodiments may further include: a battery; and a power management module including a power management circuit. In an electronic device according to various example embodiments, a processor may be configured to control the power management module to supply power from the battery to the non-volatile memory based on the storage device writing data buffered in the buffer space of the non-volatile memory into a storage space.

[0178] In an electronic device according to various example embodiments, a processor may be configured to control to send a write request to a storage device based on the storage device writing data buffered in the buffer space of a non-volatile memory into a storage space.

[0179] In an electronic device according to various example embodiments, a processor may be configured to: based on the storage device writing data buffered in the buffer space of a non-volatile memory into a storage space, control the storage device to stop writing data buffered in the buffer space of the non-volatile memory into the storage space based on creation of a new task in the electronic device, stop a power saving operation for the storage device, and resume a process of the electronic device entering a power saving mode.

[0180] As described above, an electronic device according to various example embodiments may prevent performance degradation of the electronic device and increase the available capacity of a buffer space at a time point desired by a processor of the electronic device in such a manner that the processor can set a time point at which data buffered in the buffer space is written into a storage space in a high-density data storage mode, which allows the processor to check information regarding progress of a write operation and current consumption caused by the write operation.

[0181] An electronic device according to various example embodiments may also increase the available capacity of a buffer space and a storage space for writing data in a high-density data storage mode in the following manner, such that an operation of writing data buffered in the buffer space into the storage space in the high-density data storage mode can be performed when the storage interface operates in a sleep mode or in the middle of a process of the electronic device entering a power-saving mode.

[0182] An electronic device according to various embodiments may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the present disclosure, the electronic device is not limited to the electronic devices described above.

[0183] It should be understood that various embodiments of the present disclosure and the terms used therein are not intended to limit the technical features set forth herein to specific embodiments, but include various changes, equivalent forms, or alternative forms corresponding to the respective embodiments. For the description of the drawings, like reference numerals may be used to refer to like or related elements. It will be understood that a singular form of a noun corresponding to a term may include one or more things, unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include all possible combinations of the items listed together in the corresponding one of the plurality of phrases. As used herein, terms such as "first" and "second" or "1st" and "2nd" may be used to simply distinguish a corresponding component from another component, and do not limit the component in other respects (e.g., importance or order). It will be understood that if an element (e.g., a first element) is referred to as "coupled with", "coupled to", "connected with", or "connected to" another element (e.g., a second element) in the case where the term "operably" or "communicatively" is used or in the case where the term "operably" or "communicatively" is not used, it means that the one element may be directly (e.g., wired) connected to the other element, wirelessly connected to the other element, or connected to the other element via a third element.

[0184] As used herein, the term "module" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms (e.g., "logic", "logic block", "portion", or "circuit"). A module may be a single integrated component adapted to perform one or more functions or the smallest unit or portion of the single integrated component. For example, according to an embodiment, a module may be implemented in the form of an application specific integrated circuit (ASIC).

[0185] The various embodiments described herein may be implemented as software (e.g., a program 140) including one or more instructions readable by a machine (e.g., an electronic device 101) stored in a storage medium (e.g., internal memory 136 or external memory 138). For example, under the control of a processor, a processor (e.g., processor 120) of the machine (e.g., electronic device 101) may call at least one of the one or more instructions stored in the storage medium and run the at least one instruction with or without using one or more other components. This enables the machine to operate to perform at least one function in accordance with the at least one instruction called. The one or more instructions may include code generated by a compiler or code capable of being run by an interpreter. A machine-readable storage medium may be provided in the form of a non-transitory storage medium. Herein, the term "non-transitory" only means that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but this term does not distinguish between data being stored semi-permanently in the storage medium and data being stored temporarily in the storage medium.

[0186] According to an embodiment, a method according to various embodiments of the present disclosure may be included and provided in a computer program product. The computer program product may be traded between a seller and a purchaser as a product. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play StoreTM), or may be directly distributed (e.g., downloaded or uploaded) between two user devices (e.g., smart phones). If distributed online, at least a portion of the computer program product may be generated temporarily, or at least a portion of the computer program product may be stored at least temporarily in a machine-readable storage medium (such as the memory of a manufacturer's server, an application store's server, or a forwarding server).

[0187] According to various embodiments, each of the above components (e.g., a module or a program) may include a single entity or multiple entities. According to various embodiments, one or more of the above components may be omitted, or one or more other components may be added. Optionally or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In such a case, according to various embodiments, the integrated component may still perform the one or more functions of each of the multiple components in the same or similar manner as the corresponding one of the multiple components performed the one or more functions before integration. According to various embodiments, the operations performed by a module, a program, or another component may be performed sequentially, in parallel, repeatedly, or in a heuristic manner, or one or more of the operations may be run in a different order or omitted, or one or more other operations may be added.

Claims

1. An electronic device (101), comprising: a storage (300) including a storage device controller (320), a storage interface (330), and a non - volatile memory (310) including a buffer space (313) and a storage space (315); and a processor (230) coupled to the storage via the storage interface, the processor being configured to perform control to: use the buffer space of the non - volatile memory of the storage to determine whether the storage supports a high - speed data storage mode, if the storage supports the high - speed data storage mode, send a first control command to the storage to activate the storage device controller to automatically perform flushing data in the buffer space to the storage space of the non - volatile memory when the storage interface is in a first state, and wherein, if the storage supports the high - speed data storage mode, the processor is further configured to perform control to: whenever a new data write request is generated when the storage interface is in the first state, send a second control command to the storage to provide an instruction for the transition of the storage interface from the first state to the second state; send the data write request to the storage such that the storage device controller performs the function of writing the data to the buffer space of the non - volatile memory; and when a predetermined time period during which no data request is sent to the storage expires, send a third control command to the storage to cause the storage interface to transition from the second state to the first state, wherein, the first state is a state in which the storage interface operates in a sleep mode, and wherein, the second state is a state of the storage interface that allows the storage to receive the data write request from the processor.

2. The electronic device according to claim 1, wherein, the storage device is configured to: receive the first control command from the processor when the storage interface is in the first state to automatically perform flushing data in the buffer space to the storage space, and in response to the storage interface transitioning to the first state, flush the data in the buffer space to the storage space based on the first control command.

3. The electronic device according to claim 1, the processor is further configured to: in response to a request for writing data generated when flushing the data in the buffer space, control the storage to stop flushing the data.

4. The electronic device according to claim 1, wherein, the storage device controller is further configured to determine whether to perform flushing data in the buffer space to the storage space when the storage interface transitions to the first state.

5. The electronic device according to claim 1, wherein, the first state of the storage interface is a dormant state in which the storage interface operates in a sleep mode.

6. The electronic device according to claim 1, wherein, the processor is further configured to determine a time period for flushing the data based on the available capacity of the buffer space.

7. The electronic device according to claim 1, wherein, The processor is further configured to control to maintain power supply from the battery to the memory while the memory refreshes the data.

8. A non - transitory computer - readable medium storing instructions executable by a processor of an electronic device (101), wherein, the electronic device (101) includes: a memory (300), including a memory device controller (320), a memory interface (330), and a non - volatile memory (310) including a buffer space (313) and a storage space (315), and the processor, coupled to the memory via the memory interface, wherein the instructions, when executed, cause the processor to: determine whether the memory supports a high - speed data storage mode using the buffer space of the non - volatile memory of the memory; if the memory supports the high - speed data storage mode, send a first control command to the memory to activate the memory device controller to automatically execute flushing data in the buffer space to the storage space in the non - volatile memory when the memory interface is in a first state; and wherein, if the memory supports the high - speed data storage mode, the processor is further configured to perform control to: whenever a new data write request is generated when the memory interface is in the first state, send a second control command to the memory to provide an instruction for the transition of the memory interface from the first state to a second state; send the data write request to the memory such that the memory device controller performs the function of writing the data to the buffer space of the non - volatile memory; and when a predetermined time period during which no data request is sent to the memory expires, send a third control command to the memory to cause the memory interface to transition from the second state to the first state, wherein the first state is a state in which the memory interface operates in a sleep mode, and wherein the second state is a state of the memory interface that allows the memory to receive the data write request from the processor.

9. The non - transitory computer - readable medium according to claim 8, wherein, the instructions further cause the processor to: receive, when the memory interface is in the first state, the first control command from the processor to automatically flush data in the buffer space to the storage space; and in response to the memory interface transitioning to the first state, flush data in the buffer space to the storage space based on the first control command.

10. The non - transitory computer - readable medium according to claim 8, wherein, the instructions further cause the processor to: control the memory to stop flushing the data in response to a request for written data generated while flushing data in the buffer space.

11. The non - transitory computer - readable medium according to claim 8, wherein, the instructions further cause the processor to: wherein the memory device controller is further configured to determine whether to flush data in the buffer space to the storage space when the memory interface transitions to the first state.

12. The non - transitory computer - readable medium according to claim 8, wherein, The instruction further causes the processor to: Wherein, a first state of the memory interface is a sleep state in which the memory interface operates in a sleep mode.

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