An excitation generation device for HOF simulation verification

Abstract

The present invention relates to an excitation generating device for HOF simulation verification, belonging to the technical field of chip verification, and solves the problem that the excitation for HOF simulation verification in the prior art is not easy to generate or is not convenient for flexible control and debugging after generation. The device includes a 66-bit block generator component, which is used to simulate a client to generate various data streams of the 66-bit block type, save the data streams through a blk_IF class of the interface type, and transmit the generated data streams to a hof_tx_env component through a port of the uvm_put_export type; a hof_tx_env component, which is used to transmit the data streams generated by the 66-bit block generator into an internal uvm_tlm_fifo, take out the data streams from the uvm_tlm_fifo and put them into corresponding N-way 66b_blk_fifos, and then converge to N-way hof_tx_shims respectively. According to the shim_IF classes of the interface type in the N-way hof_tx_shims, after inserting Overhead blocks into the data streams, they are respectively transmitted to N-way PHYs, where N≥1. A flexible and controllable excitation device and intuitive and fast problem positioning are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to an excitation generation device for HOF simulation verification. Background Art

[0002] During data transmission, factors such as cable length and chip working environment will cause physical losses in signal quality. The emergence of Retimer chips aims to solve this problem. The Retimer chip has a CDR (Clock and Data Recovery) function inside. When the signal passes through the Retimer chip, through the internal clock reconstruction and recovery mechanism, the energy of the signal transmission is increased and then continues to be transmitted, thus effectively reducing the jitter of the signal and lowering the loss. With the development of technology, the Retimer chip also has a gearbox function, which can realize the conversion of different modes under the condition of equal user bandwidth on both sides. However, there is currently no mode conversion in the case of unequal bandwidth on both sides, and the HOF solution can make up for this deficiency.

[0003] HOF, Hash of FlexE, still essentially conforms to the FlexE protocol and is a simplified structure of FlexE. It inherits some advantages of FlexE, meets the one-to-many transceiver requirements of the system, and has advantages such as low latency, isolation, and high flexibility.

[0004] However, the more flexible the technology, the more complex the corresponding EDA simulation verification platform is. The construction requirements of the excitation are more flexible and controllable, and the positioning requirements of problems are more intuitive and efficient. Summary of the Invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide an excitation generation device for HOF simulation verification, which is used to solve the problem that existing verification excitations are not easy to generate or are not convenient for flexible control and debugging during the one-to-many mode conversion using HOF technology in the application scenario of retimer / gearbox chips supporting multiple data paths.

[0006] The embodiments of the present invention provide an excitation generation device for HOF simulation verification, including: a 66bit block generator component, which is used to simulate a client to generate various types of 66bit block type data streams, save the data streams through an interface type blk_IF class, and transmit the generated data streams to the hof_tx_env component through a port of the uvm_put_export type.

[0007] The hof_tx_env component is used to input the data stream generated by the 66-bit block generator into the internal uvm_tlm_fifo, take out the data stream from the uvm_tlm_fifo and put it into the corresponding N-way 66b_blk_fifo, and then converge them to the N-way hof_tx_shim respectively. According to the shim_IF class of the interface type in each of the N-way hof_tx_shim, after inserting the Overhead block into the data stream, it is respectively passed to the N-way PHY, where N≥1.

[0008] For a further improvement based on the above device, according to the corresponding number of clients, instantiate the 66-bit block generator#x corresponding to each client, where x represents the x-th client, and 1 hof_tx_env instance;

[0009] Instantiate 1 blk_IF#x and 1 uvm_put_export#x in each 66-bit block generator#x;

[0010] Instantiate the uvm_tlm_fifo#x corresponding to each 66-bit block generator#x in each hof_tx_env instance. Each uvm_tlm_fifo#x corresponds to N-way 66b_blk_fifo#x.y, where y = 0, 1,..., N - 1. The y-th 66b_blk_fifo#x.y in each uvm_tlm_fifo#x converges to the corresponding hof_tx_shim#y, corresponding to the shim_IF#y interface.

[0011] For a further improvement based on the above device, the 66-bit block generator component further includes a pattern selection attribute clause49_enable, which is used for the encoding rule used by the corresponding client, and outputs a pattern that meets the protocol requirements according to the pattern selection attribute.

[0012] For a further improvement based on the above device, the attributes of the blk_IF class include: client_id, shim_id, and data. Among them, client_id is used to store the corresponding client identifier, shim_id is used to store the N-way identifier inside hof_tx_env, and data is used to store the 66-bit block type data stream generated by the 66-bit block generator#x.

[0013] Based on the further improvement of the above device, the hof_tx_env component also includes ports of the uvm_put_port type. Multiple ports are instantiated according to the number of clients and are respectively connected to the uvm_put_export#x ports in the 66-bit block generator to transfer the corresponding data stream to the uvm_tlm_fifo#x in the hof_tx_env.

[0014] Based on the further improvement of the above device, the hof_tx_env component also includes parallel processes corresponding to each uvm_tlm_fifo#x, which are used to monitor the depth of the N 66b_blk_fifo#x.y FIFOs. When the depth of any one of the N FIFOs is less than half of the depth of the uvm_tlm_fifo#x FIFO, a piece of data is taken out from the uvm_tlm_fifo and simultaneously put into the N 66b_blk_fifo#x.y.

[0015] Based on the further improvement of the above device, the shim_IF class includes: a calendar selection identifier, a 66-bit block counter, an Overhead block counter, an Overhead insertion position, and misannotation switches, misannotation quantities, and quantity thresholds for various misannotation types.

[0016] Based on the further improvement of the above device, to insert Overhead blocks into the data stream according to the shim_IF class of the interface type in each of the N hof_tx_shims, it is executed once every m * 20 66-bit blocks according to the set number of loop groups m. In each round of Overhead block insertion, the insertion is carried out in the order of Overhead1 - Overhead8, and the insertion interval of each Overhead block follows the FlexE protocol.

[0017] Based on the further improvement of the above device, to execute a round of Overhead block insertion every m * 20 66-bit blocks, and in each round of Overhead block insertion, insert in the order of Overhead1 - Overhead8, including:

[0018] Determine the time slot division rule corresponding to the selected calendar according to the calendar selection identifier in the shim_IF class, and take out data from the corresponding 66b_blk_fifo according to the division rule;

[0019] Insert Overhead1. The 66-bit block counter and the Overhead block counter in the shim_IF class start to accumulate. When it is recognized that the current position is the Overhead insertion position, insert Overhead2, and so on, until a round of insertions is completed after inserting Overhead8;

[0020] Subsequently, a new round of insertions starts from Overhead1 again every m * 20 66-bit blocks.

[0021] Based on the further improvement of the above device, according to the shim_IF class of each interface type in the N-way hof_tx_shim, when inserting Overhead blocks into the data stream, an error injection mechanism is also introduced, including: when the error injection switch flag of any error injection type in the shim_IF class is turned on, errors are injected at the specified position according to the error injection type. When the error injection quantity of any error injection type reaches the corresponding quantity threshold, the error injection switch flag of this error injection type is set to off.

[0022] Compared with the prior art, the present invention can at least achieve one of the following beneficial effects:

[0023] 1. Decouple the upstream and downstream data through independent components. The components have strong reusability, can easily meet the requirements, and support different bandwidths, the number of clients, and the error injection means are independently configurable or controllable, and can meet more complex stimulus generation requirements;

[0024] 2. Realize the independent control and error injection processing of components by introducing different types of interface classes, can save all historical data, which is visually visible on the waveform, and is convenient for positioning and tracing;

[0025] 3. Solve the problem of deviation in the rhythm of primary and backup data by introducing a flow control mechanism, avoid data congestion by establishing a buffer channel, and reduce the server hardware resource overhead.

[0026] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent specification, and some advantages can be made obvious from the specification, or understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained from the content specifically pointed out in the specification and the drawings. Description of the Drawings

[0027] The drawings are only for the purpose of showing specific embodiments, and are not considered as a limitation to the present invention. Throughout the drawings, the same reference signs represent the same components.

[0028] Figure 1Schematic diagram of the result of the excitation generation device for HOF simulation verification in the embodiments of the present invention;

[0029] Figure 2 Schematic diagram of the process of inserting an Overhead block into each hof_tx_shim in the embodiments of the present invention. Detailed implementation manners

[0030] The preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings. The accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0031] A specific embodiment of the present invention discloses an excitation generation device for HOF simulation verification, which is applicable to supporting q clients with a bandwidth of nG on a physical layer PHY with a bandwidth of pG, where the total sum of the client bandwidths cannot exceed the carrying capacity pG of the physical layer.

[0032] Exemplarily, when p = 100, q = 8, and n is 10, that is, for a 100G bandwidth PHY with a time slot granularity of 5G bandwidth, 8 clients are set to work simultaneously, and the bandwidth of each client is 2 * 5G = 10G. At this time, the total sum of the client bandwidths is 80G, which does not exceed the bandwidth of the PHY, 100G.

[0033] The excitation generation device in this embodiment provides functions such as N channels of excitation required by the retimer / gearbox chip, with consistent N-channel loads, individually controllable for any one channel of excitation, supporting error injection, and being convenient for debugging, where N ≥ 1. As Figure 1 shown, the excitation generation device includes:

[0034] A 66bitblock generator component, which is used to simulate clients to generate various types of data streams of the 66bitblock type, save the data streams through a blk_IF class of the interface type, and transmit the generated data streams to the hof_tx_env component through a port of the uvm_put_export type;

[0035] The hof_tx_env component is used to input the data streams generated by the 66bitblock generator into the internal uvm_tlm_fifo, take out the data streams from the uvm_tlm_fifo and put them into the corresponding N channels of 66b_blk_fifo, and then converge them to N channels of hof_tx_shim respectively. According to the shim_IF class of the interface type in each of the N channels of hof_tx_shim, after inserting an Overhead block into the data streams, they are respectively transmitted to N channels of PHY, where N ≥ 1.

[0036] After the simulation starts, according to the corresponding number of clients, instantiate a 66-bit block generator #x corresponding to each client, where x represents the x-th client, and one hof_tx_env instance;

[0037] Instantiate one blk_IF #x and one uvm_put_export #x in each 66-bit block generator #x;

[0038] Instantiate a uvm_tlm_fifo #x corresponding to each 66-bit block generator #x in each hof_tx_env instance. Each uvm_tlm_fifo #x corresponds to N paths of 66b_blk_fifo #x.y, where y = 0, 1,..., N - 1. The y-th path 66b_blk_fifo #x.y in each uvm_tlm_fifo #x converges to the corresponding hof_tx_shim #y, corresponding to the shim_IF #y interface.

[0039] It should be noted that the value of N is determined according to actual requirements. In Figure 1 , taking N = 2 as an example, that is, the device generates two paths of main and standby excitations. Each uvm_tlm_fifo #x corresponds to the main path 66b_blk_fifo #x.0 and the standby path 66b_blk_fifo #x.1. All the main path 66b_blk_fifo #x.0 converge to the main path hof_tx_shim #0, corresponding to the shim_IF #0 interface, and are transmitted to the main path PHY; all the standby path 66b_blk_fifo #x.1 converge to the standby path hof_tx_shim #1, corresponding to the shim_IF #1 interface, and are transmitted to the standby path PHY.

[0040] Specifically, the 66-bit block generator component includes uvm_transaction, uvm_sequencer, and uvm_driver components, which are used to simulate various 66-bit block type data streams generated by the client; it also includes a code pattern selection attribute clause49_enable, which is used to correspond to the encoding rules used by the client, and outputs a code pattern that meets the protocol requirements according to the code pattern selection attribute; it also includes a port of the uvm_put_export type, which is used to transfer the generated data stream to the hof_tx_env component.

[0041] It should be noted that the IEEE802.3 protocol defines two different 64B / 66B encoding rules. The physical layer PHY below 40G and 40G and above (including 40G) respectively adopt the encoding tables given in Chapter 49 and Chapter 82 of the protocol. Therefore, corresponding to the 64B / 66B encoding, the output will also correspond to two different code pattern sets. The 66bitblock generator component corresponds to the encoded output and outputs a code pattern that meets the protocol requirements according to the code pattern selection attribute. For example, the legal values of the Sync Header can only be 2’b01 or 2’b10. When it is 2’b01, the block type, the position and value of the O code, and the value in the Z domain, etc. must be within the legal range.

[0042] Specifically, the blk_IF class of the interface type is instantiated multiple times according to the number of clients, that is, each client corresponds to an independent blk_IF instance. The attributes of the blk_IF class include: client_id, shim_id, and data. Among them, client_id is used to store the corresponding client identifier, shim_id is used to store the N-way identifier inside hof_tx_env, and data is used to store the data stream of the 66bit block type generated by the 66bit block generator#x. It should be noted that the client_id and the shim_id of the corresponding shim can more intuitively determine the ownership relationship of the data during debugging and tracing, and are more convenient for locating problems.

[0043] Preferably, other control signals can also be declared in the blk_IF class, including:

[0044] Signals corresponding to each field of the 66b code pattern specified by the protocol, so as to more intuitively indicate the type of the current block, such as blocktype;

[0045] The enable control signal driver_enable of the driver. Since the blk_IF instance can pass the handle to the uvm_driver component in the 66bitblock generator component through the uvm_config_db, this control signal can be added to the interface to control the start, pause, and termination of the 66b block generator component, which is suitable for scenarios where only some clients need to work. For example, by configuring the driver_enable in the interface corresponding to some clients to 0, some clients can be stopped from working;

[0046] Various control signals and misinjection positions for misinjection. For example, a 1-bit control signal invalid_sh_enable is declared to inject an invalid Sync Header in real time, a 4-bit control signal ocode_data_instead is declared to inject a given O code at legal positions of the O code in the block in real time, and a 1-bit control signal invalid_blocktype_enable is declared to inject a blocktype error in real time.

[0047] In the prior art, an interface is usually used to verify the connection between the stimulus source and the design under test in the platform. However, the blk_IF class and shim_IF class of the interface type in this embodiment do not have a physical connection with the DUT, but are used to store all historical data and declare various control signals, so that all transition processes of the signals are presented in the waveform file. Compared with adding static configuration variables in components or using the method of configuration classes in the prior art, the interface in this embodiment has higher flexibility, is convenient for verifying the use or driving of components, and is intuitively visible in the waveform file, making it more convenient for debugging.

[0048] After the 66-bit block generator component generates the stimulus data, the hof_tx_env component also includes ports of the uvm_put_port type. Multiple ports are instantiated according to the number of clients and are respectively connected to the uvm_put_export#x ports in the 66-bit block generator to transfer the corresponding data stream to the uvm_tlm_fifo#x in the hof_tx_env.

[0049] It should be noted that the depth of the fifo in the uvm_tlm_fifo takes the minimum value under the condition of ensuring that the data stream provided to the DUT is not interrupted. Preferably, the depth of the fifo is defined as 80.

[0050] In actual work, the working clocks of the primary and backup paths cannot be kept completely consistent (such as the deviation introduced by clock jitter or other electrical characteristics). This makes the instantaneous beats of the primary or backup path requesting stimuli different. The existence of the 66b_blk_fifo is equivalent to establishing an independent cache channel between the stimulus source and the primary or backup path to eliminate the influence brought by this frequency inconsistency.

[0051] In addition, from Figure 1As can be seen, there is feedback between the uvm_tlm_fifo#x of each client and the corresponding N-way 66b_blk_fifo#x.y. This feedback implements a data flow control mechanism. While ensuring the normal supply of downstream data, by controlling the generation rhythm of stimuli in the 66-bit block generator component, it ensures that there is no phenomenon of a large accumulation of data causing memory leakage.

[0052] Specifically, in this embodiment, a parallel process corresponding to each uvm_tlm_fifo#x is created in the hof_tx_env component to implement the flow control mechanism, including:

[0053] The parallel process monitors the depth of the fifo of the N-way 66b_blk_fifo#x.y. When the depth of any one of the N-way fifos is less than half of the depth of the uvm_tlm_fifo#x's fifo, a piece of data is taken out from the uvm_tlm_fifo and simultaneously put into the N-way 66b_blk_fifo#x.y.

[0054] It should be noted that the y-th 66b_blk_fifo#x.y in each uvm_tlm_fifo#x converges to the corresponding hof_tx_shim#y, corresponding to the shim_IF#y interface. The shim_IF class includes: a calendar selection identifier, a 66-bit block counter, an Overhead block counter, an Overhead insertion position, and mis-injection switch identifiers, mis-injection quantities, and quantity thresholds for various mis-injection types.

[0055] Specifically, based on the two signals of calendarA and calendarB, this stimulus generation device gives two sets of 20 (100G / 5G = 20) time slot division rules. The calendar selection identifier in the shim_IF class is used to intuitively control the selection of the currently used time slot division rules; the 66-bit block counter is used to indicate the current number of 66-bit blocks in real time; the Overhead block counter is used to indicate the current number of inserted Overhead blocks in real time; the Overhead insertion position is used to indicate the insertion positions of Overhead1 to Overhead8 in real time; the mis-injection switch identifier and the quantity thresholds for various mis-injection types are used to turn on the mis-injection function in real time in the virtual sequence and automatically turn it off after the number of mis-injections specified by the threshold is completed.

[0056] Preferably, various signals corresponding to other fields of Overhead can also be declared in the shim_IF class to indicate the key information in the current Overhead in real time; the generation of a multiframe can also be achieved by declaring control signals within this interface.

[0057] In the hof_tx_env component, according to the shim_IF class of the corresponding interface type in N hof_tx_shim, an Overhead block is inserted into the data stream. According to the set number of loop groups m, an Overhead block insertion is performed every m * 20 66-bit blocks. In each round of Overhead block insertion, the insertion is carried out in the order of Overhead1 - Overhead8, and the insertion interval of each Overhead block follows the FlexE protocol. Preferably, in order to shorten the Overhead locking time of the DUT and improve the debugging efficiency, m is randomly selected from 129 and 1023.

[0058] Specifically, the process of periodically inserting Overhead blocks includes:

[0059] According to the calendar selection identifier in the shim_IF class, determine the time slot division rule corresponding to the selected calendar, and retrieve data from the corresponding 66b_blk_fifo according to the division rule;

[0060] Insert Overhead1, and the 66-bit block counter and Overhead block counter in the shim_IF class start to accumulate. When it is recognized that the current position is the Overhead insertion position, insert Overhead2, and so on, until a round of insertion is completed after inserting Overhead8;

[0061] Subsequently, a new round of insertion starts from Overhead1 again every m * 20 66-bit blocks.

[0062] Preferably, when inserting an Overhead block into the data stream using the control signals declared in the shim_IF class, an error injection mechanism is also introduced, including: when the error injection switch identifier of any error injection type in the shim_IF class is turned on, an error is injected at the specified position according to the error injection type. When the error injection quantity of any error injection type reaches the corresponding quantity threshold, the error injection switch identifier of this error injection type is set to off.

[0063] In Figure 2 shows the flow diagram of inserting an Overhead block in each hof_tx_shim. Specifically, it includes:

[0064] ① Determine the time slot division rule corresponding to the selected calendar according to the calendar selection identifier in the shim_IF class, and retrieve data from the corresponding 66b_blk_fifo according to the division rule;

[0065] ② According to the Overhead insertion position in the shim_IF class and the 66-bit block counter, identify whether the current position is the Overhead block insertion position. If not, continue to retrieve data and increment the 66-bit block counter; if so, identify whether any of the mis-injection switch identifiers in the shim_IF class is turned on;

[0066] ③ If none of the mis-injection switch identifiers for various mis-injection types is turned on, insert the corresponding Overhead block according to the Overhead block count value, and return to step ①;

[0067] ④ If any of the mis-injection switch identifiers for a mis-injection type is turned on, further identify: if the current position is the insertion position of Overhead1 and it is not the first round of insertion, insert Overhead1 and mis-inject at the synchead position, O code position, and / or blocktype position of Overhead1 according to the turned-on mis-injection switch identifier; if the current position is the insertion position of Overhead3 and it is not the first round of insertion, insert Overhead3 and mis-inject in the CRC field of Overhead3 according to the turned-on mis-injection switch identifier. If the above two conditions are not met, insert the corresponding Overhead block according to the Overhead block count value;

[0068] ⑤ For each inserted Overhead block, increment the Overhead block counter. If mis-injection occurs in the Overhead, increment the mis-injection count for the corresponding mis-injection type; at the same time, identify whether the mis-injection count for each mis-injection type has reached its respective count threshold. If it has reached, set the mis-injection switch identifier for the corresponding mis-injection type to off; return to step ①.

[0069] The device in this embodiment has a high degree of multiplexing. When multiple sets of N-channel excitations need to be provided, multiple sets of devices can be instantiated according to the number of channels and bandwidth supported by the PHY. In each set of devices, the components are further instantiated multiple times according to the corresponding number of clients, so that the requirements can be easily met and different primary / backup bandwidths, numbers of clients, and mis-injection means can be independently configured or controlled. Exemplarily, 8 clients can instantiate 2 sets of devices, each set of devices supports 4 clients, each set of devices supports providing excitations for its own N channels, and the relationships between the devices are independent.

[0070] Compared with the prior art, the excitation generation device for HOF simulation verification provided in this embodiment decouples upstream and downstream data through independent components, has strong component reusability, can easily meet requirements, and supports independent configuration or control of the bandwidth, number of clients, and error injection means for different primary and standby scenarios, capable of meeting more complex excitation generation requirements; by introducing different types of interface classes to achieve independent control and error injection processing of components, all historical data can be saved, which is visually visible on the waveform and convenient for positioning and tracing; by introducing a flow control mechanism to solve the problem of deviation in the rhythm of primary and standby data, a buffer channel is established to avoid data congestion and reduce the overhead of server hardware resources.

[0071] Those skilled in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a disk, an optical disc, a read-only memory, or a random access memory, etc.

[0072] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. An excitation generating device for HOF simulation verification, characterized in that, It includes: A 66bit block generator component, which is used to simulate a client to generate various data streams of the 66bit block type, save the data streams through the blk_IF class of the interface type, and transmit the generated data streams to the hof_tx_env component through the port of the uvm_put_export type; The hof_tx_env component is used to input the data stream generated by the 66bit block generator into the internal uvm_tlm_fifo, take out the data stream from the uvm_tlm_fifo and put it into the corresponding N-way 66b_blk_fifo, and then converge them to the N-way hof_tx_shim respectively. According to the shim_IF class of the interface type in each of the N-way hof_tx_shim, after inserting an Overhead block into the data stream, it is transmitted to the N-way PHY respectively, where N≥1.

2. The excitation generating device for HOF simulation verification according to claim 1, characterized in that In the device, according to the corresponding number of clients, 66bit block generator#x corresponding to each client is instantiated, where x represents the xth client, and 1 instance of the hof_tx_env is instantiated; 1 blk_IF#x and 1 uvm_put_export#x are instantiated in each 66bit block generator#x; In each instance of the hof_tx_env, a uvm_tlm_fifo#x corresponding to each 66bit block generator#x is instantiated. Each uvm_tlm_fifo#x corresponds to N-way 66b_blk_fifo#x.y, where y = 0, 1,..., N - 1. The yth 66b_blk_fifo#x.y in each uvm_tlm_fifo#x converges to the corresponding hof_tx_shim#y, corresponding to the shim_IF#y interface.

3. The excitation generating device for HOF simulation verification according to claim 2, wherein The 66bit block generator component further includes a pattern selection attribute clause49_enable, which is used for the encoding rule used by the corresponding client, and outputs a pattern that meets the protocol requirements according to the pattern selection attribute.

4. The excitation generation device for HOF simulation verification according to claim 2, characterized in that, The attributes of the blk_IF class include: client_id, shim_id, and data. Among them, client_id is used to store the corresponding client identifier, shim_id is used to store the N-way identifier inside the hof_tx_env, and data is used to store the data stream of the 66bit block type generated by the 66bit block generator#x.

5. The excitation generating device for HOF simulation verification according to claim 2, wherein The hof_tx_env component also includes ports of the uvm_put_port type. Multiple ports are instantiated according to the number of clients and are respectively connected to the uvm_put_export#x ports in the 66-bit block generator to transfer the corresponding data stream to the uvm_tlm_fifo#x in the hof_tx_env.

6. The excitation generating device for HOF simulation verification according to claim 5, characterized in that, The hof_tx_env component also includes parallel processes corresponding to each uvm_tlm_fifo#x, which are used to monitor the depth of the N 66b_blk_fifo#x.y fifos. When the depth of any one of the N fifos is less than half of the depth of the uvm_tlm_fifo#x, a piece of data is taken out from the uvm_tlm_fifo and simultaneously put into the N 66b_blk_fifo#x.y.

7. The excitation generating device for HOF simulation verification according to claim 5, characterized in that, The shim_IF class includes: a calendar selection identifier, a 66-bit block counter, an Overhead block counter, an Overhead insertion position, and error injection switch identifiers, error injection quantities, and quantity thresholds for various error injection types.

8. The excitation generating device for HOF simulation verification according to claim 7, characterized in that, Inserting the Overhead block into the data stream according to the shim_IF class of the interface type in each of the N hof_tx_shims is performed according to the set number of loop groups m. Every m * 20 66-bit blocks, a round of Overhead block insertion is executed. In each round of Overhead block insertion, the insertion is performed in the order of Overhead1 - Overhead8, and the insertion interval of each Overhead block follows the FlexE protocol.

9. The excitation generating device for HOF simulation verification according to claim 8, wherein Every m * 20 66-bit blocks, a round of Overhead block insertion is executed. In each round of Overhead block insertion, the insertion is performed in the order of Overhead1 - Overhead8, including: Determining the time slot division rule corresponding to the selected calendar according to the calendar selection identifier in the shim_IF class, and taking out data from the corresponding 66b_blk_fifo according to the division rule; Inserting Overhead1, and the 66-bit block counter and Overhead block counter in the shim_IF class start to accumulate counts. When it is recognized that the current position is the Overhead insertion position, insert Overhead2, and so on, until Overhead8 is inserted to complete a round of insertion; Subsequently, a new round of insertion starts from Overhead1 again every m * 20 66-bit blocks.

10. The excitation generating device for HOF simulation verification according to claim 8, characterized in that, According to the shim_IF class of the respective interface types in the N-channel hof_tx_shim, when inserting an Overhead block into the data stream, an error injection mechanism is also introduced, including: when the error injection switch flag of any error injection type in the shim_IF class is turned on, an error is injected at the specified position according to the error injection type, and when the error injection quantity of any error injection type reaches the corresponding quantity threshold, the error injection switch flag of this error injection type is set to off.

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