A frequency adjustment method for internuclear migration

Abstract

The embodiment of the present application provides a frequency adjustment method for inter-core migration, in which when the electronic device determines that the expected computing power corresponding to the current load of the first processor core is greater than a first preset value, the first task in the first task queue of the first processor core is migrated to the second task queue of the second processor core, and the first computing power corresponding to the current frequency of the first processor core and the first migration type of the first task are recorded; when the electronic device schedules the first task in the second task queue, when it is determined that the first task is a new task of the first migration type, the first frequency of the second processor core corresponding to the first computing power is determined; when the current frequency of the second processor core is less than a second preset value, the frequency of the second processor core is adjusted to the first frequency, and the second preset value is determined based on the first frequency. In this way, the target processor core can be quickly increased in frequency after inter-core migration, and the response speed of the electronic device to inter-core migration tasks can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a frequency adjustment method for inter-core migration. Background Art

[0002] With the development of technology, electronic devices such as smart phones and tablets support more and more functions, and users can use various APPs on smart terminals. For electronic devices with multi-core processors, in order to ensure the performance of electronic devices and thus meet user experience, electronic devices need to perform resource scheduling and task scheduling based on the load conditions of each processor core. In traditional technology, electronic devices are generally based on the load (capacity) of the current task in the previous period of time, using load statistics algorithms to periodically count the load contribution of each task to the system, and perform resource scheduling based on the above load contribution. For example, the frequency of the processor core is adjusted; when the load of the current task executed by the processor core increases, the frequency of the processor core is increased, and when the load of the current task executed by the processor decreases, the frequency of the processor core is reduced. In summary, the load statistics of traditional technology have a certain hysteresis, and accordingly, the frequency adjustment also has a certain hysteresis.

[0003] For example, for electronic devices with multi-core CPUs, when CPU core 1 is overloaded, the tasks of CPU core 1 can be migrated to CPU core 2 with a lighter load. For tasks that require fast response, the current frequency modulation method cannot meet the performance requirements of the task after migration between cores. Summary of the invention

[0004] The present application provides a frequency adjustment method for inter-core migration, which can achieve rapid frequency increase of a target processor core after a task is migrated between cores, and effectively improve the response speed of an electronic device to an inter-core migration task.

[0005] In the first aspect, when the electronic device determines that the expected computing power corresponding to the current load of the first processor core is greater than a first preset value, the first task in the first task queue of the first processor core is migrated to the second task queue of the second processor core, and the first computing power corresponding to the current frequency of the first processor core and the first migration type of the first task are recorded; when the electronic device schedules the first task in the second task queue, when it is determined that the first task is a new task of the first migration type in the second task queue, the first frequency of the second processor core corresponding to the first computing power is determined; when the current frequency of the second processor core is less than the second preset value, the frequency of the second processor core is adjusted to the first frequency, and the second preset value is determined based on the first frequency.

[0006] Embodiment In the embodiment of the present application, when the electronic device determines that the computing power of the current processor core cannot meet the expected computing power corresponding to the current load, the first task in the task queue of the processor core is migrated to other target processor cores with stronger computing power, and the current computing power of the source processor core and the migration type of the task are recorded. In this way, when the electronic device schedules the first task, if it is determined that the first task is a new task of inter-core migration of the first migration type, the expected frequency of the target processor core is calculated based on the above current computing power, and when the current frequency of the target processor core is less than the expected frequency, the frequency of the target processor core is adjusted to the above expected frequency. In this way, the frequency of the target processor core is quickly increased after the inter-core migration, which effectively improves the response speed of the electronic device to the first task and avoids the jamming of the electronic device after the task migration.

[0007] In one possible implementation, when it is determined that the first task is a new task of the first migration type in the second task queue, the first frequency of the second processor core corresponding to the first computing capability is determined, including: when it is determined that the first task is a new task of the first migration type in the second task queue, and the first task is a task of the first type, the first frequency of the second processor core corresponding to the first computing capability is determined.

[0008] In the embodiment of the present application, the first type of task may refer to a critical task. The various tasks performed by the electronic device include critical tasks and non-critical tasks. The electronic device can perform resource management and control in different ways for critical tasks and non-critical tasks. The frequency adjustment method for inter-core migration provided in the embodiment of the present application is only performed for critical tasks, which can respond to critical tasks in a timely manner and maximize resource utilization.

[0009] In a possible implementation, the above-mentioned migration of the first task in the first task queue of the first processor core to the second task queue of the second processor core, and recording the first computing capability corresponding to the current frequency of the first processor core and the first migration type of the first task, includes: migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and determining the first computing capability corresponding to the current frequency of the first processor core when the first task performs context switching; recording in the context of the first task that the computing capability corresponding to the current frequency of the source processor core of the first task is the first computing capability, and the migration type of the first task is the first migration type. In this way, during the context switching process of the first task, the first computing capability and the first migration type are recorded in the context of the first task, which facilitates the recording of the above two parameters and subsequent calls.

[0010] In a possible implementation, the above-mentioned migration of the first task in the first task queue of the first processor core to the second task queue of the second processor core, and recording the first computing capability corresponding to the current frequency of the first processor core and the first migration type of the first task, includes: migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and when the first task performs context switching, determining the first computing capability corresponding to the current frequency of the first processor core and whether the first task is a task of the first type; recording in the context of the first task that the computing capability corresponding to the current frequency of the source processor core of the first task is the first computing capability, the migration type of the first task is the first migration type, and the first task information, the first task information is used to characterize whether the first task is a task of the first type. In this way, during the context switching process of the first task, the first computing capability, the first migration type, and the first task information are recorded in the context of the first task, which facilitates the recording of the above two parameters and subsequent calls.

[0011] The first computing capability, the first migration type, and the first task information are not limited to being recorded in the context of the first task. The embodiment of the present application may also record the above information in other storage modules, which is not specifically limited here.

[0012] In a possible implementation, when the first task is determined to be a new task of the first migration type in the second task queue, the first frequency of the second processor core corresponding to the first computing power is determined, including: when the first task is determined to be a new task in the second task queue, the migration type and the first task information of the first task are obtained from the context of the first task; when the migration type of the first task is determined to be the first migration type, and the first task information indicates that the first task is a task of the first type, the current computing power of the source processor core of the first task when the first task is migrated is obtained from the context of the first task, and the current computing power of the source processor core of the first task is the first computing power; the electronic device determines the first frequency of the second processor core corresponding to the first computing power. In this way, when the current frequency of the second processor core is less than the expected frequency of the first task (i.e., the first frequency), the frequency of the second processor core can be quickly adjusted to the above-mentioned expected frequency, so as to realize the rapid frequency increase of the second processor core after the first task is migrated between cores, so as to respond to the first task in a timely manner.

[0013] In one possible implementation, the electronic device records the running time of each task in the second task queue on the second processor core, and determines that the first task is a new task in the second task queue, including: when the running time of the first task recorded by the electronic device on the second processor core is zero, determining that the first task is a new task in the second task queue.

[0014] In a possible implementation, the first preset value is equal to the maximum computing capability of the first processor core; or, the first preset value is equal to k1 times the maximum computing capability of the first processor core, where k1 is greater than zero and less than 1. For example, k1 is 0.9.

[0015] In a possible implementation, the second preset value is equal to the first frequency; or, the second preset value is equal to k2 times the first frequency, where k2 is greater than zero and less than 1. For example, k2 is 0.95.

[0016] In one possible implementation, the first type of tasks includes tasks of a specified type and tasks that are strongly related to tasks of the specified type; or, the first type of tasks includes tasks of a specified type of applications corresponding to the top-level application group and the foreground group, and tasks that are strongly related to tasks of the specified type; the specified type of tasks includes at least one of a drawing task, a data download task, and a data upload task.

[0017] In one possible implementation, the first type of tasks include tasks of specified applications; or, the first type of tasks include tasks of specified applications corresponding to the top-level application group and the foreground group; the specified applications include at least one of a game application, a navigation application, and a video application.

[0018] In a second aspect, the present application provides a terminal, comprising one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program codes, and the computer program codes include computer instructions, and when the one or more processors execute the computer instructions, the communication device executes the method in any possible implementation of the first aspect.

[0019] In a third aspect, an embodiment of the present application provides a computer storage medium, including computer instructions, which, when executed on an electronic device, enables a communication device to execute a method in any possible implementation of the first aspect.

[0020] In a fourth aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer, enables the computer to execute a method in any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments of the present application will be described below.

[0022] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a CPU system architecture according to an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the structure of a control group tree provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of a periodic step-by-step frequency increase provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of increasing the frequency of a target CPU core after inter-core migration provided in an embodiment of the present application;

[0027] Figure 6 A schematic flow chart of a frequency adjustment method for inter-core migration provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of a WALT algorithm time window provided in an embodiment of the present application;

[0029] Figure 8 A schematic diagram of increasing the frequency of a target CPU core after inter-core migration provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of a software architecture provided for an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0032] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to be limitations on the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0034] First, the electronic device provided in the embodiments of the present application is introduced. Figure 1 The schematic diagram of the structure of the electronic device 100 is exemplarily shown.

[0035] The electronic device 100 may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, an in-vehicle device, a smart home device and / or a smart city device. The embodiments of the present application do not impose any special restrictions on the specific type of the electronic device.

[0036] The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0037] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0038] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

[0039] In the embodiment of the present application, the processor uses the rising edge of the clock pulse as a reference for executing instructions. Therefore, the higher the clock frequency of the processor, the more instructions the processor executes per unit time, and the faster the operating speed.

[0040] Among them, the CPU is the final execution unit for information processing and program running. The CPU mainly includes an arithmetic logic unit (ALU), a cache memory (Cache), and a bus (Bus) for data (Data), control and status that realize the connection between them. In computer architecture, the CPU is the core hardware unit that controls and allocates all hardware resources (such as memory, input and output units) and performs general operations. The operations of all software layers in the computer system will eventually be mapped to CPU operations through the instruction set. The CPU's operating frequency is an important parameter of CPU performance and is very important for improving the CPU's computing speed.

[0041] The processor (e.g., CPU) involved in the embodiments of the present application may be a multi-core processor, which means that two or more complete computing engines are integrated in one processor. In this case, the processor can support multiple processors on the system bus, and the bus controller provides all bus control signals and command signals. In the embodiments of the present application, the above computing engine may be referred to as a kernel or processor core.

[0042] In the embodiment of the present application, when the maximum computing power of processor core 1 cannot meet the expected computing power corresponding to the current load of processor core 1, electronic device 100 can migrate task 1 in processor core 1 to processor core 2 with a lower load, and record the current computing power of processor core 1 and the migration type of task 1 when switching task context. Based on the current computing power of processor core 1 and the migration type of task 1, electronic device 100 can achieve rapid frequency increase after task migration, effectively improving the response speed of electronic device to tasks migrated between cores, especially the response speed of key tasks migrated between cores.

[0043] The controller may be the nerve center and command center of the electronic device 100. The controller may generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0044] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0045] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0046] The USB interface 130 is an interface that complies with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge the electronic device 100, and can also be used to transfer data between the electronic device 100 and a peripheral device. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.

[0047] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0048] The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. While the charging management module 140 is charging the battery 142, it may also power the electronic device through the power management module 141.

[0049] The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0050] The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

[0051] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0052] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0053] The modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a receiver 170B, etc.), or displays an image or video through a display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0054] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0055] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0056] The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0057] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.

[0058] The electronic device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

[0059] ISP is used to process the data fed back by camera 193. For example, when taking a photo, the shutter is opened, and the light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to ISP for processing and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, ISP can be set in camera 193.

[0060] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0061] The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0062] Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0063] NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. Through NPU, applications such as intelligent cognition of electronic device 100 can be realized, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0064] The internal memory 121 may include one or more random access memories (RAM) and one or more non-volatile memories (NVM).

[0065] Random access memory may include static random-access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM, for example, the fifth generation DDR SDRAM is generally referred to as DDR5 SDRAM), etc.

[0066] Non-volatile memory may include disk storage devices and flash memory.

[0067] Flash memory can be divided into NOR FLASH, NAND FLASH, 3D NAND FLASH, etc. according to the operating principle; single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc. according to the storage unit potential level; universal flash storage (UFS), embedded multi media card (eMMC), etc. according to the storage specification.

[0068] The random access memory can be directly read and written by the processor 110, and can be used to store executable programs (such as machine instructions) of the operating system or other running programs, and can also be used to store user and application data.

[0069] The non-volatile memory may also store executable programs and user and application data, etc., and may be loaded into the random access memory in advance for direct reading and writing by the processor 110 .

[0070] The external memory interface 120 can be used to connect to an external non-volatile memory to expand the storage capacity of the electronic device 100. The external non-volatile memory communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music and videos are stored in the external non-volatile memory.

[0071] The electronic device 100 can implement audio functions such as music playing and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0072] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the concepts that may be involved are briefly introduced below.

[0073] Task migration: For an operating system with a single processor core, task scheduling only needs to solve the problem of switching between different tasks. For an operating system with multiple processor cores, in addition to implementing switching between different tasks of the same processor core, task scheduling also includes processing the allocation of multiple tasks on multiple processor cores and task migration between different processor cores. Among them, task migration means that the electronic device 100 migrates task 1 from the task queue of processor core 1 to the task queue of processor core 2 based on one or more information such as the load of task 1 in processor core 1, the grouping of task 1, the running status of task 1, and the load information of processor core 1. Task migration can be for the purpose of achieving load balancing between different processor cores, or for the purpose of quickly meeting the resource requirements of a specific task, and the embodiments of the present application do not specifically limit this.

[0074] Big cores and small cores: Due to the constraints of heat dissipation and power consumption, hardware devices such as processors cannot continue to operate at high-performance operating frequencies. In order to better balance the relationship between performance and power consumption, a big-small core architecture, such as the Big.LITTLE architecture, was introduced. Generally, the big cores in the big-small core architecture refer to processor cores with higher power consumption and better performance, and the small cores in the big-small core architecture refer to processor cores with lower power consumption and lower performance. The main frequencies of big cores and small cores are different. For the same amount of tasks, the execution time of small cores is much higher than that of large cores. In some big-small core architectures, in addition to big cores and small cores, medium cores can also be included. The performance of medium cores is higher than that of small cores and lower than that of large cores, and the power consumption of medium cores is higher than that of small cores and lower than that of large cores.

[0075] In some embodiments of the present application, when allocating a new task, the electronic device 100 may first allocate the new task to the small core; then, the electronic device 100 schedules the task by tracking the load changes of the task. When the load of the task in the small core is too heavy, the task can be migrated from the small core to the medium core or the large core for execution; when the load of the task in the medium core is too heavy, the task can be migrated from the medium core to the large core for execution; in this way, the resource requirements of the task can be met in a timely manner to obtain a better performance experience. Conversely, when the load of the task in the large core decreases, the task can also be migrated from the large core to the medium core or the small core for execution; when the load of the task in the medium core decreases, the task can also be migrated from the medium core to the small core for execution; in this way, while ensuring the operating rate, power consumption can also be saved.

[0076] In one implementation, when a task is overloaded in a small core, the task can be migrated from the small core to the medium core. When the medium core cannot meet the resource requirements of the task, the task is migrated from the medium core to the large core. In another implementation, for a task that requires a quick response, when the task is overloaded in a small core, the task can be directly migrated from the small core to the large core to quickly meet the resource requirements of the task and avoid freezing of the electronic device. This application embodiment does not specifically limit this.

[0077] The multi-core processor involved in the embodiment of the present application can be a multi-core CPU or other multi-core processors, which are not specifically limited here. The following takes a multi-core CPU as an example to introduce the frequency adjustment method for inter-core migration provided by the embodiment of the present application.

[0078] First, the system architecture of the multi-core CPU scheduling system is introduced.

[0079] Figure 2 The system architecture of the CPU scheduling system involved in this application is exemplified. Figure 2 As shown, the system includes a CPU run queue (CPU Runqueue), a context switch (Context Switch), a main scheduler (Mainscheduler), a periodic scheduler (Tick scheduler), a load balancer (Load balancer), a deadline scheduler (Deadline scheduler, DL), a polling scheduler (realtime scheduler, RT), a completely fair scheduler (Completely fair scheduler, CFS), an idle scheduler (Idle scheduler) and a preemptive scheduler (stopscheduler). Figure 2 The CPU scheduling system shown may also include a custom scheduler. In the embodiment of the present application, the CPU core may also be referred to as CPU.

[0080] Each CPU (or each CPU core in a multi-core CPU) maintains a run queue. Each run queue can include one or more processes in a sleep state or a runnable state. The runnable state means that the process is running on the CPU or waiting in the run queue for the CPU to schedule it to run. A process can contain several threads. The process is the basic unit of operating system resource allocation, while the thread is the basic unit of task scheduling and execution. The scheduling entity corresponding to a task can be a process or a thread.

[0081] In the embodiment of the present application, the task queue of the CPU may include a running queue, a waiting queue and a ready queue. When a process has the running conditions but cannot run because it does not occupy the CPU, the process is in a ready state and is located in the ready queue; when a process cannot run due to its own reasons and must wait for a certain event to occur before it has the running conditions, the process is in a waiting state and is located in the waiting queue. The process can switch between the runnable state, the ready state and the waiting state.

[0082] The scheduler is used to allocate CPU time slices to each task, minimize the response time for real-time tasks, and maximize the overall CPU utilization. The scheduler includes the main scheduler and the periodic scheduler. The main scheduler is used to activate the scheduling class to perform task scheduling when the process enters the sleep state or abandons the current CPU for other reasons; the periodic scheduler is used to activate the scheduling class responsible for the current process at a fixed frequency to perform task scheduling to ensure the concurrency of the system.

[0083] The CPU context includes information about the CPU registers and the program counter. The CPU register is the smallest but fastest memory built into the CPU. The program counter is used to store the location of the instruction that the CPU is executing or the location of the next instruction to be executed. Context switching means saving the context of the previous task in the system kernel, then loading the context of the new task into these registers and the program counter, and finally jumping to the location indicated by the program counter to run the new task.

[0084] Currently, the CPU scheduling system includes Figure 2 The five scheduling classes shown are stop_sched_class, dl_sched_class, rt_sched_class, fair_sched_class, and idle_sched_class. Each scheduling class can correspond to a different scheduling strategy, and the scheduling strategies of different categories of processes are different. The CPU can perform task scheduling in the following four situations: (1) when a process switches from the running state to the waiting state; (2) when a process switches from the running state to the ready state; (3) when a process switches from the waiting state to the ready state; (4) when a process terminates.

[0085] In an embodiment of the present application, the electronic device 100 can schedule tasks in the task queue in combination with the computing power of the CPU. The computing power of the CPU is a quantification (normalize) of the CPU performance, and the current computing power of the CPU is determined according to the frequency at which the CPU is currently running. In one implementation, the maximum computing power corresponding to the highest frequency of the most powerful CPU in a multi-core CPU is set to 1024, and then the computing power corresponding to the highest frequency is used as a benchmark to quantify the computing power corresponding to each frequency point of the CPU and other CPUs. For example, when the frequency of the CPU is half of the highest frequency, the computing power of the CPU is equal to 512. It can be understood that in order to facilitate task scheduling between CPUs, the operating system of the electronic device 100 can numerically quantify the computing power of different CPUs at different frequency points, and through the current computing power value of the CPU, the frequency at which the CPU is currently running can also be inferred.

[0086] In the embodiment of the present application, the electronic device 100 can group all processes through a control group (cgroup), and then allocate and control resources for the entire group. Specifically, each cgroup may include one or more processes, or may not include any process. For example, Figure 3 A schematic diagram of a hierarchy is shown. The hierarchy can be understood as a cgroup tree with a hierarchical relationship. Each node of the tree is a cgroup. Figure 3 , exemplarily, the process tree includes a top-app group, a foreground group, a system-background group, and a background group. In the Android system, based on the foreground and background states of applications (also called tasks or processes), applications can be divided into different cgroups, so that the scheduler class corresponding to the cgroup to which the application belongs is executed.

[0087] The electronic device 100 can indicate the CPU bound to the cgroup through cpuset, and can also select the bound CPU core through schedtune, that is, schedtune can indicate that the cgroup is bound to the large-core CPU, the medium-core CPU and / or the small-core CPU, so that the electronic device 100 can schedule different cgroups through CPU cores with different processing capabilities.

[0088] In the embodiment of the present application, the electronic device 100 can adjust the frequency of the CPU core according to the load of the CPU core. For example, when the electronic device 100 determines that the load of a CPU core is large, the frequency of the CPU core can be increased, and when the electronic device 100 determines that the load of a CPU core is small, the frequency of the CPU core can be reduced.

[0089] The user's operation on the electronic device 100 is sudden and intermittent, and the corresponding task's demand for resources is also sudden and short-term high demand. However, the current load statistics algorithm (such as PELT and WALT) adopts a periodic accumulation calculation method, that is, based on the load of each task that has been executed for a period of time, the current CPU core load (i.e. cpu_util, for the sake of convenience, referred to as the current load of the CPU core in the following text) is periodically counted. This causes the load statistics to have a certain lag, and the actual load mutation requires a certain period of time before it can be fed back in the data, which in turn causes the CPU core frequency increase to also present a periodic step-by-step increase. Since the load statistics cycle for counting the current load of the CPU core is often long (for example, the load statistics cycle corresponding to the WALT algorithm is 20ms by default), the frequency increase speed is slower. In particular, for short-term high-demand tasks such as user interface (UI) related tasks (such as drawing tasks), the current load statistics algorithm cannot meet the rapid response requirements of the above tasks. Exemplarily, a task is added to an idle CPU core, and the load statistics are performed using the WALT algorithm. As the load is periodically counted, the frequency of the CPU core will show Figure 4 The periodic step-by-step increase shown.

[0090] For example, Figure 5 As shown, when CPU core 1 runs task 1, if it is determined that the computing power of CPU core 1 (such as a small-core CPU) cannot bear the load of all tasks in the task queue of CPU core 1, the scheduler can migrate task 1 to CPU core 2 (such as a large-core CPU) with stronger computing power. Since the load statistics algorithm uses a periodic accumulation calculation method, the actual load change requires a certain period of time to be fed back in the data. Therefore, if the current load of CPU core 2 is small (correspondingly, the frequency is also low) before task 1 is added to the task queue of CPU core 2, then after task 1 is added to the task queue of CPU core 2, CPU core 2 starts running task 1 for multiple load statistics cycles. The load imposed on the CPU by task 1 can be close to the actual load of task 1. Correspondingly, the adjusted frequency of CPU core 2 can meet the frequency required by task 1 at this time. See. Figure 5After task 1 is migrated to CPU core 2, the frequency increase speed of CPU core 2 is slow and cannot quickly meet the needs of task 1. In this way, the electronic device 100 responds slowly to task 1, and the electronic device 100 may freeze when CPU core 2 runs task 1.

[0091] The embodiment of the present application provides a frequency adjustment method for inter-core migration. When the electronic device 100 determines that the maximum computing power of the current CPU core cannot meet the expected computing power corresponding to the current load of the CPU core, task 1 in the task queue of the CPU core is migrated to other target CPU cores with stronger computing power and lower load, and the current computing power of the source CPU core of task 1 and the migration type of task 1 (i.e., the first migration type) are recorded. When the electronic device 100 schedules task 1, if it is determined that task 1 is a new task of inter-core migration of the first migration type, the electronic device 100 calculates the expected frequency of the corresponding target CPU core based on the above current computing power 1, and then adjusts the frequency of the target CPU core to the above expected frequency. In this way, the rapid frequency increase of the target CPU core after inter-core migration is achieved, which effectively improves the response speed of the electronic device 100 to task 1 and avoids the jamming of the electronic device 100 after task migration. The frequency adjustment method for inter-core migration provided by the embodiment of the present application is described in detail below.

[0092] For example, Figure 6 The flowchart of the frequency adjustment method for inter-core migration provided by the embodiment of the present application is shown, and the proposed method includes but is not limited to steps S101 to S107.

[0093] S101 . The electronic device 100 counts the expected computing capacity 1 corresponding to the current load 1 of the CPU core 1 .

[0094] In an embodiment of the present application, a load statistics algorithm (such as a PLET algorithm and a WALT algorithm) is used to periodically count the current load of the CPU core 1, and the expected computing capacity of the CPU core 1 corresponding to the current load of the CPU core 1 is determined.

[0095] It should be noted that the PLET algorithm and the WALT algorithm track the load for the scheduling entity (i.e., process or thread) corresponding to each task, and the current load of each CPU core is the statistical value of the load corresponding to all tasks in the task queue of the CPU core. Tasks of different priorities impose different loads on the system. The PELT algorithm and the WALT algorithm both consider the priority of each task. The statistical value of the load corresponding to all the above tasks can be a weighted statistical value of the load corresponding to each task, and the load weight of each task is determined based on the priority of the task.

[0096] In some embodiments, the electronic device 100 uses the WALT algorithm to perform load statistics. The WALT algorithm divides time into multiple time windows according to a certain time length, and can predict the window load of a task in the current time window based on the load of the task in the previous N time windows. For example, see Figure 7 , a time window size (WINDOW_SIZE) is 20ms, and each time window includes 5 time windows. Step S101 may specifically include steps S1 to S4. Among them:

[0097] S1. The electronic device 100 periodically counts the window load of task 1 in the task queue of CPU core 1 in each time window.

[0098] In some embodiments, based on the physical time that task 1 is in an executable state on CPU core 1 within a time window, electronic device 100 can confirm the window load of task 1 in the time window (the window load can also be referred to as walt_time). In one implementation, the window load of task 1 in the time window can be expressed as delta*(cur_freq 1 / max_freq)*(cur_IPC 1 / max_IPC).

[0099] Among them, delta represents the physical time that task 1 is in an executable state on CPU core 1 within the time window, cur_freq1 represents the current frequency of CPU core 1, max_freq represents the maximum CPU frequency in a multi-core CPU system, cur_IPC1 represents the computing efficiency of CPU core 1, and Max_IPC represents the maximum computing efficiency in a multi-core CPU system.

[0100] It should be noted that the computing efficiency of each CPU core is a fixed value determined in advance based on hardware performance. Usually, the electronic device 100 stores a file containing the computing efficiency of each CPU core, and the electronic device 100 can obtain the computing efficiency of CPU core 1 and the above maximum computing efficiency by querying the above file.

[0101] S2. At the start time of time window 1, based on the window loads of task 1 in the first N time windows of time window 1, the electronic device 100 determines the task demand value of task 1 in time window 1 using a specified value selection strategy.

[0102] In an embodiment of the present application, the value-taking strategy may include: taking the average value, taking the most recent value, taking the maximum value between the average value and the most recent value, taking the maximum value, and taking the minimum value. The electronic device 100 may configure the value-taking strategy of the WALT algorithm through the user-state configuration interface. The electronic device 100 may determine which negative value-taking strategy to use based on different system performance, power consumption requirements, etc., which is not specifically limited here. It should be noted that the task demand (task demand) of task 1 in time window 1 determined by the electronic device 100 using the specified value-taking strategy is the window load of task 1 in time window 1 predicted by the electronic device 100.

[0103] For example, Figure 7 As shown in the figure, N is 5, and the statistical window loads of task 1 in the first five time windows of time window 1 are 7, 14, 3, 6, and 9 respectively. For the five value-taking strategies of taking the average value, taking the most recent value, taking the maximum value between the average value and the most recent value, taking the maximum value, and taking the minimum value, the corresponding task demand values ​​of task 1 in time window 1 are 14, 7.8, 9, 9, and 3 respectively.

[0104] S3. Predict the current load 1 of CPU core 1 based on the task requirements of all tasks in the task queue of CPU core 1 in time window 1.

[0105] In some embodiments, the current load of CPU core 1 is a weighted statistical value of the task demand values ​​of all tasks in the task queue of CPU core 1 in time window 1 .

[0106] S4. Determine the expected computing capacity 1 corresponding to the current load 1 of the CPU core 1.

[0107] In some embodiments, the expected computing capacity 1 can be expressed as cpu_util 1*max_capacity / WINDOW_SIZE, where cpu_util 1 represents the current load 1, and max_capacity represents the maximum computing capacity value in a multi-core CPU system. For example, the default maximum computing capacity value is 1024.

[0108] In some embodiments, when the electronic device 100 uses the WALT algorithm to perform load statistics, the electronic device 100 adds the task requirement value of each task to the curr_runnable_sum member of the task queue of CPU core 1, and curr_runnable_sum saves the weighted statistical value of the task requirement values ​​of all tasks in the task queue within time window 1, that is, the current load 1.

[0109] In the embodiment of the present application, when the electronic device 100 uses the WALT algorithm to perform load statistics, the walt_time of each task in CPU core 1 within a time window is added to the prev_runnable_sum member. Within time window 1, pre_runnable_sum will save the sum of the total window loads of all tasks in the task queue of CPU core 1 in the previous time window of time window 1.

[0110] It should be noted that the present embodiment is not limited to the WALT algorithm and the PELT algorithm. Other load statistics algorithms may also be used to count the current load of the CPU core 1, which is not specifically limited here.

[0111] S102 . When the expected computing power 1 of CPU core 1 is greater than a first preset value, task 1 in the task queue of CPU core 1 is migrated, and the electronic device 100 determines that the target CPU core of task 1 is CPU core 2 based on the expected computing power 2 of task 1 .

[0112] In some embodiments, the first preset value is determined based on the maximum computing power of CPU core 1. In one implementation, the first preset value is equal to the maximum computing power of CPU core 1. In one implementation, the first preset value is equal to k1 times the maximum computing power of CPU core 1, where k1 is greater than zero and less than 1. For example, k1 is 0.9. In the embodiments of the present application, the first preset value may also be other values ​​associated with the maximum computing power, which is not specifically limited here.

[0113] In some embodiments, the small core CPU, the medium core CPU and the large core CPU each correspond to a preset fixed value. When CPU core 1 is a small core (or medium core, large core) CPU, the first preset value is the preset fixed value corresponding to the small core (or medium core, large core) CPU.

[0114] In some embodiments, the first preset value is equal to the maximum computing power of CPU core 1. When CPU core 1 schedules task 2, if it is determined that the expected computing power 1 of CPU core 1 is less than or equal to the maximum computing power of CPU core 1, the electronic device 100 adjusts the frequency of CPU core 1 based on the expected computing power 1 and runs task 2; if the maximum computing power of CPU core 1 is less than the expected computing power 1 of CPU core 1, task migration is performed on task 1 in the task queue of CPU core 1, and task 1 is inserted into the ready queue of the target CPU core. In one implementation, task 1 may be the most heavily loaded task in the task queue of CPU core 1 (e.g., the task with the largest task demand value in the current time window); in one implementation, task 1 may be the most heavily loaded critical task in the task queue of CPU core 1.

[0115] In some embodiments, the electronic device 100 determines the target CPU core of task 1 based on the expected computing capacity 2 of task 1, which may specifically include steps S5 to S7. Among them:

[0116] S5. The electronic device 100 determines the expected computing capacity 2 of task 1 based on the task requirement value of task 1 in the current time window.

[0117] In one implementation, the expected computing capacity 2 of task 1 may be expressed as demand 1*1024 / WINDOW_SIZE, where demand 1 represents the task demand value of task 1 in the current time window.

[0118] S6 . The electronic device 100 determines the control group 1 based on the expected computing capacity 2 of the task 1 .

[0119] It should be noted that, in the embodiment of the present application, the maximum computing capacity of a control group is the maximum computing capacity of one or more CPUs bound to the control group.

[0120] In some embodiments, the electronic device 100 determines at least one control group whose maximum computing power is greater than 125% of the expected computing power 2, and control group 1 is one of the at least one control group. In one implementation, the control group 1 is the control group with the smallest maximum computing power among the at least one control group.

[0121] S7. Determine CPU core 2 bound to control group 1 as the target CPU core for task 1 based on the task demand value of task 1 in the current time window.

[0122] In some embodiments, the electronic device 100 determines at least one CPU core among the CPU cores bound to the control group 1 that satisfies the following conditions: the maximum computing power of the CPU core is greater than (demand 1+pre_runnable_sum 1)*1024 / WINDOW_SIZE. Wherein, pre_runnable_sum 1 represents the sum of the window loads of all tasks in the task queue of the CPU core in the previous time window, and CPU core 2 is one of the at least one CPU core. In one implementation, the CPU core 2 is the CPU core with the smallest maximum computing power among the at least one CPU core. In one implementation, the CPU core 2 is the CPU core with the largest maximum computing power among the at least one CPU core.

[0123] The method for determining the target CPU core provided in the optional embodiment of step S102 is not limited thereto. The embodiment of the present application may also determine the target CPU core of task 1 by other methods, which are not specifically limited here.

[0124] It should be noted that when the CPU core 1 on which task 1 is currently running is a small-core CPU, the electronic device 100 can first determine the target CPU core for task 1 in the medium-core CPU. When the medium-core CPU cannot meet the resource requirements of task 1, the electronic device 100 determines the target CPU core for task 1 in the large-core CPU; or, when the CPU core 1 on which task 1 is currently running is a small-core CPU, the electronic device 100 can directly determine the target CPU core for task 1 in the large-core CPU to quickly meet the resource requirements of task 1 and avoid power consumption and time loss caused by frequent context switching.

[0125] S103 , migrating task 1 to the task queue of CPU core 2 . During the CPU context switching process of task 1 , the electronic device 100 records the current computing capability 1 of CPU core 1 and the migration type of task 1 into the context of task 1 .

[0126] In the embodiment of the present application, during the CPU context switching process, the electronic device 100 obtains the current computing power 1 corresponding to the current frequency of the CPU core 1.

[0127] In one implementation, the current computing capacity 1 corresponding to the current frequency of CPU core 1 is calculated, and the current computing capacity 1 can be expressed as (cur_freq 1 / cpu_max_freq 1)*cpu_capacity_org1. Among them, cpu_max_freq 1 represents the maximum frequency of CPU core 1, and cpu_capacity_org1 represents the relative computing capacity of CPU core 1 relative to the largest core in the multi-core CPU.

[0128] cpu_capacity_org1 can be expressed as cpu_scale 1*cpu_max_freq 1 / max_freq, where cpu_scale1 represents the maximum computing capacity of CPU core 1.

[0129] In one implementation, for a multi-core CPU system, the electronic device 100 stores a file including the maximum computing capabilities of each CPU core, and the electronic device 100 can usually query the above file to obtain the maximum computing capability of CPU core 1.

[0130] In one implementation, the electronic device 100 stores a table of mapping relationships between the frequency and computing power of each CPU core, and the electronic device 100 can query the computing power corresponding to the current frequency of the CPU core 1 according to the table.

[0131] In an embodiment of the present application, when the electronic device 100 schedules tasks in the task queue of CPU core 1, it can determine to perform inter-core task migration for tasks in the task queue of CPU core 1 based on one or more information such as the load of the currently executing task (e.g., task 1), grouping (e.g., task 1 corresponds to the control group), operating status, and current load of CPU core 1.

[0132] In some embodiments, CPU core 1 may perform inter-core task migration including but not limited to the following two situations: (1) when the computing power of CPU core 1 cannot meet the expected computing power of the current load of CPU core 1 (i.e., the above expected computing power is less than the first preset value), migrate the heavier load task to the task queue of other CPU cores with greater computing power; (2) when the task queue of CPU core 2 is empty, actively pull the task in the task queue of CPU core 1. In one implementation, the above different situations correspond to different migration types. When the electronic device 100 performs task migration of task 1 in any situation, the migration type corresponding to the situation is recorded in the context of task 1. In one implementation, when the electronic device 100 performs task migration of task 1 based on the above situation 1, the migration type corresponding to the situation is recorded in the context of task 1, and other situations are not recorded. In the embodiment of the present application, the migration type corresponding to the above situation 1 can be called the first migration type, and the migration type corresponding to the above situation 2 can be called the second migration type.

[0133] In one implementation, when the electronic device 100 schedules a task in the task queue of the CPU core, the electronic device 100 records the first identification information in the context of the task. The first identification information is used to characterize whether the task is an inter-core migration task and the specific migration type. For example, when the first identification information of task 1 is 0, it characterizes that task 1 is an inter-core migration task, and when the first identification information of task 1 is greater than 0, it characterizes that task 1 is not an inter-core migration task; specifically, when the first identification information of task 1 is 1, it can characterize that task 1 is of the first migration type, and when the first identification information of task 1 is 2, it can characterize that task 1 is of the second migration type.

[0134] In one implementation, when the electronic device 100 schedules a task in the task queue of the CPU core, the electronic device 100 records the second identification information and the third identification information in the context of the task. The second identification information is used to record whether the task is a task that is migrated between cores. For example, when the second identification information of task 1 is 1, it indicates that task 1 is a task that is migrated between cores. When the second identification information of task 1 is 0, it indicates that task 1 is not a task that is migrated between cores. The third identification information is used to record the migration type of the task. For example, when the third identification information of task 1 is 0, it indicates that task 1 is of the first migration type. When the third identification information of task 1 is 1, it indicates that task 1 is of the second migration type.

[0135] In some embodiments, during the CPU context switching process of task 1, the electronic device 100 records the current computing power 1 of CPU core 1, the migration type of task 1, and the first task information into the context of task 1, and the first task information is used to characterize whether task 1 is a critical task.

[0136] In the embodiment of the present application, various tasks corresponding to all applications of the electronic device 100 can be divided into critical tasks and non-critical tasks. For critical tasks and non-critical tasks, different resource management and control methods can be performed to maximize resource utilization.

[0137] In some embodiments, the electronic device 100 determines whether the task is a critical task based on the control group corresponding to the task. Figure 3 The tasks of the applications corresponding to the top-app group shown are determined as critical tasks, and the tasks corresponding to the other control groups are determined as non-critical tasks. Figure 3 The tasks of the applications corresponding to the top-app group and the foreground group are determined as critical tasks, and the tasks corresponding to other control groups are determined as non-critical tasks.

[0138] In some embodiments, the electronic device 100 determines whether the task is a critical task based on the task type of the task. In one implementation, tasks of a specified type and tasks that are strongly related to the specified type of tasks are determined as critical tasks, and tasks of other types are determined as non-critical tasks. Figure 3 Among the tasks of the applications corresponding to the top-app group and the foreground group shown, tasks of a specified type and tasks strongly related to the above specified type of tasks are determined as critical tasks, and tasks of other types and tasks corresponding to other control groups are determined as non-critical tasks.

[0139] In the embodiment of the present application, the above-mentioned specified types of tasks may include tasks that are more user-perceived, such as UI-related drawing tasks, etc. Exemplarily, when the electronic device 100 detects user operations involving animations such as sliding and dragging, it is determined that the drawing task corresponding to the operation is a critical task, and the electronic device 100 responds to such operations first to reduce the sense of lag in the interface display. In one implementation, the above-mentioned specified types of tasks may also include data download tasks, data upload tasks, etc.

[0140] In some embodiments, the electronic device 100 determines whether the task is a critical task based on the application to which the task corresponds. In one implementation, the task corresponding to a specified application (such as a game application and a navigation application) is determined as a critical task, and the tasks of other applications are determined as non-critical tasks. Figure 3 Among the applications corresponding to the top-app group and foreground group shown, tasks of designated applications (such as game applications, navigation applications, etc.) are determined as critical tasks, and tasks of other applications and tasks of applications corresponding to other control groups are determined as non-critical tasks.

[0141] In some embodiments, the electronic device 100 collects average historical load data of each task, and determines whether the task is a critical task based on the average historical load data of each task, wherein the average historical load data of each task may include task loads of M load statistical cycles. In one implementation, when the variance of the historical load data of a task is greater than a preset value, the task is determined to be a critical task, otherwise it is a non-critical task. In one implementation, Figure 3 Among the tasks of the applications corresponding to the top-app group and the foreground group shown, the tasks whose variance of historical load data is greater than or equal to a preset value are determined as critical tasks, and the tasks whose variance of historical load data is less than a preset value and the tasks corresponding to other control groups are determined as non-critical tasks.

[0142] In some embodiments, the electronic device 100 stores the first file locally, or the electronic device 100 can obtain the first file online. The first file is used to store identification information corresponding to each task of all applications of the electronic device 100, and attribute information of whether the task is a critical task. When task 1 is migrated between cores, it can be queried from the first file whether task 1 is a critical task based on the identification information of task 1.

[0143] In some embodiments, the electronic device 100 stores a second file locally, or the electronic device 100 can first obtain the second file. The second file is used to store identification information corresponding to each task of all applications of the electronic device 100, as well as the priority of the task. When task 1 is migrated between cores, the priority of task 1 can be queried from the second file based on the identification information of task 1, and whether task 1 is a critical process can be determined based on the priority of task 1. For example, when the task priorities in the electronic device 100 include 1 to N, tasks with priorities less than a threshold value 1 are classified as critical tasks, and tasks with priorities greater than or equal to the threshold value 1 are classified as non-critical tasks.

[0144] It should be noted that the determination method of key tasks and non-key tasks is not limited to the above, and in the embodiment of the present application, other methods can be used to determine whether task 1 is a key task, which is not specifically limited here. In some embodiments, the electronic device 100 can also adopt a combination of multiple determination methods in the above embodiments.

[0145] S104, when calling task 1 in the task queue of CPU core 2, determine whether task 1 is a new task for CPU core 2. If so, execute S105.

[0146] In the embodiment of the present application, when scheduling tasks in the task queue of CPU core 2, the running time (e.g., physical running time) of the task in CPU core 2 can be accumulated. In one implementation, if the running time of a task in CPU core 2 is zero, it can be determined that the task is a new task in the task queue of CPU core 2 that has not been run.

[0147] It should be noted that when task 1 is migrated from CPU core 1 to CPU core 2, the physical running time of task 1 on CPU core 1 will be reset.

[0148] S105 . When it is determined based on the context of task 1 that task 1 is an inter-core migration task and the migration type of task 1 is the first migration type, the current computing capability of the source CPU core in the context of task 1 is obtained.

[0149] It should be noted that task 1 migrates from CPU core 1 to CPU core 2, then CPU core 1 is the source CPU core of task 1, and CPU core 2 is the target CPU core of task 1. It can be understood that the current computing capacity of the source CPU core in the context of task 1 is the current computing capacity 1 of the aforementioned CPU core 1.

[0150] In some embodiments, when the migration type of task 1 is determined to be the first migration type based on the migration type recorded in the context of task 1, and task 1 is determined to be a critical task based on the first task information recorded in the context of task 1, the current computing power of the source CPU core in the context of task 1 is obtained.

[0151] In one implementation, the electronic device 100 does not record the first task information in the context of Task 1 in step S103 , and the electronic device 100 may identify whether the task is a critical task after confirming that Task 1 is a new task and before step S105 .

[0152] In the embodiment of the present application, after the critical task is migrated between cores, the electronic device 100 can adjust the frequency of the target CPU core based on the computing power of the source CPU core of the task to quickly meet the resource requirements of the critical task and effectively improve the user experience. For the inter-core migration of non-critical tasks, the electronic device 100 can adjust the frequency of the target CPU core based on the traditional algorithm to save resources.

[0153] The current computing capability 1 of CPU core 1, the migration type of task 1, and the first task information of task 1 are not limited to being recorded in the context of task 1, but can also be recorded in other storage modules, which is not specifically limited in the embodiment of the present application. For example, if it is recorded in storage module 1, correspondingly, in step S105, the electronic device 100 can obtain the current computing capability 1 of CPU core 1, the migration type of task 1, and the first task information of task 1 from storage module 1.

[0154] S106 , determining a first frequency of the CPU core 2 corresponding to the current computing capability of the source CPU core.

[0155] In one implementation, the first frequency of the corresponding CPU core 2 is calculated based on the current computing capacity 1 of the CPU core 1, and the first frequency can be expressed as (cur_capacity 1 / cpu_capacity_org 2)*cpu_max_freq 2. Wherein, cur_capacity 1 represents the current computing capacity 1 of the CPU core 1, cpu_max_freq 2 represents the maximum frequency of the CPU core 2, and cpu_capacity_org 2 represents the relative computing capacity of the CPU core 1 relative to the maximum core in the multi-core CPU.

[0156] cpu_capacity_org 2 can be expressed as cpu_scale 2*cpu_max_freq 1 / max_freq, where cpu_scale 2 represents the maximum computing capacity of CPU core 2.

[0157] In one implementation, the electronic device 100 stores a table of mapping relationships between the frequencies of each CPU core and the computing capabilities, and the electronic device 100 can query the first frequency of the CPU core 2 corresponding to the current computing capability 1 according to the table.

[0158] S107 . When the current frequency of the CPU core 2 is less than a second preset value, adjust the frequency of the CPU core 2 to a first frequency, where the second preset value is determined based on the first frequency.

[0159] The second preset value is equal to the first frequency; or the second preset value is equal to k2 times the first frequency, where k2 is greater than zero and less than 1. For example, k2 is 0.95. In the embodiment of the present application, the second preset value may also be other values ​​associated with the first frequency, which are not specifically limited here.

[0160] In the embodiment of the present application, when the first frequency is less than or equal to the current frequency of the CPU core 2, the CPU core 2 continues to adjust the frequency based on the load counted by the load statistics algorithm.

[0161] For example, Figure 8 As shown, when CPU core 1 runs task 1, the electronic device 100 determines that the maximum computing capacity of CPU core 1 cannot meet the expected computing capacity corresponding to the current load of CPU core 1; the electronic device 100 migrates task 1 to CPU core 2 with a lower load, and records the current computing capacity 1 of CPU core 1 and the first migration type of task 1 when switching task contexts. Figure 8 , when task 1 migrates to CPU core 2, the frequency of CPU core 2 is lower. When the electronic device 100 schedules task 1, it determines that task 1 is a new task of the first migration type of inter-core migration; the electronic device 100 calculates the expected frequency (i.e., the first frequency) of the corresponding CPU core 2 based on the above current computing power 1 recorded in the context of task 1; because the current frequency of CPU core 2 is less than the above expected frequency, the electronic device 100 increases the frequency of CPU core 2 to the above expected frequency. Rapid frequency increase for inter-core migration tasks of the first migration type is achieved, which effectively improves the response speed of the electronic device 100 and avoids the jamming of the electronic device 100 after task migration.

[0162] In an embodiment of the present application, the first processor core may be the aforementioned CPU core 1, the first task queue may be the task queue of CPU core 1, the first task may be the aforementioned task 1, and the first computing capability of the first processor core may be the aforementioned current computing capability 1; the second processor core may be the aforementioned CPU core 2, and the second task queue may be the task queue of CPU core 2; the first type of task may also be referred to as a critical task.

[0163] In the embodiment of the present application, the software system of the electronic device 100 can adopt a layered architecture, an event-driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture. The embodiment of the present application takes the Android system of the layered architecture as an example to exemplify the software structure of the electronic device 100.

[0164] See also Fig. 9 , Fig. 9FIG. 1 shows a software structure block diagram of an electronic device 100 exemplarily provided in an embodiment of the present application. Fig. 9 The software structure block diagram shown, for the inter-core task migration of the first migration type, records the current computing power of the source CPU core when the task performs context switching; when the target CPU core schedules the task, determines that the task is a new task of the first migration type in the target CPU task queue; the target CPU determines the expected frequency of the target CPU corresponding to the current computing power based on the current computing power of the CPU core in the context of the task; and the target CPU adjusts the frequency based on the expected frequency.

[0165] like Fig. 9 As shown, the layered architecture divides the software into several layers, each with clear roles and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the Android system can be divided from top to bottom into an application layer, an application framework layer, and a kernel layer. Among them:

[0166] The application layer includes a series of application packages, such as camera, gallery, etc. Other applications that can enable the front camera of the electronic device 100, such as WeChat, TikTok, etc., may also be included.

[0167] The application framework layer provides an application programming interface (API) and a programming framework for the applications in the application layer. The application framework layer includes some predefined functions.

[0168] The application layer and the application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and the application framework layer as binary files. The virtual machine is used to perform functions such as object life cycle management, stack management, thread management, security and exception management, and garbage collection.

[0169] like Fig. 9As shown, in the embodiment of the present application, the application framework layer may include an Activity Manager Service (AMS) and a critical task identification module. Among them, AMS is a system service of the Android system, which is used to control the reasonable scheduling and operation between different applications in the system. The main responsibilities of AMS include unified scheduling of the Activities of various applications, management of the processes of applications, management of memory, scheduling services, scheduling tasks, querying the current running status of the system, etc. The tasks managed by AMS include critical tasks and non-critical tasks. The critical task identification module is used to identify and manage whether the tasks performed by the electronic device 100 are critical tasks. In some embodiments, a first file is stored in the critical task identification module. The first file is used to store the identification information corresponding to each task corresponding to all applications of the electronic device 100, and the attribute information of whether the task is a critical task. In some embodiments, the critical task identification module can obtain a second file, and the second file is used to store the identification information corresponding to each task corresponding to all applications of the electronic device 100, and the priority of the task; the critical task identification module can identify whether the task is a critical task based on the priority of the task.

[0170] The kernel layer is the layer between hardware and software. The kernel layer can respond to the functions called by the application framework layer and perform corresponding operations.

[0171] In the present application embodiment, Fig. 9As shown, the kernel layer may include a load statistics module, a scheduler, a scheduling class framework, and a context switching module. Among them, the load statistics module is used to count the current load of the electronic device 100 in each load statistics cycle when the electronic device 100 performs the task this time. The scheduler is used to activate the specified scheduling class to perform task scheduling, and task scheduling is the allocation of multiple tasks on multiple CPU cores and task migration between different CPU cores. The scheduling class framework may include the following scheduling classes: stop_sched_class, dl_sched_class, rt_sched_class, fair_sched_class, and idle_sched_class. The context switching module is used to perform context switching of the task when the task migrates between cores, and the context switching module can also store the context of each task. In some embodiments, when the task migrates between cores, the current computing power of the source CPU core and the migration type of the task are recorded in the context of the task. In some embodiments, when the task migrates between cores, the context switching module calls the critical task identification module to identify whether the task is a critical task, and records the first task information of the task in the context of the task, and the first task information is used to characterize whether the task is a critical task.

[0172] In the embodiment of the present application, the core layer may also include a touch chip driver, a display driver, a sensor driver, a camera driver, an audio driver, and the like.

[0173] It should be noted that Fig. 9 This is only an exemplary description of the software structure diagram in the embodiment of the present application. Fig. 9 Each layer of the software structure diagram shown may also include other modules, which are not specifically limited here.

[0174] The present application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be completed by a computer program to instruct the relevant hardware, and the program can be stored in the above computer storage medium. When the program is executed, it can include the processes of the above method embodiments. The computer-readable storage medium includes: a read-only memory (ROM) or a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0175] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0176] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0177] The modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0178] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for adjusting the frequency of inter-nuclear migration, characterized in that: The method comprises: When the electronic device determines that the expected computing capacity corresponding to the current load of the first processor core is greater than a first preset value, the first task in the first task queue of the first processor core is migrated to the second task queue of the second processor core, and the first computing capacity corresponding to the current frequency of the first processor core and the first migration type of the first task are recorded; When the electronic device schedules the first task in the second task queue, when it is determined that the first task is a new task of the first migration type in the second task queue, determining a first frequency of the second processor core corresponding to the first computing capability; When the current frequency of the second processor core is less than a second preset value, the frequency of the second processor core is adjusted to the first frequency, where the second preset value is determined based on the first frequency.

2. The method according to claim 1, characterized in that When determining that the first task is a new task of the first migration type in the second task queue, determining a first frequency of the second processor core corresponding to the first computing capability includes: When it is determined that the first task is a new task of the first migration type in the second task queue, and the first task is a task of the first type, a first frequency of the second processor core corresponding to the first computing capability is determined.

3. The method according to claim 1 or 2, characterized in that: The step of migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and recording the first computing capability corresponding to the current frequency of the first processor core and the first migration type of the first task includes: Migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and determining the first computing capability corresponding to the current frequency of the first processor core when the first task performs context switching; It is recorded in the context of the first task that the computing capability corresponding to the current frequency of the source processor core of the first task is the first computing capability, and the migration type of the first task is the first migration type.

4. The method according to claim 2, characterized in that: The step of migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and recording the first computing capability corresponding to the current frequency of the first processor core and the first migration type of the first task includes: Migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and determining the first computing capability corresponding to the current frequency of the first processor core and whether the first task is a task of the first type when the first task performs context switching; In the context of the first task, it is recorded that the computing power corresponding to the current frequency of the source processor core of the first task is the first computing power, the migration type of the first task is the first migration type, and first task information, wherein the first task information is used to characterize whether the first task is a task of the first type.

5. The method according to claim 4, characterized in that When determining that the first task is a new task of the first migration type in the second task queue, determining a first frequency of the second processor core corresponding to the first computing capability includes: When it is determined that the first task is a new task in the second task queue, acquiring the migration type of the first task and the first task information from the context of the first task; When it is determined that the migration type of the first task is the first migration type, and the first task information indicates that the first task is a task of the first type, obtaining the current computing capability of the source processor core of the first task when the first task is migrated from the context of the first task, and the current computing capability of the source processor core of the first task is the first computing capability; The electronic device determines the first frequency of the second processor core corresponding to the first computing capability.

6. The method according to claim 5, characterized in that The electronic device records the running time of each task in the second task queue on the second processor core, and the determining that the first task is a new task in the second task queue includes: When the running time of the first task recorded by the electronic device on the second processor core is zero, it is determined that the first task is a new task in the second task queue.

7. The method according to claim 1, characterized in that The first preset value is equal to the maximum computing capability of the first processor core; or, the first preset value is equal to k1 times the maximum computing capability of the first processor core, where k1 is greater than zero and less than 1.

8. The method according to claim 1, characterized in that: The second preset value is equal to the first frequency; or, the second preset value is equal to k2 times of the first frequency, and k2 is greater than zero and less than 1.

9. The method according to claim 2, characterized in that: The first type of tasks includes tasks of a specified type and tasks that are strongly related to the tasks of the specified type; Alternatively, the first type of tasks includes the specified type of tasks of the applications corresponding to the top-level application group and the foreground group, and tasks strongly related to the specified type of tasks; The task of the specified type includes at least one of a drawing task, a data downloading task and a data uploading task.

10. The method according to claim 2, characterized in that The first type of tasks includes tasks for a specific application; Alternatively, the first type of tasks includes tasks of the designated application corresponding to the top-level application group and the foreground group; The designated application includes at least one of a game application, a navigation application, and a video application.

11. An electronic device comprising a memory, one or more processors, a plurality of applications, and one or more programs; wherein: The one or more programs are stored in the memory; it is characterized in that when the one or more processors execute the one or more programs, the electronic device implements the method according to any one of claims 1 to 10.

12. A computer storage medium, characterized in that: The method comprises computer instructions, and when the computer instructions are executed on an electronic device, the electronic device executes the method according to any one of claims 1 to 10.

13. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 10.

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