Circuit generation method and device, storage medium and electronic device

Abstract

The present disclosure relates to the field of circuit generation technology, and specifically to a circuit generation method and apparatus, a computer-readable storage medium, and an electronic device. The method comprises: obtaining a clock relationship between clock signals in a circuit; performing multi-dimensional grouping of the clock signals according to preset rules based on the clock relationships to obtain grouping results; and generating circuit constraints based on the grouping results, thereby generating the circuit according to the circuit constraints. The technical solutions of the embodiments of the present disclosure improve the accuracy of the circuit constraints generated based on the clock signals and reduce the amount of computation required during the design process.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuit generation, and in particular to a circuit generation method and apparatus, a computer-readable storage medium, and an electronic device. Background Art

[0002] In circuit design, designing the constraint relationship between clock signals is an indispensable part of ensuring the normal operation of the circuit.

[0003] The solution in the prior art based on circuit constraints generated between clock signals has low accuracy and a large amount of calculation in the design process.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a circuit generation method, a circuit generation device, a computer-readable medium and an electronic device, thereby improving the accuracy of circuit constraints generated between clock signals to at least a certain extent and reducing the amount of calculation in the design process.

[0006] According to a first aspect of the present disclosure, a circuit generation method is provided, comprising: obtaining a clock relationship between each of the clock signals in the circuit; performing multi-dimensional grouping of the clock signals according to preset rules based on the clock relationship to obtain a grouping result; and generating circuit constraints based on the grouping results to generate the circuit according to the circuit constraints.

[0007] According to a second aspect of the present disclosure, a circuit generation device is provided, comprising: an acquisition module for acquiring a clock relationship between the clock signals in the circuit; a grouping module for grouping the clock signals according to preset rules based on the clock relationship to obtain a grouping result; and a generation module for generating circuit constraints based on the grouping result, so as to generate the circuit according to the circuit constraints.

[0008] According to a third aspect of the present disclosure, a computer-readable medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above method is implemented.

[0009] According to a fourth aspect of the present disclosure, an electronic device is provided, characterized in that it includes: one or more processors; and a memory for storing one or more programs, which enables the one or more processors to implement the above-mentioned method when the one or more programs are executed by the one or more processors.

[0010] An embodiment of the present disclosure provides a circuit generation method, which obtains the clock relationship between each of the clock signals in the circuit; performs multi-dimensional grouping of the clock signals according to preset rules based on the clock relationship to obtain a grouping result; generates circuit constraints based on the grouping result, so as to generate the circuit according to the circuit constraints. Compared with the prior art, multi-dimensional grouping of clock signals based on the clock relationship between the clock signals enhances the obtained grouping results, increases the visibility when designing the constraints, and improves the accuracy of the obtained constraints. Further, circuit constraints are generated based on the grouping results obtained by multi-dimensional grouping. During the generation process, the difficulty of program operation is reduced, the amount of calculation can be reduced, and the fault tolerance of the generated circuit can be improved.

[0011] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0013] Figure 1 A schematic diagram of clock grouping in the related art is shown;

[0014] Figure 2 A schematic diagram showing an exemplary system architecture to which embodiments of the present disclosure may be applied;

[0015] Figure 3 A flow chart schematically illustrates a circuit generation method in an exemplary embodiment of the present disclosure;

[0016] Figure 4 A schematic diagram schematically illustrates a clock grouping in an exemplary embodiment of the present disclosure;

[0017] Figure 5 Schematically illustrates a flow chart for generating circuit constraints in an exemplary embodiment of the present disclosure;

[0018] Figure 6 A schematic diagram illustrating a method of setting a clock relationship between arrays in an exemplary embodiment of the present disclosure;

[0019] Figure 7 A schematic diagram of a clock structure in an exemplary embodiment of the present disclosure is provided;

[0020] Figure 8 In the exemplary embodiments of the present disclosure Figure 7 Schematic diagram of the clock grouping results corresponding to the clock signals in ;

[0021] Figure 9 Schematic diagram showing the composition of a circuit generating device in an exemplary embodiment of the present disclosure

[0022] Figure 10 A schematic diagram of an electronic device to which the embodiments of the present disclosure can be applied is shown. DETAILED DESCRIPTION

[0023] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0025] In related technologies, for SOC design, it is very important to integrate the SDC (Synopsys Design Constraints) of IP (intellectual property) into SOC (System on Chip). The clock relationships in SOC design are often very complex. Grouping the clocks can facilitate clock organization and management, and visualize the clock relationships. After grouping the clocks, the clock relationships between each clock set can be set, and the same clock relationship can be set between each set. After the IP clocks are integrated into the SOC, the clocks need to be re-grouped at the SOC level, and some of the IP clock groups can be reused.

[0026] However, in the related art, reference Figure 1As shown, clock grouping has only one dimension, and typically only one clock relationship is set within this dimension. This facilitates looping. Setting multiple clock relationships within a single dimension complicates the SDC and prevents visualization of multiple clock relationships within a single dimension. This approach fails to meet the management requirements of multiple clock relationships within the SDC. When integrating IP into an SOC, the clock grouping of IP and blocks is reused, making it difficult to expand clock grouping.

[0027] Figure 2 A schematic diagram of a system architecture is shown. System architecture 200 may include a terminal 210 and a server 220. Terminal 210 may be a terminal device such as a smartphone, tablet computer, desktop computer, or laptop computer. Server 220 generally refers to a backend system that provides circuit generation-related services in this exemplary embodiment and may be a single server or a cluster of multiple servers. Terminal 210 and server 220 may be connected via a wired or wireless communication link to exchange data.

[0028] In one embodiment, the circuit generation method may be performed by the terminal 210. For example, after a user uses the terminal 210 to obtain a clock signal and a corresponding clock relationship, the terminal 210 performs circuit generation.

[0029] In one embodiment, the circuit generation method described above may be performed by server 220. For example, after a user uses terminal 210 to obtain clock signals and the clock relationships between the clock signals, terminal 210 uploads the clock signals and their corresponding clock relationships to server 220, and server 220 generates a circuit diagram and returns the circuit diagram to terminal 210.

[0030] As can be seen from the above, the circuit generation method in this exemplary embodiment may be executed by the terminal 210 or the server 220 , and this disclosure does not limit this.

[0031] The following combination Figure 3 A circuit generation method in this exemplary embodiment will be described. Figure 3 An exemplary process of the circuit generation method is shown, which may include:

[0032] Step S310, obtaining a clock relationship between the clock signals in the circuit;

[0033] Step S320, performing multi-dimensional grouping on the clock signals according to the clock relationship and a preset rule to obtain a grouping result;

[0034] Step S330 : generating circuit constraints according to the grouping result, so as to generate the circuit according to the circuit constraints.

[0035] Based on the above method, the clock signals are multi-dimensionally grouped according to the clock relationship between the clock signals, which enhances the grouping results, increases the visibility when designing constraints, and improves the accuracy of the constraints obtained. Further, circuit constraints are generated based on the grouping results obtained by multi-dimensional grouping, which can reduce the amount of calculation during the generation process and improve the fault tolerance of the generated circuit.

[0036] Below Figure 3 Each step is described in detail.

[0037] refer to Figure 3 In step S310, the clock relationship between the clock signals in the circuit is obtained.

[0038] In an example embodiment of the present disclosure, when the circuit is designed, the number of clock signals in the circuit and the timing of each clock signal in the circuit have been limited, and the clock relationship between the above clock signals can be determined based on the timing of the above clock signals.

[0039] In this example implementation, the above-mentioned clock relationship may include a synchronous relationship and an asynchronous relationship, where the asynchronous relationship includes an asynchronous check relationship, an asynchronous non-check relationship, a logical exclusion relationship, and a physical exclusion relationship. It can also be customized according to user needs and is not specifically limited in this example implementation.

[0040] In this example implementation, a synchronous relationship indicates that the relative phase of two clocks remains unchanged, and it is necessary to check whether the timing is correct between the clocks; an asynchronous non-check relationship indicates that the phase between the clocks will continue to change, and there is no need to check whether the timing is correct; an asynchronous check relationship indicates that the phase between the clocks will continue to change, and it is necessary to check whether the timing is correct; a logical mutual exclusion relationship indicates that the clocks will actually exist at the same time in the circuit, but will not exist functionally at the same time; and a physical mutual exclusion relationship indicates that the clocks will not actually exist at the same time in the circuit.

[0041] In step S320, the clock signals are multi-dimensionally grouped according to the clock relationship and a preset rule to obtain a grouping result.

[0042] In this example embodiment, after determining the clock relationship between the above-mentioned clock signals, the above-mentioned clock signals can be divided into multiple arrays according to the clock relationship, and each array includes at least one set. Specifically, the clocks can be divided into multiple arrays according to multiple of the above-mentioned asynchronous check relationship, asynchronous non-check relationship, logical mutual exclusion relationship, and physical mutual exclusion relationship. That is, the clock signals with asynchronous non-check relationship are regarded as one array, the clock signals with asynchronous check relationship are regarded as one array, and the clock signals with logical mutual exclusion relationship are regarded as one array. The clock signals with physical mutual exclusion relationship are regarded as one array, and each of the above-mentioned arrays includes at least one set. The specific number of sets is determined by the user's circuit design and the relationship between the various clocks, and is not specifically limited in this example embodiment. The names of the sets in each array can be named in numerical order, for example, the first set, the second set, etc., and can also be customized according to user needs, which is not specifically limited in this example embodiment.

[0043] In this example embodiment, the above-mentioned array and the above-mentioned set meet a first preset condition, wherein the above-mentioned first preset condition can be that each of the clock signals is in only one set; the clock relationship between each of the clock signals in each set is a synchronous relationship; the clock relationship between each of the sets in each of the arrays is the same, and they are all asynchronous relationships; the clock relationship of all clock signals in sets with the same name in different arrays is a synchronous relationship; the clock relationship between sets with different names in different arrays is an asynchronous relationship.

[0044] In an exemplary embodiment of the present disclosure, when designing a circuit, multiple modules may be included. When grouping, the modules to which the above-mentioned clock signals belong in the circuit may be considered, and clock signals with different belonging modules may be grouped as one group. For example, Figure 4 The third array and the second array in belong to asynchronous inspection relationships, but their belonging modules are different.

[0045] The following is a specific example to illustrate the specific details of grouping the above clock signals. Figure 4 As shown, the clock signal AN is divided into three arrays, namely the first array, the second array, and the third array. The first array includes the first set, the second set, and the third set. The second array includes the first set and the second set. The third array includes the second set and the third set. It should be noted that the clock signals in the same named sets in different arrays are different.

[0046] Specific grouping conditions such as Figure 4As shown, in the first array, the second array and the third array, the clock signal AN appears only once in total, and in the same set, the clock signals are all in a synchronous relationship. For example, A and B are in a synchronous relationship with each other, and C and D are in a synchronous relationship with each other. In the same array, all sets are in an asynchronous relationship. For example, the first set and the second set in the first array are in an asynchronous non-check relationship, the second set and the third set in the first array are also in an asynchronous non-check relationship, the first set and the second set in the second array are in an asynchronous check relationship, and the second set and the third set in the third array are in an asynchronous check relationship. In different arrays, all clock signals in sets with the same name are in a synchronous relationship. For example, all clock signals in the second set in the first array, the second set in the second array and the third set in the third array are in a synchronous relationship, that is, the clocks CDIJKL are in a synchronous relationship with each other. The clock relationships between sets with different names in different arrays are all asynchronous relationships, and in this embodiment, are asynchronous, no-check relationships. For example, the clock relationship between the first set in the first array and the second set in the second array is an asynchronous, no-check relationship, and the clock relationship between the first set in the second array and the second set in the first array is an asynchronous, no-check relationship. The synchronous relationship, the asynchronous, check, and no-check relationships have been described in detail above and are not further elaborated here.

[0047] In this example implementation, the clock relationships between the third array and the second array are both asynchronous check relationships. The third array and the second array belong to different modules of the circuit, that is, the third array and the second array belong to different modules. Adding the belonging modules for grouping can make the generated circuit constraints more accurate and more visual.

[0048] In this example embodiment, the grouping result can be a group list to enhance the visibility of the grouping result, facilitate verification, and prevent errors. The grouping result can also be a tree diagram, which can also be customized according to user needs, and is not specifically limited in this example embodiment.

[0049] Step S330 : generating circuit constraints according to the grouping result, so as to generate the circuit according to the circuit constraints.

[0050] In this example embodiment, referring to Figure 5 As shown, step S510 can be first executed to group the clocks, then step S520 can be executed to set the clock relationship within the group, and then step S530 can be executed to set the component clock relationship. The specific details of the clock grouping have been set in detail above, so they will not be repeated here.

[0051] In this example embodiment, after obtaining the grouping results, circuit constraints can be generated based on the grouping results. Specifically, first, based on the intra-group relationships between the arrays, all of the sets within each array can be set to one of the asynchronous relationships. Then, inter-group relationships between the clock arrays can be set.

[0052] When setting the inter-group relationship between arrays, you can select two from all clock arrays to set the inter-group clock relationship. Assuming there are n clock arrays, this process needs to be executed in total The method for clock array extraction is to first extract an array, set the clock relationship between this array and other arrays, then exclude the extracted clock array, extract another array from the remaining array, set the clock relationship between this array and the other remaining arrays, then exclude the extracted array again, and repeat the process until only one array is left.

[0053] In this example embodiment, the clock relationship between the two clock arrays can be extracted as follows: Figure 6 As shown, in Figure 4 Extract the first set from the second array, then extract all sets in the first array that have different names from the set extracted from the second array. Set the clock relationships between these extracted sets, i.e., asynchronously without checking the relationship. Next, extract the second set from the second array, then extract all sets in the first array that have different names from the second array, respectively, as the first and third sets. Set the clock relationships between these sets, and repeat until all sets in the first array have been extracted. Multiple target groups are obtained, and the information about these groups is used as the circuit constraints described above.

[0054] Specifically, refer to Figure 6 As shown, the two target groups obtained are the first target array and the second target array, each including three sets. The first set of the first target array includes the clock GH, that is, the first set in the second array. The second set and the third set in the first target group are the second set and the third set in the above-mentioned first array. The first set in the second target group is the first set in the first array, the second set in the second target array is the second set in the second array, and the third set in the second target array is the third set in the first set.

[0055] In this example embodiment, after obtaining the above circuit constraints, a circuit behavior description can be obtained. The circuit behavior description can be preset by the user when designing the circuit, and then the corresponding circuit can be generated based on the above circuit behavior description and the above circuit constraints.

[0056] The following is a specific example to illustrate the details of the circuit generation method disclosed in the present invention. Figure 7 As shown, Figure 7 A RTL (Register Transfer Level) clock structure diagram is set up in the , including three IPs, namely IPA, IPB and IPC, among which, Figure 7 There are five clocks A, B, C, and D defined by create_clock, and five clocks AG, BG, CG, and DGEG defined by create_generated_clock. create_generated_clock is the subsequent clock connected to create_clock. The clock relationships between these clock signals, AG, BG, and CG, are asynchronous_allow_paths. Among the clocks ABC and (D, DG, E, and EG), the clock relationships between D, DG, and EEG are synchronous, and the clock relationship between (D, DG, E, and EG) and ABC is asynchronous. Therefore, set the clock relationship between ABC and (D, DG, E, and EG) to asynchronous (no asynchronous path), and set the three clocks, AG, BG, and CG, to asynchronous_allow_paths. The problem at this time is that the steps for defining the clock relationship between A BC DE and AG BG CG are relatively cumbersome. Among them, CLKA is connected to the above-mentioned CLKAG, CLKAG is connected to the above-mentioned IPA, CLKA is connected to both IPB and IPC, CLKB is connected to the above-mentioned CLKBG, CLKBG is connected to the above-mentioned IPA, CLKB is connected to IPC, CLKC is set inside the above-mentioned IPB and connected to the above-mentioned IPA through CLKCG, CLKD and CLKE are logically exclusive and are logically connected to the IPC through the above-mentioned CLKDG and CLKEG. Among them, CLKDG and CLKEG are physically exclusive, that is, only one of the above-mentioned CLKD and CLKE signals can be transmitted to the above-mentioned IPC at the same time.

[0057] First, refer to Figure 8 As shown, the above-mentioned multiple clock signals can be grouped to obtain grouping results, and then corresponding circuit constraints can be obtained based on the obtained grouping results.

[0058] In this example implementation, when generating the constraint conditions, the tool command language (tcl) may be used to implement the generation.

[0059] Specifically, the clock grouping rules group the clocks of the RTL design. Clock grouping can be implemented using the following Tcl commands:

[0060] set GROUP_1(list1)[list CLK_A] / / Place clock signal A in the first group of the first array;

[0061] set GROUP_1(list2)[list CLK_B] / / Place clock signal B in the second group of the first array;

[0062] set GROUP_1(list3)[list CLK_C] / / Place clock signal C in the third group of the first array;

[0063] set GROUP_1(list4)[list CLK_D CLK_DG CLK_E CLK_EG] / / Place the clock signals D DG EEG in the fourth group of the first array;

[0064] set GROUP_2(list1)[list CLK_AG] / / Place the clock signal AG in the first group of the second array;

[0065] set GROUP_2(list2)[list CLK_BG] / / Place the clock signal BG in the second set of the second array;

[0066] set GROUP_2(list3)[list CLK_CG] / / Place the clock signal CG in the third group of the second array;

[0067] The pseudo code for setting the clock relationship within a group is as follows:

[0068] group_set_insede(asynchronous GROUP_1)

[0069] group_set_insede(asynchronous_allow_paths GROUP_2)

[0070] group_set_inside(asynchronous GROUP_1) sets the clock relationship between all lists in GROUP_1 to asynchronous. The execution result is equivalent to the following Tcl command: set_clock_groups-asynchronous

[0071] -group$GROUP_1(list1)

[0072] -group$GROUP_1(list2)

[0073] -group$GROUP_1(list3)

[0074] -group$GROUP_1(list4)

[0075] After completing the component relationship setting between the first arrays, that is, setting all the sets between the first arrays to asynchronous non-check relationships, you can execute the following code: group_set_inside(asynchronous_allow_pathsGROUP_2) to set the clock relationship between all sets in GROUP_2 to asynchronous_allow_paths (asynchronous check relationship). The execution result is equivalent to the following Tcl command:

[0076] set_clock_groups-asynchronous-allow_paths

[0077] -group$GROUP_2(list1)

[0078] -group$GROUP_2(list2)

[0079] -group$GROUP_2(list3)

[0080] Set the clock relationships of the first set, the second set, and the third set in the second array to asynchronous check relationships

[0081] In this example implementation, after setting the clock relationship within an array, the clock relationship between arrays can be set. The specific pseudo code is as follows:

[0082] GROUPS = [listGROUP_2GROUP_1]

[0083] group_set_each(asynchronous GROUPS)

[0084] group_set_each(asynchronous GROUPS) / / Set the clock relationship between GROUP_1 and GROUP_2 to asynchronous (asynchronous does not check the relationship). The execution result is equivalent to the following Tcl command:

[0085] set_clock_groups-asynchronous

[0086] -group$GROUP_2(list1)

[0087] -group$GROUP_1(list2)

[0088] -group$GROUP_1(list3)

[0089] -group$GROUP_1(list4)

[0090] The first circuit constraint condition is obtained by replacing the first set in the first array with the first set in the second array.

[0091] set_clock_groups-asynchronous

[0092] -group$GROUP_1(list1)

[0093] -group$GROUP_2(list2)

[0094] -group$GROUP_1(list3)

[0095] -group$GROUP_1(list4)

[0096] The second set in the second array is used to replace the second set in the first array to obtain a second circuit constraint condition.

[0097] set_clock_groups-asynchronous

[0098] -group$GROUP_1(list1)

[0099] -group$GROUP_1(list2)

[0100] -group$GROUP_2(list3)

[0101] -group$GROUP_1(list4).

[0102] The third set in the second array is used to replace the third set in the first array to obtain a third circuit constraint condition.

[0103] In this exemplary embodiment, the first circuit constraint, the second constraint, and the third constraint can be used as Figure 7 Circuit constraints for the shown circuit.

[0104] In summary, in this exemplary embodiment, compared to the prior art, multi-dimensional grouping of clock signals based on their clock relationships enhances the resulting grouping results, increases visibility when designing constraints, and improves the precision of the resulting constraints. Furthermore, circuit constraints are generated based on the grouping results obtained from the multi-dimensional grouping, reducing computational complexity during the generation process while improving the fault tolerance of the generated circuit. Furthermore, the clocks are divided into multiple arrays based on the asynchronous check and asynchronous non-check relationships, and each set in each array is set to meet preset conditions. This improves the precision of the resulting circuit constraints and further reduces the error rate of the resulting circuit.

[0105] It should be noted that the above figures are merely illustrative of the processes included in the methods according to exemplary embodiments of the present disclosure and are not intended to be limiting. It is readily understood that the processes illustrated in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0106] For further reference, Figure 9 As shown, in the embodiment of this example, a circuit generation device 900 is further provided, comprising an acquisition module 910, a grouping module 920 and a generation module 930. In particular:

[0107] The acquisition module 910 may be configured to acquire the clock relationship between clock signals in the circuit.

[0108] The grouping module 920 can be used to group clock signals according to preset rules based on clock relationships to obtain grouping results, wherein performing multi-dimensional grouping of clock signals according to preset rules based on clock relationships to obtain grouping results includes: dividing the clock signals into multiple arrays according to preset rules based on clock relationships, and each array can include at least one set, and the number of sets meets a first preset condition. The above-mentioned first preset condition may include that each clock signal is only in one set; the clock relationship of each clock signal in each set is a synchronous relationship; the clock relationship between each set in each array is the same and all are asynchronous relationships; the clock relationship of all clock signals in sets with the same name in different arrays is a synchronous relationship; the clock relationship between sets with different names in different arrays is an asynchronous relationship.

[0109] In this example embodiment, the clock relationship includes an asynchronous check relationship, an asynchronous non-check relationship, a logical mutually exclusive relationship, and a physical mutually exclusive relationship. Dividing the clock signal into multiple arrays according to preset rules based on the clock relationship includes: dividing the clock signal into multiple arrays according to multiple of the asynchronous check relationship, the asynchronous non-check relationship, the logical mutually exclusive relationship, and the physical mutually exclusive relationship.

[0110] In an example embodiment of the present disclosure, a circuit includes multiple modules, and dividing the clock signal into multiple arrays according to multiple types of asynchronous check relationships, asynchronous non-check relationships, logical mutual exclusion relationships, and physical mutual exclusion relationships includes: determining the module to which each clock signal belongs in the circuit; and dividing the clock signal into multiple arrays according to multiple types of the belonging module, asynchronous check relationship, asynchronous non-check relationship, logical mutual exclusion relationship, and physical mutual exclusion relationship.

[0111] The generation module 930 can be configured to generate circuit constraints based on the grouping results, thereby generating a circuit based on the circuit constraints. Specifically, the generation module 930 can generate the circuit constraints based on the grouping results using a conversion script. Generating the circuit based on the circuit constraints includes: obtaining a circuit behavior description of the circuit; and generating the circuit based on the circuit behavior description and the circuit constraints.

[0112] The specific details of each module in the above device have been described in detail in the implementation method part. The undisclosed details can be found in the implementation method part, so they will not be repeated here.

[0113] The exemplary embodiments of the present disclosure further provide an electronic device for executing the above-mentioned circuit generation method, which may be the above-mentioned terminal 210 or server 220. Generally, the electronic device may include a processor and a memory, the memory being configured to store executable instructions of the processor, and the processor being configured to execute the above-mentioned circuit generation method by executing the executable instructions.

[0114] Below Figure 10 The structure of the electronic device is exemplarily described by taking the mobile terminal 1000 in FIG. 1 as an example. It should be understood by those skilled in the art that, in addition to the components specifically used for mobile purposes, Figure 10 The construction in can also be applied to fixed type equipment.

[0115] like Figure 10 As shown, the mobile terminal 1000 may specifically include: a processor 1001, a memory 1002, a bus 1003, a mobile communication module 1004, an antenna 1, a wireless communication module 1005, an antenna 2, a display screen 1006, a camera module 1007, an audio module 1008, a power module 1009 and a sensor module 1010.

[0116] Processor 1001 may include one or more processing units. For example, processor 1010 may include an AP (Application Processor), a modem processor, a GPU (Graphics Processing Unit), an ISP (Image Signal Processor), a controller, an encoder, a decoder, a DSP (Digital Signal Processor), a baseband processor, and / or an NPU (Neural-Network Processing Unit). The circuit generation method in this exemplary embodiment may be executed by an AP, a GPU, or a DSP. When the method involves processing related to a neural network, it may be executed by an NPU.

[0117] The processor 1001 may be connected to the memory 1002 or other components via a bus 1003 .

[0118] Memory 1002 can be used to store computer-executable program code, which includes instructions. Processor 1001 executes various functional applications and data processing of mobile terminal 1000 by running the instructions stored in memory 1002. Memory 1002 can also store application data, such as images, videos, and other files.

[0119] The communication functions of mobile terminal 1000 are implemented through mobile communication module 1004, antenna 1, wireless communication module 1005, antenna 2, a modem processor, and a baseband processor. Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Mobile communication module 1004 can provide 2G, 3G, 4G, and 5G mobile communication solutions for mobile terminal 1000. Wireless communication module 1005 can provide wireless communication solutions such as wireless LAN, Bluetooth, and near-field communication for mobile terminal 1000.

[0120] The display screen 1006 is used to implement display functions, such as displaying a user interface, images, and videos. The camera module 1007 is used to implement shooting functions, such as capturing images and videos. The audio module 1008 is used to implement audio functions, such as playing audio and capturing voice. The power module 1009 is used to implement power management functions, such as charging the battery, powering the device, and monitoring battery status. The sensor module 1010 may include a depth sensor 10101, a pressure sensor 10102, a gyroscope sensor 10103, an air pressure sensor 10104, etc., to implement corresponding sensing and detection functions.

[0121] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods, or program products. Therefore, various aspects of the present disclosure may be implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0122] The exemplary embodiments of the present disclosure further provide a computer-readable storage medium having stored thereon a program product capable of implementing the methods described above in this specification. In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product comprising program code that, when executed on a terminal device, causes the terminal device to execute the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of the present disclosure.

[0123] It should be noted that the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0124] In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the foregoing.

[0125] In addition, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, and the like, as well as conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0126] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0127] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A circuit generation method, characterized in that: include: Obtaining a clock relationship between clock signals in the circuit; Performing multi-dimensional grouping of the clock signals according to the clock relationship and a preset rule to obtain a grouping result; generating circuit constraints according to the grouping results, so as to generate the circuit according to the circuit constraints; The performing multi-dimensional grouping of the clock signals according to the clock relationship and a preset rule to obtain a grouping result includes: Dividing the clock signal into a plurality of arrays according to the clock relationship and a preset rule, wherein each array includes at least one set, and the arrays and the sets satisfy a first preset condition; Among them, the clock relationship includes a synchronous relationship and an asynchronous relationship, and the first preset condition includes: each of the clock signals is in only one set; the clock relationship of each of the clock signals in each set is a synchronous relationship; the clock relationship between each of the sets in each of the arrays is the same, and they are all asynchronous relationships; the clock relationship of all clock signals in sets with the same name in different arrays is a synchronous relationship; the clock relationship between sets with different names in different arrays is an asynchronous relationship.

2. The method according to claim 1, characterized in that The clock relationship includes an asynchronous check relationship, an asynchronous non-check relationship, a logical mutual exclusion relationship, and a physical mutual exclusion relationship. Dividing the clock signal into multiple arrays according to the clock relationship and a preset rule includes: The clock signals are divided into a plurality of arrays according to multiple of the asynchronous check relationship, the asynchronous non-check relationship, the logical mutual exclusion relationship, and the physical mutual exclusion relationship.

3. The method according to claim 2, characterized in that Dividing the clock signal into a plurality of arrays according to multiple of the asynchronous check relationship, the asynchronous non-check relationship, the logical mutual exclusion relationship, and the physical mutual exclusion relationship comprises: Determining a module to which each of the clock signals belongs in the circuit; The clock signals are divided into a plurality of arrays according to multiple of the belonging modules, the asynchronous check relationships, the asynchronous non-check relationships, the logical mutual exclusion relationships, and the physical mutual exclusion relationships.

4. The method according to claim 1, wherein Generating circuit constraints according to the grouping result includes: The circuit constraint condition is generated by using a conversion script according to the grouping result.

5. The method according to claim 1, wherein Generating the circuit according to the circuit constraint condition includes: obtaining a circuit behavior description of the circuit; The circuit is generated according to the circuit behavior description and the circuit constraint conditions.

6. A circuit generating device, characterized in that: include: An acquisition module, configured to acquire a clock relationship between clock signals in the circuit; A grouping module, configured to group the clock signals according to a preset rule based on the clock relationship to obtain a grouping result; a generating module, configured to generate circuit constraints according to the grouping result, so as to generate the circuit according to the circuit constraints; The performing multi-dimensional grouping of the clock signals according to a preset rule based on the clock relationship to obtain a grouping result includes: Dividing the clock signal into a plurality of arrays according to the clock relationship and a preset rule, wherein each array includes at least one set, and the arrays and the sets satisfy a first preset condition; Among them, the clock relationship includes a synchronous relationship and an asynchronous relationship, and the first preset condition includes: each of the clock signals is in only one set; the clock relationship of each of the clock signals in each set is a synchronous relationship; the clock relationship between each of the sets in each of the arrays is the same, and they are all asynchronous relationships; the clock relationship of all clock signals in sets with the same name in different arrays is a synchronous relationship; the clock relationship between sets with different names in different arrays is an asynchronous relationship.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the circuit generation method according to any one of claims 1 to 5 is implemented.

8. An electronic device, characterized in that: include: one or more processors; as well as A memory for storing one or more programs, which, when executed by the one or more processors, enables the one or more processors to implement the circuit generation method according to any one of claims 1 to 5.

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